Samsung S3F80P5, S3F80P5X User Manual

USER’S MANUAL

S3F80P5X

S3F80P5 MICROCONTROLLERS

April 2010

REV 1.00

Confidential Proprietary of Samsung Electronics Co., Ltd

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

S3F80P5 Microcontroller User's Manual, Revision 1.00

"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.

Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur.

Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.

Publication Number: S3-F80P5-022009

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives.

Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 446-711

TEL: (82)-(31)-209-3865 FAX: (82)-(31)-209-6494

Home Page: http://www.samsungsemi.com Printed in the Republic of Korea

Preface

The S3F80P5 Microcontroller User's Manual is designed for application designers and programmers who are using the S3F80P5 microcontroller for application development. It is organized in two main parts:

Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming

model, and address spaces. It has three chapters: Chapter 1 Product Overview

Chapter 2 Address Spaces

Chapter 1, "Product Overview," is a high-level introduction to S3F80P5 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, “Address Spaces,” describes the important feature of the S3F80P5 programming environment. Chapter 3, "Addressing Modes," describes program and data memory spaces, the internal register file, and

register addressing. Chapter 4, “Control Registers,” describes the definition, usages and supported APIs for Flash operations. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in

Part II. If you are not yet familiar with the S3FS-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1-3 carefully. Then, you can reference the information in Part II as necessary.

Part II "hardware Descriptions," has detailed information about specific hardware components of the S3F80P5 microcontroller. Also included in Part II is electrical data. It has 15 chapters:

Chapter 5 Interrupt Structure Chapter 6 Instruction Set Chapter 7 Clock and Power Circuits Chapter 8 Reset Chapter 9 I/O Ports Chapter 10 Basic Timer and Timer 0 Chapter 11 Timer 1 Chapter 12 Counter A

Two order forms are included at the back of this manual to facilitate customer order for S3F80P5 microcontroller: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

Chapter 3 Addressing Modes Chapter 4 Control Registers

Chapter 13 Timer 2 Chapter 14 Embedded Flash Memory Interface Chapter 15 Low Voltage Detector Chapter 16 Electrical Data Chapter 17 Mechanical Data Chapter 18 S3F80P5 Flash MCU Chapter 19 Development Tools

S3F80P5_UM_REV1.00 MICROCONTROLLER iii

Table of Contents

Part I — Programming Model

Chapter 1 Product Overview

S3C8/S3F8-Series Microcontrollers..............................................................................................................1-1

S3F80P5 Microcontroller...............................................................................................................................1-1

Features ........................................................................................................................................................1-2

CPU.........................................................................................................................................................1-2

Memory...................................................................................................................................................1-2

Instruction Set.........................................................................................................................................1-2

Instruction Execution Time .....................................................................................................................1-2

Interrupts.................................................................................................................................................1-2

I/O Ports..................................................................................................................................................1-2

Carrier Frequency Generator..................................................................................................................1-2

Basic Timer and Timer/Counters............................................................................................................1-2

Back-up Mode.........................................................................................................................................1-2

Low Voltage Detect Circuit .....................................................................................................................1-2

Operating Temperature Range...............................................................................................................1-2

Operating Voltage Range .......................................................................................................................1-2

Package Types.......................................................................................................................................1-2

Block Diagram (24-pin package)...................................................................................................................1-3

Pin Assignments............................................................................................................................................1-4

Pin Circuits ....................................................................................................................................................1-6

Chapter 2 Address Spaces

Overview........................................................................................................................................................2-1

Program Memory...........................................................................................................................................2-2

Smart Option...........................................................................................................................................2-3

Register Architecture.....................................................................................................................................2-5

Register Page Pointer (PP) ....................................................................................................................2-7

Register Set 1.........................................................................................................................................2-8

Register Set 2.........................................................................................................................................2-8

Prime Register Space.............................................................................................................................2-9

Working Registers...................................................................................................................................2-10

Using the Register Pointers....................................................................................................................2-11

Register Addressing......................................................................................................................................2-13

Common Working Register Area (C0H–CFH)........................................................................................2-15

Example 1:..............................................................................................................................................2-16

Example 2:..............................................................................................................................................2-16

4-Bit Working Register Addressing.........................................................................................................2-16

8-Bit Working Register Addressing.........................................................................................................2-18

System and User Stacks...............................................................................................................................2-20

Stack Operations ....................................................................................................................................2-20

User-Defined Stacks...............................................................................................................................2-20

Stack Pointers (SPL)...............................................................................................................................2-20

iv S3F80P5_UM_REV 1.00 MICROCONTROLLER

Table of Contents (Continued)

Chapter 3 Addressing Modes

Overview .......................................................................................................................................................3-1

Register Addressing Mode (R)...............................................................................................................3-2

Indirect Register Addressing Mode (IR).................................................................................................3-3

Indexed Addressing Mode (X)................................................................................................................3-7

Direct Address Mode (DA) .....................................................................................................................3-10

Direct Address MODE (Continued)........................................................................................................3-11

Indirect Address Mode (IA).....................................................................................................................3-12

Relative Address Mode (RA)..................................................................................................................3-13

Immediate Mode (IM) .............................................................................................................................3-14

Chapter 4 Control Registers

Overview .......................................................................................................................................................4-1

Chapter 5 Interrupt Structure

Overview .......................................................................................................................................................5-1

Levels .....................................................................................................................................................5-1

Vectors....................................................................................................................................................5-1

Sources...................................................................................................................................................5-1

Interrupt Types .......................................................................................................................................5-2

Interrupt Vector Addresses.....................................................................................................................5-4

Enable/Disable Interrupt Instructions (EI, DI).........................................................................................5-6

System-Level Interrupt Control Registers ..............................................................................................5-6

Interrupt Processing Control Points........................................................................................................5-7

Peripheral Interrupt Control Registers....................................................................................................5-8

System Mode Register (SYM)................................................................................................................5-9

Interrupt Mask Register (IMR)................................................................................................................5-10

Interrupt Priority Register (IPR)..............................................................................................................5-11

Interrupt Request Register (IRQ) ...........................................................................................................5-13

Interrupt Pending Function Types..........................................................................................................5-14

Overview.................................................................................................................................................5-14

Pending Bits Cleared Automatically by Hardware..................................................................................5-14

Pending Bits Cleared by the Service Routine ........................................................................................5-14

Interrupt Source Polling Sequence.........................................................................................................5-15

Interrupt Service Routines......................................................................................................................5-15

Generating interrupt Vector Addresses..................................................................................................5-16

Nesting of Vectored Interrupts................................................................................................................5-16

Instruction Pointer (IP)............................................................................................................................5-16

Fast Interrupt Processing .......................................................................................................................5-16

Fast Interrupt Processing (Continued) ...................................................................................................5-17

Procedure for Initiating Fast Interrupt.....................................................................................................5-17

Fast Interrupt Service Routine................................................................................................................5-17

Programming Guidelines........................................................................................................................5-17

S3F80P5_UM_REV1.00 MICROCONTROLLER v

Table of Contents(Continued)

Chapter 6 Instruction Set

Overview........................................................................................................................................................6-1

Data Types..............................................................................................................................................6-1

Register Addressing................................................................................................................................6-1

Addressing Modes..................................................................................................................................6-1

Flags Register (FLAGS) .........................................................................................................................6-6

Flag Descriptions....................................................................................................................................6-7

Instruction Set Notation...........................................................................................................................6-8

Condition Codes .....................................................................................................................................6-12

Instruction Descriptions ..........................................................................................................................6-13

Chapter 7 Clock and Power Circuit

Overview........................................................................................................................................................7-1

System Clock Circuit...............................................................................................................................7-1

Clock Status During Power-Down Modes ..............................................................................................7-3

System Clock Control Register (CLKCON)............................................................................................7-4

Chapter 8 RESET

Overview........................................................................................................................................................8-1

Reset Sources ........................................................................................................................................8-1

Reset Mechanism...................................................................................................................................8-4

Watch dog timer Reset ...........................................................................................................................8-4

LVD Reset...............................................................................................................................................8-4

Internal Power-On Reset ........................................................................................................................8-5

External Interrupt Reset..........................................................................................................................8-6

Stop Error Detection & Recovery............................................................................................................8-7

Power-Down Modes......................................................................................................................................8-8

Idle Mode ................................................................................................................................................8-8

IDLE Mode Release................................................................................................................................8-8

Back-up Mode.........................................................................................................................................8-9

Stop Mode...............................................................................................................................................8-11

Sources to Release Stop Mode..............................................................................................................8-12

Using IPOR to Release Stop Mode........................................................................................................8-12

Using an External Interrupt to Release Stop Mode................................................................................8-12

SED&R (Stop Error Detect and Recovery).............................................................................................8-13

System Reset Operation.........................................................................................................................8-14

Hardware Reset Values..........................................................................................................................8-15

Recommendation for Unusued Pins.......................................................................................................8-19

Summary Table of Back-up Mode, Stop Mode, and Reset Status.........................................................8-20

vi S3F80P5_UM_REV 1.00 MICROCONTROLLER

Table of Contents (Continued)

Part II

Hardware Descriptions

Chapter 9 I/O Ports

Overview .......................................................................................................................................................9-1

Port Data Registers................................................................................................................................9-3

Pull-Up Resistor Enable Registers.........................................................................................................9-4

Chapter 10 Basic timer and Timer 0

Overview .......................................................................................................................................................10-1

Basic Timer (BT).....................................................................................................................................101

Timer 0....................................................................................................................................................10-1

Basic Timer Control Register (BTCON) .................................................................................................10-2

Basic Timer Function Description...........................................................................................................10-3

Watch-dog Timer Function.....................................................................................................................10-3

Oscillation Stabilization Interval Timer Function ....................................................................................10-3

Timer 0 Control Register (T0CON).........................................................................................................10-4

Timer 0 Function Description .................................................................................................................10-6

Timer 0 Interrupts (IRQ0, Vectors FAH and FCH).................................................................................10-6

Interval Timer Mode................................................................................................................................10-6

Pulse Width Modulation Mode................................................................................................................10-7

Capture Mode.........................................................................................................................................10-8

Chapter 11 Timer 1

Overview .......................................................................................................................................................11-1

Timer 1 Overflow Interrupt ......................................................................................................................11-2

Timer 1 Capture Interrupt.......................................................................................................................11-2

Timer 1 Match Interrupt..........................................................................................................................11-3

Timer 1 Control Register (T1CON).........................................................................................................11-5

S3F80P5_UM_REV1.00 MICROCONTROLLER vii

Table of Contents (Continued)

Chapter 12 Counter A

Overview........................................................................................................................................................12-1

Counter A Control Register (CACON)....................................................................................................12-3

Counter A Pulse Width Calculations.......................................................................................................12-4

Chapter 13 Timer 2

Overview........................................................................................................................................................13-1

Timer 2 Overflow Interrupt......................................................................................................................13-2

Timer 2 Capture Interrupt .......................................................................................................................13-2

Timer 2 Match Interrupt...........................................................................................................................13-3

Timer 2 Control Register (T2CON).........................................................................................................13-5

Chapter 14 Embedded Flash Memory Interface

Overview........................................................................................................................................................14-1

Flash ROM Configuration.......................................................................................................................14-1

User Program Mode................................................................................................................................14-2

ISPTM (On-Board Programming) SECTOR..................................................................................................14-2

Smart Option...........................................................................................................................................14-3

ISP Reset Vector and ISP Sector Size...................................................................................................14-4

Flash Memory Control Registers (User Program Mode)...............................................................................14-5

Flash Memory Control Register (FMCOn)..............................................................................................14-5

Flash Memory User Programming Enable Register (FMUSR)...............................................................14-5

Flash Memory Sector Address Registers...............................................................................................14-6

Sector Erase..................................................................................................................................................14-7

The Sector Erase Procedure in User Program Mode.............................................................................14-8

Programming.................................................................................................................................................14-11

The Program Procedure in User Program Mode....................................................................................14-11

Reading.........................................................................................................................................................14-16

The Program Procedure in User Program Mode....................................................................................14-16

Hard Lock Protection.....................................................................................................................................14-17

The Program Procedure in User Program Mode....................................................................................14-17

viii S3F80P5_UM_REV 1.00 MICROCONTROLLER

Table of Contents (Conclude)

Chapter 15 Lower Voltage Detector

Overview .......................................................................................................................................................15-1

LVD.........................................................................................................................................................15-1

LVD FLAG ..............................................................................................................................................15-1

Low Voltage Detector Control Register (LVDCON) ...............................................................................15-4

Low Voltage Detector Flag Selection Register (LVDSEL) .....................................................................15-4

Chapter 16 Electrical Data

16.1 Overview...............................................................................................................................................16-1

Chapter 17 Mechanical

17.1 Overview...............................................................................................................................................17-1

Chapter 18 S3F80P5 Flash MCU

Overview .......................................................................................................................................................18-1

Operating Mode Characteristics.............................................................................................................18-4

Chapter 19 Development Tools

Overview .......................................................................................................................................................19-1

Target Boards...........................................................................................................................................19-1

Programming Socket Adapter ..................................................................................................................19-1

TB80PB Target Board ..............................................................................................................................19-3

Third Parties for Development Tools....................................................................................................19-7

In-Circuit Emulator for SAM8 Family....................................................................................................19-7

OTP/MTP Programmer ........................................................................................................................19-7

Development Tools Suppliers ..............................................................................................................19-7

8-bit In-Circuit Emulator........................................................................................................................19-7

OTP/MTP Programmer (Writer)................................................................................................................19-8

S3F80P5_UM_REV1.00 MICROCONTROLLER ix

List of Figures

Figure Title Page Number Number

1-1 Block Diagram (24-pin)..............................................................................................1-3

1-2 Pin Assignment Diagram (24-Pin SOP/SDIP Package) ............................................1-4

1-3 Pin Circuit Type 1 (Port 0)..........................................................................................1-6

1-4 Pin Circuit Type 2 (Port 1)..........................................................................................1-7

1-5 Pin Circuit Type 2 (Port 2)..........................................................................................1-8

1-6 Pin Circuit Type 4 (P3.0)............................................................................................1-9

1-7 Pin Circuit Type 5 (P3.1)............................................................................................1-10

2-1 Program Memory Address Space..............................................................................2-2

2-2 Smart Option ..............................................................................................................2-3

2-3 Internal Register File Organization.............................................................................2-6

2-4 Register Page Pointer (PP)........................................................................................2-7

2-5 Set 1, Set 2, and Prime Area Register Map...............................................................2-9

2-6 8-Byte Working Register Areas (Slices).....................................................................2-10

2-7 Contiguous 16-Byte Working Register Block.............................................................2-11

2-8 Non-Contiguous 16-Byte Working Register Block.....................................................2-12

2-9 16-Bit Register Pair....................................................................................................2-13

2-10 Register File Addressing............................................................................................2-14

2-11 Common Working Register Area ...............................................................................2-15

2-12 4-Bit Working Register Addressing............................................................................2-17

2-13 4-Bit Working Register Addressing Example.............................................................2-17

2-14 8-Bit Working Register Addressing............................................................................2-18

2-15 8-Bit Working Register Addressing Example.............................................................2-19

2-16 Stack Operations........................................................................................................2

3-1 Register Addressing...................................................................................................3-2

3-2 Working Register Addressing.....................................................................................3-2

3-3 Indirect Register Addressing to Register File.............................................................3-3

3-4 Indirect Register Addressing to Program Memory.....................................................3-4

3-5 Indirect Working Register Addressing to Register File ..............................................3-5

3-6 Indirect Working Register Addressing to Program or Data Memory..........................3-6

3-7 Indexed Addressing to Register File..........................................................................3-7

3-8 Indexed Addressing to Program or Data Memory with Short Offset..........................3-8

3-9 Indexed Addressing to Program or Data Memory......................................................3-9

3-10 Direct Addressing for Load Instructions.....................................................................3-10

3-11 Direct Addressing for Call and Jump Instructions......................................................3-11

3-12 Indirect Addressing.....................................................................................................3-12

3-13 Relative Addressing ...................................................................................................3-13

3-14 Immediate Addressing................................................................................................3-14

4-1 Register Description Format ......................................................................................4-5

-20

S3F80P5_UM_REV1.00 MICROCONTROLLER xi

List of Figures (Continued)

Figure Title Page Number Number

5-1 S3C8/S3F8-Series Interrupt Types ............................................................................5-2

5-2 S3F80P5 Interrupt Structure.......................................................................................5-3

5-3 ROM Vector Address Area.........................................................................................5-4

5-4 Interrupt Function Diagram.........................................................................................5-7

5-5 System Mode Register (SYM)....................................................................................5-9

5-6 Interrupt Mask Register (IMR)....................................................................................5-10

5-7 Interrupt Request Priority Groups...............................................................................5-11

5-8 Interrupt Priority Register (IPR)..................................................................................5-12

5-9 Interrupt Request Register (IRQ) ...............................................................................5-13

6-1 System Flags Register (FLAGS)................................................................................6-6

7-1 Main Oscillator Circuit (External Crystal or Ceramic Resonator) ............................7-2

7-2 External Clock Circuit .................................................................................................7-2

7-3 System Clock Circuit Diagram....................................................................................7-3

7-4 System Clock Control Register (CLKCON)................................................................7-4

7-5 Power Circuit (VDD) ...................................................................................................7-5

7-6 Guide Line of Chip Operating Voltage........................................................................7-5

8-1 RESET Sources of the S3F80P5 ...............................................................................8-2

8-2 RESET Block Diagram of the S3F80P5.....................................................................8-3

8-3 RESET Block Diagram by LVD for the S3F80P5 in Stop Mode.................................8-4

8-4 Timing Diagram for Internal Power-On Reset Circuit.................................................8-5

8-5 Reset Timing Diagram for the S3F80P5 in Stop Mode by IPOR ...............................8-6

8-6 Block Diagram for Back-up Mode...............................................................................8-9

8-7 Timing Diagram for Back-up Mode Input and Released by LVD ...............................8-9

8-8 Timing Diagram for Back-up Mode Input in Stop Mode.............................................8-10

9-1 S3F80P5 I/O Port Data Register Format....................................................................9-3

9-2 Pull-up Resistor Enable Registers (Port 0 and Port2)................................................9-4

10-1 Basic Timer Control Register (BTCON) .....................................................................10-2

10-2 Timer 0 Control Register (T0CON).............................................................................10-5

10-3 Timer 0 DATA Register (T0DATA).............................................................................10-5

10-4 Simplified Timer 0 Function Diagram: Interval Timer Mode.......................................10-6

10-5 Simplified Timer 0 Function Diagram: PWM Mode ....................................................10-7

10-6 Simplified Timer 0 Function Diagram: Capture Mode................................................10-8

10-7 Basic Timer and Timer 0 Block Diagram....................................................................10-9

11-1 Simplified Timer 1 Function Diagram: Capture Mode................................................11-2

11-2 Simplified Timer 1 Function Diagram: Interval Timer Mode.......................................11-3

11-3 Timer 1 Block Diagram...............................................................................................11-4

11-4 Timer 1 Control Register (T1CON).............................................................................11-5

11-5 Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL) .................................11-6

xii S3F80P5_UM_REV1.00 MICROCONTROLLER

List of Figures (Conclude)

Figure Title Page Number Number

12-1 Counter A Block Diagram...........................................................................................12-2

12-2 Counter A Control Register (CACON) .......................................................................12-3

12-3 Counter A Registers...................................................................................................12-3

12-4 Counter A Output Flip-Flop Waveforms in Repeat Mode ..........................................12-5

13-1 Simplified Timer 2 Function Diagram: Capture Mode................................................13-2

13-2 Simplified Timer 2 Function Diagram: Interval Timer Mode.......................................13-3

13-3 Timer 2 Block Diagram...............................................................................................13-4

13-4 Timer 2 Control Register (T2CON) ............................................................................13-5

13-5 Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL).................................13-6

14-1 Program Memory Address Space..............................................................................14-2

14-2 Smart Option ..............................................................................................................14-3

14-3 Flash Memory Control Register (FMCON).................................................................14-5

14-4 Flash Memory User Programming Enable Register (FMUSR)..................................14-5

14-5 Flash Memory Sector Address Register (FMSECH) .................................................14-6

14-6 Flash Memory Sector Address Register (FMSECL)..................................................14-6

14-7 Sector Configurations in User Program Mode...........................................................14-7

14-8 Sector Erase Flowchart in User Program Mode ........................................................14-8

14-9 Byte Program Flowchart in a User Program Mode....................................................14-12

14-10 Program Flowchart in a User Program Mode............................................................14-13

15-1 Low Voltage Detect (LVD) Block Diagram.................................................................15-3

15-2 Low Voltage Detect Control Register (LVDCON) ......................................................15-4

15-3 Low Voltage Detect Flag Selection Register (LVDSEL) ............................................15-4

16-1 Stop Mode Release Timing When Initiated by an External Interrupt.........................16-6

16-2 Stop Mode Release Timing When Initiated by a LVD................................................16-7

16-3 Input Timing for External Interrupts (Port 0 and Port 2).............................................16-8

16-4 Operating Voltage Range of S3F80P5.......................................................................16-11

17-1 24-Pin SOP Package Mechanical Data .....................................................................17-1

17-2 24-Pin SDIP Package Mechanical Data ....................................................................17-2

18-1 Pin Assignment Diagram (24-Pin SOP/SDIP Package) ............................................18-2

19-1 Development System Configuration...........................................................................19-2

19-2 TB80PB Target Board Configuration .........................................................................19-3

19-3 50-Pin Connector Pin Assignment for User System..................................................19-6

19-4 TB80PB Probe Adapter Cable...................................................................................19-6

S3F80P5_UM_REV1.00 MICROCONTROLLER xiii

List of Tables

Table Title Page Number Number

1-1 Pin Descriptions of 24-SOP/SDIP..............................................................................1-5

2-1 The Summary of S3F80P5 Register Type.................................................................2-5

4-1 Mapped Registers (Bank0, Set1)...............................................................................4-2

4-1 Mapped Registers (Continued)..................................................................................4-3

4-2 Mapped Registers (Bank1, Set1)...............................................................................4-4

4-3 Each Function Description and Pin Assignment of P3CON in 24 Pin Package........4-33

5-1 S3F80P5 Interrupt Vectors.........................................................................................5-5

5-2 Interrupt Control Register Overview...........................................................................5-6

5-3 Vectored Interrupt Source Control and Data Registers .............................................5-8

6-1 Instruction Group Summary.......................................................................................6-2

6-2 Flag Notation Conventions.........................................................................................6-8

6-3 Instruction Set Symbols..............................................................................................6-8

6-4 Instruction Notation Conventions...............................................................................6-9

6-5 Opcode Quick Reference...........................................................................................6-10

6-6 Condition Codes.........................................................................................................6-12

7-1 Falling and Rising Time of Operating Voltage ...........................................................7-5

8-1 Reset Condition in Stop Mode ...................................................................................8-7

8-2 Set 1, Bank 0 Register Values After Reset................................................................8-15

8-3 Set 1, Bank 1 Register Values After Reset................................................................8-17

8-4 Reset Generation According to the Condition of Smart Option.................................8-18

8-5 Guideline for Unused Pins to Reduced Power Consumption....................................8-19

8-6 Summary of Each Mode.............................................................................................8-20

9-1 S3F80P5 Port Configuration Overview (24-SOP)......................................................9-2

9-2 Port Data Register Summary .....................................................................................9-3

14-1 ISP Sector Size ..........................................................................................................14-4

14-2 Reset Vector Address ................................................................................................14-4

16-1 Absolute Maximum Ratings .......................................................................................16-2

16-2 D.C. Electrical Characteristics....................................................................................16-2

16-3 Characteristics of Low Voltage Detect Circuit............................................................16-4

16-4 Power On Reset Circuit..............................................................................................16-5

16-5 Data Retention Supply Voltage in Stop Mode............................................................16-5

16-6 Input/Output Capacitance ..........................................................................................16-7

16-7 A.C. Electrical Characteristics....................................................................................16-7

16-8 Oscillation Characteristics..........................................................................................16-9

16-9 Oscillation Stabilization Time.....................................................................................16-10

16-10 AC Electrical Characteristics for Internal Flash ROM................................................16-11

16-11 ESD Characteristics...................................................................................................16-12

S3F80P5_UM_REV1.00 MICROCONTROLLER xv

List of Tables(Conclude)

Table Title Page Number Number

18-1 Descriptions of Pins Used to Read/Write the Flash ROM..........................................18-3

18-2 Operating Mode Selection Criteria .............................................................................18-4

19-1 Components of TB80PB.............................................................................................19-4

19-2 Setting of the Jumper in TB80PB...............................................................................19-5

xvi S3F80P5_UM_REV1.00 MICROCONTROLLER

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8/S3F8-SERIES MICROCONTROLLERS

Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include:

• Efficient register-oriented architecture

• Selectable CPU clock sources

• Idle and Stop power-down mode release by interrupts

• Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum four CPU clocks) can be assigned to specific interrupt levels.

S3F80P5 MICROCONTROLLER

The S3F80P5 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture.

The S3F80P5 is the microcontroller which has 18-Kbyte Flash Memory ROM. Using a proven modular design approach, Samsung engineers developed S3F80P5 by integrating the following

peripheral modules with the powerful SAM8 RC core:

• Internal LVD circuit and 9 bit-programmable pins for external interrupts.

• One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).

• One 8-bit Timer/counter with three operating modes.

• Two 16-bit timer/counters with selectable operating modes.

• One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3F80P5 is a versatile general-purpose microcontroller, which is especially suitable for use as remote transmitter controller. It is currently available in a 24-pin SOP/SDIP package.

1-1

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00

FEATURES

CPU

• SAM8 RC CPU core

Memory

• Program memory:

- 18-Kbyte Internal Flash Memory

- 10 years data retention

- Endurance: 10,000 Erase/Program cycles

- Byte Programmable

- User programmable by ‘LDC’ instruction

• Executable memory: 1K-byte RAM

• Data memory: 272-byte general purpose RAM

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for power-

down modes

Instruction Execution Time

• 500 ns at 8-MHz f

Interrupts

• 17 interrupt sources with 14 vectors

and 7 levels.

(minimum)

OSC

Back-up Mode

• When V

is lower than V

LVD is ‘ON’ and the

LVD,

chip enters Back-up mode to block oscillation

Low Voltage Detect Circuit

• Low voltage detect to get into Back-up mode and

Reset

1.65V (Typ) ± 50mV

• Low voltage detect to control LVD_Flag bit

1.88, 1.98, 2.53, 2.73V (Typ) ± 100mV (selectable)

• LVD-Reset is enabled in the operating mode:

When the voltage at VDD is falling down and passing V

, the chip goes into back-up mode.

LVD

The voltage at VDD is rising up, the reset pulse is generated at “VDD> V

• LVD is disabled in the stop mode: If the voltage at

VDD is not falling down to V

LVD

”.

, the reset pulse is

POR

not generated.

Operating Temperature Range

• -25

C to + 85 °C

I/O Ports

• Two 8-bit I/O ports (P0, P1), one 1-bit (P2) and

2-bit (P3) for a total of 19 bit-programmable pins (24-SOP, 24-SDIP)

Carrier Frequency Generator

• One 8-bit counter with auto-reload function and

one-shot or repeat control (Counter A)

Basic Timer and Timer/Counters

• One programmable 8-bit basic timer (BT) for

oscillation stabilization control or watchdog timer (software reset) function

• One 8-bit timer/counter (Timer 0) with three

operating modes: Interval mode, Capture and PWM mode.

• One 16-bit timer/counter (Timer1) with two

operating modes: Interval and Capture mode.

• One 16-bit timer/counter (Timer2) with two

operating modes: Interval and Capture mode.

Operating Voltage Range

• 1.60V to 3.6V at 1~8MHz

Package Types

• 24-pin SOP

• 24-pin SDIP

1-2

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW

BLOCK DIAGRAM (24-PIN PACKAGE)

Figure 1-1. Block Diagram (24-pin)

1-3

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00

PIN ASSIGNMENTS

Vss

Xin

Xout

TEST SDAT/P0.0/INT0 SCLK/P0.1/INT1

nRESET/P0.2/INT2

P0.3/INT3 P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4

10 11 12

1 2 3 4 5 6 7 8 9

S3C80P5

24-SOP/SDIP

(TOP VIEW)

24 23 22 21 20 19 18 17 16 15 14 13

VDD P2.0/INT5 P3.1/REM/T0CK P3.0/T0PWM/T0CAP/T1CAP/T2CAP P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package)

1-4

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW

Table 1-1. Pin Descriptions of 24-SOP/SDIP

Names

P0.0−P0.7

P1.0−P1.7

P2.0

P3.0

P3.1

OUT, XIN

TEST

Type

I/O I/O port

Pin Description

with bit-programmable pins. Configurable

Circuit

Type

1 5-12 Ext. INT to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED&R (note) circuit built in P0 for STOP releasing. In the tool mode, P0.0 and P0.1 are assigned as serial MTP interface pins; SDAT and SCLK

I/O I/O port with bit-programmable pins. Configurable

to input mode or output mode. Pin circuits are

2 either push-pull or n-channel open-drain type.

I/O I/O port with bit-programmable pin. Configurable to

input mode, push-pull output mode, or n-channel

3 open-drain output mode. Pull-up resistor can be

assigned by software. Pin can be assigned as external interrupt input with noise filter, interrupt enable/disable, and interrupt pending control.

I/O I/O port with bit-programmable pin. Configurable to

4 26 T0PWM/T0CAP/ input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with a pull-up resistor can be assigned by software. This port 3 pin has high current drive capability. Also P3.0 can be assigned individually as an output pin for T0PWM or input pin for T0CAP/T1CAP/T2CAP.

I/O I/O port with bit-programmable pin. Configurable to

5 27 REM/T0CK input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with a pull-up resistor can be assigned by software. This port 3 pin has high current drive capability. Also P3.1 can be assigned individually as an output pin for REM or input pin for T0CK.

– System clock input and output pins – 2,3

I Test signal input pin

−

If on board programming is needed, It is recommended that add a 0.1uF capacitor between TEST pin and VSS for better noise immunity; otherwise, connect TEST pin to VSS directly.

Power supply input pin

−

Ground pin

−

28 Pin

No.

Shared

Functions

(INT0−INT3)

(INT4)

(SDAT) (SCLK)

13-20

23 Ext. INT

(INT5)

T1CAP/T2CAP

−

1-5

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00

PIN CIRCUITS

Pull-Up Resistor (67k

Pull-up Enable

Data

Output Disable

- typ)

INPUT/OUTPUT

External

Interrupt

Stop

Noise

Filter

Figure 1-3. Pin Circuit Type 1 (Port 0)

Stop Release

1-6

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW

PIN CIRCUITS (Continued)

Pull-up Resistor

-Typ)

(67k Pull-up Enable

Data

INPUT/OU TPUT

Open-Drain

Output Disable

Normal

Input

Noise

Filter

Figure 1-4. Pin Circuit Type 2 (Port 1)

1-7

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00

PIN CIRCUITS (Continued)

VDD

Pull-Up Resistor

Pull-up Enable

VDD

Data

Open-Drain

Output Disable

(67kΩ- typ)

INPUT/

OUTPUT

External Interrupt

VSS

Noise

Filter

Figure 1-5. Pin Circuit Type 2 (Port 2)

1-8

S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW

PIN CIRCUITS (Continued)

VDD

Pull-up Resistor

Pull-up Enable

P3CON.2

VDD

(67kΩ-Typ)

Output Disable

Port 3.0 Data

T0_PWM

Open-Drain

P3.0 Input

T0CAP/T1CAP/T2CAP

M U

P3CON.2,6,7

M U

Data

Noise filter

Figure 1-6. Pin Circuit Type 4 (P3.0)

P3.0/T0PWM/T0CAP/ T1CAP/T2C AP

VSS

1-9

PRODUCT OVERVIEW S3F80P5_UM_ REV1.00

PIN CIRCUITS (Continued)

VDD

Pull-up Resistor

Pull-up Enable

P3CON.5

VDD

(67kΩ-Typ)

Port 3.1 Data

Carrier On/Off (P3DAT.7)

CACON.2

Open-Drain

Output

Disable

P3.1 Input

T0CK

M U

P3CON.5,6,7

M U

Data

P3.1/REM/T0CK

VSS

Noise filter

Figure 1-7. Pin Circuit Type 5 (P3.1)

1-10

S3F80P5_UM_ REV1.00 ADDRESS SPACE

2 ADDRESS SPACE

OVERVIEW

The S3F80P5 microcontroller has two types of address space: — Internal program memory (Flash memory)

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.

The S3F80P5 has a programmable internal 18-Kbytes Flash ROM. An external memory interface is not implemented.

There are 333 mapped registers in the internal register file. Of these, 272-byte are for general-purpose use. (This number includes a 16-byte working register common area that is used as a “scratch area” for data operations, a 192-byte prime register area, and a 64-byte area (Set 2) that is also used for stack operations). Twenty-two 8-bit registers are used for CPU and system control and 39 registers are mapped peripheral control and data registers.

2-1

ADDRESS SPACE S3F80P5_UM_ REV1.00

PROGRAM MEMORY

Program memory stores program code or table data. The S3F80P5 has 18-Kbyte of internal programmable Flash memory. The program memory address range is therefore 0000H–47FFH of Flash memory (See Figure 2-1).

The first 256 bytes of the program memory (0H–0FFH) are reserved for interrupt vector addresses. Unused locations (0000H – 00FFH except 03CH, 03DH, 03EH and 03FH) in this address range can be used as normal program memory. The location 03CH, 03DH, 03EH and 03FH is used as smart option ROM cell. If you use the vector address area to store program code, be careful to avoid overwriting vector addresses stored in these locations.

The program memory address at which program execution starts after reset is 0100H(default). If you use ISP sectors as the ISP

software storage, the reset vector address can be changed by setting the Smart Option.

(Refer to Figure 2-2).

(Decimal) (HEX)

65,536

1Kbyte

Internal RAM

FFFFH

FC00H

16,383

Internal Program Memory

(Flash)

Note 1

ISP Sector

255

Interrupt Vector Area

Smart Option Rom Cell

000H

47FFH

S3F80P5(18Kbyte)

01FFH, 02FFH, 04FFH or 08FFH 0FFH

03FH 03CH

Figure 2-1. Program Memory Address Space

NOTES:

1. The size of ISP related to the ISP, ISP reset vector address can be changed one of addresses to be select (200H, 300H, 500H or 900H).

2. ISP

sector can store On Board Program Software (Refer to chapter 13. Embedded Flash Memory Interface).

sector can be varied by Smart Option. (Refer to Figure 2-2). According to the smart option setting

2-2

S3F80P5_UM_ REV1.00 ADDRESS SPACE

SMART OPTION

Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80P5 only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is 0FFH (Normal reset vector address 100H, ISP protection disable). Before execution the program memory code, user can set the smart option bits according to the hardware option for user to want to select.

ROM Address: 003CH

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

Not used

ROM Address: 003DH

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

Not used

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

ISP Reset Vector Change Selection Bit: 0 = OBP Reset vector address 1 = Normal vector (address 100H)

ISP Reset Vector Address Selection Bits: 00 = 200H (ISP Area size: 256 bytes) 01 = 300H (ISP Area size: 512 bytes) 10 = 500H (ISP Area size: 1024 bytes) 11 = 900H (ISP Area size: 2048 bytes)

.7 .6 .5 .4 .3 .2 .1 .0MSB LSB

ROM Address: 003EH

(1)

Not used

ISP Protection Size Selection Bits:

(4)

00 = 256 bytes 01 = 512 bytes

(2)

10 = 1024 bytes 11 = 2048 bytes

ISP Protection Enable/Disable Bit:

(3)

0 = Enable (Not erasable) 1 = Disable (Erasable)

ROM Address: 003FH

Not used

RESET Control Bit

(5)

0 = External interrupts by P0 and P2 or SED&R generate the reset signal 1 = External interrupts by P0 and P2 or SED&R do not generate the reset signal

Figure 2-2. Smart Option

2-3

ADDRESS SPACE S3F80P5_UM_ REV1.00

NOTES

1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless.

2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H). If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes). If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can be assigned from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be assigned from 0100H to 08FFH (2048bytes).

3. If ISP Protection Enable/Disable Bit is ‘0’, user can’t erase or program the ISP area selected by 3EH.1 and 3EH.0 in flash memory.

4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP Protection Enable/Disable Bit

(3EH.2) is ‘1’, 3EH.1 and 3EH.0 are meaningless.

5. External interrupts can be used to release stop mode. When RESET Control Bit (3FH.0) is ‘0’ and

external interrupts is enabled, external interrupts wake MCU from stop mode and generate reset signal. Any falling edge input signals of P0 can wake MCU from stop mode and generate reset signal. When RESET Control Bit (3FH.0) is ‘1’, S3F80P5 is only released stop mode and is not generated reset signal.

2-4

+ 291 hidden pages