The information in this publication has been carefully
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
personal injury or death may occur.
Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all
claims, costs, damages, expenses, and reasonable
attorney fees arising out of, either directly or
indirectly, any claim of personal injury or death that
may be associated with such unintended or
unauthorized use, even if such claim alleges that
Samsung was negligent regarding the design or
manufacture of said product.
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are
designed and manufactured in accordance with the highest quality standards and
objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 446-711
TEL: (82)-(31)-209-3865
FAX: (82)-(31)-209-6494
Home Page: http://www.samsungsemi.com
Printed in the Republic of Korea
Preface
The S3F80P5 Microcontroller User's Manual is designed for application designers and programmers who are
using the S3F80P5 microcontroller for application development. It is organized in two main parts:
Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming
model, and address spaces. It has three chapters:
Chapter 1 Product Overview
Chapter 2 Address Spaces
Chapter 1, "Product Overview," is a high-level introduction to S3F80P5 with general product descriptions, as well
as detailed information about individual pin characteristics and pin circuit types.
Chapter 2, “Address Spaces,” describes the important feature of the S3F80P5 programming environment.
Chapter 3, "Addressing Modes," describes program and data memory spaces, the internal register file, and
register addressing.
Chapter 4, “Control Registers,” describes the definition, usages and supported APIs for Flash operations.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3FS-series microcontroller family and are reading this manual for the
first time, we recommend that you first read Chapters 1-3 carefully. Then, you can reference the information in
Part II as necessary.
Part II "hardware Descriptions," has detailed information about specific hardware components of the S3F80P5
microcontroller. Also included in Part II is electrical data. It has 15 chapters:
Chapter 5 Interrupt Structure
Chapter 6 Instruction Set
Chapter 7 Clock and Power Circuits
Chapter 8 Reset
Chapter 9 I/O Ports
Chapter 10 Basic Timer and Timer 0
Chapter 11 Timer 1
Chapter 12 Counter A
Two order forms are included at the back of this manual to facilitate customer order for S3F80P5 microcontroller:
the Mask ROM Order Form, and the Mask Option Selection Form.
You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales
Representative.
Chapter 3 Addressing Modes
Chapter 4 Control Registers
Chapter 13 Timer 2
Chapter 14 Embedded Flash Memory Interface
Chapter 15 Low Voltage Detector
Chapter 16 Electrical Data
Chapter 17 Mechanical Data
Chapter 18 S3F80P5 Flash MCU
Chapter 19 Development Tools
Features ........................................................................................................................................................1-2
Program Memory...........................................................................................................................................2-2
Register Set 1.........................................................................................................................................2-8
Register Set 2.........................................................................................................................................2-8
Prime Register Space.............................................................................................................................2-9
Working Registers...................................................................................................................................2-10
Using the Register Pointers....................................................................................................................2-11
Common Working Register Area (C0H–CFH)........................................................................................2-15
Example 1:..............................................................................................................................................2-16
Example 2:..............................................................................................................................................2-16
4-Bit Working Register Addressing.........................................................................................................2-16
8-Bit Working Register Addressing.........................................................................................................2-18
System and User Stacks...............................................................................................................................2-20
Data Types..............................................................................................................................................6-1
Flag Descriptions....................................................................................................................................6-7
Instruction Set Notation...........................................................................................................................6-8
The Program Procedure in User Program Mode....................................................................................14-16
Hard Lock Protection.....................................................................................................................................14-17
The Program Procedure in User Program Mode....................................................................................14-17
LVD FLAG ..............................................................................................................................................15-1
Low Voltage Detector Control Register (LVDCON) ...............................................................................15-4
Low Voltage Detector Flag Selection Register (LVDSEL) .....................................................................15-4
19-1 Components of TB80PB.............................................................................................19-4
19-2 Setting of the Jumper in TB80PB...............................................................................19-5
xvi S3F80P5_UM_REV1.00 MICROCONTROLLER
S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
S3C8/S3F8-SERIES MICROCONTROLLERS
Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include:
• Efficient register-oriented architecture
• Selectable CPU clock sources
• Idle and Stop power-down mode release by interrupts
• Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum four CPU clocks) can be assigned to
specific interrupt levels.
S3F80P5 MICROCONTROLLER
The S3F80P5 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is
based on Samsung's newest CPU architecture.
The S3F80P5 is the microcontroller which has 18-Kbyte Flash Memory ROM.
Using a proven modular design approach, Samsung engineers developed S3F80P5 by integrating the following
peripheral modules with the powerful SAM8 RC core:
• Internal LVD circuit and 9 bit-programmable pins for external interrupts.
• One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).
• One 8-bit Timer/counter with three operating modes.
• Two 16-bit timer/counters with selectable operating modes.
• One 8-bit counter with auto-reload function and one-shot or repeat control.
The S3F80P5 is a versatile general-purpose microcontroller, which is especially suitable for use as remote
transmitter controller. It is currently available in a 24-pin SOP/SDIP package.
1 5-12 Ext. INT
to input or push-pull output mode. Pull-up resistors
are assignable by software. Pins can be assigned
individually as external interrupt inputs with noise
filters, interrupt enable/ disable, and interrupt
pending control. SED&R (note) circuit built in P0
for STOP releasing.
In the tool mode, P0.0 and P0.1 are assigned as
serial MTP interface pins; SDAT and SCLK
I/O I/O port with bit-programmable pins. Configurable
to input mode or output mode. Pin circuits are
2
either push-pull or n-channel open-drain type.
I/O I/O port with bit-programmable pin. Configurable to
input mode, push-pull output mode, or n-channel
3
open-drain output mode. Pull-up resistor can be
assigned by software. Pin can be assigned as
external interrupt input with noise filter, interrupt
enable/disable, and interrupt pending control.
I/O I/O port with bit-programmable pin. Configurable to
4 26 T0PWM/T0CAP/
input mode, push-pull output mode, or n-channel
open-drain output mode. Input mode with a pull-up
resistor can be assigned by software.
This port 3 pin has high current drive capability.
Also P3.0 can be assigned individually as an
output pin for T0PWM or input pin for
T0CAP/T1CAP/T2CAP.
I/O I/O port with bit-programmable pin. Configurable to
5 27 REM/T0CK
input mode, push-pull output mode, or n-channel
open-drain output mode. Input mode with a pull-up
resistor can be assigned by software.
This port 3 pin has high current drive capability.
Also P3.1 can be assigned individually as an
output pin for REM or input pin for T0CK.
– System clock input and output pins – 2,3
I Test signal input pin
−
If on board programming is needed, It is
recommended that add a 0.1uF capacitor between
TEST pin and VSS for better noise immunity;
otherwise, connect TEST pin to VSS directly.
Power supply input pin
−
−
Ground pin
−
−
28 Pin
No.
Shared
Functions
(INT0−INT3)
(INT4)
(SDAT)
(SCLK)
13-20
23 Ext. INT
(INT5)
T1CAP/T2CAP
4
28
1
−
−
−
−
−
1-5
PRODUCT OVERVIEW S3F80P5_UM_ REV1.00
PIN CIRCUITS
V
DD
Pull-Up
Resistor
(67k
Ω
Pull-up
Enable
Data
Output Disable
V
DD
- typ)
INPUT/OUTPUT
External
Interrupt
Stop
V
SS
Noise
Filter
Figure 1-3. Pin Circuit Type 1 (Port 0)
Stop
Release
1-6
S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW
PIN CIRCUITS (Continued)
V
DD
Pull-up
Resistor
Ω
-Typ)
(67k
Pull-up
Enable
V
DD
Data
INPUT/OU TPUT
Open-Drain
Output Disable
V
SS
Normal
Input
Noise
Filter
Figure 1-4. Pin Circuit Type 2 (Port 1)
1-7
PRODUCT OVERVIEW S3F80P5_UM_ REV1.00
PIN CIRCUITS (Continued)
VDD
Pull-Up
Resistor
Pull-up
Enable
VDD
Data
Open-Drain
Output Disable
(67kΩ- typ)
INPUT/
OUTPUT
External
Interrupt
VSS
Noise
Filter
Figure 1-5. Pin Circuit Type 2 (Port 2)
1-8
S3F80P5_UM_ REV1.00 PRODUCT OVERVIEW
PIN CIRCUITS (Continued)
VDD
Pull-up
Resistor
Pull-up
Enable
P3CON.2
VDD
(67kΩ-Typ)
Output Disable
Port 3.0 Data
T0_PWM
Open-Drain
P3.0 Input
T0CAP/T1CAP/T2CAP
M
U
X
P3CON.2,6,7
M
U
X
Data
Noise filter
Figure 1-6. Pin Circuit Type 4 (P3.0)
P3.0/T0PWM/T0CAP/
T1CAP/T2C AP
VSS
1-9
PRODUCT OVERVIEW S3F80P5_UM_ REV1.00
PIN CIRCUITS (Continued)
VDD
Pull-up
Resistor
Pull-up
Enable
P3CON.5
VDD
(67kΩ-Typ)
Port 3.1 Data
Carrier On/Off (P3DAT.7)
CACON.2
Open-Drain
Output
Disable
P3.1 Input
T0CK
M
U
X
P3CON.5,6,7
M
U
X
Data
P3.1/REM/T0CK
VSS
Noise filter
Figure 1-7. Pin Circuit Type 5 (P3.1)
1-10
S3F80P5_UM_ REV1.00 ADDRESS SPACE
2 ADDRESS SPACE
OVERVIEW
The S3F80P5 microcontroller has two types of address space:
— Internal program memory (Flash memory)
— Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The S3F80P5 has a programmable internal 18-Kbytes Flash ROM. An external memory interface is not
implemented.
There are 333 mapped registers in the internal register file. Of these, 272-byte are for general-purpose use. (This
number includes a 16-byte working register common area that is used as a “scratch area” for data operations, a
192-byte prime register area, and a 64-byte area (Set 2) that is also used for stack operations). Twenty-two 8-bit
registers are used for CPU and system control and 39 registers are mapped peripheral control and data registers.
2-1
ADDRESS SPACE S3F80P5_UM_ REV1.00
PROGRAM MEMORY
Program memory stores program code or table data. The S3F80P5 has 18-Kbyte of internal programmable Flash
memory. The program memory address range is therefore 0000H–47FFH of Flash memory (See Figure 2-1).
The first 256 bytes of the program memory (0H–0FFH) are reserved for interrupt vector addresses. Unused
locations (0000H – 00FFH except 03CH, 03DH, 03EH and 03FH) in this address range can be used as normal
program memory. The location 03CH, 03DH, 03EH and 03FH is used as smart option ROM cell. If you use the
vector address area to store program code, be careful to avoid overwriting vector addresses stored in these
locations.
The program memory address at which program execution starts after reset is 0100H(default). If you use ISP
sectors as the ISP
TM
software storage, the reset vector address can be changed by setting the Smart Option.
(Refer to Figure 2-2).
(Decimal)(HEX)
65,536
1Kbyte
Internal RAM
FFFFH
TM
FC00H
16,383
Internal
Program
Memory
(Flash)
Note 1
ISP Sector
255
Interrupt Vector Area
Smart Option Rom Cell
000H
47FFH
S3F80P5(18Kbyte)
01FFH, 02FFH, 04FFH or 08FFH
0FFH
03FH
03CH
Figure 2-1. Program Memory Address Space
NOTES:
1. The size of ISP
related to the ISP, ISP reset vector address can be changed one of addresses to be select (200H, 300H, 500H or
900H).
2. ISP
TM
sector can store On Board Program Software (Refer to chapter 13. Embedded Flash Memory Interface).
TM
sector can be varied by Smart Option. (Refer to Figure 2-2). According to the smart option setting
2-2
S3F80P5_UM_ REV1.00 ADDRESS SPACE
SMART OPTION
Smart option is the program memory option for starting condition of the chip. The program memory addresses
used by smart option are from 003CH to 003FH. The S3F80P5 only use 003EH and 003FH. User can write any
value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory
is 0FFH (Normal reset vector address 100H, ISP protection disable). Before execution the program memory
code, user can set the smart option bits according to the hardware option for user to want to select.
ISP Reset Vector Address Selection Bits:
00 = 200H (ISP Area size: 256 bytes)
01 = 300H (ISP Area size: 512 bytes)
10 = 500H (ISP Area size: 1024 bytes)
11 = 900H (ISP Area size: 2048 bytes)
.7.6.5.4.3.2.1.0MSBLSB
ROM Address: 003EH
(1)
Not used
ISP Protection Size
Selection Bits:
(4)
00 = 256 bytes
01 = 512 bytes
(2)
10 = 1024 bytes
11 = 2048 bytes
ISP Protection Enable/Disable Bit:
(3)
0 = Enable (Not erasable)
1 = Disable (Erasable)
ROM Address: 003FH
Not used
RESET Control Bit
(5)
0 = External interrupts by P0 and P2 or
SED&R generate the reset signal
1 = External interrupts by P0 and P2 or
SED&R do not generate the reset signal
Figure 2-2. Smart Option
2-3
ADDRESS SPACE S3F80P5_UM_ REV1.00
NOTES
1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP
area.
If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless.
2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address
from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or
0900H).
If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes).
If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can
be assigned from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be assigned from 0100H
to 08FFH (2048bytes).
3. If ISP Protection Enable/Disable Bit is ‘0’, user can’t erase or program the ISP area selected by
3EH.1 and 3EH.0 in flash memory.
4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP Protection Enable/Disable Bit
(3EH.2) is ‘1’, 3EH.1 and 3EH.0 are meaningless.
5. External interrupts can be used to release stop mode. When RESET Control Bit (3FH.0) is ‘0’ and
external interrupts is enabled, external interrupts wake MCU from stop mode and generate reset
signal. Any falling edge input signals of P0 can wake MCU from stop mode and
generate reset signal.
When RESET Control Bit (3FH.0) is ‘1’, S3F80P5 is only released stop mode and is not generated
reset signal.
2-4
Loading...
+ 291 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.