Samsung S3F80JB User Manual

S3F80JB

8-BIT CMOS

MICROCONTROLLERS

USER'S MANUAL

Revision 1.1

Important Notice

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any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.

S3F80JB 8-Bit CMOS Microcontrollers
User's Manual, Revision 1.1
Publication Number: 21.1-S3F-80JB-032006

"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.

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Printed in the Republic of Korea

Preface

The S3F80JB Microcontroller User's Manual is designed for application designers and programmers who are
using

S3F80JB microcontroller for application development. It is organized in two main parts:

Part I Programming Model
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming

model, instruction set, and interrupt structure. It has six chapters:
Chapter 1 Product Overview

Chapter 2 Address Spaces
Chapter 3 Addressing Modes

Chapter 1, "Product Overview," is a high-level introduction to
as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack
operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
S3C8-series CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.

Part II Hardware Descriptions

Chapter 4 Control Registers
Chapter 5 Interrupt Structure
Chapter 6 Instruction Set

S3F80JB with general product descriptions, as well

Chapter 5, "Interrupt Structure," describes the
additional information presented in the individual hardware module descriptions in Part II.

Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3F8-series
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of
each instruction are presented in a standard format. Each instruction description includes one or more practical
examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3F8-series microcontroller family and are reading this manual for the
first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information
in Chapters 4, 5, an d 6. La t er , y ou c a n reference the in f o rm ation in Part I as nece s sary.

Part II "hardware Descriptions," has detailed information about specific hardware components of the
microcontroller. Also included in Part II are electrical, mechanical, MTP, and development tools data. It has 14
chapters:

Chapter 7 Clock Circuits
Chapter 8 RESET
Chapter 9 I/O Ports
Chapter 10 Basic Timer and Timer 0
Chapter 11 Timer 1
Chapter 12 Counter A
Chapter 13 Timer 2
Chapter 14 Comparator

Two order forms are included at the back of this manual to facilitate customer order for
the Flash Factor Writing Order Form. You can photocopy these forms, fill them out, and then forward them to your
local Samsung Sales Representative.

S3F80JB interrupt structure in detail and further prepares you for

S3F80JB

Chapter 15 Embedded Flash Memory Interface
Chapter 16 Low Voltage Detector
Chapter 17 Electrical Data-4MHz
Chapter 18 Electrical Data-8MHz
Chapter 19 Mechanical Data
Chapter 20

Development Tools Data

S3F80JB microcontrollers:

S3F80JB MICROCONTROLLER iii

Table of Contents

Part I — Programming Model

Chapter 1 Product Overview

S3C8/S3F8-Series Microcontrollers ... ........................................................................................................1-1

S3F80JB Microcontroller........... ......... .... ..... .... .......... .... ..... .... ......... ..... ..... .... ......... ..... .... ..... ......................1-1

Features................................................................................................................................................. ....1-2

Block Diagram (32-pin package)................................................................... .............................................1-3

Block Diagram (44-pin package)................................................................... .............................................1-4

Pin Assignments.........................................................................................................................................1-5

Pin Circuits.................................................................................................................................................1-10

Chapter 2 Address Spaces

Overview................................................................................................................ ....................................2-1

Program Memory........................................................... ..... .... ......... ..... ..... .... ......... ..... .... .............. .............2-2

Register Architecture....... ..... ......... ..... .... ..... ......... ..... .... ..... ......... .... ..... ..... ......... .... ..... .... ....................... ....2-5

Register Page Pointer (PP)................................................................................................................2-7

Register Set1.....................................................................................................................................2-8

Register Set 2....................................................................................................................................2-8

Prime Register Space........................................................................................................................2-9

Working Registers..............................................................................................................................2-10

Using the Register Pointers...............................................................................................................2-11

Register Addressing........................... .... ......... ..... .... ..... ......... ..... .... ..... ......... ..... .... ..... ...............................2-13

Common Working Register Area (C0H–CFH)....................................................................................2-15

4-Bit Working Register Addressing....................................................................................................2-16

8-Bit Working Register Addressing....................................................................................................2-18

System and User Stacks............................................................................................................................2-20

Chapter 3 Addressing Modes

Overview................................................................................................................ ....................................3-1

Register Addressing Mode (R)..................................................................................... ......................3-2

Indirect Register Addressing Mode (IR).............................................................................................3-3

Indexed Addressing Mode (X)............................................................................................................3-7

Direct Address Mode (DA).................................................................................................................3-10

Indirect Address Mode (IA)................................................................................................................3-12

Relative Address Mode (RA)..............................................................................................................3-13

Immediate Mode (IM).......................... ..... ........ ..... ..... .... ......... ..... .... ..... ......... ..... .... ......... ..................3-14

Chapter 4 Control Registers

Overview................................................................................................................ ....................................4-1

S3F80JB MICROCONTROLLER v

Table of Contents (Continued)

Chapter 5 Interrupt Structure

Overview ....................................................................................................................................................5-1

Interrupt Types.......................................................................................... .........................................5-2

Interrupt Vector Addresses.................................................................................................................5-5

Enable/Disable Interrupt Instructions (EI, DI).....................................................................................5-7

System-Level Interrupt Control Registers...........................................................................................5-7

Interrupt Processing Control Points....................................................................................................5-8

Peripheral Interrupt Control Registers ..... ......... ..... .... ..... .... ......... ..... ..... .... ..... .... ......... ..... .... ..... .........5-9

System Mode Register (SYM).......................................................................................... ..................5-10

Interrupt Mask Register (IMR)................................... .........................................................................5-11

Interrupt Priority Register (IPR)..........................................................................................................5-12

Interrupt Request Register (IRQ).......................................................................................................5-14

Interrupt Pending Function Types......................................................................................................5-15

Interrupt Source Polling Sequence.....................................................................................................5-16

Interrupt Service Routines....................................................................................... ...........................5-16

Generating interrupt Vector Addresses..............................................................................................5-17

Nesting of Vectored Interrupts............................................................................................................5-17

Instruction Pointer (IP) ....................... ................................................................................................5-17

Fast Interrupt Processing................................................................. ..................................................5-17

Chapter 6 Instruction Set

Overview ....................................................................................................................................................6-1

Flags Register (FLAGS)........ ...................................................... ....................................................... 6-6

Flag Descriptions...............................................................................................................................6-7

Instruction Set Notation......................................................................................................................6-8

Condition Codes.................................................................................................................................6-12

Instruction Descriptions........................................................... ...........................................................6-13

Chapter 7 Clock Circuit

Overview ....................................................................................................................................................7-1

System Clock Circuit..........................................................................................................................7-1

Clock Status During Power-Down Modes ..........................................................................................7-2

System Clock Control Register (CLKCON)........................................................ ..... ......... .... ..... .... .....7-3

vi S3F80JB MICROCONTROLLER

Table of Contents (Continued)

Chapter 8 RESET

Overview................................................................................................................ ....................................8-1

Reset Sources...................................................................................................................................8-1

Reset Mechanism... ....................................................... ....................................................................8-4

External Reset Pin....................................................................... ......................................................8-4

Watch Dog Timer Reset.....................................................................................................................8-4

LVD Reset.............................................. ...........................................................................................8-4

Internal Power-On Reset ............................. ....................................................... ...............................8-5

External Interrupt Reset.....................................................................................................................8-7

Stop Error Detection & Recovery.......................................................................................................8-8

Power-Down Modes.................................... ......... .... ..... ..... ......... .... ..... ......... ..... .... ......... ..... ......................8-9

Idle Mode ... ......... ..... .... ......... ..... .... ......... ..... .... .......... .... ..... .... ......... ..... ..... ......... .... ..... ......................8-9

Back-up mode..................................................................................................... ...............................8-10

Stop Mode ..................................... ....................................................... .............................................8-11

Sources to Release Stop Mode.........................................................................................................8-12

System Reset Operation.............................. ..... .... ..... ......... .... ..... ..... ......... .... ..... ......... .... ..... .............8-14

Hardware Reset Values.....................................................................................................................8-15

Recommendation for Unusued Pins ..................................................................................... .............8-19

Summary Table of Back-Up Mode, Stop Mode, and Reset Status.....................................................8-20

Chapter 9 I/O Ports

Overview................................................................................................................ ....................................9-1

Port Data Registers............................................................................................................................9-4

Pull-Up Resistor Enable Registers.....................................................................................................9-5

S3F80JB MICROCONTROLLER vii

Table of Contents (Continued)

Chapter 10 Basic Timer and Timer 0

Overview ........................................................................................................................................... .........10-1

Basic Timer (BT)..... ...........................................................................................................................10-1

Timer 0...............................................................................................................................................10-1

Basic Timer Control Register (BTCON)..............................................................................................10-2

Basic Timer Function Description.......................................................................................................10-3

Timer 0 Control Register (T0CON)....................................................... ..............................................10-4

Timer 0 Function Description............................................. ................................................................10-6

Chapter 11 Timer 1

Overview ........................................................................................................................................... .........11-1

Timer 1 Overflow interrupt..................................................................................................................11-2

Timer 1 Capture interrupt...................................................................................................................11-2

Timer 1 Match interrupt.................................................................... ..................................................11-3

Timer 1 Control Register (T1CON)....................................................... ..............................................11-5

Chapter 12 Counter A

Overview ....................................................................................................................................................12-1

Counter A Control Register (CACON) ................................................................................................12-3

Counter A Pulse Width Calculations...................................................................................................12-4

Chapter 13 Timer 2

Overview ....................................................................................................................................................13-1

Timer 2 Overflow Interrupt..................................................................... .............................................13-2

Timer 2 Capture Interrupt...................................................................................................................13-2

Timer 2 Match Interrupt.................................................. ....................................................................13-3

Timer 2 Control Register (T2CON)....................................................... ..............................................13-5

Chapter 14 Comparator

Overview ....................................................................................................................................................14-1

Comparator Operation ....................................................................................... ................................14-3

viii S3F80JB MICROCONTROLLER

Table of Contents (Continued)

Chapter 15 Embedded Flash Memory Interface

Overview................................................................................................................ ....................................15-1

ISPTM (On-Board Programming) Sector.....................................................................................................15-3

ISP Reset Vector and ISP Sector Size...............................................................................................15-5

Flash Memory Control Registers (User Program Mode).............................................................................15-6

Flash Memory Control Register (FMCON).............................................................. ...........................15-6

Flash Memory User Programming Enable Register (FMUSR)...........................................................15-6

Flash Memory Sector Address Registers..................................... ......................................................15-7

Sector Erase .......... ....................................................... .............................................................................15-8

Programming............................................................................... ...............................................................15-12

Reading ....................................................... ....................................................... ........................................15-17

Hard Lock Protection............ ......................................................................................................................15-18

Chapter 16 Low Voltage Detector

Overview................................................................................................................ ....................................16-1

LVD....................................................................................................................................................16-1

LVD Flag............................................................................................................................................16-1

Low Voltage Detector Control Register (LVDCON)............................................................................16-3

Chapter 17 Electrical Data – 4MHz

Overview................................................................................................................ ....................................17-1

Chapter 18 Electrical Data – 8MHz

Overview................................................................................................................ ....................................18-1

Chapter 19 Mechanical Data

Overview······················································································································································19-1

Chapter 20 Development Tools Data

Overview······················································································································································20-1

Target Boards...................................................................................................................................20-1

Programming Socket Adapter...........................................................................................................20-1

TB80JB Target Board.......................................... ..... .... ..... ......... .... ..... ......... ..... .... ..... ......... .............20-2

OTP/MTP Programmer (Writer)........................................................................................................20-7

S3F80JB MICROCONTROLLER ix

List of Figures

Figure Title Page
Number Number

1-1 Block Diagram (32-pin)........................................... ..................................................1-3

1-2 Block Diagram (44-pin)........................................... ..................................................1-4

1-3 Pin Assignment Diagram (32-Pin SOP Package) .....................................................1-5

1-4 Pin Assignment Diagram (44-Pin QFP Package)............................................. .........1-6

1-5 Pin Circuit Type 1 (Port 0 and Port2)........................................................................1-10

1-6 Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)......................................................1-11

1-7 Pin Circuit Type 3 (P3.0)...........................................................................................1-12

1-8 Pin Circuit Type 4 (P3.1)...........................................................................................1-13

1-9 Pin Circuit Type 5 (P3.2 and P3.3)............................................................. ..............1-13

1-10 Pin Circuit Type 6 (nRESET)....................................................................................1-14

2-1 Program Memory Address Space.............................................................................2-2

2-2 Smart Option ............................................................................................................2-3

2-3 Internal Register File Organization...........................................................................2-6

2-4 Register Page Pointer (PP)......................................................................................2-7

2-5 Set 1, Set 2, and Prime Area Register Map ..............................................................2-9

2-6 8-Byte Working Register Areas (Slices).................................................. ..................2-10

2-7 Contiguous 16-Byte Working Register Block............................................................2-11

2-8 Non-Contiguous 16-Byte Working Register Block.....................................................2-12

2-9 16-Bit Register Pair ..................................................................................................2-13

2-10 Register File Addressing...........................................................................................2-14

2-11 Common Working Register Area..............................................................................2-15

2-12 4-Bit Working Register Addressing...........................................................................2-17

2-13 4-Bit Working Register Addressing Example............................................................2-17

2-14 8-Bit Working Register Addressing...........................................................................2-18

2-15 8-Bit Working Register Addressing Example............................................................2-19

2-16 Stack Operations......................................................................................................2-20

3-1 Register Addressing .................................................................................................3-2

3-2 Working Register Addressing ...................................................................................3-2

3-3 Indirect Register Addressing to Register File................................. .... ..... .... ..... .... .....3-3

3-4 Indirect Register Addressing to Program Memory....................................................3-4

3-5 Indirect Working Register Addressing to Register File....................... .......................3-5

3-6 Indirect Working Register Addressing to Program or Data Memory..........................3-6

3-7 Indexed Addressing to Register File.........................................................................3-7

3-8 Indexed Addressing to Program or Data Memory with Short Offset..........................3-8

3-9 Indexed Addressing to Program or Data Memory.....................................................3-9

3-10 Direct Addressing for Load Instructions....................................................................3-10

3-11 Direct Addressing for Call and Jump Instructions .......................... .... ......... ..... ..... ....3-11

3-12 Indirect Addressing...................................................................................................3-12

3-13 Relative Addressing..................................................................................................3-13

3-14 Immediate Addressing..............................................................................................3-14

4-1 Register Description Format................................... ..................................................4-4

x S3F80JB MICROCONTROLLER

List of Figures (Continued)

Figure Title Page
Number Number

5-1 S3C8/S3F8-Series Interrupt Types...........................................................................5-2

5-2 S3F80JB Interrupt Structure.....................................................................................5-4

5-3 ROM Vector Address Area.......................................................................................5-5

5-4 Interrupt Function Diagram.......................................................................................5-8

5-5 System Mode Register (SYM)..................................................................................5-10

5-6 Interrupt Mask Register (IMR)..................................................................................5-11

5-7 Interrupt Request Priority Groups.............................................................................5-12

5-8 Interrupt Priority Register (IPR)............................................................................ ....5-13

5-9 Interrupt Request Register (IRQ)..............................................................................5-14

6-1 System Flags Register (FLAGS)..............................................................................6-6

7-1 Main Oscillator Circuit (External Crystal or Ceramic Resonator)............................7-1

7-2 External Clock Circuit................................ ...............................................................7-1

7-3 System Clock Circuit Diagram ..... ..... .... ..... ......... ..... .... ..... ......... .... ..... .... ......... ..... ....7-2

7-4 System Clock Control Register (CLKCON)...............................................................7-3

8-1 RESET Sources of The S3F80JB.............................................. ...............................8-2

8-2 RESET Block Diagram of The S3F80JB ............ ......................................................8-3

8-3 RESET Block Diagram by LVD for The S3F80JB IN STOP MODE..........................8-4

8-4 Internal Power-On Reset Circuit........... ....................................................................8-5

8-5 Timing Diagram for Internal Power-On Reset Circuit ................................................8-6

8-6 Reset Timing Diagram for The S3F80JB in STOP mode by IPOR...........................8-7

8-7 Block Diagram for Back-up Mode.............. ...............................................................8-10

8-8 Timing Diagram for Back-up Mode Input and Released by LVD...............................8-10

9-1 S3F80JB I/O Port Data Register Format ..................................................................9-5

9-2 Pull-up Resistor Enable Registers (Port 0 and Port 2 only)......................................9-6

10-1 Basic Timer Control Register (BTCON)............................ ........................................10-2

10-2 Timer 0 Control Register (T0CON)....... ....................................................................10-5

10-3 Timer 0 DATA Register (T0DATA).............................................................. .............10-5

10-4 Simplified Timer 0 Function Diagram: Interval Timer Mode......................................10-6

10-5 Simplified Timer 0 Function Diagram: PWM Mode...................................................10-7

10-6 Simplified Timer 0 Function Diagram: Capture Mode...............................................10-8

10-7 Basic Timer and Timer 0 Block Diagram..................................................................10-9

11-1 Simplified Timer 1 Function Diagram: Capture Mode...............................................11-2

11-2 Simplified Timer 1 Function Diagram: Interval Timer Mode......................................11-3

11-3 Timer 1 Block Diagram.............................................................................................11-4

11-4 Timer 1 Control Register (T1CON)....... ....................................................................11-5

11-5 Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL).................................11-6

S3F80JB MICROCONTROLLER xi

List of Figures (Continued)

Figure Title Page
Number Number

12-1 Counter A Block Diagram.............................................................. ...........................12-2

12-2 Counter A Control Register (CACON)......................................................................12-3

12-3 Counter A Registers.................................................................................................12-3

12-4 Counter A Output Flip-Flop Waveforms in Repeat Mode..........................................12-5

13-1 Simplified Timer 2 Function Diagram: Capture Mode...............................................13-2

13-2 Simplified Timer 2 Function Diagram: Interval Timer Mode...................................... 13-3

13-3 Timer 2 Block Diagram.............................................................................................13-4

13-4 Timer 2 Control Register (T2CON)...........................................................................13-5

13-5 Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL).................................13-6

14-1 Comparator Block Diagram for The S3F80JB...........................................................14-2

14-2 Conversion Characteristics.......................................................................................14-3

14-3 Comparator Mode Register (CMOD)........................................................................14-4

14-4 Comparator Input Selection Register (CMPSEL)......................................................14-4

14-5 Comparator Result Register (CMPREG)..................................................................14-5

15-1 Program Memory Address Space.............................................................................15-3

15-2 Smart Option ............................................................................................................15-4

15-3 Flash Memory Control Register (FMCON).............................................. ..................15-6

15-4 Flash Memory User Programming Enable Register (FMUSR)..................................15-6

15-5 Flash Memory Sector Address Register (FMSECH ).................................................15-7

15-6 Flash Memory Sector Address Register (FMSECL)..................................................15-7

15-7 Sector Configurations in User Program Mode ..........................................................15-8

15-8 Sector Erase Flowchart in User Program Mode................................................... .....15-9

15-9 Byte Program Flowchart in a User Program Mode....................................................15-13

15-10 Program Flowchart in a User Program Mode............................................................15-14

16-1 Low Voltage Detect (LVD) Block Diagram······················································· ·········16-2
16-2 Low Voltage Detect Control Register (LVDCON)······················································16-3

17-1 Typical Low-Side Driver (Sink) Characteristics (P3.1 only)·······································17-5
17-2 Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)······· ··················17-5
17-3 Typical Low-Side Driver (Sink) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)··························································17-6
17-4 Typical High-Side Driver (Source) Characteristics (P3.1 only)··································17-6
17-5 Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)····················17-7
17-6 Typical High-Side Driver (Source) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)··························································17-7
17-7 Stop Mode Release Timing When Initiated by an External Interrupt····················· ····17-8
17-8 Stop Mode Release Timing When Initiated by a Reset·············································17-8
17-9 Stop Mode Release Timing When Initiated by a LVD···············································17-9
17-10 Input Timing for External Interrupts (Port 0 and Port 2)············································17-10
17-11 Input Timing for Reset (nRESET Pin)·······································································17-10
17-12 Operating Voltage Range of S3F80J9······································································ 17-13

xii S3F80JB MICROCONTROLLER

List of Figures (Continued)

Figure Title Page
Number Number

18-1 Typical Low-Side Driver (Sink) Characteristics (P3.1 only)··································· ····18-5
18-2 Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)·························18-5
18-3 Typical Low-Side Driver (Sink) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)········· ·················································18-6
18-4 Typical High-Side Driver (Source) Characteristics (P3.1 only)··································18-6
18-5 Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)····················18-7
18-6 Typical High-Side Driver (Source) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)········· ·················································18-7
18-7 Stop Mode Release Timing When Initiated by an External Interrupt·························18-8
18-8 Stop Mode Release Timing When Initiated by a Reset·············································18-8
18-9 Stop Mode Release Timing When Initiated by a LVD···············································18-9
18-10 Input Timing for External Interrupts (Port 0 and Port 2)············································18-10
18-11 Input Timing for Reset (nRESET Pin)·······································································18-10
18-12 Operating Voltage Range of S3F80JB·····································································18-13

19-1 32-Pin SOP Package Dimension..............................................................................19-1

19-2 44-Pin QFP Package Dimension ............................................... ...............................19-2

20-1 TB80JB Target Board Configuration·········································································20-2
20-2 50-Pin Connector Pin Assignment for TB80JB·························································20-5
20-3 TB80JB Adapter Cable for 44-QFP Package ··················· ········································20-5

S3F80JB MICROCONTROLLER xiii

List of Tables

Table Title Page
Number Number

1-1 Pin Descriptions of 32-SOP......................................................................................1-7

1-2 Pin Descriptions of 44-QFP......................................................................................1-8

2-1 S3F80JB Register Type Summary................ ..... .... .......... .... ..... .... ..... ......... ..... .... ....2-5

4-1 Mapped Registers (Bank0, Set1) .............................................................................4-2

4-2 Mapped Registers (Bank1, Set1) .............................................................................4-3

4-3 Each F unction Description and Pin Assignment of P3CON in 42/44 Pin Package ...4-32

5-1 S3F80JB Interrupt Vectors ....................................................................................... 5-6

5-2 Interrupt Control Register Overview................................................... ......................5-7

5-3 Vectored Interrupt Source Control and Data Registers.............................................5-9

6-1 Instruction Group Summary......................................................................................6-2

6-2 Flag Notation Conventions.......................................................................................6-8

6-3 Instruction Set Symbols............................................................................................6-8

6-4 Instruction Notation Conventions.............................................................................. 6-9

6-5 Opcode Quick Reference.........................................................................................6-10

6-6 Condition Codes.......................................................................................................6-12

8-1 Reset Condition in STOP Mode When IPOR / LVD Control Bit is “1”

(always LVD-On) ......................................................................................................8-8

8-2 Reset Condition in STOP Mode When IPOR / LVD Control Bit is “0”.......................8-8

8-3 Set 1, Bank 0 Register Values After Reset................................ ...............................8-15

8-4 Set 1, Bank 1 Register Values After Reset................................ ...............................8-17

8-5 Reset Generation According to the Condition of Smart Option.................................8-18

8-6 Guideline for Unused Pins to Reduced Power Consumption....................................8-19

8-7 Summary of Each Mode ...........................................................................................8-20

9-1 S3F80JB Port Configuration Overview (44-QFP) ................................... ..................9-2

9-3 S3F80JB Port Configuration Overview (32-SOP).....................................................9-3

9-4 Port Data Register Summary.............................................................. ......................9-4

S3F80JB MICROCONTROLLER xv

List of Tables (Continued)

Table Title Page
Number Number

15-1 Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode..............15-2

15-2 ISP Sector Size........................................................................................................15-5

15-3 Reset Vector Address...............................................................................................15-5

17-1 Absolute Maximum Ratings ......................................................................................17-2

17-2 D.C. Electrical Characteristics..................................................................................17-2

17-3 Characteristics of Low Voltage Detect Circuit...........................................................17-4

17-4 Data Retention Supply Voltage in Stop Mode......................................... .... .......... ....17-4

17-5 Input/Output Capacitance.........................................................................................17-9

17-6 A.C. Electrical Characteristics ..................................................................................17-9

17-7 Comparator Electrical Characteristics.......................................................................17-11

17-8 Oscillation Characteristics ........................................................................................17-11

17-9 Oscillation Stabilization Time........................................................................... .........17-12

17-10 AC Electrical Characteristics for Internal Flash ROM......................... ......... ..... .... .....17-13

18-1 Absolute Maximum Ratings ······················································································18-2
18-2 D.C. Electrical Characteristics··················································································18-2
18-3 Characteristics of Low Voltage Detect Circuit···························································18-4
18-4 Data Retention Supply Voltage in Stop Mode········································· ···· ·········· ····18-4
18-5 Input/Output Capacitance·························································································18-9
18-6 A.C. Electrical Characteristics ··················································································18-9
18-7 Comparator Electrical Characteristics·······································································18-11
18-8 Oscillation Characteristics ························································································18-11
18-9 Oscillation Stabilization Time··········································································· ·········18-12
18-10 AC Electrical Characteristics for Internal Flash ROM··············································18-13

20-1 Components Consisting of S3F80JB Target Board ··················································20-3
20-2 Default Setting of the Jumper in S3F80JB Target Board··········································20-4

xvi S3F80JB MICROCONTROLLER

List of Programming Tips

Description Page
Number

Chapter 2 Address Spaces

Setting the Register Pointers......................................................................... .............................................2-11

Using the RPs to Calculate the Sum of a Series of Registers............................................................. ........2-12

Addressing the Common Working Register Area.......................................................................... .............2-16

Standard Stack Operations Using PUSH and POP....................................................................................2-21

Chapter 8 Reset

To Enter STOP Mode.................................................................................................................................8-10

Chapter 10 Basic Timer and Timer 0

Configuring the Basic Timer.......................................................................... .............................................10-11

Programming Timer 0......................................................................................... ........................................10-12

Chapter 12 Counter A

To Generate 38 kHz, 1/3duty Signal Through P3.1.............................................................. ......................12-6

To Generate a one Pulse Signal Through P3.1............................... ...........................................................12-7

Chapter 15 Embedded Flash Memory Interface

Sector Erase .......... ....................................................... .............................................................................15-10

Programming............................................................................... ...............................................................15-15

Reading ....................................................... ....................................................... ........................................15-17

Hard Lock Protection............ ......................................................................................................................15-18

S3F80JB MICROCONTROLLER xvii

List of Register Descriptions

Register Full Register Name Page
Identifier Number

BTCON Basic Timer Control Register....................................................................................4-5

CACON Counter A Control Register ....................... ......... ..... .... ..... ......... .... ..... .... ......... ..... ....4-6

CLKCON System Clock Control Register...................... ...........................................................4-7

CMOD Comparator Mode Register......................................................................................4-8

CMPSEL Comparator Input Selection Register........................................................................4-9

EMT External Memory Timing Register................................................. ...........................4-10

FLAGS System Flags Register.............................................................................................4-11

FMCON Flash Memory Control Register............................................................... .................4-12

FMSECH Flash Memory Sector Address Register (High Byte)................................................4-13

FMSECL Flash Memory Sector Address Register (Low Byte).................................................4-13

FMUSR Flash Memory User Programming Enable Register..................................................4-13

IMR Interrupt Mask Register............................................................................................4-14

IPH Instruction Pointer (High Byte)..................................................................................4-15

IPL Instruction Pointer (Low Byte)..................................................................................4-15

IPR Interrupt Priority Register..........................................................................................4-16

LVDCON LVD Control Register.............................................................................................4-18

P0CONL Port 0 Control Register (Low Byte)...........................................................................4-20

P0INT Port 0 External Interrupt Enable Register.................................................................4-21

P0PND Port 0 External Interrupt Pending Register...............................................................4-22

P0PUR Port 0 Pull-up Resistor Enable Register........................................ ...........................4-23

P1CONH Port 1 Control Register (High Byte)..........................................................................4-24

P1CONL Port 1 Control Register (Low Byte)...........................................................................4-25

P2CONH Port 2 Control Register (High Byte)..........................................................................4-26

P2CONL Port 2 Control Register (Low Byte)...........................................................................4-27

P2INT Port 2 External Interrupt Enable Register.................................................................4-28

P2PND Port 2 External Interrupt Pending Register...............................................................4-29

P3CON Port 3 Control Register......................... ....................................................... .............4-31

P345CON Port3[4:5] Control Register .......................................................................................4-33

P4CON Port 4 Control Register......................... ....................................................... .............4-34

P4CONH Port 4 Control Register (High Byte)..........................................................................4-35

P4CONL Port 4 Control Register (Low Byte)...........................................................................4-36

PP Register Page Pointer..............................................................................................4-37

RP0 Register Pointer 0.....................................................................................................4-38

RP1 Register Pointer 1.....................................................................................................4-38

SPL Stack Pointer (Low Byte)......................................... .................................................4-39

STOPCON Stop Control Register...............................................................................................4-39

SYM System Mode Register.............................................................................................4-40

T1CON Timer 1 Control Register...................................................... ....................................4-42

T2CON Timer 2 Control Register...................................................... ....................................4-43

S3F80JB MICROCONTROLLER xix

List of Instruction Descriptions

Instruction Full Register Name Page
Mnemonic Number

ADC Add with carry..........................................................................................................6-14

ADD Add...........................................................................................................................6-15

AND Logical AND.............................................................................................................6-16

BAND Bit AND ....................................................................................................................6-17

BCP Bit Compare.............................................................................................................6-18

BITC Bit Complement........................................................................................................6-19

BITR Bit Reset...................................................................................................................6-20

BITS Bit Set ......................................................................................................................6-21

BOR Bit OR ......................................................................................................................6-22

BTJRF Bit Test, Jump Relative on False..............................................................................6-23

BTJRT Bit Test, Jump Relative on True...............................................................................6-24

BXOR Bit XOR ....................................................................................................................6-25

CALL Call Procedure .........................................................................................................6-26

CCF Complement Carry Flag ...........................................................................................6-27

CLR Clear ........................................................................................................................6-28

COM Complement.............................................................................................................6-29

CP Compare..................................................................................................................6-30

CPIJE Compare, Increment, and Jump on Equal................................................................6-31

CPIJNE Compare, Increment, and Jump on Non-Equal ........................................................6-32

DA Decimal Adjust.........................................................................................................6-33

DA Decimal Adjust.........................................................................................................6-34

DEC Decrement................................................................................................................6-35

DECW Decrement Word......................................................................................................6-36

DIV Divide (Unsigned).....................................................................................................6-38

DJNZ Decrement and Jump if Non-Zero............................................................................6-39

EI Enable Interrupts......................................................................................................6-40

ENTER Enter ........................................................................................................................6-41

EXIT Exit...........................................................................................................................6-42

IDLE Idle Operation...........................................................................................................6-43

INC Increment.................................................................................................................6-44

INCW Increment Word........................................................................................................6-45

IRET Interrupt Return........................................................................................................6-46

JP Jump........................................................................................................................6-47

JR Jump Relative ..........................................................................................................6-48

LD Load.........................................................................................................................6-49

LD Load.........................................................................................................................6-50

LDB Load Bit....................................................................................................................6-51

LDC/LDE Load Memory...........................................................................................................6-52

LDC/LDE Load Memory...........................................................................................................6-53

LDCD/LDED Load Memory and Decrement..................................................................................6-54

LDCI/LDEI Load Memory and Increment....................................................................................6-55

LDCPD/LDEPD Load Memory with Pre-Decrement......................... ..... ..... .... ......... ..... .... ..... ......... ....6-56

LDCPI/LDEPI Load Memory with Pre-Increment........................................................... ..... ..... .... ....6-57

LDW Load Word................................................................................................................6-58

MULT Multiply (Unsigned)...................................................................................................6-59

S3F80JB MICROCONTROLLER xxi

List of Instruction Descriptions (Continued)

Instruction Full Register Name Page
Mnemonic Number

NEXT Next..........................................................................................................................6-60

NOP No Operation............................................................................................................6-61

OR Logical OR................................................................................................................6-62

POP Pop From Stack ...................................................... ..................................................6-63

POPUD Pop User Stack (Decrementing)............................................................. ..................6-64

POPUI Pop User Stack (Incrementing)................................................. ................................6-65

PUSH Push To Stack........................................................ ..................................................6-66

PUSHUD Push User Stack (Decrementing)........................................................... ..................6-67

PUSHUI Push User Stack (Incrementing)........................................... .................................... 6-68

RCF Reset Carry Flag ......................................................................................................6-69

RET Return.......................................................................................................................6-70

RL Rotate Left................................................................................................................6-71

RLC Rotate Left Through Carry........................................................................................6-72

RR Rotate Right .............................................................................................................6-73

RRC Rotate Right Through Carry........................................................... ...........................6-74

SB0 Select Bank 0 ...........................................................................................................6-75

SB1 Select Bank 1 ...........................................................................................................6-76

SBC Subtract With Carry ..................................................................................................6-77

SCF Set Carry Flag ..........................................................................................................6-78

SRA Shift Right Arithmetic................................................................................................6-79

SRP/SRP0/SRP1 Set Register Pointer .................................................................................................6-80

STOP Stop Operation .........................................................................................................6-81

SUB Subtract....................................................................................................................6-82

SWAP Swap Nibbles............................................................................................................6-83

TCM Test Complement Under Mask.................................................................................6-84

TM Test Under Mask ......................................................................................................6-85

WFI Wait For Interrupt......................................................................................................6-86

XOR Logical Exclusive OR................................................................................................6-87

xxii S3F80JB MICROCONTROLLER

S3F80JB PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8/S3F8-SERIES MICROCONTROLLERS

Samsung's S3C8/S3F8-series of 8-bit single-chip CM OS mi crocon trollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include :

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupts
— Bu ilt-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (wit hin a minimum four CPU clocks) can be assigned to
specific interrupt levels.

S3F80JB MICROCONTROLLER

The S3F80JB single-chip CMOS microcontroller is fabricated usin g a highly advanced CMOS process and is
based on Samsung's newest CPU architecture.

The S3F80JB is the microcontroller which has 64-Kbyte Flash Memory ROM.
Using a proven modular design approach, Samsung engineers developed S3F80JB by integrating the following

peripheral modules with the powerful SAM8 RC core:
— Internal LVD circuit and 16 bit-programmable pins for external interrupts.

— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).
— One 8-bit Timer/counter with three oper at ing modes.
— Two 16-bit timer/counters with selectable operating modes.
— 4-bit analog voltage comparator with four/three channels (internal/extern al re ference).
— One 8-bit counter with auto-reload function and one-shot or repeat cont rol.

The S3F80JB is a versatile general-purpose microcont rol ler, which is especially suitable for use as remote
transmitter controller. It is currently av ailable in a 32-pin SOP and 44-pin QFP package.

1-1

PRODUCT OVERVIEW S3F80JB

FEATURES

CPU

• SAM8 RC CPU core

Memory

• Program memory:

- 64-Kbyte Internal Flash Memory

- Sector size: 128Bytes

- 10years data retention

- Fast Programming Time: Sector Erase: 10ms
Byte Program: 32us

- Byte Programmable

- User programmable by ‘LDC’ instruction

- Sector (128-bytes) Erase available

- External serial programming support

- Endurance: 10,000 Erase/Program cycles

- Expandable OBPTM (On Board Program)

• Data memory: 272-byte general purpose RAM

Instruction Set

• 7 8 in stru ctions

• I DLE and STOP instructions added for power-

down modes

Instruction Execution Time

• 500 ns at 8-MHz f

(minimum)

OSC

Interrupts

• 24 interrupt sources with 18 vectors

and 8 levels.

I/O Ports

• Fou r 8- bit I / O p orts (P0–P2 , P4) and 6-bit port

(P3) for a total of 38 bit-programmable p i ns.
(44-QFP)

• Fo ur 8 -bit I/O ports (P0–P2 , P4) and 4-bit port

(P3) for a total of 36 bit-programmable p i ns.
(42-SDIP)

• Th ree 8-bit I/O ports (P0–P2) and one 2-bit I / O

port (P3) for a total of 26-bit prog ramma ble pins.
(32-SOP)

Carrier Frequency Generator

• One 8-bit counter with auto-reload function and

one-shot or repeat control (Counter A)

Basic Timer and Timer/Counters

• One programmable 8-bit basic timer (BT) for

oscillation stabilization control or watchdog timer
(software reset) function

• One 8-bit timer/counter (Timer 0) with three

operating modes: Interval mode, Capture and
PWM mode.

• One 16-bit timer/counter (Timer1) with two

operating modes: Interval and Cap tu re mo de.

• One 16-bit timer/counter (Timer2) with two

operating modes: Interval and Cap tu re mo de.

Back-up Mode

• When V

is lower than V

DD

, the chip enters

LVD

Back-up mode to block oscillation and reduce the
current consumption.

In S3F80JB, this function is disabled when

operating state is “STOP mode”.

• When reset pin is lower than Input Low Voltage

), the chip enters Back-up mode to block

(V

IL

oscillation and reduce the current consumption.

Analog Voltage Comparator

• 4-bit resolution: 16-step variable reference

voltage, 150mV Input Voltage Accuracy (worst
case)

• 4-channel mode: CIN0-3, Internal refe ren ce

voltage generator

• 3-channel mode: CIN0-2, External reference

voltage source (CIN3) supply

Low Voltage Detect Circuit

• L ow v oltage detect to get into Back-up mode and

Reset

2.15V (Typ) ± 200mV at 8MHz

1.90V (Typ) ± 200mV at 4MHz

• Low voltage detect to control LVD_Flag bit

2.30V (Typ) ± 200mV at 8MHz

2.15V (Typ) ± 200mV at 4MHz

Operating Temperature Range

• –25

°

C to + 85 °C

Operating Voltage Range

• 1.95V to 3.6V at 8MHz

Package Types

• 32-pin SOP

• 44-pin QFP

1-2

S3F80JB PRODUCT OVERVIEW

BLOCK DIAGRAM (32-PIN PACKAGE)

P0.0-0.3 (INT0-INT3)

P0.4-P0.7(INT4)

P1.0-1.7

Port0 Port1

V

DD

X

IN

X

OUT

LVD

IPOR(note)

Main
OSC

8-Bit
Basic
Timer

8-Bit

Timer0

/Counter

16-Bit

Timer1

/Counter

16-Bit

Timer2

/Counter

I/O Port and Interrupt

SAM8RC CPU

64K-byte

FLASH

Memory

Comparator

Control

272-byte

Register File

Carrier Generator

(Counter A)

TEST

nRESET

Port2

Port3

P2.0-2.3
(INT5-INT8)

P2.4-2.7
(INT9)
(CIN0-CIN3)

P3.0/T0PWM/T0CAP/
SDAT/T1CAP/T2CAP

P3.1/REM/T0CK/SCLK

Figure 1-1. Block Diagram (32-pin)

NOTE

IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2)

1-3

PRODUCT OVERVIEW S3F80JB

BLOCK DIAGRAM (44-PIN PACKAGE)

P0.0-0.3 (INT0-INT3)

P0.4-P0.7(INT4)

P1.0-1.7

Port0 Port1

V

DD

X

IN

X

OUT

LVD

IPOR(note)

Main
OSC

8-Bit
Basic
Timer

8-Bit

Timer0

/Counter

16-Bit

Timer1

/Counter

16-Bit

Timer2

/Counter

I/O Port and Interrupt

SAM8RC CPU

64K-byte

FLASH

Memory

Comparator

Control

272-byte

Register File

Carrier Generator

(Counter A)

TEST

nRESET

Port2

Port3

Port4

P2.0-2.3
(INT5-INT8)

P2.4-2.7
(INT9)

(CIN0-CIN3)

P3.0/T0PWM/T0CAP/SDAT
P3.1/REM/SCLK

P3.2/T0CK
P3.3/T1CAP/T2CAP

P3.4-P3.5

P4.0-P4.7

Figure 1-2. Block Diagram (44-pin)

NOTE

IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2)

1-4

S3F80JB PRODUCT OVERVIEW

PIN ASSIGNMENTS

VSS

XOUT

XIN

TEST
P2.5/INT9/CIN1
P2.6/INT9/CIN2

nRESET

P2.7/INT9/CIN3

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

S3F80JB

(Top View)

32-SOP

VDD

32

P3.1/REM/T0CK/SCLK

31

P3.0/T0PWM/T0CAP/T1CAP/T2CAP/SDAT

30

P2.4/INT9/CIN0

29

P2.3/INT8

28

P2.2/INT7

27

P2.1/INT6

26

P2.0/INT5

25

P0.7/INT4

24

P0.6/INT4

23

P0.5/INT4

22

P0.4/INT4

21
20

P0.3/INT3

19

P0.2/INT2

18

P0.1/INT1

17

P0.0/INT0

Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package)

1-5

PRODUCT OVERVIEW S3F80JB

PIN ASSIGNMENTS (Continued)

P0.3/INT3

P0.2/INT2

P0.1/INT1

P0.0/INT0

P4.4

P4.5

P4.6

P1.7

P1.6

P1.5

P1.4

P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4

P4.3
P4.2
P4.1

P4.0
P2.0/INT5
P2.1/INT6
P2.2/INT7

3332313029282726252423
34
35
36
37
38
39
40
41
42
43
44

S3F80JB

(Top View)

(44-QFP)

1234567891011

DD

VSS

V

XOUT

P2.3/INT8

P2.4/INT9/CIN0

P3.1/REM/SCLK

P3.0/T0PWM/T0CAP/SDAT

P1.3

22

P1.2

21

P1.1

20

P4.7

19

P3.3/T1CAP/T2CAP

18

P3.2/T0CK

17

P1.0

16

P2.7/INT9/CIN3

15

P3.5

14

P3.4

13

nRESET

12

XIN

TEST

P2.5/INT9/CIN1

P2.6/INT9/CIN2

Figure 1-4. Pin Assignment Diagram (44-Pin QFP Package)

1-6

S3F80JB PRODUCT OVERVIEW

Table 1-1. Pin Descriptions of 32-SOP

Pin

Names

P0.0–P0.7

P1.0–P1.7

P2.0–P2.3
P2.4–P2.7

P3.0

P3.1

XOUT, XIN
nRESET

TEST

VDD
VSS

Pin

Type

I/O I/O port with bit-programmable pins. Configurable

to input or push-pull output mode. Pull-up resistors

Pin Description Circuit

Type

1 17–24 Ext. INT

32 Pin

No.

Functions

(INT0–INT3)
are assignable by software. Pins can be assigned
individually as external interrupt inp ut s wi th noi se
filters, interrupt enable/ disable, and interrupt
pending control. SED&R (note) circuit built in P0
for STOP releasing.

I/O I/O port with bit-programmable pins. Configurable

2 9–16 –
to input mode or output mode. Pin circuits are
either push-pull or n-channel open-drain type.

I/O I/O port with bit-programmable pins. Configurable

to input or push-pull output mode. Pull-up resistors

1

25–28

29,5,6,8

(INT5–INT8)
can be assigned by software. Pins can be
assigned individually as external inte rru pt inputs

(CIN0-CIN3)
with noise filters, interrupt enable/disa ble , a nd
interrupt pending control. SED & R (note) circu it
built in P2-P2.7 for STOP releasing. Also P2.4­P2.7 can be assigned individually as analog input
pins for Comparator.

I/O I/O port with bit-programmable pin. Configurable to

3 30 T0PWM/T0CAP
input mode, push-pull output mode, or n-channel
open-drain output mode. Input mode wit h a pu ll- up
resistor can be assigned by software.
This port 3 pin has high current drive capability.
Also P3.0 can be assigned individually as an
output pin for T0PWM or input pin for T0CAP.
In the tool mode, P3.0 is assigned as serial MTP
interface pin; SDAT

I/O I/O port with bit-programmable pin. Configurable to

4 31 REM
input mode, push-pull output mode, or n-channel
open-drain output mode. Input mode wit h a p ull- up
resistor can be assigned by software.
This port 3 pin has high current drive capability .
Also P3.1 can be assigned individually as an
output pin for REM.
In the tool mode, P3.1 is assigned as serial MTP
interface pin; SCLK

– System clock input and output pins – 2,3 –

I System reset signal input pin and back-up mode

6 7 –
input.

I Test signal input pin

(for factory use only; must be connected to V

–

Power supply input pin

–

Ground pin

SS

).

– 4 –

– 32 –

– 1 –

Shared

(INT4)

Ext. INT

(INT9)

(SDAT)

(SCLK)

1-7

PRODUCT OVERVIEW S3F80JB

Table 1-2. Pin Descriptions of 44-QFP

Pin

Names

Pin

Type

Pin Description Circuit

P0.0–P0.7 I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output
mode. Pull-up resistors can be assigned
by software. Pins can be assigned
individually as external interrupt inputs
with noise filters, interrupt enable/
disable, and interrupt pending control.
SED & R(note)circuit built in P0 for STOP
releasing.

P1.0–P1.7 I/O I/O port with bit-programmable pins.

Configurable to input mode or output
mode. Pin circuits are either push-pull or
n-channel open-drain type.

P2.0–P2.3
P2.4–P2.7

I/O I/O port with bit- pro gra mmable pins.

Configurable to input or push-pull output
mode. Pull-up resistors can be assigned
by software. Pins can be assigned
individually as external interrupt inputs
with noise filters, interrupt enable/
disable, and interrupt pending control.
SED & R(note) circuit built in P2.4-P2.7
for STOP releasing. Also P2.4-P2.7 can
be assigned individually as analog input
pins for Comparator.

P3.0 I/O I/O port with bit- pro gra mmab le pin.

Configurable to input mode, push-pull
output mode, or n-channel open-drai n
output mode. Input mode with a pull-up
resistor can be assigned by software.
This port 3pin has high current drive
capability. Also P3.0 can be assigned
individually as an output pin for T0PWM
or input pin for T0CAP.
In the tool mode, P3.0 is assigned as
serial MTP interface pin; SDAT

Type

44 Pin

No.

Shared

Functions

1 30–37 Ext. INT

(INT0–INT3)

(INT4)

2 16

–

20–26

1

42–44

1, 2,

10,11,

15

Ext. INT

(INT5–INT8)

(INT9)

(CIN0-CIN3)

3 3 T0PWM/T0CAP

(SDAT)

NOTE: SED & R means “STOP Error Detect & Recovery”. The Stop Error Detect & Recovery Circuit is used to release stop
mode and prevent abnormal-stop mode. Refer to page 8-11.

1-8

S3F80JB PRODUCT OVERVIEW

Table 1-2. Pin Descriptions of 44-QFP (Continued)

Pin

Names

P3.1

Pin

Pin Description Circuit

Type

I/O I/O port with bit-prog rammable pin. Configurable to

input mode, push-pull output mode, or n-channel

44 Pin

Type

No.

4 4 REM

open-drain output mode. Input mode with a pull-up
resistor can be assigned by software.
This port 3pin has high current drive capability.
Also P3.1 can be assigned individually as an
output pin for REM.
In the tool mode, P3.1 is assigned as serial MTP
interface pin; SCLK

P3.2–P3.3 I C-MOS Input port with a pull-up resistor 5 17

18

P3.4–P3.5 I/O I/O port with bit-programmable pins. Configurable

2 13–14 –
to input mode or output mode. Pin circuits are
either push-pull or n-channel open-drain type. Pull­up resistors can be assigned by software.

P4.0–P4.7 I/O I/O port with bit-programmable pins. Configurable

to input mode or output mode. Pin circuits are
either push-pull or n-channel open-drain type.

X

OUT

, XIN

– System clock input and output pins – 7,8 –

nRESET I System reset signal input pin and back-up mode

2 38–41

27–29

19

6 12 –
input.

TEST I Test signal input pin

(for factory use only; must be connected to V

VDD

– Power supply input pin – 5 –

SS

.)

_ 9 _

Shared

Functions

(SCLK)

(T0CK)

(T1CAP/T2CAP)

–

VSS

– Ground pin – 6 –

1-9

PRODUCT OVERVIEW S3F80JB

PIN CIRCUITS

V

DD

Pull-Up
Resistor

Ω

- typ)

Pull-up
Enable

Data

Output Disable

V

DD

(55k

INPUT/OUTPUT

P2.4-P2.7 Only

External

Interrupt

Stop

V

SS

P2CONx.x

CMPSEL.0-.3

External REF (P2.7 only)

+

MUX

-

Comparator

REF

Noise

Filter

Stop
Release

Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2)

1-10

S3F80JB PRODUCT OVERVIEW

PIN CIRCUITS (Continued)

V

DD

Pull-up
Resistor
(55k

Ω

-Typ)
Pull-up
Enable

V

DD

Data

INPUT/OUTPU T

Open-Drain

Output Disable

V

SS

Normal

Input

Noise

Filter

Figure 1-6. Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)

1-11

PRODUCT OVERVIEW S3F80JB

PIN CIRCUITS (Continued)

V

DD

Pull-up
Resistor
(55k

Ω

Pull-up
Enable

P3CON.2

V

DD

-Typ)

Port 3.0 Data

T0_PWM

Open-Drain

Output Disable

P3.0 Input

T0CAP/(T1CAP/T2CAP)

M
U

X

P3CON.2,6,7

M
U
X

Data

Noise filter

P3.0/T0PWM T0CAP/
(T1CAP/T2CAP)

V

SS

Figure 1-7. Pin Circuit Type 3 (P3.0)

1-12