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S3F80JB
User Manual
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Samsung S3F80JB User Manual

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S3F80JB
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.1
Preface
The S3F80JB Microcontroller User's Manual is designed for application designers and programmers who are using
S3F80JB microcontroller for application development. It is organized in two main parts:
Part I Programming Model Part I contains software-related information to familiarize you with the microcontroller's architecture, programming
model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Product Overview
Chapter 2 Address Spaces Chapter 3 Addressing Modes
Chapter 1, "Product Overview," is a high-level introduction to as detailed information about individual pin characteristics and pin circuit types.
Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations.
Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the S3C8-series CPU.
Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs.
Part II Hardware Descriptions
Chapter 4 Control Registers Chapter 5 Interrupt Structure Chapter 6 Instruction Set
S3F80JB with general product descriptions, as well
Chapter 5, "Interrupt Structure," describes the additional information presented in the individual hardware module descriptions in Part II.
Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3F8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the S3F8-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, an d 6. La t er , y ou c a n reference the in f o rm ation in Part I as nece s sary.
Part II "hardware Descriptions," has detailed information about specific hardware components of the microcontroller. Also included in Part II are electrical, mechanical, MTP, and development tools data. It has 14 chapters:
Chapter 7 Clock Circuits Chapter 8 RESET Chapter 9 I/O Ports Chapter 10 Basic Timer and Timer 0 Chapter 11 Timer 1 Chapter 12 Counter A Chapter 13 Timer 2 Chapter 14 Comparator
Two order forms are included at the back of this manual to facilitate customer order for the Flash Factor Writing Order Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
S3F80JB interrupt structure in detail and further prepares you for
S3F80JB
Chapter 15 Embedded Flash Memory Interface Chapter 16 Low Voltage Detector Chapter 17 Electrical Data-4MHz Chapter 18 Electrical Data-8MHz Chapter 19 Mechanical Data Chapter 20
Development Tools Data
S3F80JB microcontrollers:
S3F80JB MICROCONTROLLER iii

Table of Contents

Part I — Programming Model
Chapter 1 Product Overview
S3C8/S3F8-Series Microcontrollers ... ........................................................................................................1-1
S3F80JB Microcontroller........... ......... .... ..... .... .......... .... ..... .... ......... ..... ..... .... ......... ..... .... ..... ......................1-1
Features................................................................................................................................................. ....1-2
Block Diagram (32-pin package)................................................................... .............................................1-3
Block Diagram (44-pin package)................................................................... .............................................1-4
Pin Assignments.........................................................................................................................................1-5
Pin Circuits.................................................................................................................................................1-10
Chapter 2 Address Spaces
Overview................................................................................................................ ....................................2-1
Program Memory........................................................... ..... .... ......... ..... ..... .... ......... ..... .... .............. .............2-2
Register Architecture....... ..... ......... ..... .... ..... ......... ..... .... ..... ......... .... ..... ..... ......... .... ..... .... ....................... ....2-5
Register Page Pointer (PP)................................................................................................................2-7
Register Set1.....................................................................................................................................2-8
Register Set 2....................................................................................................................................2-8
Prime Register Space........................................................................................................................2-9
Working Registers..............................................................................................................................2-10
Using the Register Pointers...............................................................................................................2-11
Register Addressing........................... .... ......... ..... .... ..... ......... ..... .... ..... ......... ..... .... ..... ...............................2-13
Common Working Register Area (C0H–CFH)....................................................................................2-15
4-Bit Working Register Addressing....................................................................................................2-16
8-Bit Working Register Addressing....................................................................................................2-18
System and User Stacks............................................................................................................................2-20
Chapter 3 Addressing Modes
Overview................................................................................................................ ....................................3-1
Register Addressing Mode (R)..................................................................................... ......................3-2
Indirect Register Addressing Mode (IR).............................................................................................3-3
Indexed Addressing Mode (X)............................................................................................................3-7
Direct Address Mode (DA).................................................................................................................3-10
Indirect Address Mode (IA)................................................................................................................3-12
Relative Address Mode (RA)..............................................................................................................3-13
Immediate Mode (IM).......................... ..... ........ ..... ..... .... ......... ..... .... ..... ......... ..... .... ......... ..................3-14
Chapter 4 Control Registers
Overview................................................................................................................ ....................................4-1
S3F80JB MICROCONTROLLER v
Table of Contents (Continued)
Chapter 5 Interrupt Structure
Overview ....................................................................................................................................................5-1
Interrupt Types.......................................................................................... .........................................5-2
Interrupt Vector Addresses.................................................................................................................5-5
Enable/Disable Interrupt Instructions (EI, DI).....................................................................................5-7
System-Level Interrupt Control Registers...........................................................................................5-7
Interrupt Processing Control Points....................................................................................................5-8
Peripheral Interrupt Control Registers ..... ......... ..... .... ..... .... ......... ..... ..... .... ..... .... ......... ..... .... ..... .........5-9
System Mode Register (SYM).......................................................................................... ..................5-10
Interrupt Mask Register (IMR)................................... .........................................................................5-11
Interrupt Priority Register (IPR)..........................................................................................................5-12
Interrupt Request Register (IRQ).......................................................................................................5-14
Interrupt Pending Function Types......................................................................................................5-15
Interrupt Source Polling Sequence.....................................................................................................5-16
Interrupt Service Routines....................................................................................... ...........................5-16
Generating interrupt Vector Addresses..............................................................................................5-17
Nesting of Vectored Interrupts............................................................................................................5-17
Instruction Pointer (IP) ....................... ................................................................................................5-17
Fast Interrupt Processing................................................................. ..................................................5-17
Chapter 6 Instruction Set
Overview ....................................................................................................................................................6-1
Flags Register (FLAGS)........ ...................................................... ....................................................... 6-6
Flag Descriptions...............................................................................................................................6-7
Instruction Set Notation......................................................................................................................6-8
Condition Codes.................................................................................................................................6-12
Instruction Descriptions........................................................... ...........................................................6-13
Chapter 7 Clock Circuit
Overview ....................................................................................................................................................7-1
System Clock Circuit..........................................................................................................................7-1
Clock Status During Power-Down Modes ..........................................................................................7-2
System Clock Control Register (CLKCON)........................................................ ..... ......... .... ..... .... .....7-3
vi S3F80JB MICROCONTROLLER
Table of Contents (Continued)
Chapter 8 RESET
Overview................................................................................................................ ....................................8-1
Reset Sources...................................................................................................................................8-1
Reset Mechanism... ....................................................... ....................................................................8-4
External Reset Pin....................................................................... ......................................................8-4
Watch Dog Timer Reset.....................................................................................................................8-4
LVD Reset.............................................. ...........................................................................................8-4
Internal Power-On Reset ............................. ....................................................... ...............................8-5
External Interrupt Reset.....................................................................................................................8-7
Stop Error Detection & Recovery.......................................................................................................8-8
Power-Down Modes.................................... ......... .... ..... ..... ......... .... ..... ......... ..... .... ......... ..... ......................8-9
Idle Mode ... ......... ..... .... ......... ..... .... ......... ..... .... .......... .... ..... .... ......... ..... ..... ......... .... ..... ......................8-9
Back-up mode..................................................................................................... ...............................8-10
Stop Mode ..................................... ....................................................... .............................................8-11
Sources to Release Stop Mode.........................................................................................................8-12
System Reset Operation.............................. ..... .... ..... ......... .... ..... ..... ......... .... ..... ......... .... ..... .............8-14
Hardware Reset Values.....................................................................................................................8-15
Recommendation for Unusued Pins ..................................................................................... .............8-19
Summary Table of Back-Up Mode, Stop Mode, and Reset Status.....................................................8-20
Chapter 9 I/O Ports
Overview................................................................................................................ ....................................9-1
Port Data Registers............................................................................................................................9-4
Pull-Up Resistor Enable Registers.....................................................................................................9-5
S3F80JB MICROCONTROLLER vii
Table of Contents (Continued)
Chapter 10 Basic Timer and Timer 0
Overview ........................................................................................................................................... .........10-1
Basic Timer (BT)..... ...........................................................................................................................10-1
Timer 0...............................................................................................................................................10-1
Basic Timer Control Register (BTCON)..............................................................................................10-2
Basic Timer Function Description.......................................................................................................10-3
Timer 0 Control Register (T0CON)....................................................... ..............................................10-4
Timer 0 Function Description............................................. ................................................................10-6
Chapter 11 Timer 1
Overview ........................................................................................................................................... .........11-1
Timer 1 Overflow interrupt..................................................................................................................11-2
Timer 1 Capture interrupt...................................................................................................................11-2
Timer 1 Match interrupt.................................................................... ..................................................11-3
Timer 1 Control Register (T1CON)....................................................... ..............................................11-5
Chapter 12 Counter A
Overview ....................................................................................................................................................12-1
Counter A Control Register (CACON) ................................................................................................12-3
Counter A Pulse Width Calculations...................................................................................................12-4
Chapter 13 Timer 2
Overview ....................................................................................................................................................13-1
Timer 2 Overflow Interrupt..................................................................... .............................................13-2
Timer 2 Capture Interrupt...................................................................................................................13-2
Timer 2 Match Interrupt.................................................. ....................................................................13-3
Timer 2 Control Register (T2CON)....................................................... ..............................................13-5
Chapter 14 Comparator
Overview ....................................................................................................................................................14-1
Comparator Operation ....................................................................................... ................................14-3
viii S3F80JB MICROCONTROLLER
Table of Contents (Continued)
Chapter 15 Embedded Flash Memory Interface
Overview................................................................................................................ ....................................15-1
ISPTM (On-Board Programming) Sector.....................................................................................................15-3
ISP Reset Vector and ISP Sector Size...............................................................................................15-5
Flash Memory Control Registers (User Program Mode).............................................................................15-6
Flash Memory Control Register (FMCON).............................................................. ...........................15-6
Flash Memory User Programming Enable Register (FMUSR)...........................................................15-6
Flash Memory Sector Address Registers..................................... ......................................................15-7
Sector Erase .......... ....................................................... .............................................................................15-8
Programming............................................................................... ...............................................................15-12
Reading ....................................................... ....................................................... ........................................15-17
Hard Lock Protection............ ......................................................................................................................15-18
Chapter 16 Low Voltage Detector
Overview................................................................................................................ ....................................16-1
LVD....................................................................................................................................................16-1
LVD Flag............................................................................................................................................16-1
Low Voltage Detector Control Register (LVDCON)............................................................................16-3
Chapter 17 Electrical Data – 4MHz
Overview................................................................................................................ ....................................17-1
Chapter 18 Electrical Data – 8MHz
Overview................................................................................................................ ....................................18-1
Chapter 19 Mechanical Data
Overview······················································································································································19-1
Chapter 20 Development Tools Data
Overview······················································································································································20-1
Target Boards...................................................................................................................................20-1
Programming Socket Adapter...........................................................................................................20-1
TB80JB Target Board.......................................... ..... .... ..... ......... .... ..... ......... ..... .... ..... ......... .............20-2
OTP/MTP Programmer (Writer)........................................................................................................20-7
S3F80JB MICROCONTROLLER ix
List of Figures
Figure Title Page Number Number
1-1 Block Diagram (32-pin)........................................... ..................................................1-3
1-2 Block Diagram (44-pin)........................................... ..................................................1-4
1-3 Pin Assignment Diagram (32-Pin SOP Package) .....................................................1-5
1-4 Pin Assignment Diagram (44-Pin QFP Package)............................................. .........1-6
1-5 Pin Circuit Type 1 (Port 0 and Port2)........................................................................1-10
1-6 Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)......................................................1-11
1-7 Pin Circuit Type 3 (P3.0)...........................................................................................1-12
1-8 Pin Circuit Type 4 (P3.1)...........................................................................................1-13
1-9 Pin Circuit Type 5 (P3.2 and P3.3)............................................................. ..............1-13
1-10 Pin Circuit Type 6 (nRESET)....................................................................................1-14
2-1 Program Memory Address Space.............................................................................2-2
2-2 Smart Option ............................................................................................................2-3
2-3 Internal Register File Organization...........................................................................2-6
2-4 Register Page Pointer (PP)......................................................................................2-7
2-5 Set 1, Set 2, and Prime Area Register Map ..............................................................2-9
2-6 8-Byte Working Register Areas (Slices).................................................. ..................2-10
2-7 Contiguous 16-Byte Working Register Block............................................................2-11
2-8 Non-Contiguous 16-Byte Working Register Block.....................................................2-12
2-9 16-Bit Register Pair ..................................................................................................2-13
2-10 Register File Addressing...........................................................................................2-14
2-11 Common Working Register Area..............................................................................2-15
2-12 4-Bit Working Register Addressing...........................................................................2-17
2-13 4-Bit Working Register Addressing Example............................................................2-17
2-14 8-Bit Working Register Addressing...........................................................................2-18
2-15 8-Bit Working Register Addressing Example............................................................2-19
2-16 Stack Operations......................................................................................................2-20
3-1 Register Addressing .................................................................................................3-2
3-2 Working Register Addressing ...................................................................................3-2
3-3 Indirect Register Addressing to Register File................................. .... ..... .... ..... .... .....3-3
3-4 Indirect Register Addressing to Program Memory....................................................3-4
3-5 Indirect Working Register Addressing to Register File....................... .......................3-5
3-6 Indirect Working Register Addressing to Program or Data Memory..........................3-6
3-7 Indexed Addressing to Register File.........................................................................3-7
3-8 Indexed Addressing to Program or Data Memory with Short Offset..........................3-8
3-9 Indexed Addressing to Program or Data Memory.....................................................3-9
3-10 Direct Addressing for Load Instructions....................................................................3-10
3-11 Direct Addressing for Call and Jump Instructions .......................... .... ......... ..... ..... ....3-11
3-12 Indirect Addressing...................................................................................................3-12
3-13 Relative Addressing..................................................................................................3-13
3-14 Immediate Addressing..............................................................................................3-14
4-1 Register Description Format................................... ..................................................4-4
x S3F80JB MICROCONTROLLER
List of Figures (Continued)
Figure Title Page Number Number
5-1 S3C8/S3F8-Series Interrupt Types...........................................................................5-2
5-2 S3F80JB Interrupt Structure.....................................................................................5-4
5-3 ROM Vector Address Area.......................................................................................5-5
5-4 Interrupt Function Diagram.......................................................................................5-8
5-5 System Mode Register (SYM)..................................................................................5-10
5-6 Interrupt Mask Register (IMR)..................................................................................5-11
5-7 Interrupt Request Priority Groups.............................................................................5-12
5-8 Interrupt Priority Register (IPR)............................................................................ ....5-13
5-9 Interrupt Request Register (IRQ)..............................................................................5-14
6-1 System Flags Register (FLAGS)..............................................................................6-6
7-1 Main Oscillator Circuit (External Crystal or Ceramic Resonator)............................7-1
7-2 External Clock Circuit................................ ...............................................................7-1
7-3 System Clock Circuit Diagram ..... ..... .... ..... ......... ..... .... ..... ......... .... ..... .... ......... ..... ....7-2
7-4 System Clock Control Register (CLKCON)...............................................................7-3
8-1 RESET Sources of The S3F80JB.............................................. ...............................8-2
8-2 RESET Block Diagram of The S3F80JB ............ ......................................................8-3
8-3 RESET Block Diagram by LVD for The S3F80JB IN STOP MODE..........................8-4
8-4 Internal Power-On Reset Circuit........... ....................................................................8-5
8-5 Timing Diagram for Internal Power-On Reset Circuit ................................................8-6
8-6 Reset Timing Diagram for The S3F80JB in STOP mode by IPOR...........................8-7
8-7 Block Diagram for Back-up Mode.............. ...............................................................8-10
8-8 Timing Diagram for Back-up Mode Input and Released by LVD...............................8-10
9-1 S3F80JB I/O Port Data Register Format ..................................................................9-5
9-2 Pull-up Resistor Enable Registers (Port 0 and Port 2 only)......................................9-6
10-1 Basic Timer Control Register (BTCON)............................ ........................................10-2
10-2 Timer 0 Control Register (T0CON)....... ....................................................................10-5
10-3 Timer 0 DATA Register (T0DATA).............................................................. .............10-5
10-4 Simplified Timer 0 Function Diagram: Interval Timer Mode......................................10-6
10-5 Simplified Timer 0 Function Diagram: PWM Mode...................................................10-7
10-6 Simplified Timer 0 Function Diagram: Capture Mode...............................................10-8
10-7 Basic Timer and Timer 0 Block Diagram..................................................................10-9
11-1 Simplified Timer 1 Function Diagram: Capture Mode...............................................11-2
11-2 Simplified Timer 1 Function Diagram: Interval Timer Mode......................................11-3
11-3 Timer 1 Block Diagram.............................................................................................11-4
11-4 Timer 1 Control Register (T1CON)....... ....................................................................11-5
11-5 Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL).................................11-6
S3F80JB MICROCONTROLLER xi
List of Figures (Continued)
Figure Title Page Number Number
12-1 Counter A Block Diagram.............................................................. ...........................12-2
12-2 Counter A Control Register (CACON)......................................................................12-3
12-3 Counter A Registers.................................................................................................12-3
12-4 Counter A Output Flip-Flop Waveforms in Repeat Mode..........................................12-5
13-1 Simplified Timer 2 Function Diagram: Capture Mode...............................................13-2
13-2 Simplified Timer 2 Function Diagram: Interval Timer Mode...................................... 13-3
13-3 Timer 2 Block Diagram.............................................................................................13-4
13-4 Timer 2 Control Register (T2CON)...........................................................................13-5
13-5 Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL).................................13-6
14-1 Comparator Block Diagram for The S3F80JB...........................................................14-2
14-2 Conversion Characteristics.......................................................................................14-3
14-3 Comparator Mode Register (CMOD)........................................................................14-4
14-4 Comparator Input Selection Register (CMPSEL)......................................................14-4
14-5 Comparator Result Register (CMPREG)..................................................................14-5
15-1 Program Memory Address Space.............................................................................15-3
15-2 Smart Option ............................................................................................................15-4
15-3 Flash Memory Control Register (FMCON).............................................. ..................15-6
15-4 Flash Memory User Programming Enable Register (FMUSR)..................................15-6
15-5 Flash Memory Sector Address Register (FMSECH ).................................................15-7
15-6 Flash Memory Sector Address Register (FMSECL)..................................................15-7
15-7 Sector Configurations in User Program Mode ..........................................................15-8
15-8 Sector Erase Flowchart in User Program Mode................................................... .....15-9
15-9 Byte Program Flowchart in a User Program Mode....................................................15-13
15-10 Program Flowchart in a User Program Mode............................................................15-14
16-1 Low Voltage Detect (LVD) Block Diagram······················································· ·········16-2 16-2 Low Voltage Detect Control Register (LVDCON)······················································16-3
17-1 Typical Low-Side Driver (Sink) Characteristics (P3.1 only)·······································17-5 17-2 Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)······· ··················17-5 17-3 Typical Low-Side Driver (Sink) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)··························································17-6 17-4 Typical High-Side Driver (Source) Characteristics (P3.1 only)··································17-6 17-5 Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)····················17-7 17-6 Typical High-Side Driver (Source) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)··························································17-7 17-7 Stop Mode Release Timing When Initiated by an External Interrupt····················· ····17-8 17-8 Stop Mode Release Timing When Initiated by a Reset·············································17-8 17-9 Stop Mode Release Timing When Initiated by a LVD···············································17-9 17-10 Input Timing for External Interrupts (Port 0 and Port 2)············································17-10 17-11 Input Timing for Reset (nRESET Pin)·······································································17-10 17-12 Operating Voltage Range of S3F80J9······································································ 17-13
xii S3F80JB MICROCONTROLLER
List of Figures (Continued)
Figure Title Page Number Number
18-1 Typical Low-Side Driver (Sink) Characteristics (P3.1 only)··································· ····18-5 18-2 Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)·························18-5 18-3 Typical Low-Side Driver (Sink) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)········· ·················································18-6 18-4 Typical High-Side Driver (Source) Characteristics (P3.1 only)··································18-6 18-5 Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)····················18-7 18-6 Typical High-Side Driver (Source) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)········· ·················································18-7 18-7 Stop Mode Release Timing When Initiated by an External Interrupt·························18-8 18-8 Stop Mode Release Timing When Initiated by a Reset·············································18-8 18-9 Stop Mode Release Timing When Initiated by a LVD···············································18-9 18-10 Input Timing for External Interrupts (Port 0 and Port 2)············································18-10 18-11 Input Timing for Reset (nRESET Pin)·······································································18-10 18-12 Operating Voltage Range of S3F80JB·····································································18-13
19-1 32-Pin SOP Package Dimension..............................................................................19-1
19-2 44-Pin QFP Package Dimension ............................................... ...............................19-2
20-1 TB80JB Target Board Configuration·········································································20-2 20-2 50-Pin Connector Pin Assignment for TB80JB·························································20-5 20-3 TB80JB Adapter Cable for 44-QFP Package ··················· ········································20-5
S3F80JB MICROCONTROLLER xiii

List of Tables

Table Title Page Number Number
1-1 Pin Descriptions of 32-SOP......................................................................................1-7
1-2 Pin Descriptions of 44-QFP......................................................................................1-8
2-1 S3F80JB Register Type Summary................ ..... .... .......... .... ..... .... ..... ......... ..... .... ....2-5
4-1 Mapped Registers (Bank0, Set1) .............................................................................4-2
4-2 Mapped Registers (Bank1, Set1) .............................................................................4-3
4-3 Each F unction Description and Pin Assignment of P3CON in 42/44 Pin Package ...4-32
5-1 S3F80JB Interrupt Vectors ....................................................................................... 5-6
5-2 Interrupt Control Register Overview................................................... ......................5-7
5-3 Vectored Interrupt Source Control and Data Registers.............................................5-9
6-1 Instruction Group Summary......................................................................................6-2
6-2 Flag Notation Conventions.......................................................................................6-8
6-3 Instruction Set Symbols............................................................................................6-8
6-4 Instruction Notation Conventions.............................................................................. 6-9
6-5 Opcode Quick Reference.........................................................................................6-10
6-6 Condition Codes.......................................................................................................6-12
8-1 Reset Condition in STOP Mode When IPOR / LVD Control Bit is “1”
(always LVD-On) ......................................................................................................8-8
8-2 Reset Condition in STOP Mode When IPOR / LVD Control Bit is “0”.......................8-8
8-3 Set 1, Bank 0 Register Values After Reset................................ ...............................8-15
8-4 Set 1, Bank 1 Register Values After Reset................................ ...............................8-17
8-5 Reset Generation According to the Condition of Smart Option.................................8-18
8-6 Guideline for Unused Pins to Reduced Power Consumption....................................8-19
8-7 Summary of Each Mode ...........................................................................................8-20
9-1 S3F80JB Port Configuration Overview (44-QFP) ................................... ..................9-2
9-3 S3F80JB Port Configuration Overview (32-SOP).....................................................9-3
9-4 Port Data Register Summary.............................................................. ......................9-4
S3F80JB MICROCONTROLLER xv
List of Tables (Continued)
Table Title Page Number Number
15-1 Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode..............15-2
15-2 ISP Sector Size........................................................................................................15-5
15-3 Reset Vector Address...............................................................................................15-5
17-1 Absolute Maximum Ratings ......................................................................................17-2
17-2 D.C. Electrical Characteristics..................................................................................17-2
17-3 Characteristics of Low Voltage Detect Circuit...........................................................17-4
17-4 Data Retention Supply Voltage in Stop Mode......................................... .... .......... ....17-4
17-5 Input/Output Capacitance.........................................................................................17-9
17-6 A.C. Electrical Characteristics ..................................................................................17-9
17-7 Comparator Electrical Characteristics.......................................................................17-11
17-8 Oscillation Characteristics ........................................................................................17-11
17-9 Oscillation Stabilization Time........................................................................... .........17-12
17-10 AC Electrical Characteristics for Internal Flash ROM......................... ......... ..... .... .....17-13
18-1 Absolute Maximum Ratings ······················································································18-2 18-2 D.C. Electrical Characteristics··················································································18-2 18-3 Characteristics of Low Voltage Detect Circuit···························································18-4 18-4 Data Retention Supply Voltage in Stop Mode········································· ···· ·········· ····18-4 18-5 Input/Output Capacitance·························································································18-9 18-6 A.C. Electrical Characteristics ··················································································18-9 18-7 Comparator Electrical Characteristics·······································································18-11 18-8 Oscillation Characteristics ························································································18-11 18-9 Oscillation Stabilization Time··········································································· ·········18-12 18-10 AC Electrical Characteristics for Internal Flash ROM··············································18-13
20-1 Components Consisting of S3F80JB Target Board ··················································20-3 20-2 Default Setting of the Jumper in S3F80JB Target Board··········································20-4
xvi S3F80JB MICROCONTROLLER
List of Programming Tips
Description Page Number
Chapter 2 Address Spaces
Setting the Register Pointers......................................................................... .............................................2-11
Using the RPs to Calculate the Sum of a Series of Registers............................................................. ........2-12
Addressing the Common Working Register Area.......................................................................... .............2-16
Standard Stack Operations Using PUSH and POP....................................................................................2-21
Chapter 8 Reset
To Enter STOP Mode.................................................................................................................................8-10
Chapter 10 Basic Timer and Timer 0
Configuring the Basic Timer.......................................................................... .............................................10-11
Programming Timer 0......................................................................................... ........................................10-12
Chapter 12 Counter A
To Generate 38 kHz, 1/3duty Signal Through P3.1.............................................................. ......................12-6
To Generate a one Pulse Signal Through P3.1............................... ...........................................................12-7
Chapter 15 Embedded Flash Memory Interface
Sector Erase .......... ....................................................... .............................................................................15-10
Programming............................................................................... ...............................................................15-15
Reading ....................................................... ....................................................... ........................................15-17
Hard Lock Protection............ ......................................................................................................................15-18
S3F80JB MICROCONTROLLER xvii

List of Register Descriptions

Register Full Register Name Page Identifier Number
BTCON Basic Timer Control Register....................................................................................4-5
CACON Counter A Control Register ....................... ......... ..... .... ..... ......... .... ..... .... ......... ..... ....4-6
CLKCON System Clock Control Register...................... ...........................................................4-7
CMOD Comparator Mode Register......................................................................................4-8
CMPSEL Comparator Input Selection Register........................................................................4-9
EMT External Memory Timing Register................................................. ...........................4-10
FLAGS System Flags Register.............................................................................................4-11
FMCON Flash Memory Control Register............................................................... .................4-12
FMSECH Flash Memory Sector Address Register (High Byte)................................................4-13
FMSECL Flash Memory Sector Address Register (Low Byte).................................................4-13
FMUSR Flash Memory User Programming Enable Register..................................................4-13
IMR Interrupt Mask Register............................................................................................4-14
IPH Instruction Pointer (High Byte)..................................................................................4-15
IPL Instruction Pointer (Low Byte)..................................................................................4-15
IPR Interrupt Priority Register..........................................................................................4-16
LVDCON LVD Control Register.............................................................................................4-18
P0CONL Port 0 Control Register (Low Byte)...........................................................................4-20
P0INT Port 0 External Interrupt Enable Register.................................................................4-21
P0PND Port 0 External Interrupt Pending Register...............................................................4-22
P0PUR Port 0 Pull-up Resistor Enable Register........................................ ...........................4-23
P1CONH Port 1 Control Register (High Byte)..........................................................................4-24
P1CONL Port 1 Control Register (Low Byte)...........................................................................4-25
P2CONH Port 2 Control Register (High Byte)..........................................................................4-26
P2CONL Port 2 Control Register (Low Byte)...........................................................................4-27
P2INT Port 2 External Interrupt Enable Register.................................................................4-28
P2PND Port 2 External Interrupt Pending Register...............................................................4-29
P3CON Port 3 Control Register......................... ....................................................... .............4-31
P345CON Port3[4:5] Control Register .......................................................................................4-33
P4CON Port 4 Control Register......................... ....................................................... .............4-34
P4CONH Port 4 Control Register (High Byte)..........................................................................4-35
P4CONL Port 4 Control Register (Low Byte)...........................................................................4-36
PP Register Page Pointer..............................................................................................4-37
RP0 Register Pointer 0.....................................................................................................4-38
RP1 Register Pointer 1.....................................................................................................4-38
SPL Stack Pointer (Low Byte)......................................... .................................................4-39
STOPCON Stop Control Register...............................................................................................4-39
SYM System Mode Register.............................................................................................4-40
T1CON Timer 1 Control Register...................................................... ....................................4-42
T2CON Timer 2 Control Register...................................................... ....................................4-43
S3F80JB MICROCONTROLLER xix

List of Instruction Descriptions

Instruction Full Register Name Page Mnemonic Number
ADC Add with carry..........................................................................................................6-14
ADD Add...........................................................................................................................6-15
AND Logical AND.............................................................................................................6-16
BAND Bit AND ....................................................................................................................6-17
BCP Bit Compare.............................................................................................................6-18
BITC Bit Complement........................................................................................................6-19
BITR Bit Reset...................................................................................................................6-20
BITS Bit Set ......................................................................................................................6-21
BOR Bit OR ......................................................................................................................6-22
BTJRF Bit Test, Jump Relative on False..............................................................................6-23
BTJRT Bit Test, Jump Relative on True...............................................................................6-24
BXOR Bit XOR ....................................................................................................................6-25
CALL Call Procedure .........................................................................................................6-26
CCF Complement Carry Flag ...........................................................................................6-27
CLR Clear ........................................................................................................................6-28
COM Complement.............................................................................................................6-29
CP Compare..................................................................................................................6-30
CPIJE Compare, Increment, and Jump on Equal................................................................6-31
CPIJNE Compare, Increment, and Jump on Non-Equal ........................................................6-32
DA Decimal Adjust.........................................................................................................6-33
DA Decimal Adjust.........................................................................................................6-34
DEC Decrement................................................................................................................6-35
DECW Decrement Word......................................................................................................6-36
DIV Divide (Unsigned).....................................................................................................6-38
DJNZ Decrement and Jump if Non-Zero............................................................................6-39
EI Enable Interrupts......................................................................................................6-40
ENTER Enter ........................................................................................................................6-41
EXIT Exit...........................................................................................................................6-42
IDLE Idle Operation...........................................................................................................6-43
INC Increment.................................................................................................................6-44
INCW Increment Word........................................................................................................6-45
IRET Interrupt Return........................................................................................................6-46
JP Jump........................................................................................................................6-47
JR Jump Relative ..........................................................................................................6-48
LD Load.........................................................................................................................6-49
LD Load.........................................................................................................................6-50
LDB Load Bit....................................................................................................................6-51
LDC/LDE Load Memory...........................................................................................................6-52
LDC/LDE Load Memory...........................................................................................................6-53
LDCD/LDED Load Memory and Decrement..................................................................................6-54
LDCI/LDEI Load Memory and Increment....................................................................................6-55
LDCPD/LDEPD Load Memory with Pre-Decrement......................... ..... ..... .... ......... ..... .... ..... ......... ....6-56
LDCPI/LDEPI Load Memory with Pre-Increment........................................................... ..... ..... .... ....6-57
LDW Load Word................................................................................................................6-58
MULT Multiply (Unsigned)...................................................................................................6-59
S3F80JB MICROCONTROLLER xxi
List of Instruction Descriptions (Continued)
Instruction Full Register Name Page Mnemonic Number
NEXT Next..........................................................................................................................6-60
NOP No Operation............................................................................................................6-61
OR Logical OR................................................................................................................6-62
POP Pop From Stack ...................................................... ..................................................6-63
POPUD Pop User Stack (Decrementing)............................................................. ..................6-64
POPUI Pop User Stack (Incrementing)................................................. ................................6-65
PUSH Push To Stack........................................................ ..................................................6-66
PUSHUD Push User Stack (Decrementing)........................................................... ..................6-67
PUSHUI Push User Stack (Incrementing)........................................... .................................... 6-68
RCF Reset Carry Flag ......................................................................................................6-69
RET Return.......................................................................................................................6-70
RL Rotate Left................................................................................................................6-71
RLC Rotate Left Through Carry........................................................................................6-72
RR Rotate Right .............................................................................................................6-73
RRC Rotate Right Through Carry........................................................... ...........................6-74
SB0 Select Bank 0 ...........................................................................................................6-75
SB1 Select Bank 1 ...........................................................................................................6-76
SBC Subtract With Carry ..................................................................................................6-77
SCF Set Carry Flag ..........................................................................................................6-78
SRA Shift Right Arithmetic................................................................................................6-79
SRP/SRP0/SRP1 Set Register Pointer .................................................................................................6-80
STOP Stop Operation .........................................................................................................6-81
SUB Subtract....................................................................................................................6-82
SWAP Swap Nibbles............................................................................................................6-83
TCM Test Complement Under Mask.................................................................................6-84
TM Test Under Mask ......................................................................................................6-85
WFI Wait For Interrupt......................................................................................................6-86
XOR Logical Exclusive OR................................................................................................6-87
xxii S3F80JB MICROCONTROLLER

S3F80JB PRODUCT OVERVIEW

1 PRODUCT OVERVIEW
S3C8/S3F8-SERIES MICROCONTROLLERS
Samsung's S3C8/S3F8-series of 8-bit single-chip CM OS mi crocon trollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include :
— Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupts — Bu ilt-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (wit hin a minimum four CPU clocks) can be assigned to specific interrupt levels.
S3F80JB MICROCONTROLLER
The S3F80JB single-chip CMOS microcontroller is fabricated usin g a highly advanced CMOS process and is based on Samsung's newest CPU architecture.
The S3F80JB is the microcontroller which has 64-Kbyte Flash Memory ROM. Using a proven modular design approach, Samsung engineers developed S3F80JB by integrating the following
peripheral modules with the powerful SAM8 RC core: — Internal LVD circuit and 16 bit-programmable pins for external interrupts.
— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset). — One 8-bit Timer/counter with three oper at ing modes. — Two 16-bit timer/counters with selectable operating modes. — 4-bit analog voltage comparator with four/three channels (internal/extern al re ference). — One 8-bit counter with auto-reload function and one-shot or repeat cont rol.
The S3F80JB is a versatile general-purpose microcont rol ler, which is especially suitable for use as remote transmitter controller. It is currently av ailable in a 32-pin SOP and 44-pin QFP package.
1-1
PRODUCT OVERVIEW S3F80JB
FEATURES
CPU
• SAM8 RC CPU core
Memory
• Program memory:
- 64-Kbyte Internal Flash Memory
- Sector size: 128Bytes
- 10years data retention
- Fast Programming Time: Sector Erase: 10ms Byte Program: 32us
- Byte Programmable
- User programmable by ‘LDC’ instruction
- Sector (128-bytes) Erase available
- External serial programming support
- Endurance: 10,000 Erase/Program cycles
- Expandable OBPTM (On Board Program)
• Data memory: 272-byte general purpose RAM
Instruction Set
• 7 8 in stru ctions
• I DLE and STOP instructions added for power-
down modes
Instruction Execution Time
• 500 ns at 8-MHz f
(minimum)
OSC
Interrupts
• 24 interrupt sources with 18 vectors
and 8 levels.
I/O Ports
• Fou r 8- bit I / O p orts (P0–P2 , P4) and 6-bit port
(P3) for a total of 38 bit-programmable p i ns. (44-QFP)
• Fo ur 8 -bit I/O ports (P0–P2 , P4) and 4-bit port
(P3) for a total of 36 bit-programmable p i ns. (42-SDIP)
• Th ree 8-bit I/O ports (P0–P2) and one 2-bit I / O
port (P3) for a total of 26-bit prog ramma ble pins. (32-SOP)
Carrier Frequency Generator
• One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)
Basic Timer and Timer/Counters
• One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer (software reset) function
• One 8-bit timer/counter (Timer 0) with three
operating modes: Interval mode, Capture and PWM mode.
• One 16-bit timer/counter (Timer1) with two
operating modes: Interval and Cap tu re mo de.
• One 16-bit timer/counter (Timer2) with two
operating modes: Interval and Cap tu re mo de.
Back-up Mode
• When V
is lower than V
DD
, the chip enters
LVD
Back-up mode to block oscillation and reduce the current consumption.
In S3F80JB, this function is disabled when
operating state is “STOP mode”.
• When reset pin is lower than Input Low Voltage
), the chip enters Back-up mode to block
(V
IL
oscillation and reduce the current consumption.
Analog Voltage Comparator
• 4-bit resolution: 16-step variable reference
voltage, 150mV Input Voltage Accuracy (worst case)
• 4-channel mode: CIN0-3, Internal refe ren ce
voltage generator
• 3-channel mode: CIN0-2, External reference
voltage source (CIN3) supply
Low Voltage Detect Circuit
• L ow v oltage detect to get into Back-up mode and
Reset
2.15V (Typ) ± 200mV at 8MHz
1.90V (Typ) ± 200mV at 4MHz
• Low voltage detect to control LVD_Flag bit
2.30V (Typ) ± 200mV at 8MHz
2.15V (Typ) ± 200mV at 4MHz
Operating Temperature Range
• –25
°
C to + 85 °C
Operating Voltage Range
• 1.95V to 3.6V at 8MHz
Package Types
• 32-pin SOP
• 44-pin QFP
1-2
S3F80JB PRODUCT OVERVIEW
BLOCK DIAGRAM (32-PIN PACKAGE)
P0.0-0.3 (INT0-INT3)
P0.4-P0.7(INT4)
P1.0-1.7
Port0 Port1
V
DD
X
IN
X
OUT
LVD
IPOR(note)
Main OSC
8-Bit Basic Timer
8-Bit
Timer0
/Counter
16-Bit
Timer1
/Counter
16-Bit
Timer2
/Counter
I/O Port and Interrupt
SAM8RC CPU
64K-byte
FLASH
Memory
Comparator
Control
272-byte
Register File
Carrier Generator
(Counter A)
TEST
nRESET
Port2
Port3
P2.0-2.3 (INT5-INT8)
P2.4-2.7 (INT9) (CIN0-CIN3)
P3.0/T0PWM/T0CAP/ SDAT/T1CAP/T2CAP
P3.1/REM/T0CK/SCLK
Figure 1-1. Block Diagram (32-pin)
NOTE
IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2)
1-3
PRODUCT OVERVIEW S3F80JB
BLOCK DIAGRAM (44-PIN PACKAGE)
P0.0-0.3 (INT0-INT3)
P0.4-P0.7(INT4)
P1.0-1.7
Port0 Port1
V
DD
X
IN
X
OUT
LVD
IPOR(note)
Main OSC
8-Bit Basic Timer
8-Bit
Timer0
/Counter
16-Bit
Timer1
/Counter
16-Bit
Timer2
/Counter
I/O Port and Interrupt
SAM8RC CPU
64K-byte
FLASH
Memory
Comparator
Control
272-byte
Register File
Carrier Generator
(Counter A)
TEST
nRESET
Port2
Port3
Port4
P2.0-2.3 (INT5-INT8)
P2.4-2.7 (INT9)
(CIN0-CIN3)
P3.0/T0PWM/T0CAP/SDAT P3.1/REM/SCLK
P3.2/T0CK P3.3/T1CAP/T2CAP
P3.4-P3.5
P4.0-P4.7
Figure 1-2. Block Diagram (44-pin)
NOTE
IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2)
1-4
S3F80JB PRODUCT OVERVIEW
PIN ASSIGNMENTS
VSS
XOUT
XIN
TEST P2.5/INT9/CIN1 P2.6/INT9/CIN2
nRESET
P2.7/INT9/CIN3
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S3F80JB
(Top View)
32-SOP
VDD
32
P3.1/REM/T0CK/SCLK
31
P3.0/T0PWM/T0CAP/T1CAP/T2CAP/SDAT
30
P2.4/INT9/CIN0
29
P2.3/INT8
28
P2.2/INT7
27
P2.1/INT6
26
P2.0/INT5
25
P0.7/INT4
24
P0.6/INT4
23
P0.5/INT4
22
P0.4/INT4
21 20
P0.3/INT3
19
P0.2/INT2
18
P0.1/INT1
17
P0.0/INT0
Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package)
1-5
PRODUCT OVERVIEW S3F80JB
PIN ASSIGNMENTS (Continued)
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0
P4.4
P4.5
P4.6
P1.7
P1.6
P1.5
P1.4
P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4
P4.3 P4.2 P4.1
P4.0 P2.0/INT5 P2.1/INT6 P2.2/INT7
3332313029282726252423 34 35 36 37 38 39 40 41 42 43 44
S3F80JB
(Top View)
(44-QFP)
1234567891011
DD
VSS
V
XOUT
P2.3/INT8
P2.4/INT9/CIN0
P3.1/REM/SCLK
P3.0/T0PWM/T0CAP/SDAT
P1.3
22
P1.2
21
P1.1
20
P4.7
19
P3.3/T1CAP/T2CAP
18
P3.2/T0CK
17
P1.0
16
P2.7/INT9/CIN3
15
P3.5
14
P3.4
13
nRESET
12
XIN
TEST
P2.5/INT9/CIN1
P2.6/INT9/CIN2
Figure 1-4. Pin Assignment Diagram (44-Pin QFP Package)
1-6
S3F80JB PRODUCT OVERVIEW
Table 1-1. Pin Descriptions of 32-SOP
Pin
Names
P0.0–P0.7
P1.0–P1.7
P2.0–P2.3 P2.4–P2.7
P3.0
P3.1
XOUT, XIN nRESET
TEST
VDD VSS
Pin
Type
I/O I/O port with bit-programmable pins. Configurable
to input or push-pull output mode. Pull-up resistors
Pin Description Circuit
Type
1 17–24 Ext. INT
32 Pin
No.
Functions
(INT0–INT3) are assignable by software. Pins can be assigned individually as external interrupt inp ut s wi th noi se filters, interrupt enable/ disable, and interrupt pending control. SED&R (note) circuit built in P0 for STOP releasing.
I/O I/O port with bit-programmable pins. Configurable
2 9–16 – to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type.
I/O I/O port with bit-programmable pins. Configurable
to input or push-pull output mode. Pull-up resistors
1
25–28
29,5,6,8
(INT5–INT8) can be assigned by software. Pins can be assigned individually as external inte rru pt inputs
(CIN0-CIN3) with noise filters, interrupt enable/disa ble , a nd interrupt pending control. SED & R (note) circu it built in P2-P2.7 for STOP releasing. Also P2.4­P2.7 can be assigned individually as analog input pins for Comparator.
I/O I/O port with bit-programmable pin. Configurable to
3 30 T0PWM/T0CAP input mode, push-pull output mode, or n-channel open-drain output mode. Input mode wit h a pu ll- up resistor can be assigned by software. This port 3 pin has high current drive capability. Also P3.0 can be assigned individually as an output pin for T0PWM or input pin for T0CAP. In the tool mode, P3.0 is assigned as serial MTP interface pin; SDAT
I/O I/O port with bit-programmable pin. Configurable to
4 31 REM input mode, push-pull output mode, or n-channel open-drain output mode. Input mode wit h a p ull- up resistor can be assigned by software. This port 3 pin has high current drive capability . Also P3.1 can be assigned individually as an output pin for REM. In the tool mode, P3.1 is assigned as serial MTP interface pin; SCLK
– System clock input and output pins – 2,3 –
I System reset signal input pin and back-up mode
6 7 – input.
I Test signal input pin
(for factory use only; must be connected to V
–
Power supply input pin
–
Ground pin
SS
).
– 4 –
– 32 –
– 1 –
Shared
(INT4)
Ext. INT
(INT9)
(SDAT)
(SCLK)
1-7
PRODUCT OVERVIEW S3F80JB
Table 1-2. Pin Descriptions of 44-QFP
Pin
Names
Pin
Type
Pin Description Circuit
P0.0–P0.7 I/O I/O port with bit-programmable pins.
Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED & R(note)circuit built in P0 for STOP releasing.
P1.0–P1.7 I/O I/O port with bit-programmable pins.
Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type.
P2.0–P2.3 P2.4–P2.7
I/O I/O port with bit- pro gra mmable pins.
Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED & R(note) circuit built in P2.4-P2.7 for STOP releasing. Also P2.4-P2.7 can be assigned individually as analog input pins for Comparator.
P3.0 I/O I/O port with bit- pro gra mmab le pin.
Configurable to input mode, push-pull output mode, or n-channel open-drai n output mode. Input mode with a pull-up resistor can be assigned by software. This port 3pin has high current drive capability. Also P3.0 can be assigned individually as an output pin for T0PWM or input pin for T0CAP. In the tool mode, P3.0 is assigned as serial MTP interface pin; SDAT
Type
44 Pin
No.
Shared
Functions
1 30–37 Ext. INT
(INT0–INT3)
(INT4)
2 16
–
20–26
1
42–44
1, 2,
10,11,
15
Ext. INT
(INT5–INT8)
(INT9)
(CIN0-CIN3)
3 3 T0PWM/T0CAP
(SDAT)
NOTE: SED & R means “STOP Error Detect & Recovery”. The Stop Error Detect & Recovery Circuit is used to release stop mode and prevent abnormal-stop mode. Refer to page 8-11.
1-8
S3F80JB PRODUCT OVERVIEW
Table 1-2. Pin Descriptions of 44-QFP (Continued)
Pin
Names
P3.1
Pin
Pin Description Circuit
Type
I/O I/O port with bit-prog rammable pin. Configurable to
input mode, push-pull output mode, or n-channel
44 Pin
Type
No.
4 4 REM
open-drain output mode. Input mode with a pull-up resistor can be assigned by software. This port 3pin has high current drive capability. Also P3.1 can be assigned individually as an output pin for REM. In the tool mode, P3.1 is assigned as serial MTP interface pin; SCLK
P3.2–P3.3 I C-MOS Input port with a pull-up resistor 5 17
18
P3.4–P3.5 I/O I/O port with bit-programmable pins. Configurable
2 13–14 – to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type. Pull­up resistors can be assigned by software.
P4.0–P4.7 I/O I/O port with bit-programmable pins. Configurable
to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type.
X
OUT
, XIN
– System clock input and output pins – 7,8 –
nRESET I System reset signal input pin and back-up mode
2 38–41
27–29
19
6 12 – input.
TEST I Test signal input pin
(for factory use only; must be connected to V
VDD
– Power supply input pin – 5 –
SS
.)
_ 9 _
Shared
Functions
(SCLK)
(T0CK)
(T1CAP/T2CAP)
–
VSS
– Ground pin – 6 –
1-9
PRODUCT OVERVIEW S3F80JB
PIN CIRCUITS
V
DD
Pull-Up Resistor
Ω
- typ)
Pull-up Enable
Data
Output Disable
V
DD
(55k
INPUT/OUTPUT
P2.4-P2.7 Only
External
Interrupt
Stop
V
SS
P2CONx.x
CMPSEL.0-.3
External REF (P2.7 only)
+
MUX
-
Comparator
REF
Noise
Filter
Stop Release
Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2)
1-10
S3F80JB PRODUCT OVERVIEW
PIN CIRCUITS (Continued)
V
DD
Pull-up Resistor (55k
Ω
-Typ) Pull-up Enable
V
DD
Data
INPUT/OUTPU T
Open-Drain
Output Disable
V
SS
Normal
Input
Noise
Filter
Figure 1-6. Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)
1-11
PRODUCT OVERVIEW S3F80JB
PIN CIRCUITS (Continued)
V
DD
Pull-up Resistor (55k
Ω
Pull-up Enable
P3CON.2
V
DD
-Typ)
Port 3.0 Data
T0_PWM
Open-Drain
Output Disable
P3.0 Input
T0CAP/(T1CAP/T2CAP)
M U
X
P3CON.2,6,7
M U X
Data
Noise filter
P3.0/T0PWM T0CAP/ (T1CAP/T2CAP)
V
SS
Figure 1-7. Pin Circuit Type 3 (P3.0)
1-12
S3F80JB PRODUCT OVERVIEW
PIN CIRCUITS (Continued)
V
DD
Pull-up Resistor (55k
Ω
Pull-up Enable
P3CON.5
V
DD
-Typ)
Port 3.1 Data
Carrier On/Off (P3.7)
CACON.2
Open-Drain
Output
Disable
P3.1 Input
M
Data
U X
P3CON.5,6,7
M
T0CK
U
Noise filter
X
Figure 1-8. Pin Circuit Type 4 (P3.1)
P3.1/REM /(T0CK)
V
SS
V
DD
Pull-up Resistor (55k
Ω
-Typ)
Input
T0CK : P3.2
T1CAP/T2C A P: P3.3
1-13
INPUT
P3CON.2,6,7
M
U X
Figure 1-9. Pin Circuit Type 5 (P3.2 and P3.3)
PRODUCT OVERVIEW S3F80JB
PIN CIRCUITS (Continued)
V
DD
Pull-up Resistor (500k
Ω
-Typ) nRESET
Figure 1-10. Pin Circuit Type 6 (nRESET)
1-14
S3F80JB ADDRESS SPACE

2 ADDRESS SPACE

OVERVIEW
The S3F80JB microcontroller has two types of address space: — Internal program memory (Flash memory)
— Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.
The S3F80JB has a programmable internal 64 -Kbytes Flash ROM. An external memory interface is not implemented.
There are 333 mapped registers in the int ern al register file. Of these, 272 are for gen er al- pu rpose use. ( This number includes a 16-byte working reg i st er common area that is used as a “scratch area” for d ata operations, a 192-byte prime register area, and a 64-byte area (Set 2) that is also used for stack operations). Twenty-two 8-bit registers are used for CPU and system control and 39 registers are mapped peripheral contro l and data registers.
2-1
S3F80JB ADDRESS SPACES
PROGRAM MEMORY
Program memory (Flash memory) stores program cod e or table data. The S3F80JB has 64-Kbyte of inte rnal programmable Flash memory. The program memory address range is therefore 0000H–FFFFH of Flash memory (See Figure 2-1).
The first 256 bytes of the prog ram memory (0H–0FFH) are reserved for inter ru pt vector addresses. Unused locations (0000H – 00FFH except 03CH, 03DH, 03EH and 03FH) in this address range can be used as normal program memory. The location 03CH, 03DH, 03E H an d 03 FH is used as smart option ROM cell. If you use the vector address area to store program code, be careful to avoid overwriting vector addresses stored in these locations.
The program memory address at which program execution starts after reset is 0100H(default). If you use ISP sectors as the ISP
TM
software storage, the reset vector address can be changed by setting the Smart Option.
(Refer to Figure 2-2).
TM
(Decimal)
65,536
384(256+128)byte
Internal RAM
Internal Program Memory
(Flash)
Note 1
255
000H
ISP Sector
Interrupt Vector Area
Smart Option Rom Cell
(HEX)
FFFFH
FE80H
01FFH, 02FFH, 04FFH or 08FFH 0FFH
03FH 03CH
Figure 2-1. Program Memory Address Space
S3F80JB(64Kbyte)
NOTES:
1. The size of ISP
TM
sector can be varied by Smart Option. (Refer to Figure 2-2). According to the smart option setting related to the ISP, ISP reset vector address can be changed one of addresses to be select (200H, 300H, 500H or 900H).
2. ISP
TM
sector can store On Board Program Software (Refer to chapter 15. Embedded Flash Memory Interface).
2-2
S3F80JB ADDRESS SPACES
SMART OPTION
Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can wr ite any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is 0FFH (IPOR disable, LVD enable in th e stop mode, Normal reset vector address 100 H, ISP protection disable). Before execution the program memo ry code, user can set the smart option bits according to the hardware option for user to want to select.
ROM Address: 003CH
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Not used
ROM Address: 003DH
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Not used
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
ISP Reset Vector Change Selection Bit: 0 = OBP Reset vector address 1 = Normal vector (address 100H)
ISP Reset Vector Address Selection Bits: 00 = 200H (ISP Area size: 256 bytes) 01 = 300H (ISP Area size: 512 bytes) 10 = 500H (ISP Area size: 1024 bytes) 11 = 900H (ISP Area size: 2048 bytes)
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
IPOR / LVD Control Bit 0 = IPOR enable LVD disable in the stop mode 1 = IPOR disable LVD enable in the stop mode
ROM Address: 003EH
(1)
Not used
(2)
ROM Address: 003FH
Frequency Selection Bits Operating Frequency Range 111110 = 1MHz ~ 4MHz 11111 = 1MHz ~ 8MHz
(5)
(6)
Figure 2-2. Smart Option
ISP Protection Size Selection Bits:
(4)
00 = 256 bytes 01 = 512 bytes 10 = 1024 bytes 11 = 2048 bytes
ISP Protection Enable/Disable Bit: 0 = Enable (Not erasable) 1 = Disable (Erasable)
Not used
(7)
:
(3)
2-3
S3F80JB ADDRESS SPACES
NOTES
1. By setting ISP Reset Vector Change Sele ctio n Bit (3EH.7) to ‘0’, user can have the available ISP area. If IS P Reset Vector Change Selection Bit (3EH. 7) i s ‘1’, 3EH.6 and 3EH.5 are meaningless.
2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H). If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes). If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can be assigned from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be assigned from 0100H to 08FFH (2 048bytes).
3. If ISP Protection Enable/Disable Bit is ‘0’, user can’t erase or program the ISP area selected by 3EH.1 and 3EH. 0 in flash memory.
4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP Protection Enable/Disable Bit (3EH.2) is ‘1’, 3EH.1 and 3EH.0 are meaningless.
5. If IPOR / LVD Control Bit (3FH.7) is '0', IPOR is enabled regardless of operating mode and LVD block is disabled in the STOP mode. So, the current con sumption in the stop mode can be decreased by setting IPOR / LVD Control Bit (3FH.7) to ‘0’. Although LVD block is disabled, IPOR can make power on reset on the behalf of LVD. When CPU wakes up by an y interrupts or reset sources, CPU comes back norma l op era ting mode and LVD block is re-enabled automa tically. But, user can’t disabl e LVD in the no rma l op er ating mode.
6. If IPOR / LVD Control Bit (3FH.7) is '1', LVD block will not be disabled in the STOP mode. In this case, LVD can ma ke power on reset and IPOR is disabled in the normal operating and STOP mode.
7. If Frequency Selection Bits (3FH.6-2) are '11110', operating max frequency is from 1MHz to 4MHz, and operating voltage range is from 1.7V to 3.6V. If Frequency Selection Bits (3FH.6-2) are ‘11111’, operating max frequency is from 1MHz to 8MHz, and operating voltage range is from 1.95V to 3.6V.
2-4
S3F80JB ADDRESS SPACES
REGISTER ARCHITECTURE
In the S3F80JB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byt e common area.
In case of S3F80JB the total number of addressable 8-bit registers is 333. Of these 333 registers, 22 bytes are for CPU and system control registers, 39 bytes are for peripheral control and data registers, 16 bytes are used as shared working registers, and 272 registers are for general-purpose use.
The extension of register space into sep ara tely addressable areas (sets, banks) is supported b y various addressing mode restrictions: the select bank instructions, SB0 and SB1.
Specific register types and the area occu pied in the S3F80JB internal register space are summarized in Table 2-
1.
Table 2-1. The Summary of S3F80JB Register Type
Register Type Number of Bytes
General-purpose registers (including the 16-byte common working register area, the 64-byte set 2 area and 192-byte prime register area of page 0)
CPU and system control registers 22 Mapped clock, peripheral, and I/O control and data registers
(bank 0: 27 registers, bank 1: 12 registers)
Total Addressable Bytes 333
272
39
2-5
S3F80JB ADDRESS SPACES
64
Bytes
FFH
E0H
DFH
D0H CFH
C0H
Set 1
Bank1
Bank 0
System and
Peripheral
Control Register
(Register Addressing
Mode)
System Register
(Register Addressing
Mode)
Working Register
(Working Register
Addressing only)
E0H
32
Bytes
32
Bytes
192
Bytes
Set 2
Page 0
General Purpose
Data Register
(Indirect Register or
Indexed Addressing
Modes or
Stack Operations)
Page 0
Prime
Data Register
(All Addressing
Mode)
FFH
256
Bytes
C0H BFH
00H
Figure 2-3. Internal Register File Organization
2-6
S3F80JB ADDRESS SPACES
REGISTER PAGE POINTER (PP)
The S3C8/S3F8-series architecture suppo rts the logical expansion of the physical 33 3-byte internal register files (using an 8-bit data bus) into as many as 16 sepa ra te ly addressable register pages. Page addressi ng is controlled by the register page pointer PP (D FH, Set 1, Bank0). In the S3F80JB microcontroller, a paged register file expansion is not implemented an d the register page pointer settings th er efore always point to “page 0”.
Following a reset, the page pointer's sour ce value (lower nibble) and destination va lue (up pe r nib bl e) a re al wa ys '0000'automatically. Therefore, S3F80JB is always selected page 0 as the source and destination page for register addressing. These page pointer (PP) register settings, as shown in Figure 2-4, should not be modified during normal operation.
Register Page Pointer (PP)
DFH ,Set 1, Bank0, R/W
MSB LSB
Destination Register Page Seleciton Bits:
NOTE:
.7 .6 .5 .4 .3 .2 .1 .0
Source Register Page Selection Bi t s :
Destination: page 0
A hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. These values should not be modified to address other pages.
0 0 0 00 0 0 0
Source: page 0
Figure 2-4. Register Page Pointer (PP)
2-7
S3F80JB ADDRESS SPACES
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two 32-byte register banks, bank 0 and
bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3F80JB microcontroller, bank 1 is implement ed . The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing.
The upper two 32-byte area of set 1, bank 0, (E0H–FFH) contains 31mapped system and peripheral control registers. Also, the upper 32-byte area of set1, bank1 (E0H–FFH) contains 16 mapped peripheral control register. The lower 32-byte area contains 15 system registers (D0H–DFH) and a 16-byte common working register area (C0H–CFH). You can use the common working register area as a “scratch” area for data operations being performed in other areas of the register file.
Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte working register area can only be accessed using working register addr essing. (For more information about working register addressing, please refer to Chapter 3, “Addressing Mode s,”)
REGISTER SET 2
The same 64-byte physical space that is used fo r set 1 locations C0H–FFH is logically duplicated to ad d an other 64 bytes of register space. This expanded area of the register file is called set 2. The set 2 locations (C0H–FFH) is accessible on page 0 in the S3F80JB register space.
The logical division of set 1 and set 2 is ma int ained by means of addressing mode restrictions: You can use only Register addressing mode to access set 1 locations; t o access regi st ers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode.
The set 2 register area is commonly used for stack operations.
2-8
S3F80JB ADDRESS SPACES
PRIME REGISTER SPACE
The lower 192 bytes of the 256-byte ph ysical internal register file (00H–BFH) are called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.). The prime register area on page 0 is immediately addressable follow i ng a reset.
Set 1
FFH
FCH
Bank 0
Bank 1
FFH
Page 0
E0H D0H C0H
CPU and system control
General-purpose
Peripheral and IO
C0H BFH
00H
Set 2
Page 0
Prime
Register
Area
Figure 2-5. Set 1, Set 2, and Prime Area Register Map
2-9
S3F80JB ADDRESS SPACES
WORKING REGISTERS
Instructions can access specific 8-bit register s or 16 -b it register pairs using either 4-bit or 8-bit addre ss fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit re gist e rs.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register blo ck. Usin g the register pointers, you can move this 1 6-b y te register block anywhere in the addressable register file, except for the set 2 area.
The terms slice and block are used in this manual to help you v isualize the size and relative locations of select ed working register space s:
— One working register slice is 8 bytes (eight 8-bit working registers; R0–R7 or R8–R15) — One working register block is 16 bytes (sixteen 8-bit working registers; R0–R15)
All of the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-b y te register slices are contained in register po inters RP0 and RP1.
After a reset, RP0 and RP1 alway s po int to the 16-byte common area in set 1 (C0 H–CFH).
1 1 1 1 1 X X X
RP1 (Registers R8-R15)
Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block.
0 0 0 0 0 X X X
RP0 (Registers R0-R7)
Figure 2-6. 8-Byte Working Register Areas (S lices)
Slice 32
~
Slice 1
~
FFH F8H F7H F0H
CFH C0H
10H 0FH 08H
07H 00H
Set 1 Only
2-10
S3F80JB ADDRESS SPACES
USING THE REGISTER POINTERS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
To change a register pointer value, y ou load a new value to RP0 and/or RP1 using an SRP or LD in str uct ion (see Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, we recommend that RP0 point to the "lower" slice and RP1 poi nt to the "upper" slice (see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to t he either of the two 8-byte slices in the working re gister block, you can define the working register area very flexibly to support program requirements.
PROGRAMMING TIP — Setting the Register Pointers
SRP #70H ; RP0 ← 70H, RP1 ← 78H
SRP1 #48H ; RP0 ← no change, RP1 ← 48H, SRP0 #0A0H ; RP0 ← A0H, RP1 ← no change CLR RP0 ; RP0 ← 00H, RP1 ← no change LD RP1,#0F8H ; RP0 ← no change, RP1 ← 0F8H
Register File
Contains 32
8-Byte Slices
0 0 0 0 1 X X X
RP1
0 0 0 0 0 X X X
RP0
8-Byte Slice
8-Byte Slice
0FH (R15) 08H
07H 00H (R0)
16-byte contiguous working register block
Figure 2-7. Contiguous 16-Byte Working Register Block
2-11
S3F80JB ADDRESS SPACES
F7H (R7)
8-Byte Slice
F0H (R0)
Register File
1 1 1 1 0 X X X
RP0
0 0 0 0 0 X X X
RP1
Contains 32
8-Byte Slices
07H (R15)
8-Byte Slice
00H (R0)
16-byte non-contiguous working register block
Figure 2-8. Non-Contiguous 16-Byte Working Register Block
PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H contains the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively :
SRP0 #80H ; RP0 ← 80H ADD R0,R1 ; R0 ← R0 + R1 ADC R0,R2 ; R0 ← R0 + R2 + C ADC R0,R3 ; R0 ← R0 + R3 + C ADC R0,R4 ; R0 ← R0 + R4 + C ADC R0,R5 ; R0 ← R0 + R5 + C
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruct ion cod e an d its execution time is 36 cycles. If the reg ister pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used:
ADD 80H,81H ; 80H ← (80H) + (81H) ADC 80H,82H ; 80H ← (80H) + (82H) + C
ADC 80H,83H ; 80H ← (80H) + (83H) + C ADC 80H,84H ; 80H ← (80H) + (84H) + C ADC 80H,85H ; 80H ← (80H) + (85H) + C
Now, the sum of the six registers is also locate d in registe r 80 H. However, this instruction string takes 15 byte s of instruction code instead of 12 byt es, and its execution time is 50 cycles inste ad of 36 cy cles.
2-12
S3F80JB ADDRESS SPACES
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruct ion formats to reduce execution time.
With Register (R) addressing mode, in which th e operand value is the content of a specif ic re gister or register pair, you can access all locations in the register file except for set 2. With working re gist er addressing, you use a register pointer to specify an 8-byte workin g register space in the register file and an 8-bit re gister within that space.
Registers are addressed either as a single 8-b i t register or as a paired 16-bit register space. I n a 16- bit re gister pair, the address of the first 8-bi t register is always an even number and th e ad dress of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in t h e ne xt (+ 1) odd-numbered register.
Working register addressing differs from Register addressing because it uses a register pointer to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB
Rn
LSB
Rn+1
n = Even address
Figure 2-9. 16-Bit Register Pair
2-13
S3F80JB ADDRESS SPACES
Special-Purpose Registers General-Purpose Register s
Bank 1
Bank 0
FFH
Control Registers
E0H
System
D0H
Registers
C0H BFH
RP1
Register Pointers
RP0
Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set
2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to th e co m m o n working register area).
NOTE:
In the S3F80JB microcontroller,only page0 is implemented.Page0 contain s all of the addressable registers in the internal register file.
FFH
Set 2
CFH
C0H
Prime
Registers
00H
Page 0
Indirect
Register,
Indexed
Register Addressing Only
Page 0
All
Addressing
Modes
Addressing
Can be Pointed by Registe r Po in ter
Modes
Figure 2-10. Register File Addressing
2-14
S3F80JB ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H–CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte workin g re gister block:
RP0 → C0H–C7H RP1 → C8H–CFH
This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations.
FFH
F0H
E0H
D0H C0H
Following a hareware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH.
RP0 =
RP1 =
1100 000
Set 1
FFH
C0H BFH
0
01100 100
00H
Figure 2-11. Common Working Register Area
Page 0
Set 2
Page 0
Prime
Area
~~
2-15
S3F80JB ADDRESS SPACES
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only.
Example 1:
LD 0C2H,40H ; Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H LD R2,40H ; R2 (C2H) ← the value in location 40H
Example 2:
ADD 0C3H,#45H ; Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H ADD R3,#45H ; R3 (C3H) ← R3 + 45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" tha t ma kes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits ar e con catenated in the following way to form a complete 8-bit address:
— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1); — The five high-order bits in the register pointer select an 8-byte slice of th e re gister space; — The three low-order bits of the 4-bit address select one of the eight registers in t he slice.
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction 'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the re gister address 76H (01110110B).
2-16
S3F80JB ADDRESS SPACES
RP0 RP1
Selects RP0 or RP1
Register pointer provides five high-order bits
Figure 2-12. 4-Bit Working Register Addressing
RP0
0 1 1 1 0 0 0 0
Address
Together they create an
8-bit register address
OPCODE
0 1 1 1 0 0 01
4-bit address procides three low-order bits
RP1
0 1 1 1 0 1 1 0
Figure 2-13. 4-Bit Working Register Addressing Example
2-17
Selects RP0
Register address (76H)
R6
0110 1110
OPCODE
Instruction: 'INC R6'
S3F80JB ADDRESS SPACES
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addre ssin g to acce ss registers in a selected working register area. To initiate 8-bit working register add re ssing, the upper four bits of the instruction ad dr ess must contain the value 1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same ef fect as 4-bit working register addressing.
As shown in Figure 2-13, the lower nibble of th e 8- bit address is concatenated in much the same way as f or 4 -b it addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address. The three low-order bits of the complet e a dd ress a re p rov id ed by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing. The four high-orde r bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. The five-address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH (10101011B).
These address
bits indicate
8-bit working
register
addressing
RP0 RP1
Selects RP0 or RP1
Address
1 1 0 0
Register pointer provides five high-order bits
8-bit physical address
8-bit logical address
Three low­order bits
Figure 2-14. 8-Bit Working Register Addressing
2-18
S3F80JB ADDRESS SPACES
01 1 10 1 10
Specifies working register addressing
Figure 2-15. 8-Bit Working Register Addressing Example
RP0
01 1 1 0 0 000 1 1 1 0 0 0 0
Selects RP1
R11
8-bit address from instruction 'LD R11, R2'
Register address (0ABH) 01101 110
RP1
2-19
S3F80JB ADDRESS SPACES
SYSTEM AND USER STACKS
S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system sta ck opera tions. The S3F80JB architecture supports stack operations in the internal register file.
Stack Operations
Return addresses for procedure calls, in terrupts and data are stored on the stack. The co ntents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS registers are pushed to the stack. The IRET instruction then pops t he se values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-15.
High Address
PCL
Top of
stack
PCL
PCH
Stack contents
after a call instruction
Top of
stack
Low Address
PCH
Flags
Stack contents
after an
interrupt
Figure 2-16. Stack Operations
User-Defined Stacks
You can freely define stacks in the inte rnal register file as data storage locations. Th e instructions PUSHUI, PUSHUD, POPUI, and POPUD support use r-d efined stack operations.
Stack Pointers (SPL)
Register location D9H contains the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset, the SPL value is undetermined. Be cau se only internal memory 256-byte is implemente d in The S3F80JB, the SPL must be initialized to an 8-bit value in the range 00–FFH.
2-20
S3F80JB ADDRESS SPACES
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to pe rform stack operations in the internal register f ile using PUSH and POP instructions:
LD SPL,#0FFH ; SPL ← FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine)
•
•
PUSH PP ; Stack address 0FEH ← PP PUSH RP0 ; Stack address 0FDH ← RP0
PUSH RP1 ; Stack address 0FCH ← RP1 PUSH R3 ; Stack address 0FBH ← R3
•
•
POP R3 ; R3 ← Stack address 0FBH
POP RP1 ; RP1 ← Stack address 0 F CH POP RP0 ; RP0 ← Stack address 0 F DH
POP PP ; PP ← Stack address 0FEH
•
•
2-21
S3F80JB ADDRESSING MODES

3 ADDRESSING MODES

OVERVIEW
The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data opera nd . The operands specified in instructions may be condit ion code s, immediate data, or a location in the register file, program memory, or data memory.
The S3C8/S3F8-series instruction set supp orts seven explicit addressing modes. Not all of t he se addressing modes are available for each instruction:
— Register (R) — Indirect Register (IR) — Indexed (X) — Direct Address (DA) — Indirect Address (IA) — Rel ative Address (RA) — Immediate (IM)
3-1
ADDRESSING MODES S3F80JB
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing because it uses a register pointer to specify an 8­byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory Register File
8-bit register
file address
One-Operand
Instruction
(Example)
Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address
dst
OPCODE
Points to one
register in register
file
Value used in
instruction execution
OPERAND
Figure 3-1. Register Addressing
4-bit
Working Register
Two-Operand
Instruction (Example)
Register File
MSB Points to
RP0 ot RP1
Program Memory
dst
OPCODE
Sample Instruction: ADD R1, R2 ; Where R1 and R2 are registers in the curruntly
src
3 LSBs
Points to the
woking register
(1 of 8)
selected working register area.
RP0 or RP1
Selected RP points to start of working register block
OPERAND
Figure 3-2. Working Register Addressing
3-2
S3F80JB ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction use d, the actual address may point to a register in t he reg ister file, to program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. An y 16- bit register pair can be used to indirectly address another memory loca tion. Remember, however, that loca tions C0H–FFH in set 1 cannot be accessed using Indirect Register addressing mode.
Program Memory Register File
8-bit register
file address
One-Operand
Instruction
(Example)
dst
OPCODE
Points to one
register in register
file
Address of operand
used by instruction
ADDRESS
Value used in
instruction execution
Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address.
OPERAND
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES S3F80JB
INDIRECT REGISTER ADDRESSING MODE (Co n ti nued)
Register File
Program Memory
Example
Instruction
References
Program
Memory
Sample Instructions: CALL @RR2
JP @RR2
Register
dst
OPCODE
Points to
Register Pair
Value used in
instruction
Pair
Program Memory
OPERAND
Figure 3-4. Indirect Register Addressing to Program Memory
16-Bit Address Points to Program Memory
3-4
S3F80JB ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
MSB Points to
4-bit Working Register Address
Program Memory
dst
OPCODE
src
RP0 or RP1
3 LSBs
Point to the
Woking Register
(1 of 8)
RP0 or RP1
~ ~
ADDRESS
Selected RP points to start of woking register block
~ ~
Sample Instruction: OR R3, @R6
Value used in
instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES S3F80JB
INDIRECT REGISTER ADDRESSING MODE (Co n ti nued)
Register File
MSB Points to
4-bit Working
Register Address
Example Instruction
References either
Program Memory or
Data Memory
Program Memory
dst
OPCODE
src
RP0 or RP1
Next 2-bit Point
to Working
Register Pair
(1 of 4)
LSB Selects
Value used in
Instruction
RP0 or RP1
Register
Pair
Program Memory
or
Data Memory
OPERAND
Selected RP points to start of working register block
16-Bit address points to program memory or data memory
Sample Instructions: LCD R5,@RR6 ; Program memory access
LDE R3,@RR14 ; External data memory access LDE @RR4, R8 ; External data memory access
NOTE:
LDE command is not available, because an external interface is not implemented for the S3F80JB.
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
S3F80JB ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective oper an d a ddress (see Figure 3–7). You can use Indexed addre ssin g mode to access locations in the internal register file or in external memory (if implemented). You cannot, however, access locations C0H–FFH in set 1 using indexed addressin g.
In short offset Indexed addressing mode, the 8-bit displacement is treat e d as a signed integer in the range –128 to +127. This applies to external memory accesses only (see Figure 3–8).
For register file addressing, an 8-bit base ad dress provided by the instruction is added t o an 8-b i t offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see Figure 3–9).
The only instruction that supports index ed addressing mode for the internal regist er f ile i s th e Load instruction (LD). The LDC and LDE instructions sup port indexed addressing mode for internal program memory and for external data memory (if implemented).
Register File
Two-Operand Instruction Example
Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value.
MSB Points to RP0 or RP1
RP0 or RP1
~
Value used in Instruction
+
Program Memory
Base Address
dst/src
OPCODE
x
Figure 3-7. Indexed Addressing to Register File
3 LSBs
Points to one of the
Woking Registers
(1 of 8)
OPERAND
~ ~
~
Selected RP points to start of working register block
INDEX
3-7
ADDRESSING MODES S3F80JB
INDEXED ADDRESSING MODE (Continued)
Register File
MSB Points to
4-bit Working
Register Address
Program Memory
OFFSET
dst/src
OPCODE
x
RP0 or RP1
NEXT 2 BITS
Point to Working
Register Pair
(1 of 4)
LSB Selects
RP0 or RP1
~ ~
Register
Pair
Program Memory
or
Data Memory
Selected RP points to start of working register block
16-Bit address added to offset
+
8-Bit
16-Bit
16-Bit
Sample Instructions: LDC R4, #04H[RR2] ; The values in the program address (RR2 + 04H)
are loaded into register R4.
LDE R4,#04H[RR2] ; Identical operation to LDC example, except that
external data memory is accessed.
NOTE:
LDE command is not available, because an external interface is not implemented for the S3F80JB.
OPERAND
Value used in Instruction
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
S3F80JB ADDRESSING MODES
INDEXED ADDRESSING MODE (Continued)
Register File
MSB Points to
4-bit Working
Register Address
Program Memory
OFFSET OFFSET
dst/src
OPCODE
x
RP0 or RP1
NEXT 2 BITS
Point to Working
Register Pair
LSB Selects
RP0 or RP1
Register
Pair
Program Memory
or
Data Memory
~~
Selected RP points to start of working register block
16-Bit address added to offset
+
16-Bit
16-Bit
16-Bit
Sample Instructions: LDC R4, #1000H[RR2] ; The values in the program address (RR2 + 1000H)
are loaded into register R4.
LDE R4,#1000H[RR2] ; Identical operation to LDC example, except that
external data memory is accessed.
NOTE:
LDE command is not available, because an external interface is not implemented for the S3F80JB.
OPERAND
Value used in Instruction
Figure 3-9. Indexed Addressing to Program or Data Memory
3-9
ADDRESSING MODES S3F80JB
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mod e t o sp ecify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Memory
Program Memory
Address Used
Upper Address Byte
Lower Address Byte
dst/src
Sample Instructions: LDC R5,1234H ; The values in the program address (1234H) LDE R5,1234H ; Identical operation to LDC example, except
NOTE:
LDE command is not available, because an external interface is not implemented for the S3F80JB.
"0" or "1"
OPCODE
are loaded into register R5. that external data memory is accessed.
LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory
Figure 3-10. Direct Addressing for Load Instructions
3-10
S3F80JB ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Program Memory Address Used
Lower Address Byte Upper Address Byte
OPCODE
Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address
CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES S3F80JB
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, th e instruction specifies an address located in the lo west 256 bytes of the program memory. The selected pair of memory l oca tions contains the actual address of the next instruction to be executed. Only the CALL instruction can use th e Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros.
Program Memory
Next Instruction
LSB Must be Zero
Current
Instruction
Lower Address Byte Upper Address Byte
Sample Instruction: CALL #40H ; The 16-bit value in program memory addresses 40H
and 41H is the subroutine start address.
dst
OPCODE
Program Memory Locations 0-255
Figure 3-12. Indirect Addressing
3-12
S3F80JB ADDRESSING MODES
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC cont a ins the address of the instruction immediately following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJR T, DJNZ, CPIJE, CPIJNE, and JR.
Program Memory
Next OPCODE
Displacement
Current Instruction
Sample Instructions: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128
OPCODE
Program Memory Address Used
Current
PC Value
Signed Displacement Value
+
Figure 3-13. Relative Addressing
3-13
ADDRESSING MODES S3F80JB
IMMEDIATE MODE (IM)
In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in leng th, depending on the instruction used. Immediate addressing mode is useful for loading constant valu es in to registers.
Program Memory
OPERAND
OPCODE
(The operand value is in the instruction)
Sample Instruction: LD R0,#0AAH
Figure 3-14. Immediate Addressing
3-14
S3F80JB CONTROL REGISTERS

4 CONTROL REGISTERS

OVERVIEW
In this section, detailed descriptions of the S3F80JB control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the st an da rd reg i ste r d escrip tion format.
Control register descriptions are arrang ed in a l ph abetical order ( detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual.
Data and counter registers are not described in detail in this reference section. More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual.
A~Z) according to the register mnemonic. More
4-1
CONTROL REGISTERS S3F80JB
Table 4-1. Mapped Registers (Bank0, Set1)
Register Name Mnemonic Decimal Hex R/W
Timer 0 Counter T0CNT 208 D0H
R
(NOTE)
Timer 0 Data Register T0DATA 209 D1H R/W Timer 0 Control Register T0CON 210 D2H R/W Basic Timer Control Register BTCON 211 D3H R/W Clock Control Register CLKCON 212 D4H R/W System Flags Register FLAGS 213 D5H R/W Register Pointer 0 RP0 214 D6H R/W Register Pointer 1 RP1 215 D7H R/W
Location D8H is not mapped. Stack Pointer (Low Byte) SPL 217 D9H R/W Instruction Pointer (High Byte) IPH 218 DAH R/W Instruction Pointer (Low Byte ) IPL 219 DBH R/W Interrupt Request Register IRQ 220 DCH
R
(NOTE)
Interrupt Mask Register IMR 221 DDH R/W System Mode Register SYM 222 DEH R/W Register Page Pointer PP 223 DFH R/W Port 0 Data Register P0 224 E0H R/W Port 1 Data Register P1 225 E1H R/W Port 2 Data Register P2 226 E2H R/W Port 3 Data Register P3 227 E3H R/W Port 4 Data Register P4 228 E4H R/W Port 2 Interrupt Enable Registe r P2IN T 229 E5H R/W Port 2 Interrupt Pending Reg i ster P2PND 230 E6H R/W Port 0 Pull-up Resistor Enable Register P0PUR 231 E7H R/W Port 0 Control Register (High Byt e) P0CONH 232 E8H R/W Port 0 Control Register (Low Byt e) P0CONL 233 E9H R/W Port 1 Control Register (High Byt e) P1CONH 234 EAH R/W Port 1 Control Register (Low Byt e) P1CONL 235 EBH R/W Port 2 Control Register (High Byt e) P2CONH 236 ECH R/W Port 2 Control Register (Low Byt e) P2CONL 237 EDH R/W Port 2 Pull-up Enable Register P2PUR 238 EEH R/W Port 3 Control Register P3CON 239 EFH R/W Port 4 Control Register P4CON 240 F0H R/W Port 0 Interrupt Enable Registe r P0INT 241 F1H R/W Port 0 Interrupt Pending Reg ister P0PND 242 F2H R/W
4-2
S3F80JB CONTROL REGISTERS
Table 4-1. Mapped Registers (Continued)
Register Name Mnemonic Decimal Hex R/W
Counter A Control Register CACON 243 F3H R/W Counter A Data Register (High Byte) CADATAH 244 F4H R/W Counter A Data Register (Low Byte) CADATAL 245 F5H R/W Timer 1 Counter Register (High Byte) T1CNTH 246 F6H Timer 1 Counter Register (Low Byte) T1CNTL 247 F7H
R R
(NOTE) (NOTE)
Timer 1 Data Register (High Byte) T1DATAH 248 F8H R/W Timer 1 Data Register (Low Byte) T1DATAL 249 F9H R/W Timer 1 Control Register T1CON 250 FAH R/W STOP Control Register STOPCON 251 FBH W
Location FCH is not mapped.
Basic Timer Counter BTCNT 253 FDH
R
(NOTE)
External Memory Timing Register EMT 254 FEH R/W Interrupt Priority Register IP R 255 FFH R/W
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
Table 4-2. Mapped Registers (Bank1, Set1)
Register Name Mnemonic Decima l Hex R/W
LVD Control Register LVDCON 224 E0 R/W Port 3 [4:5] Control Register P345CON 225 E1 R/W Port 4 Control Register (High Byte) P4CONH 226 E2 R/W Port 4 Control Register (Low Byte) P4CONL 227 E3 R/W Timer 2 Counter Register (High Byte ) T2CNTH 228 E4 Timer 2 Counter Register (Low Byte) T2CNTL 229 E5
R R
(NOTE) (NOTE)
Timer 2 Data Register (High Byte) T2DATAH 230 E6 R/W Timer 2 Data Register (Low Byte) T2DATAL 231 E7 R/W Timer 2 Control Register T2CON 232 E8 R/W Comparator Mode Register CMOD 233 E9 R/W Comparison Result Register CMPREG 234 EA
R
(NOTE)
Comparator Input Selection Register CMPSEL 235 EB R/W Flash Memory Sector Address Register (High Byte ) FMSECH 236 EC R/W Flash Memory Sector Address Register (Low Byte) FMSECL 237 ED R/W Flash Memory User Programming Enable Register FMUSR 238 EE R/W Flash Memory Control Register FMCON 239 EF R/W
Not mapped in address F0H to 0FFH.
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
4-3
CONTROL REGISTERS S3F80JB
Bit number(s) that is/are appended to the register name for bit addressing
Register
mnemonic
FLAGS
Bit Identifier Reset Value Read/Write
.7 Carry Flag Bit (C)
.6
.5
Full register name
- System Flags Register
.7 .6 .5 .4 .2.3 .1 .0
x
R/WxR/W
0 Operation dose not generate a carry or borrow condition 1 Operation generates carry-out or borrow into high-order bit7
Zero Flag Bit (Z)
0 Operation result is a non-zero value 1 Operation result is zero
Sign Flag Bit (S)
0 Operation generates positive number (MSB = "0") 1 Operation generates negative number (MSB = "1")
Name of individual
bit or bit function
x
R/W
x
R/W
Register address
(Hexadecimal)
D5H
x
R/W
x
R/W
Register address (Set )
Register address (Bank )
Set1 Bank0
0
R/W
0
R/W
R = Read-only W = Write-only R/W = Read/write ' - ' = Not used
Addressing mode or modes you can use to modify register values
Description of the effect of specific bit settings
RESET value notation: '-' = Not used 'x' = Undetermind value '0' = Logic zero '1' = Logic one
Bit number: MSB = Bit 7 LSB = Bit 0
Figure 4-1. Register Description Format
4-4
S3F80JB CONTROL REGISTERS
BTCON — Basic Timer Control Register D3H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 – .4 Watchdog Timer Function Enable Bits (for System Reset)
.3 and .2 Basic Timer Input Clock Selection Bits
.1
.0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
1 0 1 0 Disable watchdog timer function Any other value Enable watchdog timer function
f
0 0 0 1 1 0
OSC
f
OSC
f
OSC
/4096 /1024 /128
1 1 Not used for S3F80JB.
(1)
Basic Timer Counter Clear Bit
0 No effect 1 Clear the basic timer counter value
(2)
Clock Frequency Divider Clear Bit for Basic Timer and Timer 0
0 No effect 1 Clear both block frequency dividers
NOTES:
1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to ‘00H’. Immediately following the write operation, the BTCON.1 value is automatically cleared to “0”.
2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to '00H'. Immediately following the write operation, the BTCON.0 value is automatically cleared to "0".
4-5
CONTROL REGISTERS S3F80JB
CACON — Counter A Control Register F3H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6 Counter A Input Clock Selection Bits
.5 and .4 Counter A Interrupt Timing Selection Bits
.3 Counter A Interrupt Enable Bit
.2 Counter A Start Bit
.1 Counter A Mode Selection Bit
.0 Counter A Output Flip-Flop Control Bit
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
f
0 0 0 1 1 0 1 1
0 0 Elapsed time for Low data value 0 1 Elapsed time for High data value 1 0 Elapsed time for combined Low and High data values 1 1 Not used for S3F80JB.
0 Disable interrupt 1 Enable interrupt
0 Stop counter A 1 Start counter A
0 One-shot mode 1 Repeating mode
0 Flip-Flop Low level (T-FF = Low) 1 Flip-flop High level (T-FF = High)
OSC
f
OSC
f
OSC
f
OSC
/2 /4 /8
4-6
S3F80JB CONTROL REGISTERS
CLKCON — System Clock Control Register D4H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 – .5
.4 and .3
1 0
.2 – .0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Not used for S3F80JB
(1)
CPU Clock (System Clock) Selection Bits
/16
0 0 0 1
1 1
Subsystem Clock Selection Bits
f
OSC
f
/8
OSC
/2
f
OSC
f
(non-divided)
OSC
(2)
1 0 1 Not used for S3F80JB.
Other value Select main system clock (MCLK)
NOTES:
1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster cloc k speeds, load the appropriate values to CLKCON.3 and CLKCON.4.
2. These selection bits CLKCON.0, .1, .2 are required only for systems that have a main clock and a subsystem clock. The S3F80JB uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.
4-7
CONTROL REGISTERS S3F80JB
CMOD — Comparator Mode Register E9H Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 Comparator Enable Bit
.6 Conversion Timer Control Bit
1
.5 External Reference Selection Bit
.4
.3 – .0 Reference Voltage Selection Bits
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 Comparator operation disable 1 Comparator operat ion enable
8 × 2 8 × 2
7
/ f
, 256 at 8 MHz
OSC
4
/ f
, 32 at 8 MHz
OSC
0
0 Internal reference, CIN0-3: Analog input 1 External reference, CIN0-2: Analog input, CIN3: Reference inpu t
Not used for S3F80JB.
= V
Selected V
REF
× (N + 0.5)/16, N = 0 to 15
DD
NOTE: You can select the number of analog input pin for your purpose by setting the CMPSEL.
4-8
S3F80JB CONTROL REGISTERS
CMPSEL — Comparator Input Selection Register EBH Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7– .4
.3 P2.7 Function Selection Bit
.2 P2.6 Function Selection Bit
.1 P2.5 Function Selection Bit
.0 P2.4 Function Selection Bit
– – – – 0 0 0 0 – – – – R/W R/W R/W R/W
Register addressing mode only
Not used for S3F80JB.
0 Normal I/O selection 1 Alternativ e f un c t i on enable: CIN3
0 Normal I/O selection 1 Alternativ e f un c t i on enable: CIN2
0 Normal I/O selection 1 Alternativ e f un c t i on enable: CIN1
0 Normal I/O selection 1 Alternativ e f un c t i on enable: CIN0
NOTE: If a bit of CMPSEL is set to “1”(Comparator input is selected), the port pin is operated as comparator input regardless of the P2CONH settings.
4-9
CONTROL REGISTERS S3F80JB
EMT — External Memory Timing Register
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 External WAIT Input Function Enable Bit
.6 Slow Memory Timing Enable Bit
.5 and .4 Program Memory Automatic Wait Control Bits
.3 and .2 Data Memory Automatic Wait Control Bits
.1 Stack Area Selection Bit
.0
0 1 1 1 1 1 0 –
R/W R/W R/W R/W R/W R/W R/W –
Register addressing mode only
0 Disable WAIT input function for external device 1 Enable WAIT input function for external device
0 Disable slow memory timing 1 Enable slow memory timing
0 0 No wait 0 1 Wait one cycle 1 0 Wait two cycles 1 1 Wait three cycles
0 0 No wait 0 1 Wait one cycle 1 0 Wait two cycles 1 1 Wait three cycles
0 Select internal register file area 1 Select external data memory area
Not used for S3F80JB
(NOTE)
FEH Set1 Bank0
NOTE: The EMT register is not used for S3F80JB, because an external peripheral interface is not implemented in the
S3F80JB. The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT values during normal operation may cause a system malfunction.
4-10
S3F80JB CONTROL REGISTERS
FLAGS — System Flags Register D5H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 Carry Flag Bit (C) 0 Operation does not generate a carry or borrow condition
.6 Zero Flag Bit (Z)
.5 Sign Flag Bit (S)
.4 Overflow Flag Bit (V)
.3 Decimal Adjust Flag Bit (D)
1 Subtraction operation completed
.2 Half-Carry Flag Bit (H)
.1 Fast Interrupt Status Flag Bit (FIS)
.0 Bank Address Selection Flag Bit (BA) 0 Bank 0 is selected
x x x x x x 0 0
R/W R/W R/W R/W R/W R/W R R/W
Register addressing mode only
1 Operation genera tes a carry-out or borrow into high-order bit 7
0 Operation result is a n on- zero value 1 Operation result is zero
0 Operation genera t es a po sitive number (MSB = "0") 1 Operation gene ra tes a negative number (MSB = "1" )
0
Operation result is ≤ +127 or ≥ –128
1 Operation result is > +127 or < –128
0 Add operation completed
0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3
0 Interrupt return (IRET) in progress (when read) 1 Fast interrupt service routine in progress (when read)
1 Bank 1 is selected
4-11
CONTROL REGISTERS S3F80JB
FMCON — Flash Memory Control Register EFH Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 – .4 Flash Memory Mode Selection Bits
0110
.3 – .1
.0 Flash Operation Start Bit (available for Erase and Hard Lock mode only)
0 0 0 0 – – – 0
R/W R/W R/W R/W – – – R/W
Register addressing mode only
0101 Programming mode 1010 Erase mode
(NOTE)
Hard Lock mode
Others Not used for S3F80JB
Not used for S3F80JB
0 Operation stop 1 Operation start (a uto clear bit)
NOTE: Hard Lock mode is one of the flash protection modes. Refer to page 15-18.
4-12
S3F80JB CONTROL REGISTERS
FMSECH — Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 – .0 Flash Memory Sector Address (High Byte)
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Note: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.
FMSECL — Flash Memory Sector Address Register(Low Byte) EDH Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 – .0 Flash Memory Sector Address (Low Byte)
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
Note: The low-byte flash memory sector address poin ter value is the lower eight bits of the 16-bit pointer address.
FMUSR — Flash Memory User Programming Enabl e Register EEH Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write Addressing Mode
.7—.0 Flash Memory User Programming Enable Bits
1 0 1 0 0 1 0 1 Enable user programming mode Other values Disable user programming mode
NOTES:
1. To enable flash memory user programming, write 10100101B to FMUSR.
2. To disable flash memory operation, write other value except 10100101B into FMUSR.
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
4-13
CONTROL REGISTERS S3F80JB
IMR — Interrupt Mask Register DDH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4 0 Disable (mask)
.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
.5 Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P2.7–P2.4
.4 Interrupt Level 4 (IRQ4) Enable Bit; External Interrupts P2.3–P2.0
.3 0 Disable (mask)
.2 Interrupt Level 2 (IRQ2) Enable Bit; Counter A Interrupt
.1 Interrupt Level 1 (IRQ 1) Enable Bit; Timer 1 Match or Overfl ow
.0 Interrupt Level 0 (IRQ 0) Enable Bit; Timer 0 Match or Overfl ow
x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
1 Enable (un-mask)
0 Disable (mask) 1 Enable (un-mask)
0 Disable (mask) 1 Enable (un-mask)
0 Disable (mask) 1 Enable (un-mask)
Interrupt Level 3 (IRQ3) En abl e Bit; Timer 2 Match or Overflow
1 Enable (un-mask)
0 Disable (mask) 1 Enable (un-mask)
0 Disable (mask) 1 Enable (un-mask)
0 Disable (mask) 1 Enable (un-mask)
4-14
S3F80JB CONTROL REGISTERS
IPH — Instruction Pointer (High Byte) DAH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value
Read/Write Addressing Mode
.7 – .1 Instruction Pointer Address (High Byte)
x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH).
IPL — Instruction Pointer (Low Byte) DBH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 – .0 Instruction Pointer Address (Low Byte)
x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH register (DAH).
4-15
CONTROL REGISTERS S3F80JB
IPR — Interrupt Priority Register FFH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C
0 0 0 Group priority undefined 0 0 1 B > C > A 0 1 0 A > B > C 0 1 1 B > A > C 1 0 0 C > A > B 1 0 1 C > B > A 1 1 0 A > C > B 1 1 1 Group priority undefined
.6 Interrupt Subgroup C Priority Control Bit
.5 Interrupt Group C Priority Control Bit
.3
.2
.0 Interrupt Group A Priority Control Bit
x x x x x x x x
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 IRQ6 > IRQ7 1 IRQ7 > IRQ6
0 IRQ5 > (IRQ6, IRQ7) 1 (IRQ6, IRQ7 ) > IRQ 5
Interrupt Subgroup B Priority Control Bit
0 IRQ3>IRQ4 1 IRQ4>IRQ3
Interrupt Group B Priority Control Bit
0 IRQ2 >(IRQ3, IRQ4) 1 (IRQ3, IRQ4 ) > IRQ 2
0 IRQ0 > IRQ1 1 IRQ1 > IRQ0
(See Note)
(See Note)
NOTE: The S3F80JB interrupt structure uses eight levels: IRQ0-IRQ7.
4-16
S3F80JB CONTROL REGISTERS
IRQ — Interrupt Request Register DCH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4 0 Not pending
.6 Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0
.5 Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.7–P2.4
.4 Level 4 (IRQ4) Request Pending Bit; External Interrupts P2.3–P2.0
.3 Level 3 (IRQ3) Request Pending Bit; Timer 2 Match/Capture or Overflow
.2 Level 2 (IRQ2) Request Pending Bit; Counter A Interrupt
.1 Level 1 (IRQ1) Request Pending Bit; Timer 1 Match/Capture or Overflow
.0 Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow
0 0 0 0 0 0 0 0
R R R R R R R R
Register addressing mode only
1 Pending
0 Not pending 1 Pending
0 Not pending 1 Pending
0 Not pending 1 Pending
0 Not pending 1 Pending
0 Not pending 1 Pending
0 Not pending 1 Pending
0 Not pending 1 Pending
4-17
CONTROL REGISTERS S3F80JB
LVDCON — LVD Control Register E0H Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 – .1
.0 LVD Flag (2.3V) Indicator Bit
NOTE: When LVD detects LVD_FLAG level (2.3V), LVDCON.0 flag bit is set automatically. When VDD is upper 2.3V,
LVDCON.0 flag bit is cleared automatically.
– – – – – – – 0 – – – – – – – R/W
Register addressing mode only
Not used for S3F80JB.
LVD_FLAG Level (2.3V)
V
0
DD ≥
1
< LVD_FLAG Level (2.3V)
V
DD
4-18
S3F80JB CONTROL REGISTERS
P0CONH — Port 0 Control Register (High Byte) E8H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6 P0.7/INT4 Mode Selection Bits
1 0 Push-pull output mode
.5 and .4 P0.6/INT4 Mode Selection Bits
0 1 C-MOS input mode; interrupt on rising and falling edges
.3 and .2 P0.5/INT4 Mode Selection Bits
.1 and .0 P0.4/INT4 Mode Selection Bits
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges
1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges
1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges 1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges 1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector address (E8H).
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register. (P0PUR.7 – P0PUR.4)
4-19
CONTROL REGISTERS S3F80JB
P0CONL — Port 0 Control Register (Low Byte) E9H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6 P0.3/INT3 Mode Selection Bits
1 0 Push-pull output mode
.5 and .4 P0.2/INT2 Mode Selection Bits
0 1 C-MOS input mode; interrupt on rising and falling edges
.3 and .2 P0.1/INT1 Mode Selection Bits
.1 and .0 P0.0/INT0 Mode Selection Bits
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges
1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges
1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges 1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges 1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT3–INT0 external interrupts at P0.3–P0.0 are interrupt level IRQ6. Each interrupt has a separate vector address.
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR regist er. (P0PUR.3 – P0PUR.0)
4-20
S3F80JB CONTROL REGISTERS
P0INT — Port 0 External Interrupt Enable Register F1H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 P0.7 External Interrupt (INT4) Enable Bit 0 Disable interrupt
.6 P0.6 External Interrupt (INT4) Enable Bit
.5 P0.5 External Interrupt (INT4) Enable Bit
.4 P0.4 External Interrupt (INT4) Enable Bit
.3 P0.3 External Interrupt (INT3) Enable Bit
.2 P0.2 External Interrupt (INT2) Enable Bit
.1 P0.1 External Interrupt (INT1) Enable Bit
.0 P0.0 External Interrupt (INT0) Enable Bit
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
4-21
CONTROL REGISTERS S3F80JB
P0PND — Port 0 External Interrupt Pending Register F2H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7
.6 P0.6 External Interrupt (INT4) Pending Flag Bit
.5 P0.5 External Interrupt (INT4) Pending Flag Bit
.4 P0.4 External Interrupt (INT4) Pending Flag Bit
.3 P0.3 External Interrupt (INT3) Pending Flag Bit 0 No P0.3 external interrupt pending (when read)
.2 P0.2 External Interrupt (INT2) Pending Flag Bit
.1 P0.1 External Interrupt (INT1) Pending Flag Bit
1 P0.1 external interrupt is pending (when read)
.0 P0.0 External Interrupt (INT0) Pending Flag Bit
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P0.7 External Interrupt (INT4) Pending Flag Bit
0 No P0.7 external interrupt pending (when read) 1 P0.7 external interrupt is pending (when read)
0 No P0.6 external interrupt pending (when read) 1 P0.6 external interrupt is pending (when read)
0 No P0.5 external interrupt pending (when read) 1 P0.5 external interrupt is pending (when read)
0 No P0.4 external interrupt pending (when read) 1 P0.4 external interrupt is pending (when read)
1 P0.3 external interrupt is pending (when read)
0 No P0.2 external interrupt pending (when read) 1 P0.2 external interrupt is pending (when read)
0 No P0.1 external interrupt pending (when read)
0 No P0.0 external interrupt pending (when read) 1 P0.0 external interrupt is pending (when read)
(see Note)
NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt
pending flag (P0PND.7–0) has no effect.
4-22
S3F80JB CONTROL REGISTERS
P0PUR — Port 0 Pull-up Resistor Enable Register E7H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 P0.7 Pull-up Resistor Enable Bit 0 Disable pull-up resistor
.6 P0.6 Pull-up Resistor Enable Bit
.5 P0.5 Pull-up Resistor Enable Bit
.4 P0.4 Pull-up Resistor Enable Bit
.3 P0.3 Pull-up Resistor Enable Bit
.2 P0.2 Pull-up Resistor Enable Bit
.1 P0.1 Pull-up Resistor Enable Bit
.0 P0.0 Pull-up Resistor Enable Bit
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
4-23
CONTROL REGISTERS S3F80JB
P1CONH — Port 1 Control Register (High Byte) EAH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6 P1.7 Mode Selection Bits
1 0 Push-pull output mode
.5 and .4 P1.6 Mode Selection Bits
0 1 Open-drain output mode
.3 and .2 P1.5 Mode Selection Bits
.1 and .0 P1.4 Mode Selection Bits
1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 0 C-MOS input mode 0 1 Open-drain output mode
1 1 C-MOS input with pull up mode
0 0 C-MOS input mode
1 0 Push-pull output mode 1 1 C-MOS input with pull up mode
0 0 C-MOS input mode 0 1 Open-drain output mode 1 0 Push-pull output mode 1 1 C-MOS input with pull up mode
0 0 C-MOS input mode 0 1 Open-drain output mode 1 0 Push-pull output mode 1 1 C-MOS input with pull up mode
4-24
S3F80JB CONTROL REGISTERS
P1CONL — Port 1 Control Register (Low Byte) EBH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6 P1.3 Mode Selection Bits
1 0 Push-pull output mode
.5 and .4 P1.2 Mode Selection Bits
0 1 Open-drain output mode
.3 and .2 P1.1 Mode Selection Bits
.1 and .0 P1.0 Mode Selection Bits
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 0 C-MOS input mode 0 1 Open-drain output mode
1 1 C-MOS input with pull up mode
0 0 C-MOS input mode
1 0 Push-pull output mode 1 1 C-MOS input with pull up mode
0 0 C-MOS input mode 0 1 Open-drain output mode 1 0 Push-pull output mode 1 1 C-MOS input with pull up mode
0 0 C-MOS input mode 0 1 Open-drain output mode 1 0 Push-pull output mode 1 1 C-MOS input with pull up mode
4-25
CONTROL REGISTERS S3F80JB
P2CONH — Port 2 Control Register (High Byte) ECH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6 P2.7/INT9 Mode Selection Bits
1 0 Push-pull output mode
.5 and .4 P2.6/INT9 Mode Selection Bits
0 1 C-MOS input mode; interrupt on rising and falling edges
.3 and .2 P2.5/INT9 Mode Selection Bits
.1 and .0 P2.4/INT9 Mode Selection Bits
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges
1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges
1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges 1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising and falling edges 1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. Pull-up resistors can be assigned to individual port2 pins by making the appropriate setting s to the P2PUR c ontrol register, location EEH, set 1, bank0.
2. Analog comparator inputs (CIN0-CIN3) for P2.4-P2.7 can be assigned to individual port 2 pins by making the appropriate settings to the CMPSEL register, location EBH, set 1, bank1. If an analog comparator input is selected by the CMPSEL register, normal I/O inputs for P2.4 -P2.7 are disc onnec ted regardle ss of P2CONH regis ter’s setting value.
4-26
S3F80JB CONTROL REGISTERS
P2CONL — Port 2 Control Register (Low Byte) EDH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6
1 0 Push-pull output mode
.5 and .4 P2.2/INT7 Mode Selection Bits
0 1 C-MOS input mode; interrupt on rising edges and falling edges
.3 and .2 P2.1/INT6 Mode Selection Bits
.1 and .0 P2.0/INT5 Mode Selection Bits
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
P2.3/INT8 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising edges and falling edges
1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges
1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising edges and falling edges 1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
0 0 C-MOS input mode; interrupt on falling edges 0 1 C-MOS input mode; interrupt on rising edges and falling edges 1 0 Push-pull output mode 1 1 C-MOS input mode; interrupt on rising edges
NOTE: Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control
register, location EEH, set 1,bank0.
4-27
CONTROL REGISTERS S3F80JB
P2INT — Port 2 External Interrupt Enable Register E5H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 P2.7 External Interrupt (INT9) Enable Bit 0 Disable interrupt
.6 P2.6 External Interrupt (INT9) Enable Bit
5. P2.5 External Interrupt (INT9) Enable Bit
.4 P2.4 External Interrupt (INT9) Enable Bit
.3 P2.3 External Interrupt (INT8) Enable Bit
.2 P2.2 External Interrupt (INT7) Enable Bit
.1 P2.1 External Interrupt (INT6) Enable Bit
.0 P2.0 External Interrupt (INT5) Enable Bit
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
0 Disable interrupt 1 Enable interrupt
4-28
S3F80JB CONTROL REGISTERS
P2PND — Port 2 External Interrupt Pending Register E6H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 P2.7 External Interrupt (INT9) Pending Flag Bit (see Note)
.6 P2.6 External Interrupt (INT9) Pending Flag Bit
.5 P2.5 External Interrupt (INT9) Pending Flag Bit
.4 P2.4 External Interrupt (INT9) Pending Flag Bit
.3 P2.3 External Interrupt (INT8) Pending Flag Bit
.2 P2.2 External Interrupt (INT7) Pending Flag Bit 0 No P2.2 external interrupt pending (when read)
.1 P2.1 External Interrupt (INT6) Pending Flag Bit
.0 P2.0 External Interrupt (INT5) Pending Flag Bit
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 No P2.7 external interrupt pending (when read) 1 P2.7 external interrupt is pending (when read)
0 No P2.6 external interrupt pending (when read) 1 P2.6 external interrupt is pending (when read)
0 No P2.5 external interrupt pending (when read) 1 P2.5 external interrupt is pending (when read)
0 No P2.4 external interrupt pending (when read) 1 P2.4 external interrupt is pending (when read)
0 No P2.3 external interrupt pending (when read) 1 P2.3 external interrupt is pending (when read)
1 P2.2 external interrupt is pending (when read)
0 No P2.1 external interrupt pending (when read) 1 P2.1 external interrupt is pending (when read)
0 No P2.0 external interrupt pending (when read) 1 P2.0 external interrupt is pending (when read)
NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt rending flag (P2PND.0–7) has no effect.
4-29
CONTROL REGISTERS S3F80JB
P2PUR — Port 2 Pull-up Resistor Enable Register EEH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 P2.7 Pull-up Resistor Enable Bit 0 Disable pull-up resistor
.6 P2.6 Pull-up Resistor Enable Bit
.5 P2.5 Pull-up Resistor Enable Bit
.4 P2.4 Pull-up Resistor Enable Bit
.3 P2.3 Pull-up Resistor Enable Bit
.2 P2.2 Pull-up Resistor Enable Bit
.1 P2.1 Pull-up Resistor Enable Bit
.0 P2.0 Pull-up Resistor Enable Bit
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
0 Disable pull-up resistor 1 Enable pull-up resistor
4-30
S3F80JB CONTROL REGISTERS
P3CON — Port 3 Control Register EFH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6 Package Selection and Alternative Function Select Bits
.5 P3.1 Function Selection Bit
.4 and .3 P3.1 Mode Selection Bits
.2 Function Selection Bit for P3.0 & P3.3
.1 and .0 P3.0 Mode Selection Bits
1 1 Schmitt trigger input with pull up resistor.
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Register addressing mode only
0 0 32 pin package
P3.0: T0PWM/T0CAP/T1CAP/T2CAP, P3.1: REM/T0CK
Others 42/44 pin package
P3.0: T0PWM/T0CAP, P3.3: T1CAP/T2CAP P3.1: REM, P3.2: T0CK
0 Normal I/O selection 1 Alternativ e f un c t i on enable (REM/T0CK)
0 0 Schmitt trigger input mode 0 1 Open- drain output mode 1 0 Push pull output mode 1 1 Schmitt trigger input with pull up resistor.
0 Normal I/O selection 1 Alternative f un ction enable (P3.0: T0PWM/T0CAP, P3 .3 : T1CAP/T2CAP)
0 0 Schmitt trigger input mode 0 1 Open- drain output mode 1 0 Push pull output mode
4-31
CONTROL REGISTERS S3F80JB
NOTES:
1. The port 3 data register, P3, at location E3H, set1, bank0, contain s sev en bit value s which correspond to the following Port 3 pin functions (bit 6 is not used for the S3F80JB: a. Port3, bit 7: carrier signal on (“1”) or off (“0”). b. Port3, bit 1,0: P3.1/REM/ T 0CK pin, bit 0: P3.0/T0PWM/T0CAP/T1CAP pin. c. Port3, bit 3,2: P3.3, P3.2 are selected only to input pin with pull up resistor automatically. d. Port3, bit 5,4: P3.5, P3.4 are selected into digital I/O by setting P345CON register at E1H, Set1, Bank1.
2. The alternative function enable/disable are enabled in accordance with function selection bit (bit5 and bit2).
3. In case of 42/44pin package, the pin assign for alternative functions can be selectable relating to mode selection bit (bit0, 1, 2, 3, 4 and 5)
4. Following Table is the specific example about the alternative func tion and pin ass ignmen t acc ording to the each bit control of P3CON in 42/44pin package.
Table 4-3. Each Function Description and Pin Assignment of P3CON in 42/44 Pin Package
P3CON Each Function Description and Assignment to P3.0–P3.3
B5 B4 B3 B2 B1 B0 P3.0 P3.1 P3.2 P3.3
0 x x 0 x x Normal I/O Normal I/O Normal Input Normal Input 0 x x 1 0 0 T0_CAP Normal I/O Normal Input T1CAP/Normal Input 0 x x 1 1 1 T0_CAP Normal I/O Normal Input T1CAP/Normal Input 0 x x 1 0 1 T0PWM Normal I/O Normal Input T1CAP/Normal Input 0 x x 1 1 0 T0PWM Normal I/O Normal Input T1CAP/Normal Input 1 0 0 0 x x Normal I/O Normal Input T0CK Normal Input 1 1 1 0 x x Normal I/O Normal Input T0CK Normal Input 1 0 1 0 x x Normal I/O REM T0CK Normal Input 1 1 0 0 x x Normal I/O REM T0CK Normal Input 1 0 0 1 0 0 T0_CAP Normal Input T0CK/Normal Input T1CAP/Normal Input 1 1 1 1 1 1 T0_CAP Normal Input T0CK/Normal Input T1CAP/Normal Input 1 0 1 1 0 1 T0PWM REM T0CK/Normal Input T1CAP/Normal Input 1 1 0 1 1 0 T0PWM REM T0CK/Normal Input T1CAP/Normal Input 1 0 0 1 0 1 T0PWM Normal Input T0CK/Normal Input T1CAP/Normal Input 1 1 1 1 1 0 T0PWM Normal Input T0CK/Normal Input T1CAP/Normal Input 1 0 1 1 0 0 T0_CAP REM T0CK/Normal Input T1CAP/Normal Input 1 1 0 1 1 1 T0_CAP REM T0CK/Normal Input T1CAP/Normal Input
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S3F80JB CONTROL REGISTERS
P345CON — Port3[4:5] Control Register E1H Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value Read/Write Addressing Mode
.7 and .6
0 1 Open-drain output mode
.5 and .4 P3.4 Mode Selection Bits
.3 and .1
.0 Port 4 Control Register Selection Bit
0 1 0 1 – – – 0
R/W R/W R/W R/W – – – R/W
Register addressing mode only
P3.5 Mode Selection Bits
0 0 C-MOS input mode
1 0 Push-pull output mode 1 1 C-MOS input with pull up mode
0 0 C-MOS input mode 0 1 Open-drain output mode 1 0 Push-pull output mode 1 1 C-MOS input with pull up mode
Not used for S3F80JB.
0 P4CON Register selection 1 P4CONH/P4CONL Register selection
NOTE: After CPU reset, P3.4 and P3.5 will be Open-drain output mode by the reset value of P345CON register at E1H, Set1, Bank1. P345CON will be initialized as “50h” to set P3.4 into the open-drain output mode after reset operation. Port4 control register P4CON will be selected by the reset value of P345CON.0 bit. If you use the Port4 input and output mode, set P345CON.0 to “1”.
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