Samsung S3F401F User Manual
USER′S MANUAL
S3F401F
Confidential Proprietary of Samsung Electronics Co., Ltd
Copyright © 2007 Samsung Electronics, Inc. All Rights Reserved
16/32-BIT RISC
MICROPROCESSOR
November, 2007
REV 1.00
Important Notice
The information in this publication has been carefully
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
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semiconductor devices described herein any license
under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.
S3F401F 16/32-Bit RISC Microprocessor
User's Manual, Revision 1.00
Publication Number: 21-S3-F401F-112007
"Typical" parameters can and do vary in different
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Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu
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TEL: (82) (31) 209-4956
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NOTIFICATION OF REVISIONS
ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea
PRODUCT NAME: S3F401F Microcontroller
DOCUMENT NAME: S3F401F User's Manual, Revision 1.00
DOCUMENT NUMBER: S3F401F-112007
EFFECTIVE DATE: Nov, 2007
SUMMARY: As a result of S3F410F development, designed with preliminary specification,
S3F401F User's Manual Revision 1.0 has been completed.
DIRECTIONS: Please note the changes into the next page, if you find some to be changed in
your copy (copies) of the S3F401F User’s Manual, Revision 1.0.
REVISION HISTORY
Revision Description of Change Author(s) Date
1.00 This Spec of S3F401F can be released officially.
Juil Kim 0.00 Preliminary Spec for internal release only.
Younghee Jin
Younghee Jin
Nov, 2006
Nov, 2007
REVISION DESCRIPTIONS (REV 1.00)
Chapter
Chapter Name Page
− − −
Subjects (Major changes comparing with last version)
Table of Contents
Chapter 1 Product Overview
1. Overview ..................................................................................................................................................1-1
1.1 Introduction.....................................................................................................................................1-1
2. Features...................................................................................................................................................1-2
3. Block Diagram..........................................................................................................................................1-3
4. Pin Assignments.......................................................................................................................................1-4
5. Pin Descriptions .......................................................................................................................................1-9
6. Memory Address......................................................................................................................................1-12
Chapter 2 A/D Converter
1. Overview ..................................................................................................................................................2-1
1.1 Features..........................................................................................................................................2-1
2. Block Diagram..........................................................................................................................................2-2
3. A/D Converter Operation..........................................................................................................................2-3
3.1 Function Description.......................................................................................................................2-3
4. Registers Description...............................................................................................................................2-7
Chapter 3 Basic Timer & Watchdog Timer
1. Overview ..................................................................................................................................................3-1
2. Function Description.................................................................................................................................3-2
2.1 Interval Timer Function...................................................................................................................3-2
2.2 Watchdog Timer Operation ............................................................................................................3-3
2.3 Timer Duration................................................................................................................................3-4
2.4 Watch Dog Timer Duration.............................................................................................................3-5
3. Registers Description...............................................................................................................................3-6
S3F401F_UM_REV1.00 MICROCONTROLLER iii
Table of Contents (Continued)
Chapter 4 Encoder Counter
1. Overview.................................................................................................................................................. 4-1
2. Function Description................................................................................................................................ 4-3
2.1 Position Counter Operation............................................................................................................ 4-3
3. Registers Description............................................................................................................................... 4-4
Chapter 5 Internal Flash ROM
1. Overview.................................................................................................................................................. 5-1
1.2 Features......................................................................................................................................... 5-1
2. Block Diagram .........................................................................................................................................5-1
3. Flash Configuration.................................................................................................................................. 5-2
3.1 Flash ROM Configuration ..............................................................................................................5-2
3.2 Address Alignment......................................................................................................................... 5-2
3.3 Working Mode................................................................................................................................ 5-2
3.4 Program Mode ...............................................................................................................................5-2
4. Programming Modes ........................................................................................................... ....................5-3
4.1 User Program Mode....................................................................................................................... 5-3
4.2 Normal Program............................................................................................................................. 5-4
4.3 Option Program.............................................................................................................................. 5-5
4.4 Sector Erase ..................................................................................................................................5-6
4.5 Chip Erase Flowchart..................................................................................................................... 5-7
4.6 Tool Program Mode .......................................................................................................... .............5-8
5. Data Protection........................................................................................................................................ 5-9
5.1 Protection Option Configuration..................................................................................................... 5-9
5.2 Jtag Interface Protection Bit 8........................................................................................................ 5-10
5.3 Hardware Protection Bit 17............................................................................................................ 5-10
5.4 Read Protection Bit 27................................................................................................................... 5-11
6. Registers Description............................................................................................................................... 5-12
iv S3F401F_UM_REV1.00 MICROCONTROLLER
Table of Contents (Continued)
Chapter 6 Inverter Motor Controller (IMC)
1. Overview ..................................................................................................................................................6-1
2. Block Diagram..........................................................................................................................................6-2
3. Function Description.................................................................................................................................6-3
3.1 Tri-Angular Wave............................................................................................................................6-3
3.2 Saw-Tooth Wave............................................................................................................................6-4
4. Phase Signal Generation .........................................................................................................................6-5
4.1 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-5
4.2 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-7
4.3 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-9
4.4 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-10
4.5 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-11
4.6 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-13
4.7 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-14
4.8 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-15
4.9 Saw-Tooth Wave (IMMODE = 1)....................................................................................................6-16
4.10 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-19
4.11 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-20
4.12 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-21
4.13 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-22
4.14 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-23
4.15 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-24
4.16 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-25
5. Inverter Motor Special Function Register.................................................................................................6-26
Chapter 7 Interrupt Controller
1. Overview ..................................................................................................................................................7-1
2. Functional Description..............................................................................................................................7-3
2.1 Configuring IRQ and FIQ Interrupt Service ....................................................................................7-3
2.2 Interrupt Registers..........................................................................................................................7-3
2.3 Interrupt Sources............................................................................................................................7-5
3. Registers Description...............................................................................................................................7-8
S3F401F_UM_REV1.00 MICROCONTROLLER v
Table of Contents (Continued)
Chapter 8 I/O Ports
1. Overview.................................................................................................................................................. 8-1
2. S3F401F Port Configuration Overview.................................................................................................... 8-2
3. I/O Port Control Registers ....................................................................................................................... 8-3
4. Registers Description............................................................................................................................... 8-4
Chapter 9 Clock & Power Management
1. Overview.................................................................................................................................................. 9-1
2. Phase Locked Loop................................................................................................................................. 9-4
2.1 PLL................................................................................................................................................. 9-4
2.2 PLL Value Change Steps............................................................................................................... 9-5
2.3 Capacitor for PLL Loop Filter......................................................................................................... 9-5
3. Mode Change.......................................................................................................................................... 9-6
3.1 Changing clock speed from normal mode to highspeed mode [NORMAL Æ HIGHSPEED]........ 9-6
3.2 Changing clock speed from highspeed mode to normal mode [HIGHSPEED Æ NORMAL]........ 9-6
3.3 Entering the stop mode from high speed mode [HIGHSPEED Æ STOP]..................................... 9-6
3.4 Exit From the STOP mode............................................................................................................. 9-6
3.5 Exit From the Clock fail mode........................................................................................................ 9-6
3.6 IDLE Mode and Internal Flash ROM.............................................................................................. 9-6
4. Registers Description............................................................................................................................... 9-7
vi S3F401F_UM_REV1.00 MICROCONTROLLER
Table of Contents (Continued)
Chapter 10 SSP (Synchronous Serial Port)
1. Overview ..................................................................................................................................................10-1
1.1 Features..........................................................................................................................................10-1
1.2 Programmable Parameters ............................................................................................................10-1
2. Block Diagram..........................................................................................................................................10-2
2.1 SSP Functional Description............................................................................................................10-3
2.2 Frame Format.................................................................................................................................10-6
2.3 Interrupt ..........................................................................................................................................10-13
3. Registers Description...............................................................................................................................10-14
Chapter 11 16-Bit Timers
1. Overview ..................................................................................................................................................11-1
2. Operation Description...............................................................................................................................11-3
2.1 Interval Mode Operation.................................................................................................................11-3
2.2 Match & Overflow Mode Operation ................................................................................................11-4
2.3 Capture Mode Operation................................................................................................................11-5
2.4 PWM Mode Operation....................................................................................................................11-6
S3F401F_UM_REV1.00 MICROCONTROLLER vii
Table of Contents (Continued)
Chapter 12 UART
1. Overview.................................................................................................................................................. 12-1
1.1 The Uart Performs: ........................................................................................................................ 12-1
1.2 IrDA SIR Block............................................................................................................................... 12-2
1.3 Features......................................................................................................................................... 12-2
1.4 Programmable Parameters............................................................................................................ 12-3
1.5 Variations from the 16C550 Uart ...................................................................................................12-4
2. Block Diagram .........................................................................................................................................12-5
3. Function Description................................................................................................................................ 12-6
3.1 Baud Rate Generator..................................................................................................................... 12-6
3.2 Transmit FIFO................................................................................................................................ 12-7
3.3 Transmit Logic................................................................................................................................ 12-7
3.4 Receive FIFO................................................................................................................................. 12-7
3.5 Receive Logic................................................................................................................................. 12-7
3.6 Uart Operation................................................................................................................................ 12-7
3.7 IrDA SIR Operation........................................................................................................................ 12-9
3.8 Interrupts........................................................................................................................................ 12-11
4. Registers Description............................................................................................................................... 12-14
Chapter 13 Electrical Data
1. DC Electrical Characteristics................................................................................................................... 13-1
Chapter 14 Mechanical Data
1. Overview.................................................................................................................................................. 14-1
viii S3F401F_UM_REV1.00 MICROCONTROLLER
List of Figures
Figure Title Page
Number Number
1-1 S3F401F Block Diagram..............................................................................................1-3
1-2 S3F401F Package Pin Assignments (100-QFP-1420)................................................1-4
2-1 A/D Converter Block Diagram......................................................................................2-2
2-2 ADC Operation Flow Chart ..........................................................................................2-6
3-1 Basic Timer Block Diagram..........................................................................................3-1
4-1 Encoder Counter Block Diagram .................................................................................4-2
4-2 Position Counter Operation..........................................................................................4-3
5-1 Flash Memory Controller Read/Write Block Diagram..................................................5-1
5-2 Normal Program Flowchart..........................................................................................5-4
5-3 Option Program Flowchart...........................................................................................5-5
5-4 Sector Erase Flowchart................................................................................................5-6
5-5 Chip Erase Flowchart...................................................................................................5-7
6-1 Inverter Motor Controller (IMC) Block Diagram ...........................................................6-2
6-2 Inverter Motor Controller (IMC) Signal generation (Tri-angular wave) ........................6-3
6-3 Inverter Motor Controller (IMC) Signal generation (Saw-tooth wave)..........................6-4
6-4 Inverter Motor Controller (IMC) Signal generation (Tri-angular wave) ........................6-5
7-1 S3F401F Interrupt Structure........................................................................................7-2
9-1 Clock State Machine Diagram .....................................................................................9-2
9-2 Clock Circuit Diagram ..................................................................................................9-3
9-3 PLL (Phase-Locked Loop) Block Diagram...................................................................9-5
9-4 Capacitor for PLL Loop Filter.......................................................................................9-5
S3F401F_UM_REV1.00 MICROCONTROLLER ix
List of Figures (Continued)
Figure Title Page
Number Number
10-1 SSP Block Diagram..................................................................................................... 10-2
10-2 SUB Block Diagram..................................................................................................... 10-3
10-3 SSP frame format (single transfer) with SPO=0 and SPH=0...................................... 10-7
10-4 SSP frame format (continuous transfer) with SPO=0 and SPH=0.............................. 10-7
10-5 SSP frame format with SPO=0 and SPH=1................................................................ 10-8
10-6 SSP frame format (single transfer) with SPO=1 and SPH=0...................................... 10-9
10-7 SSP frame format (continuous transfer) with SPO=1 and SPH=0.............................. 10-9
10-8 SSP Frame Format with SPO=1 and SPH=1.............................................................. 10-10
10-9 PrimeCell SSP Master Coupled to Two Slaves .......................................................... 10-11
10-10 SPI master coupled to two PrimeCell SSP slaves...................................................... 10-12
11-1 16-Bit Timer Block Diagram ........................................................................................ 11-2
11-2 Simplified Timer Function Diagram: Interval Timer Mode........................................... 11-3
11-3 Simplified Timer Function Diagram: Match & Overflow Timer Mode.......................... 11-4
11-4 Simplified Timer Function Diagram: Capture Mode.................................................... 11-5
11-5 Simplified Timer Function Diagram: PWM Mode........................................................ 11-6
11-6 PWM Signal Generation Diagram............................................................................... 11-7
12-1 UART Block Diagram (with FIFO)............................................................................... 12-5
12-2 UART character frame ................................................................................................ 12-7
12-3 IrDA data modulation................................................................................................... 12-10
13-1 ADC Offset Error .........................................................................................................13-6
13-2 ADC DLE, ILE.............................................................................................................. 13-7
14-1 100-QFP-1420 Package Dimensions.......................................................................... 14-1
x S3F401F_UM_REV1.00 MICROCONTROLLER
List of Tables
Table Title Page
Number Number
1-1 Pin Assignments − Pin Number Order.........................................................................1-5
1-2 S3F401F Pin Descriptions ...........................................................................................1-9
1-3 S3F401F Default Memory Map after Reset.................................................................1-12
1-4 The Base Address of Peripheral Special Registers.....................................................1-13
2-1 ADC Input & Output Range..........................................................................................2-3
2-2 ADC Control Special Function Registers.....................................................................2-7
3-1 Basic timer & WDT Special Function Registers...........................................................3-6
4-1 ENC Special Function Registers..................................................................................4-4
5-1 The Pins Used to Read/Write/Erase the Flash ROM in Tool Program Mode..............5-8
5-2 Protection Option Address and Protection Bits............................................................5-9
5-3 Smart Option Address Configuration...........................................................................5-10
5-4 Hardware Protection Area............................................................................................5-11
5-5 Internal Flash Special Function Registers ...................................................................5-12
6-1 IMC Special Function Registers...................................................................................6-25
7-1 S3F401F Interrupt Sources..........................................................................................7-5
7-2 Interrupt Controller Special Function Registers...........................................................7-8
8-1 S3F401F Port Configuration Overview........................................................................8-2
8-2 Port Control Special Function Registers......................................................................8-4
9-1 Clock & Power Management Special Function Register.............................................9-7
9-2 MDIV/PDIV/SDIV Allowed Values................................................................................9-11
10-1 UART Interrupts In Connection With FIFO ..................................................................10-13
10-2 Clock & Power Management Special Function Register.............................................10-14
11-1 TIMER Special Function Registers..............................................................................11-8
12-1 UART Special Function Registers ...............................................................................12-14
13-1 Absolute Maximum Ratings .........................................................................................13-1
13-2 D.C. Electrical Characteristics .....................................................................................13-2
13-3 Timing Constants.........................................................................................................13-3
13-4 PLL Timing Constants..................................................................................................13-3
13-5 Internal RC Oscillation Characteristics ........................................................................13-4
13-6 AC Electrical Characteristics........................................................................................13-4
13-7 12-bit ADC Electrical Characteristics...........................................................................13-5
13-8 AC Electrical Characteristics for Internal Flash ROM..................................................13-8
S3F401F_UM_REV1.00 MICROCONTROLLER xi
S3F401F_UM_REV1.00 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
1. OVERVIEW
1.1 INTRODUCTION
Samsung's S3F401F 16/32-bit RISC microcontroller is a cost-effective and high-performance microcontroller
solution for an inverter motor and a general-purpose application.
An outstanding feature of the S3F401F is its CPU core, a 16/32-bit RISC processor (ARM7TDMI-S) designed by
Advanced RISC Machines, Ltd. The ARM7TDMI-S core is a low-power, general purpose, microprocessor macrocell, which was developed for the use in application-specific and customer-specific integrated circuits. Its simple,
elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive application. Using the
ARM7TDMI-S core, CMOS standard cell, and a data path compiler has developed the S3F401F. Most of the onchip function blocks have been designed using an HDL synthesizer
The integrated on-chip functions, which are described in this document include:
• Built-in 256Kbyte NOR-Flash memory
• Internal 20Kbyte SRAM for stack, data memory, or code memory
• Interrupt controller: 90 interrupt sources, interrupt priority control logic and interrupt vector generation by H/W.
• Three programmable I/O port groups
• Two inverter timer, Two channel 16bit encoder counter, having PHASE A,B and Z
• Two-channel UART, Two-channel SSP
• Six-channel 16-bit timers with capture and PWM
• Fifteen-channel 12-bit ADC
• One-channel 8-bit basic timer and 3-bit watch-dog timer
• Crystal/Ceramic oscillator or external clock can be used as the clock source and PLL
• Power control: Normal, Idle, and Stop mode
• Clock monitor
1-1
PRODUCT OVERVIEW S3F401F_UM_REV1.00
2. FEATURES
CPU
• ARM7TDMI-S CPU Core
• 32-bit RISC architecture
Memory
• 256 Kbytes Internal Program Full Flash
• 20 Kbytes Internal SRAM
• Only little-endian support
General purpose I/O Pins
• Max. 65 pins
• 31 external interrupts
8-Bit Basic Timer
• Programmable interval timer
• Watch-dog timer’s clock source, overflow of 8-bit
counter
Watchdog Timer
• System reset when 3-bit counter overflow
Six 16-bit Timer/Counters (T/C0 - T/C5)
• Programmable interval timer
• External event counter function
• PWM function and capture function
Two Inverter Motor Controllers
• 3-Phase pairs’ PWM generation
• Programmable dead time insertion
• ADC conversion start signal generation
Two 16-Bit Encoder Counter
• Support position counter and speed counter
• Up/Down counter
• 3 inputs, Phase A,B and Z
• Capture mode support
Two channel 16-Bit Synchronous Serial Port
• Master or slave operation
• Programmable clock bit rate and pre-scale
• Separate 8x16bit transmit/receive FIFO
• 4 to 16-bit transmit/receive mode
Two Channels UART
• Programmable use of UART or IrDA SIR input
/output
• Separate 16x8bit transmit and 16x12bit receive
FIFO
• Programmable baud rate generator
• Standard asynchronous communication bits
(start, stop, parity)
• Auto generating parity bit
Analog to Digital Converter
• 15-channel analog inputs
• 12-bit resolution
• Simultaneous Sampling of 3 Single-Ended
Interrupt Controller
• Supports normal or fast interrupt modes
(IRQ, FIQ)
• Supports vectored interrupt
(Hard-wired Interrupt)
• S/W programmable interrupt priority
Two Power-Down Modes
• Idle: only CPU clock stops
• Stop: selected system clock and CPU clock stop
Clock Manager (CM)
• CPU and peripherals can be deactivated
individually
Phase-Locked Loop (PLL)
• Programmable clock synthesizer (Max 90MHz)
Operating Voltage Range
• 3.0 V to 3.6 V at 4.0MHz − 90.0MHz
(external crystal: 4.0MHz − 8MHz)
Power-On Reset (POR)
• Clock Monitor
Operating Temperature Range
• −40°C to +85°C
Available in 100 QFP Package
1-2
S3F401F_UM_REV1.00 PRODUCT OVERVIEW
3. BLOCK DIAGRAM
Crystal or
Ceramic
Oscillator
CLOCK
MONITOR
I/O
CONTROLLER
ARM7TDMI-S
CORE
INTERRUPT
CONTROLLER
PLL
IMC0/1
BRIDGE
SSP0/1
SSP0/1
AHB
FLASH-ROM
256KB
SRAM
20KB
TAP CONTROLLER
For JTAG
ENC0/1
ENC0/1IMC0/1
UART0/1
UART0/1
APB
BT & WDT
Timer0/1/2/3/4/5
Timer0/1/2/3/4/5
Timer0/1/2/3/4/5
12-BIT ADC
Figure 1-1. S3F401F Block Diagram
Timer0/1/2/3/4/5
TIMER 0/1/2/3/4/5
1-3
PRODUCT OVERVIEW S3F401F_UM_REV1.00
4. PIN ASSIGNMENTS
PLLVSSIP
P0.0/T0CLK
P0.1/T0CAP
P0.2/T0PWM
P0.3/T1CLK
P0.4/T1CAP
P0.5/T1PWM
P0.6/T2CLK
P0.7/T2CAP
P0.8/T2PWM/ADTRG
P0.9/PHASEA0
P0.10/PHASEB0
P0.11/PHASEZ0
Xin
Xout
VSSCORE0
VDDCORE0
P0.12/PWM0OFF
P0.13/PWM0U0
P0.14/PMW0D0
P0.15/PMW0U1
P0.16/PWM0D1
P0.17/PWM0U2
P0.18/PMW0D2
P1.0/UARTRXD0/INT0
P1.1/UARTTXD0/INT1
P1.2/UARTRXD1/INT2
P1.3/UARTTXD1/INT3
P1.4/T3CLK/INT4
P1.5/T3CAP/INT5
P1.6/T3PWM/INT6
RTCK
TMS
TDI
nRESET
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
TCK
99989796959493929190898887868584838281
VDDIO2
TDO
nTRST
VSSIO2
S3F401F
(100-QFP-1420C)
PLLVDDOUT
PLLVDDCORE
PLLCAP
PLLVSSCORE
ADCVSSIO
ADCVSSCORE
ADCVDDCORE
ADCVDDIO
P2.14/AIN14
P2.13/AIN13
P2.12/AIN12
80
79
P2.11/AIN11
78
P2.10/AIN10
77
P2.9/AIN9
76
P2.8/AIN8
75
P2.7/AIN7
74
P2.6/AIN6
73
P2.5/AIN5
72
P2.4/AIN4
71
P2.3/AIN3
70
P2.2/AIN2
69
P2.1/AIN1
68
P2.0/AIN0
VSSCORE2
67
VDDCORE2
66
65
P1.30/PWM1D2/INT30
64
P1.29/PWM1U2/INT29
63
P1.28/PWM1D1/INT28
62
P1.27/PWM1U1/INT27
61
P1.26/PWM1D0/INT26
60
P1.25/PWM1U0/INT25
59
P1.24/PWM1OFF/INT24
58
P1.23/PHASEZ1/INT23
57
P1.22/PHASEB1/INT22
56
P1.21/PHASEA1/INT21
55
P1.20/SSPFSS1/INT20
54
P1.19/SSPCLK1/INT19
53
P1.18/SSPRXD1/INT18
52
P1.17/SSPTXD1/INT17
51
MD2
50
MD1
MD0
P1.15/SSPCLK0/INT15
P1.16/SSPFSS0/INT16
P1.14/SSPRXD0/INT14
VSSIO0
VSSIP
VDDIO0
P1.7/T4CLK/INT7
P1.8/T4CAP/INT8
P1.9/T4PWM/INT9
VDDOUT
P1.10/T5CLK/INT10
P1.11/P5CAP/INT11
P1.12/T5PWM/INT12
VSSIO1
VDDIO1
VSSCORE1
VDDCORE1
P1.13/SSPTXD0/INT13
Figure 1-2. S3F401F Package Pin Assignments (100-QFP-1420)
1-4
S3F401F_UM_REV1.00 PRODUCT OVERVIEW
Table 1-1. Pin Assignments − Pin Number Order
No. Pin Name Default Function State Flash Function
1 P0.0 T0CLK
2 P0.1 T0CAP
3 P0.2 T0PWM
4 P0.3 T1CLK
5 P0.4 T1CAP
6 P0.5 T1PWM
7 P0.6 T2CLK
8 P0.7 T2CAP
−
−
−
−
−
−
−
−
9 P0.8 T2PWM ADTRG P0.8 I/O
10 P0.9 PHASEA0
11 P0.10 PHASEB0
12 P0.11 PHASEZ0
13 Xin
14 Xout
15 VSSCORE0
16 VDDCORE0
− −
− −
− −
− −
17 P0.12 PWM0OFF
18 P0.13 PWM0U0
19 P0.14 PMW0D0
20 P0.15 PMW0U1
21 P0.16 PWM0D1
22 P0.17 PWM0U2
23 P0.18 PMW0D2
−
−
−
−
−
−
−
−
−
−
24 P1.0 UARTRXD0 INT0 P1.0 I/O
25 P1.1 UARTTXD0 INT1 P1.1 I/O
26 P1.2 UARTRXD1 INT2 P1.2 I/O
27 P1.3 UARTTXD1 INT3 P1.3 I/O
28 P1.4 T3CLK INT4 P1.4 I/O
29 P1.5 T3CAP INT5 P1.5 I/O
30 P1.6 T3PWM INT6 P1.6 I/O
P0.2 I/O
P0.1 I/O
P0.2 I/O
P0.3 I/O
P0.4 I/O
P0.5 I/O
P0.6 I/O
P0.7 I/O
P0.9 I/O
P0.10 I/O
P0.11 I/O
Xin I
Xout O
VSS P
VDD P
P0.12 I/O
P0.13 I/O
P0.14 I/O
P0.15 I/O
P0.16 I/O
P0.17 I/O
P0.18 I/O
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1-5
PRODUCT OVERVIEW S3F401F_UM_REV1.00
Table 1-1. Pin Assignments − Pin Number Order (Continued)
No. Pin Name Default Function State Flash Function
31 VSSIO0
32 VDDIO0
33 VSSIP
− −
− −
− −
34 P1.7 T4CLK INT7 P1.7 I/O
35 P1.8 T4CAP INT8 P1.8 I/O
36 P1.9 T4PWM INT9 P1.9 I/O
37 P1.10 T5CLK INT10 P1.10 I/O
38 P1.11 T5CAP INT11 P1.11 I/O
39 P1.12 T5PWM INT12 P1.12 I/O
40 VDDOUT
41 VSSCORE1
42 VDDCORE1
43 VSSIO1
44 VDDIO1
− −
− −
− −
− −
− −
45 P1.13 SSPTXD0 INT13 P1.13 I/O
46 P1.14 SSPRXD0 INT14 P1.14 I/O
VSS P
VDD P
VSS P
VDDOUT P
VSS P
VDD P
VSS P
VDD P
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
47 P1.15 SSPCLK0 INT15 P1.15 I/O SDAT (I/O)
48 P1.16 SSPFSS0 INT16 P1.16 I/O SCLK (I)
49 MD0
50 MD1
− −
− −
MD0 I MD0
MD1 I MD1
1-6
S3F401F_UM_REV1.00 PRODUCT OVERVIEW
Table 1-1. Pin Assignments − Pin Number Order (Continued)
No. Pin Name Default Function State Flash Function
51 MD2
− −
52 P1.17 SSPTXD1 INT17 P1.17 I/O
53 P1.18 SSPRXD1 INT18 P1.18 I/O
54 P1.19 SSPCLK1 INT19 P1.19 I/O
55 P1.20 SSPFSS1 INT20 P1.20 I/O
56 P1.21/ PHASEA1 INT21 P1.21 I/O
57 P1.22 PHASEB1 INT22 P1.22 I/O
58 P1.23 PHASEZ1 INT23 P1.23 I/O
59 P1.24 PWM1OFF INT24 P1.24 I/O
60 P1.25 PWM1U0 INT25 P1.25 I/O
61 P1.26 PWM1D0 INT26 P1.26 I/O
62 P1.27 PWM1U1 INT27 P1.27 I/O
63 P1.28/ PWM1D1 INT28 P1.28 I/O
64 P1.29 PWM1U2 INT29 P1.29 I/O
65 P1.30 PWM1D2 INT30 P1.30 I/O
66 VDDCORE2
67 VSSCORE2
68 P2.0 AIN0
69 P2.1 AIN1
70 P2.2 AIN2
71 P2.3 AIN3
72 P2.4 AIN4
73 P2.5 AIN5
74 P2.6 AIN6
75 P2.7 AIN7
76 P2.8 AIN8
77 P2.9 AIN9
78 P2.10 AIN10
79 P2.11 AIN11
80 P2.12 AIN12
− −
− −
−
−
−
−
−
−
−
−
−
−
−
−
−
MD2 I MD2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
VDD P
VSS P
P2.0 I/O
P2.1 I/O
P2.2 I/O
P2.3 I/O
P2.4 I/O
P2.5 I/O
P2.6 I/O
P2.7 I/O
P2.8 I/O
P2.9 I/O
P2.10 I/O
P2.11 I/O
P2.12 I/O
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1-7
PRODUCT OVERVIEW S3F401F_UM_REV1.00
Table 1-1. Pin Assignments − Pin Number Order (Continued)
No. Pin Name Default Function State Flash Function
81 P2.13 AIN13
82 P2.14 AIN14
83 ADCVDDIO
84 ADCVSSIO
85 ADCVDDCORE
86 ADCVSSCORE
87 PLLVSSCORE
88 PLLCAP
89 PLLVDDCORE
90 PLLVDDOUT
91 PLLVSSIP
92 VSSIO2
93 VDDIO2
94 nTRST
95 TDO
96 TCK
97 TDI
98 TMS
99 RTCK
100 nRESET
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
−
−
P2.13 I/O –
P2.14 I/O –
VDD P –
VSS P –
VDD P –
VSS P –
VSS P –
PLLCAP I –
VDD P –
VDDPLLOUT P –
VSS P –
VSS P –
VDD P –
nTRST I –
TDO O –
TCK I –
TDI I –
TMS I –
RTCK O –
nRESET I nRESET
1-8
S3F401F_UM_REV1.00 PRODUCT OVERVIEW
5. PIN DESCRIPTIONS
Table 1-2. S3F401F Pin Descriptions
Module Pin Name Description I/O
BUS
MD[2:0]
CONTROLLER
INTERRUPT INT[30:0] External interrupt request 31 to 0. I
CLOCK & Xin Crystal input of oscillator circuit for system clock. I
RESET Xout Crystal output of oscillator circuit for system clock. O
nRESET Reset input: The global system reset input for the S3F401F.
16-BIT TIMER
T[5:0]CLK External clock input for Timer I
T[5:0]CAP Capture input for Timer I
T[5:0]PWM PWM output for Timer O
UARTRXD[1:0] UART receive I UART
UARTTXD[1:0] UART transmit O
SSP
SSPRXD[1:0] SSP receive I
SSPTXD[1:0] SSP transmit O
SSPCLK[1:0] SSP clock I/O
SSPFSS[1:0] SSP frame input (for slave) / slave select output (for master) I/O
AIN[14:0] ADC input AI ADC
ADTRG ADC trigger input I
The MD[2:0] can configure the operating mode of chip.
000 = Normal mode
001 = SPGM mode (Flash programming mode with writing tool)
Others = Test mode
Connect to GND through a 100nF capacitor with each mode
pin.
Capacitor for PLL loop filter. PLLCAP
Connect to GND through a 1200pF capacitor
For a system initialization, nRESET must be held to LOW level
for at least 1uSec. Connect to GND through 100nF and 10nF
capacitor.
I
I
I
1-9
PRODUCT OVERVIEW S3F401F_UM_REV1.00
Table 1-2. S3F401F Pin Descriptions (Continued)
Module Pin Name Description I/O
SDAT Serial Data pin (Output when reading, Input when writing)
I/O TOOL Program
Input & Push-pull output port can be assigned.
SCLK Serial Clock, input only
I
Writer speed : Max 250kHz, Read speed: Max 3MHz
JTAG
nTRST nTRST (TAP Controller Reset) can reset the TAP controller at
I
power-up. A 200K pull-up resistor is connected to nTRST pin,
internally. If the debugger is not used, nTRST pin should be
"Low" level or low active pulse should be applied before CPU
running. For example, nRESET signal can be tied with
nTRST.
TMS TMS (TAP Controller Mode Select) can control the sequence
I
of the state diagram of TAP controller. A 200K pull-up resistor
is connected to TMS pin, internally.
TCK TCK (TAP Controller Clock) can provide the clock input for the
I
JTAG logic. This pin is floating pin. When reduced the current
and not debugging mode, connect to the VDD with pull-up
resistor.
RTCK RTCK (TAP Controller Retiming Clock) can provide the clock
I
output for the JTAG logic.
Connect to GND through a 33pF capacitor.
TDI TDI (TAP Controller Data Input) is the serial input for JTAG
I
port. A 200K pull-up resistor is connected to TDI pin,
internally.
TDO TDO (TAP Controller Data Output) is the serial output for
O
JTAG port.
INVERTER
MOTOR
CONTROLLER
PWM[1:0]U[2:0] PWM output for inverter motor O
PWM[1:0]D[2:0] PWM output for inverter motor O
PWM[1:0]OFF Input pin for PWM output off I
ENCODER PHASEA[1:0] Phase A input pin I
PHASEB[1:0] Phase B input pin I
PHASEZ[1:0] Phase Z input pin I
GERNAL
PURPOSE
PORT
P0.[18:0] General input/output port 0 I/O
P1.[30:0] General input/output port 1 I/O
P2.[14:0] General input/output port 2 I/O
1-10
S3F401F_UM_REV1.00 PRODUCT OVERVIEW
Table 1-2. S3F401F Pin Descriptions (Continued)
Module Pin Name Description I/O
POWER VDDCORE[2:0]
VSSCORE[2:0]
VDDIO[2:0]
Core logic V
Core logic V
I/O VDD (Typ. 3.3V)
(Typ. 3.3V)
DD
SS
P
P
P
Connect to GND through a 100nF capacitor.
SS
SS
(Typ. 3.3V)
DD
SS
(Typ. 3.3V)
DD
SS
VSSIO[2:0]
VSSIP
ADCVDDCORE
ADCVSSCORE
ADCVDDIO
ADCVSSIO
PLLVDDCORE
I/O V
V
ADC Core logic V
ADC Core logic V
ADC I/O V
ADC I/O V
PLL Core logic VDD (Typ. 3.3V)
Connect to GND through a 100nF capacitor.
PLLVSSCORE
PLLVSSIP
PLL Core logic V
V
SS
SS
PLLVDDOUT Connect to GND through a 1uF capacitor (From internal regulator) P
VDDOUT Connect to GND through a 1uF capacitor (From internal regulator) P
P
P
P
P
P
P
P
P
P
1-11
PRODUCT OVERVIEW S3F401F_UM_REV1.00
6. MEMORY ADDRESS
When the reset of S3F401F micro-controller is asserted, the ARM core is in boot mode to access the internal flash
at address 0x00000000. The internal RAM is located at address 0x00400000.
Table 1-3. S3F401F Default Memory Map after Reset
Memory Space Size Application Abort when Accessed
0xFFFFFFFF
−
0xFF000000
0xFEFFFFFF
−
0x00405000
0x00404FFF
−
−
−
20Kbytes
Peripheral devices
Reserved
Internal RAM
0x00400000
0x003FFFFF
−
0x00040000
0x0003FFFF
−
−
256Kbytes
Reserved
Internal flash
0x00000000
No
Yes
No
Yes
No
1-12
S3F401F_UM_REV1.00 PRODUCT OVERVIEW
Table 1-4. The Base Address of Peripheral Special Registers
Peripheral Base Address
CM 0xFF00_0000
BT/WDT 0xFF00_4000
TC0 0xFF00_8000
TC1 0xFF00_C000
TC2 0xFF01_0000
TC3 0xFF01_4000
TC4 0xFF01_8000
TC5 0xFF01_C000
IMC0 0xFF02_0000
IMC1 0xFF02_4000
ENC0 0xFF02_8000
ENC1 0xFF02_C000
SSP0 0xFF03_0000
SSP1 0xFF03_4000
UART0 0xFF03_8000
UART1 0xFF03_C000
ADC 0xFF04_0000
IOPORT 0xFF04_4000
IFC 0xFFF0_0000
VIC 0xFFFF_FF00
1-13
S3F401F_UM_REV1.00 A/D CONVERTER
2 A/D CONVERTER
1. OVERVIEW
The S3F401F has a 12-bit ADC. It converts the analog input signal into 12-bit binary digital codes at a maximum
sampling rate of 4MHz. The device is a monolithic ADC with on-chip, which consists of three sample and hold
amplifiers, four multiplying DACs, five sub-ranging flash ADCs and current reference. Normal speed of input is
below 100kHz which can be quantized by 4MHz clock.
1.1 FEATURES
• ADC Resolution: 12-bit
• DLE (Differential Linearity Error): Max. ± 1.0 LSB (Least Bit)
• ILE (Integral Linearity Error): Max. ± 3.2 LSB
• Maximum Conversion Rate: 4MHz clock
• Low Power Consumption
• Power Supply Voltage: 3.3V
• Analog Input Range: 0.0V ∼ 3.3V
2-1
A/D CONVERTER S3F401F_UM_REV1.00
2. BLOCK DIAGRAM
AIN0
AIN1
AIN13
AIN14
ADCCON.15-.12: SHA1SEL
AIN0
AIN1
AIN13
AIN14
ADCCON.19-.16:SHA2SEL
AIN0
AIN1
AIN13
AIN14
ADCCON.23-.20:SHA3SEL
ADTRG
SHA1
SHA2
SHA3
ADCCON.9-.8:MODESEL
ADCCON.9-.8:MODESEL
12bit ADC
From
ADCCON.3-.2:TRIGSEL
ADCCON.0:START
IMC
Figure 2-1. A/D Converter Block Diagram
ADCRESULT1.11-.0 :
ADCRESULT2.11-.0 :
ADCRESULT3.11-.0 :
INTMASK
INTPND
DATA1
DATA2
DATA3
INT_EOC
2-2
S3F401F_UM_REV1.00 A/D CONVERTER
3. A/D CONVERTER OPERATION
3.1 FUNCTION DESCRIPTION
ADC has 3-analog input channels, SHA1, SHA2 and SHA3. After 3 conversion of ADC, the result of SHA1 is
pushed into the ADCRESULT1, the result of SHA2 is pushed into the ADCRESULT2 and the result of SHA3 is
pushed into the ADCRESULT3.
3.1.1 ADC Input
AIN[14:0] function pins are used for an analog input source to convert by ADC. ADC 3-input channels can be
selected one among AIN[14:0] inputs. Input signal range is followed by the boundary of reference, Reference TOP
and Reference BOTTOM.
Input Voltage Range: 0.0V ~ 3.3V
Reference Bottom = 0.0V, Reference Top = 3.3V
1 LSB
Reference Top - Reference Bottom
=
Resolution
2
3.3V - 0.0V
===
12
2
3.3V
4096
0.806mV
Table 2-1. ADC Input & Output Range
Index SHA1, SHA2, SHA3 Input (V) Digital Output (Binary) Digital Output (HEX)
0 0.000000 ~ 0.000806 0000_0000_0000 0x000
1 0.000806 ~ 0.001612 0000_0000_0001 0x001
2 0.001612 ~ 0.002418 0000_0000_0010 0x002
••• ••• ••• •••
1239 0.998634 ~ 0.999440 0100_1101_0111 0x4D7
1240 0.999440 ~ 1.000246 0100_1101_1000 0x4D8
1241 1.000246 ~ 1.001052 0100_1101_1001 0x4D9
••• ••• ••• •••
2047 1.649194 ~ 1.650000 0111_1111_1111 0x7FF
2048 1.650000 ~ 1.650806 1000_0000_0000 0x800
2049 1.650806 ~ 1.651612 1000_0000_0001 0x801
••• ••• ••• •••
4093 3.297582 ~ 3.298388 1111_1111_1101 0xFFD
4094 3.298388 ~ 3.299194 1111_1111_1110 0xFFE
4095 3.299194 ~ 3.300000 1111_1111_1111 0xFFF
2-3
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