Samsung S3F401F User Manual

USER′S MANUAL

S3F401F

Confidential Proprietary of Samsung Electronics Co., Ltd

Copyright © 2007 Samsung Electronics, Inc. All Rights Reserved

16/32-BIT RISC

MICROPROCESSOR

November, 2007

REV 1.00

Important Notice

The information in this publication has been carefully
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.

Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.

This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.

S3F401F 16/32-Bit RISC Microprocessor
User's Manual, Revision 1.00
Publication Number: 21-S3-F401F-112007

"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.

Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
personal injury or death may occur.

Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all
claims, costs, damages, expenses, and reasonable
attorney fees arising out of, either directly or
indirectly, any claim of personal injury or death that
may be associated with such unintended or
unauthorized use, even if such claim alleges that
Samsung was negligent regarding the design or
manufacture of said product.

Copyright © 2007 Samsung Electronics Co., Ltd.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are designed
and manufactured in accordance with the highest quality standards and objectives.

Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu
Yongin-City, Gyunggi-Do, Korea
C.P.O. Box #37, Suwon 446-711

TEL: (82) (31) 209-4956
FAX: (82) (31) 209-3262
Home-Page URL: Http://www.samsungsemi.com

Printed in the Republic of Korea

NOTIFICATION OF REVISIONS

ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea

PRODUCT NAME: S3F401F Microcontroller

DOCUMENT NAME: S3F401F User's Manual, Revision 1.00

DOCUMENT NUMBER: S3F401F-112007

EFFECTIVE DATE: Nov, 2007

SUMMARY: As a result of S3F410F development, designed with preliminary specification,

S3F401F User's Manual Revision 1.0 has been completed.

DIRECTIONS: Please note the changes into the next page, if you find some to be changed in

your copy (copies) of the S3F401F User’s Manual, Revision 1.0.

REVISION HISTORY

Revision Description of Change Author(s) Date

1.00 This Spec of S3F401F can be released officially.

Juil Kim 0.00 Preliminary Spec for internal release only.
Younghee Jin

Younghee Jin

Nov, 2006

Nov, 2007

REVISION DESCRIPTIONS (REV 1.00)

Chapter

Chapter Name Page

− − −

Subjects (Major changes comparing with last version)

Table of Contents

Chapter 1 Product Overview

1. Overview ..................................................................................................................................................1-1

1.1 Introduction.....................................................................................................................................1-1

2. Features...................................................................................................................................................1-2

3. Block Diagram..........................................................................................................................................1-3

4. Pin Assignments.......................................................................................................................................1-4

5. Pin Descriptions .......................................................................................................................................1-9

6. Memory Address......................................................................................................................................1-12

Chapter 2 A/D Converter

1. Overview ..................................................................................................................................................2-1

1.1 Features..........................................................................................................................................2-1

2. Block Diagram..........................................................................................................................................2-2

3. A/D Converter Operation..........................................................................................................................2-3

3.1 Function Description.......................................................................................................................2-3

4. Registers Description...............................................................................................................................2-7

Chapter 3 Basic Timer & Watchdog Timer

1. Overview ..................................................................................................................................................3-1

2. Function Description.................................................................................................................................3-2

2.1 Interval Timer Function...................................................................................................................3-2

2.2 Watchdog Timer Operation ............................................................................................................3-3

2.3 Timer Duration................................................................................................................................3-4

2.4 Watch Dog Timer Duration.............................................................................................................3-5

3. Registers Description...............................................................................................................................3-6

S3F401F_UM_REV1.00 MICROCONTROLLER iii

Table of Contents (Continued)

Chapter 4 Encoder Counter

1. Overview.................................................................................................................................................. 4-1

2. Function Description................................................................................................................................ 4-3

2.1 Position Counter Operation............................................................................................................ 4-3

3. Registers Description............................................................................................................................... 4-4

Chapter 5 Internal Flash ROM

1. Overview.................................................................................................................................................. 5-1

1.2 Features......................................................................................................................................... 5-1

2. Block Diagram .........................................................................................................................................5-1

3. Flash Configuration.................................................................................................................................. 5-2

3.1 Flash ROM Configuration ..............................................................................................................5-2

3.2 Address Alignment......................................................................................................................... 5-2

3.3 Working Mode................................................................................................................................ 5-2

3.4 Program Mode ...............................................................................................................................5-2

4. Programming Modes ........................................................................................................... ....................5-3

4.1 User Program Mode....................................................................................................................... 5-3

4.2 Normal Program............................................................................................................................. 5-4

4.3 Option Program.............................................................................................................................. 5-5

4.4 Sector Erase ..................................................................................................................................5-6

4.5 Chip Erase Flowchart..................................................................................................................... 5-7

4.6 Tool Program Mode .......................................................................................................... .............5-8

5. Data Protection........................................................................................................................................ 5-9

5.1 Protection Option Configuration..................................................................................................... 5-9

5.2 Jtag Interface Protection Bit 8........................................................................................................ 5-10

5.3 Hardware Protection Bit 17............................................................................................................ 5-10

5.4 Read Protection Bit 27................................................................................................................... 5-11

6. Registers Description............................................................................................................................... 5-12

iv S3F401F_UM_REV1.00 MICROCONTROLLER

Table of Contents (Continued)

Chapter 6 Inverter Motor Controller (IMC)

1. Overview ..................................................................................................................................................6-1

2. Block Diagram..........................................................................................................................................6-2

3. Function Description.................................................................................................................................6-3

3.1 Tri-Angular Wave............................................................................................................................6-3

3.2 Saw-Tooth Wave............................................................................................................................6-4

4. Phase Signal Generation .........................................................................................................................6-5

4.1 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-5

4.2 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-7

4.3 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-9

4.4 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-10

4.5 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-11

4.6 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-13

4.7 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-14

4.8 Tri-Angular Wave (IMMODE = 0) ...................................................................................................6-15

4.9 Saw-Tooth Wave (IMMODE = 1)....................................................................................................6-16

4.10 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-19

4.11 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-20

4.12 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-21

4.13 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-22

4.14 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-23

4.15 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-24

4.16 Saw-Tooth Wave (IMMODE = 1)..................................................................................................6-25

5. Inverter Motor Special Function Register.................................................................................................6-26

Chapter 7 Interrupt Controller

1. Overview ..................................................................................................................................................7-1

2. Functional Description..............................................................................................................................7-3

2.1 Configuring IRQ and FIQ Interrupt Service ....................................................................................7-3

2.2 Interrupt Registers..........................................................................................................................7-3

2.3 Interrupt Sources............................................................................................................................7-5

3. Registers Description...............................................................................................................................7-8

S3F401F_UM_REV1.00 MICROCONTROLLER v

Table of Contents (Continued)

Chapter 8 I/O Ports

1. Overview.................................................................................................................................................. 8-1

2. S3F401F Port Configuration Overview.................................................................................................... 8-2

3. I/O Port Control Registers ....................................................................................................................... 8-3

4. Registers Description............................................................................................................................... 8-4

Chapter 9 Clock & Power Management

1. Overview.................................................................................................................................................. 9-1

2. Phase Locked Loop................................................................................................................................. 9-4

2.1 PLL................................................................................................................................................. 9-4

2.2 PLL Value Change Steps............................................................................................................... 9-5

2.3 Capacitor for PLL Loop Filter......................................................................................................... 9-5

3. Mode Change.......................................................................................................................................... 9-6

3.1 Changing clock speed from normal mode to highspeed mode [NORMAL Æ HIGHSPEED]........ 9-6

3.2 Changing clock speed from highspeed mode to normal mode [HIGHSPEED Æ NORMAL]........ 9-6

3.3 Entering the stop mode from high speed mode [HIGHSPEED Æ STOP]..................................... 9-6

3.4 Exit From the STOP mode............................................................................................................. 9-6

3.5 Exit From the Clock fail mode........................................................................................................ 9-6

3.6 IDLE Mode and Internal Flash ROM.............................................................................................. 9-6

4. Registers Description............................................................................................................................... 9-7

vi S3F401F_UM_REV1.00 MICROCONTROLLER

Table of Contents (Continued)

Chapter 10 SSP (Synchronous Serial Port)

1. Overview ..................................................................................................................................................10-1

1.1 Features..........................................................................................................................................10-1

1.2 Programmable Parameters ............................................................................................................10-1

2. Block Diagram..........................................................................................................................................10-2

2.1 SSP Functional Description............................................................................................................10-3

2.2 Frame Format.................................................................................................................................10-6

2.3 Interrupt ..........................................................................................................................................10-13

3. Registers Description...............................................................................................................................10-14

Chapter 11 16-Bit Timers

1. Overview ..................................................................................................................................................11-1

2. Operation Description...............................................................................................................................11-3

2.1 Interval Mode Operation.................................................................................................................11-3

2.2 Match & Overflow Mode Operation ................................................................................................11-4

2.3 Capture Mode Operation................................................................................................................11-5

2.4 PWM Mode Operation....................................................................................................................11-6

S3F401F_UM_REV1.00 MICROCONTROLLER vii

Table of Contents (Continued)

Chapter 12 UART

1. Overview.................................................................................................................................................. 12-1

1.1 The Uart Performs: ........................................................................................................................ 12-1

1.2 IrDA SIR Block............................................................................................................................... 12-2

1.3 Features......................................................................................................................................... 12-2

1.4 Programmable Parameters............................................................................................................ 12-3

1.5 Variations from the 16C550 Uart ...................................................................................................12-4

2. Block Diagram .........................................................................................................................................12-5

3. Function Description................................................................................................................................ 12-6

3.1 Baud Rate Generator..................................................................................................................... 12-6

3.2 Transmit FIFO................................................................................................................................ 12-7

3.3 Transmit Logic................................................................................................................................ 12-7

3.4 Receive FIFO................................................................................................................................. 12-7

3.5 Receive Logic................................................................................................................................. 12-7

3.6 Uart Operation................................................................................................................................ 12-7

3.7 IrDA SIR Operation........................................................................................................................ 12-9

3.8 Interrupts........................................................................................................................................ 12-11

4. Registers Description............................................................................................................................... 12-14

Chapter 13 Electrical Data

1. DC Electrical Characteristics................................................................................................................... 13-1

Chapter 14 Mechanical Data

1. Overview.................................................................................................................................................. 14-1

viii S3F401F_UM_REV1.00 MICROCONTROLLER

List of Figures

Figure Title Page
Number Number

1-1 S3F401F Block Diagram..............................................................................................1-3

1-2 S3F401F Package Pin Assignments (100-QFP-1420)................................................1-4

2-1 A/D Converter Block Diagram......................................................................................2-2

2-2 ADC Operation Flow Chart ..........................................................................................2-6

3-1 Basic Timer Block Diagram..........................................................................................3-1

4-1 Encoder Counter Block Diagram .................................................................................4-2

4-2 Position Counter Operation..........................................................................................4-3

5-1 Flash Memory Controller Read/Write Block Diagram..................................................5-1

5-2 Normal Program Flowchart..........................................................................................5-4

5-3 Option Program Flowchart...........................................................................................5-5

5-4 Sector Erase Flowchart................................................................................................5-6

5-5 Chip Erase Flowchart...................................................................................................5-7

6-1 Inverter Motor Controller (IMC) Block Diagram ...........................................................6-2

6-2 Inverter Motor Controller (IMC) Signal generation (Tri-angular wave) ........................6-3

6-3 Inverter Motor Controller (IMC) Signal generation (Saw-tooth wave)..........................6-4

6-4 Inverter Motor Controller (IMC) Signal generation (Tri-angular wave) ........................6-5

7-1 S3F401F Interrupt Structure........................................................................................7-2

9-1 Clock State Machine Diagram .....................................................................................9-2

9-2 Clock Circuit Diagram ..................................................................................................9-3

9-3 PLL (Phase-Locked Loop) Block Diagram...................................................................9-5

9-4 Capacitor for PLL Loop Filter.......................................................................................9-5

S3F401F_UM_REV1.00 MICROCONTROLLER ix

List of Figures (Continued)

Figure Title Page
Number Number

10-1 SSP Block Diagram..................................................................................................... 10-2

10-2 SUB Block Diagram..................................................................................................... 10-3

10-3 SSP frame format (single transfer) with SPO=0 and SPH=0...................................... 10-7

10-4 SSP frame format (continuous transfer) with SPO=0 and SPH=0.............................. 10-7

10-5 SSP frame format with SPO=0 and SPH=1................................................................ 10-8

10-6 SSP frame format (single transfer) with SPO=1 and SPH=0...................................... 10-9

10-7 SSP frame format (continuous transfer) with SPO=1 and SPH=0.............................. 10-9

10-8 SSP Frame Format with SPO=1 and SPH=1.............................................................. 10-10

10-9 PrimeCell SSP Master Coupled to Two Slaves .......................................................... 10-11

10-10 SPI master coupled to two PrimeCell SSP slaves...................................................... 10-12

11-1 16-Bit Timer Block Diagram ........................................................................................ 11-2

11-2 Simplified Timer Function Diagram: Interval Timer Mode........................................... 11-3

11-3 Simplified Timer Function Diagram: Match & Overflow Timer Mode.......................... 11-4

11-4 Simplified Timer Function Diagram: Capture Mode.................................................... 11-5

11-5 Simplified Timer Function Diagram: PWM Mode........................................................ 11-6

11-6 PWM Signal Generation Diagram............................................................................... 11-7

12-1 UART Block Diagram (with FIFO)............................................................................... 12-5

12-2 UART character frame ................................................................................................ 12-7

12-3 IrDA data modulation................................................................................................... 12-10

13-1 ADC Offset Error .........................................................................................................13-6

13-2 ADC DLE, ILE.............................................................................................................. 13-7

14-1 100-QFP-1420 Package Dimensions.......................................................................... 14-1

x S3F401F_UM_REV1.00 MICROCONTROLLER

List of Tables

Table Title Page
Number Number

1-1 Pin Assignments − Pin Number Order.........................................................................1-5

1-2 S3F401F Pin Descriptions ...........................................................................................1-9

1-3 S3F401F Default Memory Map after Reset.................................................................1-12

1-4 The Base Address of Peripheral Special Registers.....................................................1-13

2-1 ADC Input & Output Range..........................................................................................2-3

2-2 ADC Control Special Function Registers.....................................................................2-7

3-1 Basic timer & WDT Special Function Registers...........................................................3-6

4-1 ENC Special Function Registers..................................................................................4-4

5-1 The Pins Used to Read/Write/Erase the Flash ROM in Tool Program Mode..............5-8

5-2 Protection Option Address and Protection Bits............................................................5-9

5-3 Smart Option Address Configuration...........................................................................5-10

5-4 Hardware Protection Area............................................................................................5-11

5-5 Internal Flash Special Function Registers ...................................................................5-12

6-1 IMC Special Function Registers...................................................................................6-25

7-1 S3F401F Interrupt Sources..........................................................................................7-5

7-2 Interrupt Controller Special Function Registers...........................................................7-8

8-1 S3F401F Port Configuration Overview........................................................................8-2

8-2 Port Control Special Function Registers......................................................................8-4

9-1 Clock & Power Management Special Function Register.............................................9-7

9-2 MDIV/PDIV/SDIV Allowed Values................................................................................9-11

10-1 UART Interrupts In Connection With FIFO ..................................................................10-13

10-2 Clock & Power Management Special Function Register.............................................10-14

11-1 TIMER Special Function Registers..............................................................................11-8

12-1 UART Special Function Registers ...............................................................................12-14

13-1 Absolute Maximum Ratings .........................................................................................13-1

13-2 D.C. Electrical Characteristics .....................................................................................13-2

13-3 Timing Constants.........................................................................................................13-3

13-4 PLL Timing Constants..................................................................................................13-3

13-5 Internal RC Oscillation Characteristics ........................................................................13-4

13-6 AC Electrical Characteristics........................................................................................13-4

13-7 12-bit ADC Electrical Characteristics...........................................................................13-5

13-8 AC Electrical Characteristics for Internal Flash ROM..................................................13-8

S3F401F_UM_REV1.00 MICROCONTROLLER xi

S3F401F_UM_REV1.00 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

1. OVERVIEW

1.1 INTRODUCTION

Samsung's S3F401F 16/32-bit RISC microcontroller is a cost-effective and high-performance microcontroller
solution for an inverter motor and a general-purpose application.

An outstanding feature of the S3F401F is its CPU core, a 16/32-bit RISC processor (ARM7TDMI-S) designed by
Advanced RISC Machines, Ltd. The ARM7TDMI-S core is a low-power, general purpose, microprocessor macro­cell, which was developed for the use in application-specific and customer-specific integrated circuits. Its simple,
elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive application. Using the
ARM7TDMI-S core, CMOS standard cell, and a data path compiler has developed the S3F401F. Most of the on­chip function blocks have been designed using an HDL synthesizer

The integrated on-chip functions, which are described in this document include:

• Built-in 256Kbyte NOR-Flash memory

• Internal 20Kbyte SRAM for stack, data memory, or code memory

• Interrupt controller: 90 interrupt sources, interrupt priority control logic and interrupt vector generation by H/W.

• Three programmable I/O port groups

• Two inverter timer, Two channel 16bit encoder counter, having PHASE A,B and Z

• Two-channel UART, Two-channel SSP

• Six-channel 16-bit timers with capture and PWM

• Fifteen-channel 12-bit ADC

• One-channel 8-bit basic timer and 3-bit watch-dog timer

• Crystal/Ceramic oscillator or external clock can be used as the clock source and PLL

• Power control: Normal, Idle, and Stop mode

• Clock monitor

1-1

PRODUCT OVERVIEW S3F401F_UM_REV1.00

2. FEATURES

CPU

• ARM7TDMI-S CPU Core

• 32-bit RISC architecture

Memory

• 256 Kbytes Internal Program Full Flash

• 20 Kbytes Internal SRAM

• Only little-endian support

General purpose I/O Pins

• Max. 65 pins

• 31 external interrupts

8-Bit Basic Timer

• Programmable interval timer

• Watch-dog timer’s clock source, overflow of 8-bit

counter

Watchdog Timer

• System reset when 3-bit counter overflow

Six 16-bit Timer/Counters (T/C0 - T/C5)

• Programmable interval timer

• External event counter function

• PWM function and capture function

Two Inverter Motor Controllers

• 3-Phase pairs’ PWM generation

• Programmable dead time insertion

• ADC conversion start signal generation

Two 16-Bit Encoder Counter

• Support position counter and speed counter

• Up/Down counter

• 3 inputs, Phase A,B and Z

• Capture mode support

Two channel 16-Bit Synchronous Serial Port

• Master or slave operation

• Programmable clock bit rate and pre-scale

• Separate 8x16bit transmit/receive FIFO

• 4 to 16-bit transmit/receive mode

Two Channels UART

• Programmable use of UART or IrDA SIR input

/output

• Separate 16x8bit transmit and 16x12bit receive

FIFO

• Programmable baud rate generator

• Standard asynchronous communication bits

(start, stop, parity)

• Auto generating parity bit

Analog to Digital Converter

• 15-channel analog inputs

• 12-bit resolution

• Simultaneous Sampling of 3 Single-Ended

Interrupt Controller

• Supports normal or fast interrupt modes

(IRQ, FIQ)

• Supports vectored interrupt

(Hard-wired Interrupt)

• S/W programmable interrupt priority

Two Power-Down Modes

• Idle: only CPU clock stops

• Stop: selected system clock and CPU clock stop

Clock Manager (CM)

• CPU and peripherals can be deactivated

individually

Phase-Locked Loop (PLL)

• Programmable clock synthesizer (Max 90MHz)

Operating Voltage Range

• 3.0 V to 3.6 V at 4.0MHz − 90.0MHz

(external crystal: 4.0MHz − 8MHz)

Power-On Reset (POR)

• Clock Monitor

Operating Temperature Range

• −40°C to +85°C

Available in 100 QFP Package

1-2

S3F401F_UM_REV1.00 PRODUCT OVERVIEW

3. BLOCK DIAGRAM

Crystal or

Ceramic

Oscillator

CLOCK

MONITOR

I/O

CONTROLLER

ARM7TDMI-S

CORE

INTERRUPT

CONTROLLER

PLL

IMC0/1

BRIDGE

SSP0/1

SSP0/1

AHB

FLASH-ROM

256KB

SRAM

20KB

TAP CONTROLLER

For JTAG

ENC0/1

ENC0/1IMC0/1

UART0/1

UART0/1

APB

BT & WDT

Timer0/1/2/3/4/5

Timer0/1/2/3/4/5

Timer0/1/2/3/4/5

12-BIT ADC

Figure 1-1. S3F401F Block Diagram

Timer0/1/2/3/4/5

TIMER 0/1/2/3/4/5

1-3

PRODUCT OVERVIEW S3F401F_UM_REV1.00

4. PIN ASSIGNMENTS

PLLVSSIP

P0.0/T0CLK

P0.1/T0CAP

P0.2/T0PWM

P0.3/T1CLK

P0.4/T1CAP

P0.5/T1PWM

P0.6/T2CLK

P0.7/T2CAP

P0.8/T2PWM/ADTRG

P0.9/PHASEA0
P0.10/PHASEB0
P0.11/PHASEZ0

Xin

Xout

VSSCORE0

VDDCORE0

P0.12/PWM0OFF

P0.13/PWM0U0
P0.14/PMW0D0
P0.15/PMW0U1
P0.16/PWM0D1
P0.17/PWM0U2
P0.18/PMW0D2

P1.0/UARTRXD0/INT0

P1.1/UARTTXD0/INT1

P1.2/UARTRXD1/INT2

P1.3/UARTTXD1/INT3

P1.4/T3CLK/INT4

P1.5/T3CAP/INT5

P1.6/T3PWM/INT6

RTCK

TMS

TDI

nRESET

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

TCK

99989796959493929190898887868584838281

VDDIO2

TDO

nTRST

VSSIO2

S3F401F

(100-QFP-1420C)

PLLVDDOUT

PLLVDDCORE

PLLCAP

PLLVSSCORE

ADCVSSIO

ADCVSSCORE

ADCVDDCORE

ADCVDDIO

P2.14/AIN14

P2.13/AIN13

P2.12/AIN12

80
79

P2.11/AIN11

78

P2.10/AIN10

77

P2.9/AIN9

76

P2.8/AIN8

75

P2.7/AIN7

74

P2.6/AIN6

73

P2.5/AIN5

72

P2.4/AIN4

71

P2.3/AIN3

70

P2.2/AIN2

69

P2.1/AIN1

68

P2.0/AIN0
VSSCORE2

67

VDDCORE2

66
65

P1.30/PWM1D2/INT30

64

P1.29/PWM1U2/INT29

63

P1.28/PWM1D1/INT28

62

P1.27/PWM1U1/INT27

61

P1.26/PWM1D0/INT26

60

P1.25/PWM1U0/INT25

59

P1.24/PWM1OFF/INT24

58

P1.23/PHASEZ1/INT23

57

P1.22/PHASEB1/INT22

56

P1.21/PHASEA1/INT21

55

P1.20/SSPFSS1/INT20

54

P1.19/SSPCLK1/INT19

53

P1.18/SSPRXD1/INT18

52

P1.17/SSPTXD1/INT17

51

MD2

50

MD1

MD0

P1.15/SSPCLK0/INT15

P1.16/SSPFSS0/INT16

P1.14/SSPRXD0/INT14

VSSIO0

VSSIP

VDDIO0

P1.7/T4CLK/INT7

P1.8/T4CAP/INT8

P1.9/T4PWM/INT9

VDDOUT

P1.10/T5CLK/INT10

P1.11/P5CAP/INT11

P1.12/T5PWM/INT12

VSSIO1

VDDIO1

VSSCORE1

VDDCORE1

P1.13/SSPTXD0/INT13

Figure 1-2. S3F401F Package Pin Assignments (100-QFP-1420)

1-4

S3F401F_UM_REV1.00 PRODUCT OVERVIEW

Table 1-1. Pin Assignments − Pin Number Order

No. Pin Name Default Function State Flash Function

1 P0.0 T0CLK
2 P0.1 T0CAP
3 P0.2 T0PWM
4 P0.3 T1CLK
5 P0.4 T1CAP
6 P0.5 T1PWM
7 P0.6 T2CLK
8 P0.7 T2CAP

−

−

−

−

−

−

−

−

9 P0.8 T2PWM ADTRG P0.8 I/O
10 P0.9 PHASEA0
11 P0.10 PHASEB0
12 P0.11 PHASEZ0
13 Xin
14 Xout
15 VSSCORE0
16 VDDCORE0

− −

− −

− −

− −

17 P0.12 PWM0OFF
18 P0.13 PWM0U0
19 P0.14 PMW0D0
20 P0.15 PMW0U1
21 P0.16 PWM0D1
22 P0.17 PWM0U2
23 P0.18 PMW0D2

−

−

−

−

−

−

−

−

−

−

24 P1.0 UARTRXD0 INT0 P1.0 I/O
25 P1.1 UARTTXD0 INT1 P1.1 I/O
26 P1.2 UARTRXD1 INT2 P1.2 I/O
27 P1.3 UARTTXD1 INT3 P1.3 I/O
28 P1.4 T3CLK INT4 P1.4 I/O
29 P1.5 T3CAP INT5 P1.5 I/O
30 P1.6 T3PWM INT6 P1.6 I/O

P0.2 I/O
P0.1 I/O
P0.2 I/O
P0.3 I/O
P0.4 I/O
P0.5 I/O
P0.6 I/O
P0.7 I/O

P0.9 I/O
P0.10 I/O
P0.11 I/O

Xin I
Xout O
VSS P

VDD P
P0.12 I/O
P0.13 I/O
P0.14 I/O
P0.15 I/O
P0.16 I/O
P0.17 I/O
P0.18 I/O

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

1-5

PRODUCT OVERVIEW S3F401F_UM_REV1.00

Table 1-1. Pin Assignments − Pin Number Order (Continued)

No. Pin Name Default Function State Flash Function

31 VSSIO0
32 VDDIO0
33 VSSIP

− −

− −

− −

34 P1.7 T4CLK INT7 P1.7 I/O
35 P1.8 T4CAP INT8 P1.8 I/O
36 P1.9 T4PWM INT9 P1.9 I/O
37 P1.10 T5CLK INT10 P1.10 I/O
38 P1.11 T5CAP INT11 P1.11 I/O
39 P1.12 T5PWM INT12 P1.12 I/O
40 VDDOUT
41 VSSCORE1
42 VDDCORE1
43 VSSIO1
44 VDDIO1

− −

− −

− −

− −

− −

45 P1.13 SSPTXD0 INT13 P1.13 I/O
46 P1.14 SSPRXD0 INT14 P1.14 I/O

VSS P
VDD P
VSS P

VDDOUT P

VSS P
VDD P
VSS P
VDD P

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

47 P1.15 SSPCLK0 INT15 P1.15 I/O SDAT (I/O)
48 P1.16 SSPFSS0 INT16 P1.16 I/O SCLK (I)
49 MD0
50 MD1

− −

− −

MD0 I MD0
MD1 I MD1

1-6

S3F401F_UM_REV1.00 PRODUCT OVERVIEW

Table 1-1. Pin Assignments − Pin Number Order (Continued)

No. Pin Name Default Function State Flash Function

51 MD2

− −

52 P1.17 SSPTXD1 INT17 P1.17 I/O
53 P1.18 SSPRXD1 INT18 P1.18 I/O
54 P1.19 SSPCLK1 INT19 P1.19 I/O
55 P1.20 SSPFSS1 INT20 P1.20 I/O
56 P1.21/ PHASEA1 INT21 P1.21 I/O
57 P1.22 PHASEB1 INT22 P1.22 I/O
58 P1.23 PHASEZ1 INT23 P1.23 I/O
59 P1.24 PWM1OFF INT24 P1.24 I/O
60 P1.25 PWM1U0 INT25 P1.25 I/O
61 P1.26 PWM1D0 INT26 P1.26 I/O
62 P1.27 PWM1U1 INT27 P1.27 I/O
63 P1.28/ PWM1D1 INT28 P1.28 I/O
64 P1.29 PWM1U2 INT29 P1.29 I/O
65 P1.30 PWM1D2 INT30 P1.30 I/O
66 VDDCORE2
67 VSSCORE2
68 P2.0 AIN0
69 P2.1 AIN1
70 P2.2 AIN2
71 P2.3 AIN3
72 P2.4 AIN4
73 P2.5 AIN5
74 P2.6 AIN6
75 P2.7 AIN7
76 P2.8 AIN8
77 P2.9 AIN9
78 P2.10 AIN10
79 P2.11 AIN11
80 P2.12 AIN12

− −

− −

−

−

−

−

−

−

−

−

−

−

−

−

−

MD2 I MD2

−

−

−

−

−

−

−

−

−

−

−

−

−

−

VDD P
VSS P
P2.0 I/O
P2.1 I/O
P2.2 I/O
P2.3 I/O
P2.4 I/O
P2.5 I/O
P2.6 I/O
P2.7 I/O
P2.8 I/O

P2.9 I/O
P2.10 I/O
P2.11 I/O
P2.12 I/O

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

1-7

PRODUCT OVERVIEW S3F401F_UM_REV1.00

Table 1-1. Pin Assignments − Pin Number Order (Continued)

No. Pin Name Default Function State Flash Function

81 P2.13 AIN13
82 P2.14 AIN14
83 ADCVDDIO
84 ADCVSSIO
85 ADCVDDCORE
86 ADCVSSCORE
87 PLLVSSCORE
88 PLLCAP
89 PLLVDDCORE
90 PLLVDDOUT
91 PLLVSSIP
92 VSSIO2
93 VDDIO2
94 nTRST
95 TDO
96 TCK
97 TDI
98 TMS
99 RTCK

100 nRESET

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

− −

−

−

P2.13 I/O –
P2.14 I/O –

VDD P –
VSS P –
VDD P –
VSS P –
VSS P –

PLLCAP I –

VDD P –

VDDPLLOUT P –

VSS P –
VSS P –
VDD P –

nTRST I –

TDO O –
TCK I –

TDI I –

TMS I –

RTCK O –

nRESET I nRESET

1-8

S3F401F_UM_REV1.00 PRODUCT OVERVIEW

5. PIN DESCRIPTIONS

Table 1-2. S3F401F Pin Descriptions

Module Pin Name Description I/O

BUS

MD[2:0]

CONTROLLER

INTERRUPT INT[30:0] External interrupt request 31 to 0. I
CLOCK & Xin Crystal input of oscillator circuit for system clock. I
RESET Xout Crystal output of oscillator circuit for system clock. O

nRESET Reset input: The global system reset input for the S3F401F.

16-BIT TIMER

T[5:0]CLK External clock input for Timer I
T[5:0]CAP Capture input for Timer I

T[5:0]PWM PWM output for Timer O
UARTRXD[1:0] UART receive I UART
UARTTXD[1:0] UART transmit O

SSP

SSPRXD[1:0] SSP receive I

SSPTXD[1:0] SSP transmit O
SSPCLK[1:0] SSP clock I/O
SSPFSS[1:0] SSP frame input (for slave) / slave select output (for master) I/O

AIN[14:0] ADC input AI ADC

ADTRG ADC trigger input I

The MD[2:0] can configure the operating mode of chip.
000 = Normal mode
001 = SPGM mode (Flash programming mode with writing tool)
Others = Test mode
Connect to GND through a 100nF capacitor with each mode

pin.

Capacitor for PLL loop filter. PLLCAP
Connect to GND through a 1200pF capacitor

For a system initialization, nRESET must be held to LOW level
for at least 1uSec. Connect to GND through 100nF and 10nF
capacitor.

I

I

I

1-9

PRODUCT OVERVIEW S3F401F_UM_REV1.00

Table 1-2. S3F401F Pin Descriptions (Continued)

Module Pin Name Description I/O

SDAT Serial Data pin (Output when reading, Input when writing)

I/O TOOL Program

Input & Push-pull output port can be assigned.

SCLK Serial Clock, input only

I

Writer speed : Max 250kHz, Read speed: Max 3MHz

JTAG

nTRST nTRST (TAP Controller Reset) can reset the TAP controller at

I
power-up. A 200K pull-up resistor is connected to nTRST pin,
internally. If the debugger is not used, nTRST pin should be
"Low" level or low active pulse should be applied before CPU
running. For example, nRESET signal can be tied with
nTRST.

TMS TMS (TAP Controller Mode Select) can control the sequence

I
of the state diagram of TAP controller. A 200K pull-up resistor
is connected to TMS pin, internally.

TCK TCK (TAP Controller Clock) can provide the clock input for the

I
JTAG logic. This pin is floating pin. When reduced the current
and not debugging mode, connect to the VDD with pull-up
resistor.

RTCK RTCK (TAP Controller Retiming Clock) can provide the clock

I
output for the JTAG logic.

Connect to GND through a 33pF capacitor.

TDI TDI (TAP Controller Data Input) is the serial input for JTAG

I
port. A 200K pull-up resistor is connected to TDI pin,
internally.

TDO TDO (TAP Controller Data Output) is the serial output for

O

JTAG port.

INVERTER
MOTOR
CONTROLLER

PWM[1:0]U[2:0] PWM output for inverter motor O
PWM[1:0]D[2:0] PWM output for inverter motor O

PWM[1:0]OFF Input pin for PWM output off I
ENCODER PHASEA[1:0] Phase A input pin I
PHASEB[1:0] Phase B input pin I
PHASEZ[1:0] Phase Z input pin I
GERNAL

PURPOSE
PORT

P0.[18:0] General input/output port 0 I/O
P1.[30:0] General input/output port 1 I/O
P2.[14:0] General input/output port 2 I/O

1-10

S3F401F_UM_REV1.00 PRODUCT OVERVIEW

Table 1-2. S3F401F Pin Descriptions (Continued)

Module Pin Name Description I/O

POWER VDDCORE[2:0]
VSSCORE[2:0]
VDDIO[2:0]

Core logic V
Core logic V
I/O VDD (Typ. 3.3V)

(Typ. 3.3V)

DD
SS

P
P
P

Connect to GND through a 100nF capacitor.

SS

SS

(Typ. 3.3V)

DD
SS

(Typ. 3.3V)

DD
SS

VSSIO[2:0]
VSSIP
ADCVDDCORE
ADCVSSCORE
ADCVDDIO
ADCVSSIO
PLLVDDCORE

I/O V
V
ADC Core logic V
ADC Core logic V
ADC I/O V
ADC I/O V
PLL Core logic VDD (Typ. 3.3V)
Connect to GND through a 100nF capacitor.

PLLVSSCORE
PLLVSSIP

PLL Core logic V
V

SS

SS

PLLVDDOUT Connect to GND through a 1uF capacitor (From internal regulator) P
VDDOUT Connect to GND through a 1uF capacitor (From internal regulator) P

P
P
P
P
P
P
P

P
P

1-11

PRODUCT OVERVIEW S3F401F_UM_REV1.00

6. MEMORY ADDRESS

When the reset of S3F401F micro-controller is asserted, the ARM core is in boot mode to access the internal flash
at address 0x00000000. The internal RAM is located at address 0x00400000.

Table 1-3. S3F401F Default Memory Map after Reset

Memory Space Size Application Abort when Accessed

0xFFFFFFFF

−

0xFF000000

0xFEFFFFFF

−

0x00405000

0x00404FFF

−

−

−

20Kbytes

Peripheral devices

Reserved

Internal RAM

0x00400000

0x003FFFFF

−

0x00040000

0x0003FFFF

−

−

256Kbytes

Reserved

Internal flash

0x00000000

No

Yes

No

Yes

No

1-12

S3F401F_UM_REV1.00 PRODUCT OVERVIEW

Table 1-4. The Base Address of Peripheral Special Registers

Peripheral Base Address

CM 0xFF00_0000

BT/WDT 0xFF00_4000

TC0 0xFF00_8000
TC1 0xFF00_C000
TC2 0xFF01_0000
TC3 0xFF01_4000
TC4 0xFF01_8000

TC5 0xFF01_C000
IMC0 0xFF02_0000
IMC1 0xFF02_4000

ENC0 0xFF02_8000
ENC1 0xFF02_C000
SSP0 0xFF03_0000

SSP1 0xFF03_4000
UART0 0xFF03_8000
UART1 0xFF03_C000

ADC 0xFF04_0000

IOPORT 0xFF04_4000

IFC 0xFFF0_0000
VIC 0xFFFF_FF00

1-13

S3F401F_UM_REV1.00 A/D CONVERTER

2 A/D CONVERTER

1. OVERVIEW

The S3F401F has a 12-bit ADC. It converts the analog input signal into 12-bit binary digital codes at a maximum
sampling rate of 4MHz. The device is a monolithic ADC with on-chip, which consists of three sample and hold
amplifiers, four multiplying DACs, five sub-ranging flash ADCs and current reference. Normal speed of input is
below 100kHz which can be quantized by 4MHz clock.

1.1 FEATURES

• ADC Resolution: 12-bit

• DLE (Differential Linearity Error): Max. ± 1.0 LSB (Least Bit)

• ILE (Integral Linearity Error): Max. ± 3.2 LSB

• Maximum Conversion Rate: 4MHz clock

• Low Power Consumption

• Power Supply Voltage: 3.3V

• Analog Input Range: 0.0V ∼ 3.3V

2-1

A/D CONVERTER S3F401F_UM_REV1.00

2. BLOCK DIAGRAM

AIN0
AIN1

AIN13
AIN14

ADCCON.15-.12: SHA1SEL

AIN0
AIN1

AIN13
AIN14

ADCCON.19-.16:SHA2SEL

AIN0
AIN1

AIN13
AIN14

ADCCON.23-.20:SHA3SEL

ADTRG

SHA1

SHA2

SHA3

ADCCON.9-.8:MODESEL

ADCCON.9-.8:MODESEL

12bit ADC

From

ADCCON.3-.2:TRIGSEL

ADCCON.0:START

IMC

Figure 2-1. A/D Converter Block Diagram

ADCRESULT1.11-.0 :
ADCRESULT2.11-.0 :
ADCRESULT3.11-.0 :

INTMASK

INTPND

DATA1

DATA2

DATA3

INT_EOC

2-2

S3F401F_UM_REV1.00 A/D CONVERTER

3. A/D CONVERTER OPERATION

3.1 FUNCTION DESCRIPTION

ADC has 3-analog input channels, SHA1, SHA2 and SHA3. After 3 conversion of ADC, the result of SHA1 is
pushed into the ADCRESULT1, the result of SHA2 is pushed into the ADCRESULT2 and the result of SHA3 is
pushed into the ADCRESULT3.

3.1.1 ADC Input

AIN[14:0] function pins are used for an analog input source to convert by ADC. ADC 3-input channels can be
selected one among AIN[14:0] inputs. Input signal range is followed by the boundary of reference, Reference TOP
and Reference BOTTOM.

Input Voltage Range: 0.0V ~ 3.3V
Reference Bottom = 0.0V, Reference Top = 3.3V

1 LSB

Reference Top - Reference Bottom

=

Resolution

2

3.3V - 0.0V

===

12

2

3.3V
4096

0.806mV

Table 2-1. ADC Input & Output Range

Index SHA1, SHA2, SHA3 Input (V) Digital Output (Binary) Digital Output (HEX)

0 0.000000 ~ 0.000806 0000_0000_0000 0x000
1 0.000806 ~ 0.001612 0000_0000_0001 0x001
2 0.001612 ~ 0.002418 0000_0000_0010 0x002

••• ••• ••• •••

1239 0.998634 ~ 0.999440 0100_1101_0111 0x4D7
1240 0.999440 ~ 1.000246 0100_1101_1000 0x4D8
1241 1.000246 ~ 1.001052 0100_1101_1001 0x4D9

••• ••• ••• •••

2047 1.649194 ~ 1.650000 0111_1111_1111 0x7FF
2048 1.650000 ~ 1.650806 1000_0000_0000 0x800
2049 1.650806 ~ 1.651612 1000_0000_0001 0x801

••• ••• ••• •••

4093 3.297582 ~ 3.298388 1111_1111_1101 0xFFD
4094 3.298388 ~ 3.299194 1111_1111_1110 0xFFE
4095 3.299194 ~ 3.300000 1111_1111_1111 0xFFF

2-3

A/D CONVERTER S3F401F_UM_REV1.00

3.1.2 A/D Conversion

3.1.2.1 The Sampling Mode

S3F401F′s ADC can get the result of maximum 3 converted digital data at one time. In other means, user can get
the AD conversion data one, two or three by one conversion. This is determined the ADC Mode Selection Bits in
ADCCON register.

MODESEL[1:0] Description Active Channel

0 0 ′b
0 1 ′b
1 0 ′b
1 1 ′b

3-point simultaneous sampling SHA1 SHA2 SHA3
1-point sampling SHA1
2-point simultaneous sampling SHA1 SHA2
Reserved

− − −

− −

−

3.1.2.2 The Conversion Start

The ADC conversion can be started by 3 triggered sources. Start trigger source is determined by TRIGSEL[1:0]
bits in ADCCON register. User should select the corresponding value each application.

a. Software Command
b. Inverter Motor Control Block (IMC) trigger signal
c. External Signal inserted into ADCTRG pin.

3.1.2.3 The End of Conversion

After finishing the conversion, user can catch the valid data by reading each result register. The end of conversion
is informed by the value of EOC bit in the interrupt pending register. So after ADC conversion, user should check
EOC pending bit and clear.

3.1.2.4 The Conversion Time

When the external/internal clock (Fin) frequency is 8MHz and the divider value is ‘1’ (Fin/2), total 12-bit conversion
time is as follows:

A/D converter clock = 8MHz / 2 = 4MHz

Conversion speed = 4MHz / 11cycles = 363.6 kHz → Conversion time = 2.75 us

NOTES:

1. This A/D converter was designed to operate at maximum 4MHz clock. If 1xchannel is selected for ADC conversion
(ADCCON.9-.8 = 01), maximum 9xclocks are needed for ADC conversion. If 2xchannels are selected for ADC conversion
(ADCCON.9-.8 = 10), maximum 10xclocks are needed for ADC conversion. If 3xchannels are selected for ADC
conversion (ADCCON.9-.8 = 00), maximum 11xclocks are needed for ADC conversion.

2. ADCCLK source is Fin, not PCLK. ADCCLK must be less than PCLK or equal.

2-4

S3F401F_UM_REV1.00 A/D CONVERTER

3.1.3 Standby Mode

Standby mode is activated when ADCCON.1 is set to '0'. In this mode, A/D conversion operation is halted and all
ADC result registers are set to ‘0’.

3.1.4 ADC Interrupt

The ADC generates an EOC interrupt when conversion is completed while ADC interrupt is enabled. You can
know if whether that interrupt occurs or not by reading the interrupt pending register. This interrupt bit can be
enabled or disabled using respectively the interrupt enable register and interrupt disable register.

NOTE

If you know whether an interrupt from ADC (EOC) occurs or not, read and check the EOC bit in the
interrupt pending register. It can cause the different result to read ADCSTATUS.0 (STATUS) bit to check
EOC interrupt.

2-5

A/D CONVERTER S3F401F_UM_REV1.00

ADC Enable

ADC Clock Setting

Which ADC Trigger Source

ADCTRG

Software

IMC

ADCTRG Pin setting
EDGE Type Selection

Which Sampling Mode?

1-sampling

SHA1

2-sampling

SHA1, SHA2

ADC START

Conversion SHA1 Conversion SHA1

Conversion SHA2

EOC = '1' ?

read

ADCRESULT1

read

ADCRESULT1

read

ADCRESULT2

3-sampling

SHA1,SHA2,SHA3

Conversion SHA1
Conversion SHA2
Conversion SHA3

read

ADCRESULT1

read

ADCRESULT2

read

ADCRESULT3

STOP

Figure 2-2. ADC Operation Flow Chart

2-6

S3F401F_UM_REV1.00 A/D CONVERTER

4. REGISTERS DESCRIPTION

Base Address − 0xFF04_0000

Table 2-2. ADC Control Special Function Registers

Offset Address Register Description R/W Reset Value

0x000 ADCCON ADC control register R/W 0x0000_0000
0x004 ADCSTATUS ADC status register R 0x0000_0000
0x008 ADCRESULT1 12bit ADC result register 1 R 0x0000_0000

0x00C ADCRESULT2 12bit ADC result register 2 R 0x0000_0000

0x010 ADCRESULT3 12bit ADC result register 3 R 0x0000_0000

2-7

A/D CONVERTER S3F401F_UM_REV1.00

ADC Control Register ADCCON (0x000) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

SHA3SEL [23:20] SHA2SEL [17:16]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

SHA1SEL [15:12]

− −

MODESEL[9:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

−

TRIGEDGESEL CLKSEL[5:4] TRIGSEL[3:2] EN START

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

START ADC Conversion Start Bit

0 = No effect
1 = Start

Note: This bit is auto-clear bit.

EN ADC Block Enable Bit

0 = Disable
1 = Enable

TRIGSEL ADC Start Trigger Signal Selection Field

00 = Software (By ADCCON.0)
01 = Inverter block
1x = ADCTRG pin

CLKSEL ADC Clock (ADCCLK) Selection Field

000 = Fin
001 = Fin /2
010 = Fin /4
011 = Fin /8

Note: ADCCLK source is Fin, not PCLK, and ADCCLK is less than PCLK or equal.

TRIGEDGESEL

ADC Trigger Edge Selection Bit for ADTRG pin

0 = Falling edge
1 = Rising edge

2-8

S3F401F_UM_REV1.00 A/D CONVERTER

ADC Control Register (Continued) ADCCON (0x000) Access: Read/Write

MODESEL ADC Mode Selection Field

00 = 3-point simultaneous sampling
01 = 1-point sampling
10 = 2-point simultaneous sampling

SHA1SEL

ADC Input Selection Field for SHA1

0000 = AIN0 0101 = AIN5 1010 = AIN10
0001 = AIN1 0110 = AIN6 1011 = AIN11
0010 = AIN2 0111 = AIN7 1100 = AIN12
0011 = AIN3 1000 = AIN8 1101 = AIN13
0100 = AIN4 1001 = AIN9 1110 = AIN14

SHA2SEL

ADC Input Selection Field for SHA2

0000 = AIN0 0101 = AIN5 1010 = AIN10
0001 = AIN1 0110 = AIN6 1011 = AIN11
0010 = AIN2 0111 = AIN7 1100 = AIN12
0011 = AIN3 1000 = AIN8 1101 = AIN13
0100 = AIN4 1001 = AIN9 1110 = AIN14

SHA3SEL

ADC Input Selection Field for SHA3

0000 = AIN0 0101 = AIN5 1010 = AIN10
0001 = AIN1 0110 = AIN6 1011 = AIN11
0010 = AIN2 0111 = AIN7 1100 = AIN12
0011 = AIN3 1000 = AIN8 1101 = AIN13
0100 = AIN4 1001 = AIN9 1110 = AIN14

NOTE

After ADC block is enabled (ADCEN==1), 40us stabilization time must be needed.

2-9

A/D CONVERTER S3F401F_UM_REV1.00

ADC Status Register ADCSTATUS (0x004) Access: Read Only

31 30 29 28 27 26 25 24

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

23 22 21 20 19 18 17 16

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

15 14 13 12 11 10 9 8

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

− − − − − − −

STATUS

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

STATUS

NOTE

ADC Status Monitoring Bit:

This bit can notify the status of ADC.
0 = ADC is not on operating
1 = ADC is on operating

To change the configuration of ADC, You must check ADCSTATUS (ADC Status Register)

2-10

S3F401F_UM_REV1.00 A/D CONVERTER

ADC Converter Data1 Register ADCRESULT1 (0x008) Access: Read Only

31 30 29 28 27 26 25 24

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

23 22 21 20 19 18 17 16

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

15 14 13 12 11 10 9 8

− − − −

DATA1 [11:8]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

DATA1 [7:0]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

DATA1

NOTE

A/D Converted Output Data Value

−

0x000

When A/D conversion is finished, the conversion result can be read from the ADCRESULT1/2/3 register.
The ADCRESULT1/2/3 register should be read after the conversion is finished.

0xFFF

2-11

A/D CONVERTER S3F401F_UM_REV1.00

ADC Converter Data2 Register ADCRESULT2 (0x00C) Access: Read Only

31 30 29 28 27 26 25 24

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

23 22 21 20 19 18 17 16

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

15 14 13 12 11 10 9 8

− − − −

DATA2 [11:8]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

DATA2 [7:0]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

DATA2

NOTE

A/D Converted Output Data Value

−

0x000

When A/D conversion is finished, the conversion result can be read from the ADCRESULT1/2/3 register.
The ADCRESULT1/2/3 register should be read after the conversion is finished

0xFFF

2-12

S3F401F_UM_REV1.00 A/D CONVERTER

ADC Converter Data3 Register ADCRESULT3 (0x010) Access: Read Only

31 30 29 28 27 26 25 24

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

23 22 21 20 19 18 17 16

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

15 14 13 12 11 10 9 8

− − − −

DATA3 [11:8]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

DATA3 [7:0]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

DATA3

NOTE

A/D Converted Output Data Value

−

0x000

When A/D conversion is finished, the conversion result can be read from the ADCRESULT1/2/3 register.
The ADCRESULT1/2/3 register should be read after the conversion is finished

0xFFF

2-13

S3F401F_UM_REV1.00 BASIC TIMER & WDT

3 BASIC TIMER & WATCHDOG TIMER

1. OVERVIEW

Basic Timer/Watch-Dog Timer can be used to resume the controller operation when it is disturbed due to noise,
system error, or other kinds of malfunction.

To have a configuration on Watch-dog Timer, the overflow signal from 8-bit Basic Timer should be fed to t he clock
input of 3-bit Watch-dog Timer as shown in below figure. User can enable or disable the Watch-dog Timer by
software, i.e., by controlling the configuration in BTCON register. If users do not want to use the configuration of
Watch-dog Timer, the 8-bit Basic Timer can only be used as a normal interval timer to request t he interru pt service.
Also, it works to signal the end of the required oscillation interval after a reset or Stop mode release.

For example, the Basic Timer can give the overflow signal to necessary logic blocks after a reset or release from
Stop mode. In this case, the overflow signal from Basic Timer can guarantee the necessary time delay for stable
clock from external oscillator circuit.

BTCON.0 : WDTC

BTCON.3-.2: CS

CLK DIV

12

Fin/2

10

Fin

4,6 or 8MHz

.

NOTE: In the clock fail mode, the clock source of basic timer is internal oscillator.

Fin/2

6

Fin/2

5

Fin/2

BTCON.1: BTC

BTCNT.7-.0: BCV

8-Bit Basic Counter

Clear

Figure 3-1. Basic Timer Block Diagram

BTCON.15-.8: WDTE

RESET or STOP

BTCNT.11-.8: WCV

3-Bit WDTimer Counter

INTPND

After releasing from RESET or STOP mode,
when BTCNT.4 is set , CPU Start.

RESET or STOP or IDLE

Clear

OVF

nRESET

INTMSK

INT_BT

3-1

BASIC TIMER & WDT S3F401F_UM_REV1.00

2. FUNCTION DESCRIPTION

2.1 INTERVAL TIMER FUNCTION

The primary function of Basic Timer is to measure the elapsed time between events. The standard time interval is
equal to 256 basic timer clock pulses, which is an overflow signal from 8-bit Basic Timer.

The content of 8-bit counter register, BTCNT, is increased it content every when a clock signal is detected which
corresponds to the frequency selected by BTCON. The BTCNT con tinues its co unting until an overflow occurs, i.e.,
the content reaches to 255. An overflow can cause the BT interrupt pending flag to be set, which signal s that the
designated time interval has elapsed. In this case, when an interrupt request is generated, BTCNT is cleared to all
zero, and the counting continues from 0x00, again.

2.1.1 Oscillation Stabilization Using Interval Timer Function

You can use the Basic Timer to have programmable delay time, which is necessary for stabil izing the clock signal
from oscillator circuit after reset or Stop mode release.

When the S3F401F is in Stop mode, the reset or external interrupt request can wake up the S3F401F. Please
understand that the oscillator circuit is in disable state when the S3F401F is in Stop mode. In case of wake-up by
reset, the oscillator should start first. Because the default clock division ratio is Fin / 2^12, the Fin / 2^12 clock will be
fed to the 8-bit Basic Timer. When an overflow occurs from Bit 4 of BTCNT register(Not using 8-bit, but 4-bit of Basic
Timer), this kind of overflow signal can release the clock blocking to CPU. In other word, the normal clo ck can be fed
to S3F401F when an overflow of Bit 4 in Basic Timer. In case of wake-up by external interrupt request, the only
difference from reset, is clock division ratio. While we should use the default value of clock division ratio for the case
of wake-up by reset, we use the pre-defined value of clock division ratio before entering into Stop mode for the case
of wake-up by external interrupt request. In any case, the CPU ca n resum e its operation wh en normal clock can b e
fed to the blocks in S3F401F.

In summary, please take following sequence for releasing S3F401F from Stop mode:

1. When S3F401F is in Stop mode, the escape from Stop mode can be made by a power-on reset or an external
interrupt. At same time, the oscillator can start its oscillation.

2. In case of wake-up by power-on reset, the Basic Timer will increase its content(BTCNT) at the rate of Fin / 2^12,
which is the default rate of clock division ration. In case of wake-up by external interrupt request, the Basic Timer
will increase its content (BTCNT) at the rate of preset value, which is written before entering into Stop mode.

3. The normal clock from oscillator will be delayed to be fed to all logic blocks inside S3F401F until the 4

th

bit of
Basic Timer is generated. It means that you can use the Basic Timer to guarantee the stable clock from
oscillator, i.e., waiting up to stable oscillation.

4. When the normal clock can be fed to S3F401F, the S3F401F can resume the operation.

3-2

S3F401F_UM_REV1.00 BASIC TIMER & WDT

2.2 WATCHDOG TIMER OPERATION

The Basic Timer can also be used as a "Watch-Dog" Timer to recover the S3F401F from the unexpe cted program
sequence, that is, system or program operation error due to external factor. For example, the external noise can
cause this kind of situation, which means that the CPU is running the unexpected code sequence, i.e., malfunction
of CPU. To recover the CPU from the unexpected sequence, the Watch -Dog Timer should reset the CPU in ca se of
malfunction. But, during normal sequence, the instruction which clear the Watch-Dog Timer before the overflo w of
Watch-Dog Timer (Within a given period) should be executed at the proper points in a program. If this instruction can
be executed in certain circumstance, it means the overflow of Watch-Dog Timer and it can generate the internal
reset signal generation to restart the CPU from the beginning. In summary, an operation of Watch-Dog Timer is as
follows:

• Each time BTCNT overflows, an overflow signal should be sent to the Watch-Dog Timer Count er, WDTCNT.

• If WDTCNT overflows, system reset should be generated.

NOTE

A reset signal can clear the BTCON as 0x0000. This value can enable the Watch -Dog Timer because it is
not 0xA5 (Please understand the Watch-Dog Timer can be disable when its content (WDTE field in
BTCON[15:8] register) is 0xA5). For normal program sequen ce, the application program should prevent the
overflow. To do this, the WDTCNT value should be cleared (by writing a "1" to WDTC bit of the Basic Timer
Control Register (BTCON[0])) before the overflow occurs.

3-3

BASIC TIMER & WDT S3F401F_UM_REV1.00

2.3 TIMER DURATION

2.3.1 Basic Timer Duration

The Basic Timer Counter, BTCNT, can be used to specify the time -out duration, and i s a free-runnin g 8-bit counte r.
Please keep below table as reference for duration of timer.

Clock Source Resolution Interval Time

Fin = 4MHz Fin / 2^5 8 us 2^5 * 2^8 / Fin = 2.048 ms
Fin = 4MHz Fin / 2^6 16 us 2^6 * 2^8 / Fin = 4.098 ms
Fin = 4MHz Fin / 2^10 256 us 2^10 * 2^8 / Fin = 65.536 ms
Fin = 4MHz Fin / 2^12 1024 us 2^12 * 2^8 / Fin = 262.144 ms

Clock Source Resolution Interval Time

Fin = 6MHz Fin / 2^5 5.33 us 2^5 * 2^8 / Fin = 1.364 ms
Fin = 6MHz Fin / 2^6 10.66us 2^6 * 2^8 / Fin = 2.728 ms
Fin = 6MHz Fin / 2^10 166.66 us 2^10 * 2^8 / Fin = 42.664 ms
Fin = 6MHz Fin / 2^12 682.66 us 2^12 * 2^8 / Fin = 174.760 ms

Clock Source Resolution Interval Time

Fin = 8MHz Fin / 2^5 4 us 2^5 * 2^8 / Fin = 1.024 ms
Fin = 8MHz Fin / 2^6 8 us 2^6 * 2^8 / Fin = 2.048 ms
Fin = 8MHz Fin / 2^10 128 us 2^10 * 2^8 / Fin = 32.768 ms
Fin = 8MHz Fin / 2^12 512 us 2^12 * 2^8 / Fin = 131.072 ms

3-4

S3F401F_UM_REV1.00 BASIC TIMER & WDT

2.4 WATCH DOG TIMER DURATION

The Watch-Dog Timer Counter, WTCNT, can be used to specify the time-out duration and is a free-running 3-bit
counter. To enable Watch-Dog Timer, you should write the data in BTCON[15:8] register except 0xA5. In case of
0xA5, it will disable the Watch-Dog Timer. After writing certain value in BTCON[15:8] except 0xA5, there will be a
system reset if the overflow occurs.

Clock Source Resolution Watch-Dog Timer Interval Time

Fin = 4MHz Fin / 2^5* 2^8 2.048 m s 2^5 * 2^8 * 2^3 / Fin =16.384 ms
Fin = 4MHz Fin / 2^6* 2^8 4.098 m s 2^6 * 2^8 * 2^3 / Fin = 32.784 ms
Fin = 4MHz Fin / 2^10 * 2^8 65.536 ms 2^10 * 2^8 * 2^3 / Fin = 524.288 ms
Fin = 4MHz Fin / 2^12 * 2^8 262.144 ms 2^12 * 2^8 *2^3 / Fin = 2.097 s

Clock Source Resolution Watch-Dog Timer Interval Time

Fin = 6MHz Fin / 2^5* 2^8 1.364 ms 2^5 * 2^8 * 2^3 / Fin = 10.912 ms
Fin = 6MHz Fin / 2^6* 2^8 2.728 ms 2^6 * 2^8 * 2^3 / Fin = 21.824 ms
Fin = 6MHz Fin / 2^10 * 2^8 42.664 ms 2^10 * 2^8 * 2^3 / Fin = 341.312 ms
Fin = 6MHz Fin / 2^12 * 2^8 174.760 ms 2^12 * 2^8 *2^3 / Fin = 1.398 s

Clock Source Resolution Watch-Dog Timer Interval Time

Fin = 8MHz Fin / 2^5* 2^8 1.024 ms 2^5 * 2^8 * 2^3 / Fin = 8.192 ms
Fin = 8MHz Fin / 2^6* 2^8 2.048 ms 2^6 * 2^8 * 2^3 / Fin = 16.384 ms
Fin = 8MHz Fin / 2^10* 2^8 32.768 ms 2^10 * 2^8 * 2^3 / Fin = 262.144 ms
Fin = 8MHz Fin / 2^12 * 2^8 131.072 ms 2^12 * 2^8 *2^3 / Fin = 1.048 s

3-5

BASIC TIMER & WDT S3F401F_UM_REV1.00

3. REGISTERS DESCRIPTION

Base Address − 0xFF00_4000

Table 3-1. Basic timer & WDT Special Function Registers

Offset Address Register Description R/W Reset Value

0x000 BTCON Basic timer control register R/W 0x0000_0000
0x004 BTCNT Basic timer count register R 0x0000_0000

3-6

S3F401F_UM_REV1.00 BASIC TIMER & WDT

Basic Timer Control Register BTCON (0x000) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

WDTE[15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

− − − −

CS[3:2] BTC WDTC

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

WDTC Watch-Dog Timer Clear Bit

0 = No effect
1 = Watch-Dog Timer Counter will be cleared to all zero.

Note: This bit is auto-clear bit.

BTC Basic Timer Clear Bit

0 = No effect
1 = Basic Timer Counter will be cleared to all zero.

Note: This bit is auto-clear bit.

CS Clock Source Select Field

00 = Fin / 2^12
01 = Fin / 2^10
10 = Fin / 2^6
11 = Fin / 2^5

WDTE Watchdog Timer Enable Bit

0xA5 = Watchdog Timer Counter will be stopped
Others = Watchdog Timer Counter can enable, and make a system reset when overflow

DBGEN Debug Enable Bit

0 = BT/WDT is halted during processor debug mode.
1 = BT/WDT is not halted during processor debug mode.

3-7

BASIC TIMER & WDT S3F401F_UM_REV1.00

Basic Timer Count Register BTCNT (0x004) Access: Read Only

31 30 29 28 27 26 25 24

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

23 22 21 20 19 18 17 16

− − − − − − − −

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

15 14 13 12 11 10 9 8

− − − − −

WCV[10:8]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

BCV[7:0]

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

BCV

Basic Timer Count Value Field

0x00 ~ 0xFF

Watchdog Timer Count Value Field WCV

0x0 ~ 0x7

3-8

S3F401F_UM_REV1.00 ENCODER COUNTER

4 ENCODER COUNTER

1. OVERVIEW

The S3F401F has two encoder counter blocks. The encoder count er blo ck ca n be used for m easuri ng posi tion and
speed.

The following list summarizes the main features of the encoder counter block:

• Three input signals: PHASEA, PHASEB and PHASEZ

• Two 16-bit up/down counters: PCNT, SCNT

• Capture function supports for slow rotating: PACAP, PBCAP

• Filter in the PHASEZ and edge selector of PHASEZ

4-1

ENCODER COUNTER S3F401F_UM_REV1.00

ENCCON1.8:PACNTCL

ENCCON1.9: PAEN

ENCCLK

ENCCON1.11-.10: ESELA

ENCCON1.0: PBCNTCL

ENCCON1.1: PBEN

ENCCLK

ENCCON1.3-.2: ESELB

ENCCON1.8:PACNTCL

Clear Clear

4-bit

Prescaler

PACLK

PACNT.15-.0:PACV
16-bit Up Counter

PACAP.15-.0:PACAPDAT

PA Capure Data Register

ENCCON1.0: PBCNTCL

Clear

4-bit

Prescaler

PBCLK

PBCAP.15-.0:PBCAPDAT

Clear

PBCNT.15-.0:PBCV

16-bit Up Counter

PB Capure Register

Clear

Clear

INTPND

INTPND

INTPND

INTPND

INTMASK

INT_OVF_ A

INTMASK

INT_CAP_A

INTMASK

INT_OVF_ B

INTMASK

INT_CAP_B

PHASEA
PHASEB

Filter

PHASEZ

ENCCON0.6-.4:ENCFILTER

ENCCON0.3:ESELZ

ENCCON0.7: PZCLEN

PCNT.15-.0: PCV

Edge

selector

Clear

16-bit Up/Down

Position Counter

16-bit Comparator

PREF.15-.0:PREFDAT

16-bit Position Reference

SCNT.15-.0: SCV

16-bit Up/Down

Speed Counter

16-bit Comparator

SREF.15-.0:SREFDAT

16-bit

Speed

Reference

Figure 4-1. Encoder Counter Block Diagram

Clear

ENCCON0.0: PCNTCL

INTMASK

INTPND

Clear

ENCCON0.1: SCNTCL

INTMASK

INTPND

INTPND

INT_MAT_P

INT_MAT_S

INTMASK

INT_PHASEZ

4-2

S3F401F_UM_REV1.00 ENCODER COUNTER

2. FUNCTION DESCRIPTION

PHASEA

PHASEB

PCNT

ENCSTATUS.0 = DIRECTION 0 1

+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1

Figure 4-2. Position Counter Operation

To measure position and speed the encoder counter has the three input signals, PHASEA, PHASEB and PHASEZ.
The difference of phase between phase A and phase B pulse is 90°. The input of PHASEZ is one-pulse signal to be

generated at specific position 1 cyclic.

2.1 POSITION COUNTER OPERATION

Direction of Rotation

When DIRECTIONT bit is ‘0’, the counter value of PCNT increases. On the other hands, when DIRECTION bit is ‘1’,
PCNT decreases. Position counter is an up and down cou nter. The DIRECTION bit status and counting direction are
decided which phase signal between PHASE A and PHASE B is leading.

NOTE

Although the PBEN and PAEN bit are ‘0’, disable, if inserted any signal into PHASE A, PHASE B input port
and CAP_A0/A1 and CAP_B0/B1 interrupt are unmask, those interrupts occur until interrupts mask or
non-signal.

4-3

ENCODER COUNTER S3F401F_UM_REV1.00

3. REGISTERS DESCRIPTION

Base Address − ENC0: 0xFF02_8000

− ENC1: 0xFF02_C000

Table 4-1. ENC Special Function Registers

Offset Address Register Description R/W Reset value

0x000 ENCCON0 Encoder counter control register 0 R/W 0x0000_0000
0x004 ENCCON1 Encoder counter control register 1 R/W 0x0000_0000
0x008 ENCSTATUS Encoder counter status register R/W 0x0000_0000

0x00C PCNT 16bit Position counter register R/W 0x0000_0000

0x010 PREF 16bit Position reference register R/W 0x0000_0000
0x014 SCNT 16bit Speed counter register R/W 0x0000_0000
0x018 SREF 16bit Speed reference register R/W 0x0000_0000

0x01C PACNT 16bit Phase A capture counter register R/W 0x0000_0000

0x020 PACAP 16bit Phase A capture data register R/W 0x0000_0000
0x024 PBCNT 16bit Phase B capture counter register R/W 0x0000_0000
0x028 PBCAP 16bit Phase B capture data register R/W 0x0000_0000

NOTE: The PCNT, SCNT are 2’s complement. The range of PCNT and SCNT are -215 ~ (+215-1).

4-4

S3F401F_UM_REV1.00 ENCODER COUNTER

Encoder Counter Control Register 0 ENCCON0 (0x000) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

− − − −

DBGEN ENCCLKSEL[10:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

PZCLEN ENCFILTER[6:4] ESELZ ENCEN SCNTCL PCNTCL

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

PCNTCL Position Counter (PCNT) Clear Bit

0 = No effect
1 = Clear the counter register

Note: This bit is auto-clear bit.

SCNTCL Speed Counter (SCNT) Clear Bit

0 = No effect
1 = Clear the counter register

Note: This bit is auto-clear bit.

ENCEN Encoder Counter Block Enable Bit

0 = Disable encoder counter block
1 = Enable encoder counter block

ESELZ Phase Z Edge Type Selection Field

0 = Falling edge is selected for PHASEZ
1 = Rising edge is selected for PHASEZ

ENCFILTER Filter Clock Selection Field of Encoder Counter

000 = ENCCLK 100 = ENCCLK /16
001 = ENCCLK /2 101 = ENCCLK /32
010 = ENCCLK /4 110 = ENCCLK /64
011 = ENCCLK /8 111 = ENCCLK /128

Note: Only 5 times same level in a row is recognized as effective signal.

4-5

ENCODER COUNTER S3F401F_UM_REV1.00

Encoder Counter Control Register 0 (Continued) ENCCON0 (0x000) Access: Read/Write

PZCLEN

PCNT Clear Enable by Phase Z.

0 = Enable
1 = Disable

ENCCLKSEL Encoder Counter Clock (DECCLK) Selection Field

000 = ENCCLK 100 = ENCCLK /16
001 = ENCCLK /2 101 = E NCCLK /32
010 = ENCCLK /4 110 = E NCCLK /64
011 = ENCCLK /8 111 = E NCCLK /128

DBGEN Debug Enable Bit

0 = ENC is halted during processor debug mode.
1 = ENC is not halted during processor debug mode. Although you break the debugger, you

can see count register and several bits of status register changing according to the ope ration
setting.

NOTE

Several bits of status - These bits are ENCSTATUS.0, ENCSTATUS.2 and ENCSTATUS.3. Because
these bits can a read-only bit.

4-6

S3F401F_UM_REV1.00 ENCODER COUNTER

Encoder Counter Status Register ENCSTATUS (0x008) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

PRESCALEA[15:12] ESELA[11:10] PAEN PACNTCL

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

− − − −

PASTAT PBSTAT GLITCH DIRECTION

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

DIRECTION

GLITCH

PBSTAT

PASTAT

Direction of Motor Rotation Bit

0 = Clockwise - The value of PCNT is increased.
1 = Counter-clockwise - The value of PCNT is decreased.

Note: This bit is read-only bit.

Glitch Detection Field of Phase A, Phase B and Phase Z

0 = Glitch is not occurred READ
1 = Glitch is occurred
0 = Glitch bit is cleared WRITE
1 = No effect

Note: Glitch is detected according to the checking whether if 5 times same level in a row is recognized as
effective signal.

Phase B Status Bit

0 = Low level
1 = High level

Note: This bit is read only bit.

Phase A Status Bit

0 = Low level
1 = High level

Note: This bit is read only bit.

4-7

ENCODER COUNTER S3F401F_UM_REV1.00

Encoder Counter Status Register (Continued) ENCSTATUS (0x008) Access: Read/Write

OFPCNT Overflow Detection of PCNT

0 = Overflow is not occurred READ
1 = Overflow is occurred

WRITE

0 = OFPCNT bit is cleared.
1 = No effect

UFPCNT Underflow Detection of PCNT

0 = Underflow is not occurred READ
1 = Underflow is occurred

WRITE

0 = UFPCNT bit is cleared.
1 = No effect

OFSCNT Overflow Detection of SCNT

0 = Overflow is not occurred READ
1 = Overflow is occurred

WRITE

0 = OFSCNT bit is cleared.
1 = No effect

UFSCNT Underflow Detection of SCNT

0 = Underflow is not occurred READ
1 = Underflow is occurred

WRITE

0 = UFSCNT bit is cleared.
1 = No effect

NOTE

ENCSTATUS.4− .7 are cleared automatically by counter clear signal. (PHASEZ, ENCCON0.1− .0)

4-8

S3F401F_UM_REV1.00 ENCODER COUNTER

16 Bit Position Counter Register PCNT (0x00C) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

PCV[15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

PCV[7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

PCV

The Current Position Counter Value Field

0x0000 ~ 0xFFFF

16 Bit Position Reference Register PREF (0x010) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

PREFDAT [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

PREFDAT [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

PREFDAT

The Reference Value for Position Counter

0x0000 ~ 0xFFFF

4-9

ENCODER COUNTER S3F401F_UM_REV1.00

16 Bit Speed Counter Register SCNT (0x014) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

SCV [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

SCV [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

SCV

The Current Speed Counter Value Field

0x0000 ~ 0xFFFF

16 Bit Speed Reference Register SREF (0x018) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

SREFDAT [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

SREFDAT [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

SREFDAT

The Reference Value for Speed Counter

0x0000 ~ 0xFFFF

4-10

S3F401F_UM_REV1.00 ENCODER COUNTER

16 Bit Phase A Capture Counter Register PACNT (0x01C) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

PACV [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

PACV [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

PACV

The Phase A Capture Counter Value Field

0x0000 ~ 0xFFFF

16 Bit Phase A Capture Data Register PACAP (0x020) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

PACAPDAT [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

PACAPDAT [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

PACAPDAT

The Phase A Captured Value Field

0x0000 ~ 0xFFFF

4-11

ENCODER COUNTER S3F401F_UM_REV1.00

16 Bit t Phase B Capture Counter Register PBCNT (0x024) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

PBCV [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

PBCV [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

PBCV

The Phase B Capture Counter Value Field

0x0000 ~ 0xFFFF

16 Bit Phase B Capture Data Register PBCAP (0x028) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

PBCAPDAT [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

PBCAPDAT [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

PBCAPDAT

The Phase B Captured Value Field

0x0000 ~ 0xFFFF

4-12

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

5 INTERNAL FLASH ROM

1. OVERVIEW

The S3F401F has an on-chip flash ROM, internally. The memory flash size is 256Kbytes. To improve operating
speed, the memory is composed of two interleaved flash memories.

1.2 FEATURES

• Flash memory size: 256Kbytes

• Two working modes: Non-interleave mode, Interleave mode

• Two programming modes: User program mode, Tool program mode

• Protection supports: Hardware protection, Read protection

2. BLOCK DIAGRAM

Figure 5-1. Flash Memory Controller Read/Write Block Diagram

5-1

INTERNAL FLASH ROM S3F401F_UM_REV1.00

3. FLASH CONFIGURATION

3.1 FLASH ROM CONFIGURATION

The 256KBytes Flash ROM consists of 256 sectors. Each sector consists of 1024bytes. So, the total size of flash
ROM is 256(sector number) x 1024(each sector size) bytes (256Kbyte). You can era se the fla sh memory a
sector-unit at a time and write the data into the flash memory a word-unit at a time.

3.2 ADDRESS ALIGNMENT

To set an address value in FMADDR register, abide by the following rules.
♦ Sector Erase

When erasing a sector, the lower 10-bits of address should be ‘0’, because the size of a sector is 1024Bytes.

You can select one as the SECTOR_ORDER from 0 to 255, among 256 sectors.

− FMADDR [31:0] = (SECTOR_ ORDER << 10)
♦ Program
When programming Flash ROM, the lower 2-bits should be ‘0’, because data should be written to the Flash

ROM by a word-unit (4bytes). You can select one as the ADDRESS from 0x0000 to 0x3FFFF, in 256Kbytes
range. In the tool program mode, the low 2-bit address also should be 00b.

− FMADDR [31:0] = ADDRESS & 0xFFFFFFFC

3.3 WORKING MODE

There are two-different working modes following:
♦ NON-INTERLEAVE MODE

The flash memories are able to work at the system clock frequency (MCLK). In this case, all read accesses are
executed with no wait state.

♦ INTERLEAVE MODE

The flash memories work at the system clock frequency (MCLK ) divided by 2. In this case, no n-sequential read
accesses require one wait state and sequential read accesses are executed with no wait state. Thanks to a
cache buffer, fetch accesses at consecutive address are performed with no wait state.

3.4 PROGRAM MODE

For writing the data in flash ROM, you can access the flash ROM by a program or the external serial interface.
Because of the feature of NOR flash memory, you can program the data in any address a nd in any time. The size of
embedded flash memory in S3F401F is 256K-byte and it has the following features:

♦ User program mode (AHB Interface)
♦ Tool program mode (Use the dedicated serial interface)

♦ Protection mode: hardware protection and read protection

The S3F401F has several pins used for flash ROM writer to read/write/erase the flash memory (VDDIO[3:0],
VSSIO[3:0], nRESET, VDDCORE[3:0], VSSCORE[3:0], SDAT, SCLK), which is the programming by tool program
mode. These several pins are multiplexed with other functional pins.

5-2

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

4. PROGRAMMING MODES

The Flash Memory Controller supports two kinds of program mode:

♦ User program mode

♦ Tool program mode

4.1 USER PROGRAM MODE

The user program mode for flash memory programming and sector erasing uses the internal high voltage generator,
which is necessary for flash memory programming and secto r erasing. In other words, the Fla sh Memory Controlle r
has an internal high voltage pumping circuit. Therefore, high voltage to V
into the flash ROM or sector erase in this mode, several control registers should be used, which will be explained
below.

4.1.1 The Program Procedure in the User Program Mode

In order to program to flash memory, you should write the address to be written into the address register (FMADDR)
and the data into the data register (FMDATA), respectively. As a next step, you should write the value 0x5A5A5A5A
into the FMKEY register. Before command bit set and start, you must enable flash counter clock
(FMUCON.7-UOSCEN bit Set). Finally, by writing the appropriate data into flash memory control register
(FMUCON). After the completion of the write operation, all registers except FMUCON.8bit (INTERLEAVE) will be
cleared. To perform the next writing operation, all register should be written again as before.

In order to perform sector erase procedure is the same as program proced ure except not setting the data register
(FMDATA) in Flash Memory Controller.

In order to perform chip erase procedure will be enough to setting the key register (FMKEY) and control register
(FMUCON) in Flash Memory Controller.

PP pin is not needed. To program the data

5-3

INTERNAL FLASH ROM S3F401F_UM_REV1.00

4.2 NORMAL PROGRAM

START

FMADDR 32-bit Address
FMDATA 32-bit Data

; Address set
; Data set

FMKEY 0x5A5A5A5A

FMUCON + UOSCEN Bit

FMUCON + CommandBit + CPUStatus Bit + Start Bit

CPUHOLD?

Yes

32-bit Data Writing

Command Bit Clear

COUNT=END?

Yes

No

Can be executed another

+

instruction in SRAM/SDRAM

No

FMADDR New 32-bit Address
FMDATA New 32-bit Data

FINISH

; Key value set whenenver starts

; Enable flash osc

; Program command select & start

Command: FMUCON.2-UPGMR

; Check command bit to know
if operation is completed or not

; Compare End address

; Next address/data set

Figure 5-2. Normal Program Flowchart

5-4

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

4.3 OPTION PROGRAM

START

FMADDR 0x00000E38 or 0x00000E3C
FMDATA Option Bit Set

; Protection/Smart option register address set
; Option Bit set

FMKEY 0x5A5A5A5A

FMUCON + UOSCEN Bit

FMUCON + CommandBit + CPUStatus Bit + Start Bit

CPUHOLD?

Yes

32-bit Data Writing

Command Bit Clear

COUNT=END?

Yes

No

Another instruction can be

+

executed in SRAM/SDRAM

No

FMADDR 0x00000E38 or 0x00000E3C
FMDATA Other Option Bit Set

FINISH

; Key value set whenenver starts

; Enable flash osc

; Program command select & start
Command: FMUCON.5-UOPGMR

; Check command bit to know
if operation is completed or not

; Compare End address

Figure 5-3. Option Program Flowchart

5-5

INTERNAL FLASH ROM S3F401F_UM_REV1.00

4.4 SECTOR ERASE

START

FMADDR Sector Base Address

; Address set
; Data set

FMKEY 0x5A5A5A5A

FMUCON + UOSCEN Bit

FMUCON + CommandBit + CPUStatus Bit + Start Bit

CPUHOLD?

Yes

32-bit Data Writing

Command Bit Clear

COUNT=END?

Yes

No

Another instruction can be

+

executed in SRAM/SDRAM

No

FMADDR New 32-bit Address
FMDATA New 32-bit Data

FINISH

; Key value set whenenver starts

; Enable flash osc

; Program command select & start
Command: FMUCON.1 - USERSR

; Check command bit to know
if operation is completed or not

; Compare End address

; Next address/data set

Figure 5-4. Sector Erase Flowchart

5-6

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

4.5 CHIP ERASE FLOWCHART

START

FMKEY 0x5A5A5A5A

FMUCON + UOSCEN Bit

FMUCON + CommandBit + CPUStatus Bit + Start Bit

CPUHOLD?

Yes

32-bit Data Writing

Command Bit Clear

No

Another instruction can be

+

executed in SRAM/SDRAM

; Key value set whenenver starts

; Enable flash osc

; Program command select & start
Command: FMUCON.0 - UCERSR

; Check command bit to know
if operation is completed or not

FINISH

Figure 5-5. Chip Erase Flowchart

5-7

INTERNAL FLASH ROM S3F401F_UM_REV1.00

4.6 TOOL PROGRAM MODE

The tool program mode is the flash memory program mode, which uses an equipment tool such as SPW2Plus Flash
ROM Writer or US-PRO Flash ROM Writer. If you want to make a dedicated Flash ROM writer for S3F401F, please
contact us for more detail document.

Table 5-1. The Pins Used to Read/Write/Erase the Flash ROM in Tool Program Mode

Pin No. Pin Name Interface Signal I/O Function

47 P1.15/SSPCLK0/INT15

SDAT

I/O

Serial bi-directional DATA pin(Output
when reading, Input when writing). Input &
push-pull output port can be assigned

48 P1.16/SSPFSS0/INT16

SCLK

Serial CLOCK input pin.

I

(Write speed: Max 200 KHz, Read speed :
Max 10 MHz)

100 nRESET
16, 42, 66 VDDCORE[3:0] 3.3V Power supply pin for Flash block
32, 44, 93 VDDIO[3:0]
15, 41, 67 VSSCORE[3:0] GND Power supply pin for Flash block
31, 43, 92 VSSIO[3:0]

RESET

VDD

VSS

P

P

Chip Initialization

I

3.3V Power supply pin for I/O interface

GND Power supply pin for I/O interface

NOTE: More detail information about SPW2Plus and US-PRO is available in www.cnatech.com and www.seminix.com.

5-8

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

5. DATA PROTECTION

The data programmed in flash memory need to be protected. For this situation, the Internal Fl ash Memory Controller
of S3F401F supports three kinds of protection mechanism.

♦ HARDWARE PROTECTION
Flash Full Region Protection or Selected Block Protection among total 16blocks
♦ READ PROTECTION
In the case of serial interface, Flash Read protection
♦ JTAG PROTECTION

These protection modes can be enabled by programming the protection option bits. The protection option bits can
be enabled or disabled with configuration at address 0x00000E38 and address 0x00000E3C.

5.1 PROTECTION OPTION CONFIGURATION

Table 5-2. Protection Option Address and Protection Bits

FMADDR FMDATA Description Initial Value (at Fabrication)

0x00000E3C Bit[7:0] Not used Undefined

0 : JTAG Protection Enable Bit[8]

1

1 : JTAG Protection Disable

Bit[16:9] Not used Undefined

0 : Hardware Protection Enable Bit[17]

1(Note 1)

1 : Hardware Protection Disable

Bit[26:18] Not used Undefined

0 : Serial Read Protection Enable Bit[27]

1

1 : Serial Read Protection Disable

Bit[31:28] Not used Undefined

NOTE: For enabling Hardware Protection, you must set the Protection Option and Smart Option. That is, Protection Option is

used for enabling the Hardware Protection of selected group of sectors by Smart Option. Smart Option is used for
selecting the group of sectors for hardware protection. When you set the Smart Option, Hardware Protection bit in
Protection Option must be disabled. After you set the Smart Option, you should enable the hardware protection bit in
Protection Option.

5-9

INTERNAL FLASH ROM S3F401F_UM_REV1.00

5.2 JTAG INTERFACE PROTECTION BIT 8

This Bit is used for JTAG Access enable or disable (If chip designers would like to debug through JTAG in in itial chip
development state, JTAG Interface Protection Bit should be disabled, but, In final desi gn developm ent stat e, If chip
designers enable the JTAG interface Protection, other user can not access the flash memory data via JTAG
interface)

5.3 HARDWARE PROTECTION BIT 17

If Hardware Protection was enabled, user cannot write or erase the data in a flash memory area. In addition
Protection Option and Smart Option cannot be set or released. Hardware Protection function affects a tool program
mode as well as a user program mode. This protection can be released only by the chip erase execution.

Hardware Protection can be set in user program mode as follows. You should write 0x0E3C into the address a nd the
proper data (Refer to the above Protection Bit table) into the data register (FMDATA), respectively. As a next step,
you should write the values (0x5A5A5A5A) into key register(FMKEY). Finally, set FMUCON. Please refer to
figure3(Option Program Flowchart).

For enable to Hardware Protection, two Option registers, Protection Option(FMADDR: 0x0E3C) and Smart
Option(FMADDR: 0x0E38) are used. That is, Protection Option is used for enabling the hardware protection of the
selected group of sectors by Smart Option. Smart Option is used for selecting the group of sectors for hardware
protection. When you set the Smart Option, hardware protection bit in Protection Option must be disabled. After you
set the Smart Option, you should enable the hardware protection bit in Protection Option(FMADDR: 0x0E3C) On the
other way, you can set Hardware Protection in tool program mode by executing its functions and release Hardware
Protection by chip erase, which results in initializing all Protection bits, smart option bits and erasing internal Flash
ROM data,

5.3.1 SMART OPTION FMADDR - 0X0E38

In the Hardware protection function, the protection on certain block can be disabled by setting the correspon ding
smart option bits. Four bits are allocated in the address of smart option (0x0E38) for this function.

To enable the protection function on a certain block,
> Configure the smart option bits in advance

> Configure the Hardware Protection Option (0x0E3C).

Table 5-3. Smart Option Address Configuration

FMADDR FMDATA Description Reset Value

0x00000E38 Bit [15:0]

H/W protection is disable / enable : These bits are each mapped

0xFFFF
to a corresponding group which is composed of 32 sectors(32KB). In
other word, the Bit[0] is mapped from sector 1 to sector 16. And the
Bit[1] is mapped from sector 17 to sector 32 and so on.

Therefore, these 16 bits are used for 256KB internal Flash.
0 = Enable H/W protection of selected group
1 = Disable H/W protection of selected group

5-10

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

Table 5-4. Hardware Protection Area

FMDATA[15:0] Hardware Protection Area Sector Protec ted Area Addres s

0xFFFE Sector 000 ~ Sector 015 0x0000_0000 ~ 0x0000_3FFF
0xFFFD Sector 016~ Sector 031 0x0000_4000 ~ 0x0000_7FFF
0xFFFB Sector 032~ Sector 047 0x0000_8000 ~ 0x0000_BFFF
0xFFF7 Sector 048~ Sector 063 0x0000_C000 ~ 0x0000_FFFF
0xFFEF Sector 064~ Sector 079 0x0001_0000 ~ 0x0001_3FFF
0xFFDF Sector 080~ Sector 095 0x0001_4000 ~ 0x0001_7FFF
0xFFBF Sector 096~ Sector 111 0x0001_8000 ~ 0x0001_BFFF
0xFF7F Sector 112~ Sector 127 0x0001_C000 ~ 0x0001_FFFF
0xFEFF Sector 128~ Sector 143 0x0002_0000 ~ 0x0002_3FFF
0xFDFF Sector 144~ Sector 159 0x0002_4000 ~ 0x0002_7FFF
0xFBFF Sector 160~ Sector 175 0x0002_8000 ~ 0x0002_BFFF
0xF7FF Sector 176~ Sector 191 0x0002_C000 ~ 0x0002_FFFF
0xEFFF Sector 192~ Sector 207 0x0003_0000 ~ 0x0003_3FFF
0xDFFF Sector 208~ Sector 223 0x0003_4000 ~ 0x0003_7FFF
0xBFFF Sector 224~ Sector 239 0x0003_8000 ~ 0x0003_BFFF
0x7FFF Sector 240~ Sector 255 0x0003_C000 ~ 0x0003_FFFF

5.4 READ PROTECTION BIT 27

Most users want that their data and code in memory would not be read by others. Read Protection can give the
solution for it by preventing the flash data from being read serially in the tool program mode.

When this function is enabled, reading the flash data in the tool program mode will result in all zero read-out. You
should write the proper data (refer to the above Protection Bit table) into the address 0x00000E3C. The ad dress
0x00000E3C should be written the register FMADDR. The data consisting of protection bit should be written the
register FMDATA. As a next step, you should write the values (0x5A5A5A5A) into key register (FMKEY). Finally, set
FMUCON. Please refer to figure3. (Option Sector Program Flowchart)

5-11

INTERNAL FLASH ROM S3F401F_UM_REV1.00

6. REGISTERS DESCRIPTION

Base Address − 0xFFF0_0000

Table 5-5. Internal Flash Special Function Registers

Offset Address Register Description R/W Reset Value

0x000 FMKEY Flash program / erase Key register W 0x0000_0000
0x004 FMADDR Flash program / sector erase address register R/W 0x0000_0000
0x008 FMDATA Flash program data register R/W 0x0000_0000

0x00C FMUCON Flash program/sector erase control register R/W 0x0000_0000

0x010 FSO Smart Option bits read register R 0xXXXX

_FFFF

(PROT[15:0])

0x014 FPO Protection Option bits read register R 0bXXXX_1XXX_

(bit27:RDP)

XXXX_XX1X_

(bit17:HDP)

XXXX_XXX1_

(bit8:LDCP)

XXXX_ XXXX

5-12

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

Flash Memory Key Register FMKEY (0x000) Access: Write Only

31 30 29 28 27 26 25 24

FMKEYDAT [31:24]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

FMKEYDAT [23:16]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

FMKEYDAT [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

FMKEYDAT [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

FMKEYDAT

NOTE

Flash Memory Key

Key register data to do program, erase, protection operation
To program any data into the flash memory by the user program mode, a specific key register

with 0x5A5A5A5A is required to prevent flash data from being destroyed under undesired
situations.

The FMKEY register will be cleared automatically just after the completion of erase or program.

5-13

INTERNAL FLASH ROM S3F401F_UM_REV1.00

Flash Memory Address Register FMADDR (0x004) Access: Read/Write

31 30 29 28 27 26 25 24

FMADDRDAT [31:24]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

FMADDRDAT [23:16]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

FMADDRDAT [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

FMADDRDAT [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

FMADDRDAT

NOTE

Flash Memory Address

Flash program / sector erase address register data

In option programming, set FMADDR to 0x0E38 (Smart Option = Real Address “E”) or 0xE3C
(Protection Option = Real Address “F”) and FMDATA by the appropriate value and start the write

operation.
FMADDR [31:0] Å Address to be selected by user in flash memory range

FMADDR [31:0] Å 0x00000E38 on programming smart option for hardware protectio n
FMADDR [31:0] Å 0x00000E3C on programming protection option

5-14

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

Flash Memory Data Register FMDATA (0x008) Access: Read/Write

31 30 29 28 27 26 25 24

FMDATADAT [31:24]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

FMDATADAT [23:16]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

FMDATADAT [15:8]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

FMDATADAT [7:0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

FMDATADAT

NOTE

Flash Memory Data

Flash program data register data

FMDATA [31:0]ÅSpecific word data (4bytes) selected by user to be written into the flash memory
FMDATA [31:0]ÅHardware protection group data in programming smart option for hardware protection
FMDATA [31:0]Å Protection option data in programming protection option

5-15

INTERNAL FLASH ROM S3F401F_UM_REV1.00

Flash Memory Control Register FMUCON (0x00C) Access: Read/Write

31 30 29 28 27 26 25 24

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

23 22 21 20 19 18 17 16

− − − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

− − − − − − −

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

UOSCEN USTRSTPT UOPGMR − UCPUH UPGMR USERSR UCERSR

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

INTERLEAVE

UCERSR Chip Erase Enable Bit

0 = Disable
1 = Enable

USERSR Sector Erase Enable Bit

0 = Disable
1 = Enable

Note: This bit can be used in only user program mode.

UPGMR Normal Program Enable Bit

0 = Disable
1 = Enable

UCPUH CPU Hold Control Bit

0 = CPU work during Flash programming/erasing.
In this case, the flash programming/erasing code should not be on the internal flash ROM. The
advantage is that CPU can perform other tasks until the completion of an operation.

1 = CPU hold during Flash programming / erasing

Note: This bit can be used user and tool program mode. This bit can be read written data in specific

sequence. That mean’s although you write the ‘1’, when you read the register, the data will be ‘0’.

written data is affected at the time flash on-going, operation start bit is ‘1’.

UOPGMR

Option Program Enable Bit (For protection option setting)

0 = Disable

1 = Enable

Note: This bit can be used user and tool program mode.

The

5-16

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

Flash Memory Control Register (Continued) FMUCON (0x00C) Access: Read/Write

USTRSTPT Operation(note) Start Bit

0 = Stop
1 = Start

UOSCEN

Count Clock Enable Bit

0 = Disable
1 = Enable

INTERLEAVE Flash Memory Operation Mode Bit

0 = Not interleave mode
1 = Interleave mode

Note: Interleave mode must be used for above 45MHz.

NOTE

Important Note

The FMUCON can determine the program / erase operation. In user program mode, the Flash Memory
Controller can support normal program, option program, sector erase and chip erase. Among operating
modes, only one operating mode can be selected.

S3F401F supports the following program type-Chip Erase, Sector Erase, Normal Program and Option
Program. Each command is UCERSR, USERSR, UPGMR and UOPGMR bit.

UOSCEN

must be enabled before starting erase/program operation.(Refer to the flow-chart)

5-17

INTERNAL FLASH ROM S3F401F_UM_REV1.00

Smart Option Bits Read Register FSO (0x010) Access: Read Only

31 30 29 28 27 26 25 24

FSODAT [31:24]

R-U R-U R-U R-U R-U R-U R-U R-U

23 22 21 20 19 18 17 16

FSODAT [23:16]

R-U R-U R-U R-U R-U R-U R-U R-U

15 14 13 12 11 10 9 8

FSODAT [15:8]

R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1

7 6 5 4 3 2 1 0

FSODAT [7:0]

R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

FSODAT

NOTE

Smart Option

Smart Option bits read register data
0xXXXX_FFFF(PROT[15:0])

Reading the Smart Option Bits (PROT [15:0] which are port of Flash Memory) is possible only through
FSO Register, because the bits of Smart Option cannot be read like normal cell.

5-18

S3F401F_UM_REV1.00 INTERNAL FLASH ROM

Protection Option Bits Read Register FPO (0x014) Access: Read Only

31 30 29 28 27 26 25 24

FPODAT [31:24]

R-U R-U R-U R-U R-1 R-U R-U R-U

23 22 21 20 19 18 17 16

FPODAT [23:16]

R-U R-U R-U R-U R-U R-U R-1 R-U

15 14 13 12 11 10 9 8

FPODAT [15:8]

R-U R-U R-U R-U R-U R-U R-U R-1

7 6 5 4 3 2 1 0

FPODAT [7:0]

R-U R-U R-U R-U R-U R-U R-U R-U

W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset

FPODAT

NOTE

Smart Option

Protection Option bits read register data

0bXXXX_1XXX_(bit27:RDP)
XXXX_XX1X_(bit17:HDP)
XXXX_XXX1_(bit8:LDCP)
XXXX_ XXXX (at Fabrication)

Reading the Protection Option Bits (LDCP(bit[8])/HDP(bit[17])/RDP(bit[27]) which are port of Flash
Memory) is possible only through the register FPO, because the bits of protection option cannot be read
like normal cell.

5-19

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

6 INVERTER MOTOR CONTROLLER (IMC)

1. OVERVIEW

This inverter motor controller can be used for 3-phase (U, V, W) inverter motor in the washing machine and air
conditioner application etc.

The main features on the inverter motor controller are summarized as the following:

• 3 Pair-PWM signal outputs
(PWMxU0, PWMxD0), (PWMxU1, PWMxD1), (PWMxU2, PWMxD2)

• Dead-time insertion of each PWM Signal

• 8 compare-registers to generate ADC start trigger signal and interrupt

• High-Z output generation by PWM output level control function

6-1

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

2. BLOCK DIAGRAM

IMCON0.12:PWMOFFEN

IMCON0.10-.8:IMFILTER

IMCON0.7-.6:ELESPWMOFF

INTMASK

PWMxOFF

Filter

IMCON0.0:IMEN

Clear

PCLK

3-bit

prescaler

IMCON0.18 -.16:IMCLKSEL

IMCLK

PACMPR.15-.0: PACMPRDAT
PACMPF.15-.0: PACMPFDAT
PBCMPR.15-.0: PBCMPRDAT
PBCMPF.15-.0: PBCMPFDAT
PCCMPR.15-.0: PCCMPRDAT
PCCMPF.15-.0: PCCMPFDAT

TOPCMP.15-.0: TOPCMPDAT
ADCSTARTSEL. 1 : 0SEL

ADCCMPR0.15-.0:ADDCMPR0DAT
ADCCMPF0.15-.0:ADDCMPF0DAT
ADCCMPR1.15-.0:ADDCMPR1DAT
ADCCMPF1.15-.0:ADDCMPF1DAT
ADCCMPR2.15-.0:ADDCMPR2DAT
ADCCMPF2.15-.0:ADDCMPF2DAT

IMCON0.13:PWMOUTOFFEN

IMCON0.14:PWMOUTEN

IMSTATUS.1:UPDOWNSTAT

IMCNT.15-.0: CV

16-bit Up/Down Counter

16-bit Comparator

DTCMP : DTCMPDAT
IMCON0.1: IMMODE
IMCON0.3: PWMSWAP
IMCON0.4: PWMPOLU
IMCON0.5: PWMPOLD

IMCON0.24-.20:NUMSKIP

16-bit Comparator

Clear

IMCON0.0:IMEN

MODE: POLARITY:

DEAD-TIME Controller

Interrupt Controller

INTPND

IMSTATUS.0:FAULTSTAT

IMCON1.5-.0:PWMxDnEN

INTMASK

INTPND

ADC Start Trigger

ADCSTARTSEL.7-.0

INT_FAULT

PWMxU0
PWMxD0

PWMxU1
PWMxD1

PWMxU2
PWMxD2

INTs (8EA)

ADC BLOCK

Figure 6-1. Inverter Motor Controller (IMC) Block Diagram

6-2

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

3. FUNCTION DESCRIPTION

3.1 TRI-ANGULAR WAVE

PWMxU0

PWMxD0

INTERRUPT

can be used as ADC Trigger Signal

Low Start

High Start

IMCLK

IMCNT

DTCNT

TOPCMP=7

DTCMP=2

PACMPR=3

PACMPF=4

0123456765432101

0000100000010000

Switch ON

7

2

3
4

ADCCMPR0=6

6

Figure 6-2. Inverter Motor Controller (IMC) Signal generation (Tri-angular wave)

6-3

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

3.2 SAW-TOOTH WAVE

PWMxU0

Low Start

Dead-Time High Start

PWMxD0

INTERRUPT

can be used as ADC Trigger Signal

IMCLK

IMCNT

DTCNT

TOPCMP=7

DTCMP=2

PACMPR=3

0123456012345601

0000100010010000

7

2

3

ADCCMPR0=6

Figure 6-3. Inverter Motor Controller (IMC) Signal generation (Saw-tooth wave)

6-4

6

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

4. PHASE SIGNAL GENERATION

4.1 TRI-ANGULAR WAVE (IMMODE = 0)

PWMSWAP = 0, PWMPOLU = 0 (Low start), PWMPOLD = 1 (High start)

These phase signals are used when switches of UP side and DOWN side are high active in inverter motor
application. That means one pair switches of UP side and DOWN side don’t have condition with high active at the
same time. So dead time is inserted the following that.

PWMxU0

PWMxD0

PWMxU1

ADCCMPR2
ADCCMPR1

PCCMPR

PBCMPR
ADCCMPR0
PACMPR

Low start

High start

Low start

TOPCMP

TOPCMP

PCCMPF
ADCCMPF1
PBCMPF
ADCCMPF2
PACMPF

ADCCMPF0

PWMxD1

PWMxU2

PWMxD2

High start

Low start

High start

Interrupt

(Can be used by ADC trigger signal)

Figure 6-4. Inverter Motor Controller (IMC) Signal generation (Tri-angular wave)

6-5

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

For 100% duty of upside, the rising/falling compare register must be set to ‘0’. For 0% duty of upside, the rising
compare register must be greater than TOPCMP value.

The signal of PWM is described in the below picture. (Assumption: Duration of deadtime is 2% duty.)

Upside 0% duty setting Upside 33% duty setting

Upside 33% duty setting

Upside 100% duty setting

Upside 1% duty setting Upside 33% duty setting

Upside 33% duty setting

Upside 99% duty setting

6-6

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

4.2 TRI-ANGULAR WAVE (IMMODE = 0)

PWMSWAP = 1, PWMPOLU = 0 (Low start), PWMPOLD = 1 (High start)

TOPCMP

TOPCMP

ADCCMPR2
ADCCMPR1

PWMxU0

PWMxD0

PWMxU1

PWMxD1

PCCMPR

PBCMPR
ADCCMPR0
PACMPR

Low start swap

High start swap

Low start swap

High start swap

PCCMPF
ADCCMPF1
PBCMPF
ADCCMPF2
PACMPF

ADCCMPF0

PWMxU2

PWMxD2

Low start swap

High start swap

Interrupt

(Can be used by ADC trigger signal)

NOTES:

1. Switches of up side and down side are high active.

2. For 0% duty of upside, the rising/falling compare register must be set to ‘0’. For 100% duty of upside, the rising compare

register must be greater than TOPCMP value.

6-7

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

The signal of PWM is described in the below picture. (Assumption: Duration of deadtime is 2% duty.)

Upside 0% duty setting

Upside 67% duty setting

Upside 100% duty setting

Upside 67% duty setting

Upside 1% duty setting

Upside 67% duty setting

Upside 99% duty setting

Upside 67% duty setting

6-8

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

4.3 TRI-ANGULAR WAVE (IMMODE = 0)

PWMSWAP = 0, PWMPOLU = 0 (Low start), PWMPOLD = 0 (Low start)

TOPCMP

TOPCMP

ADCCMPR2
ADCCMPR1

PWMxU0

PWMxD0

PWMxU1

PWMxD1

PCCMPR

PBCMPR
ADCCMPR0
PACMPR

Low start

Low start

Low start

Low start

PCCMPF
ADCCMPF1
PBCMPF
ADCCMPF2
PACMPF

ADCCMPF0

PWMxU2

PWMxD2

Low start

Low start

Interrupt

(Can be used by ADC trigger signal)

NOTES:

1. Switch of up side is high active and switch of down side is low active.

2. For 100% duty of upside, the rising/falling compare register must be set to ‘0’. For 0% duty of upside, the rising compare

register must be greater than TOPCMP value.

6-9

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

4.4 TRI-ANGULAR WAVE (IMMODE = 0)

PWMSWAP = 1, PWMPOLU = 0 (Low start), PWMPOLD = 0 (Low start)

TOPCMP

TOPCMP

ADCCMPR2
ADCCMPR1

PWMxU0

PWMxD0

PWMxU1

PWMxD1

PCCMPR

PBCMPR
ADCCMPR0
PACMPR

Low start

Low start

Low start

Low start

PCCMPF
ADCCMPF1
PBCMPF
ADCCMPF2
PACMPF

ADCCMPF0

PWMxU2

PWMxD2

Low start

Low start

Interrupt

(Can be used by ADC trigger signal)

NOTES:

1. Switch of up side is low active and switch of down side is high active.

2. For 0% duty of upside, the rising/falling compare register must be set to ‘0’. For 100% duty of upside, the rising compare
register must be greater than TOPCMP value.

6-10

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

4.5 TRI-ANGULAR WAVE (IMMODE = 0)

PWMSWAP = 0, PWMPOLU = 1 (High start), PWMPOLD = 0 (Low start)

TOPCMP

TOPCMP

ADCCMPR2
ADCCMPR1

PWMxU0

PWMxD0

PWMxU1

PWMxD1

PCCMPR

PBCMPR
ADCCMPR0
PACMPR

Low start

High start

Low start

High start

PCCMPF
ADCCMPF1
PBCMPF
ADCCMPF2
PACMPF

ADCCMPF0

PWMxU2

PWMxD2

Low start

High start

Interrupt

(Can be used by ADC trigger signal)

NOTES:

1. Switches of up side and down side are low active.

2. For 100% duty of upside, the rising/falling compare register must be set to ‘0’. For 0% duty of upside, the rising compare

register must be greater than TOPCMP value.

6-11

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

The signal of PWM is described in the below picture. (Assumption: Duration of dead-time is 2% duty.)

Upside
0% duty

setting

Upside

100% duty

setting

Upside
1% duty

setting

Upside

99% duty

setting

Upside

33% duty

setting

Upside

33% duty

setting

Upside

33% duty

setting

Upside

33% duty

setting

6-12

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

4.6 TRI-ANGULAR WAVE (IMMODE = 0)

PWMSWAP = 1, PWMPOLU = 1 (High start), PWMPOLD = 0 (Low start)

TOPCMP

ADCCMPR2

PCCMPR

ADCCMPR1

ADCCMPF2

ADCCMPR0

ADCCMPF1

ADCCMPF0

PCCMPF
PBCMPR

PBCMPF
PACMPR

PACMPF

PWMxU0

PWMxU1

PWMxU2

PWMxD0

PWMxD1

PWMxD2

Interrupt

(Can be used by ADC

trigger signal)

NOTES:

1. Switches of up side and down side are low active.

2. For 0% duty of upside, the rising/falling compare register must be set to ‘0’. For 100% duty of upside, the rising compare

register must be greater than TOPCMP value.

6-13

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

4.7 TRI-ANGULAR WAVE (IMMODE = 0)

PWMSWAP = 0, PWMPOLU = 1 (High start), PWMPOLD = 1 (High start)

TOPCMP

ADCCMPR2

PCCMPR

ADCCMPR1
ADCCMPF2

ADCCMPR0

ADCCMPF1

ADCCMPF0

PCCMPF
PBCMPR

PBCMPF
PACMPR

PACMPF

PWMxU0

PWMxU1

PWMxU2

PWMxD0

PWMxD1

PWMxD2

Interrupt

(Can be used by ADC

trigger signal)

NOTES:

1. Switch of up side is low active and switch of down side is high active.

2. For 100% duty of upside, the rising/falling compare register must be set to ‘0’. For 0% duty of upside, the rising compare
register must be greater than TOPCMP value.

6-14

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

4.8 TRI-ANGULAR WAVE (IMMODE = 0)

PWMSWAP = 1, PWMPOLU = 1 (High start), PWMPOLD = 1 (High start)

TOPCMP

ADCCMPR2

PCCMPR

ADCCMPR1

ADCCMPF2

ADCCMPR0

ADCCMPF1

ADCCMPF0

PCCMPF
PBCMPR

PBCMPF
PACMPR

PACMPF

PWMxU0

PWMxU1

PWMxU2

PWMxD0

PWMxD1

PWMxD2

Interrupt

(Can be used by ADC

trigger signal)

NOTES:

1. Switch of up side is high active and switch of down side is low active.

2. For 0% duty of upside, the rising/falling compare register must be set to ‘0’. For 100% duty of upside, the rising compare

register must be greater than TOPCMP value.

6-15

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

4.9 SAW-TOOTH WAVE (IMMODE = 1)

PWMSWAP = 0, PWMPOLU = 0 (Low start), PWMPOLD = 1 (High start)

TOPCMP

ADCCMPR2

PCCMPR

ADCCMPR1

ADCCMPR0

PBCMPR

PACMPR

PWMxU0

PWMxU1

PWMxU2

PWMxD0

PWMxD1

PWMxD2

Interrupt

(Can be used by ADC

trigger signal)

NOTES:

1. Switches of up side and down side are high active.

2. For 100% duty of upside, the rising/falling compare register must be set to ‘0’. For 0% duty of upside, the rising compare
register must be greater than TOPCMP value.

6-16

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

Upside

0% duty

setting

Upside

100% duty

setting

Upside

1% duty

setting

Upside

99% duty

setting

Upside

50% duty

setting

Upside

50% duty

setting

50% duty

setting

Upside

50% duty

setting

6-17

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

4.10 SAW-TOOTH WAVE (IMMODE = 1)

PWMSWAP = 1, PWMPOLU = 0 (Low start), PWMPOLD = 1 (High start)

TOPCMP

ADCCMPR2

PCCMPR

ADCCMPR1

ADCCMPR0

PBCMPR

PACMPR

PWMxU0

PWMxU1

PWMxU2

PWMxD0

PWMxD1

PWMxD2

Interrupt

(Can be used by ADC

trigger signal)

NOTES:

1. Switches of up side and down side are high active.

2. For 0% duty of upside, the rising/falling compare register must be set to ‘0’. For 100% duty of upside, the rising compare
register must be greater than TOPCMP value.

6-18

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

4.11 SAW-TOOTH WAVE (IMMODE = 1)

PWMSWAP = 0, PWMPOLU = 0 (Low start), PWMPOLD = 0 (Low start)

TOPCMP

ADCCMPR2

PCCMPR

ADCCMPR1

ADCCMPR0

PBCMPR

PACMPR

PWMxU0

PWMxU1

PWMxU2

PWMxD0

PWMxD1

PWMxD2

Interrupt

(Can be used by ADC

trigger signal)

NOTES:

1. Switch of up side is high active and switch of down side is low active.

2 For 100% duty of upside, the rising/falling compare register must be set to ‘0’. For 0% duty of upside, the rising compare
register must

be greater than TOPCMP value.

6-19

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00

4.12 SAW-TOOTH WAVE (IMMODE = 1)

PWMSWAP = 1, PWMPOLU = 0 (Low start), PWMPOLD = 0 (Low start)

TOPCMP

ADCCMPR2

PCCMPR

ADCCMPR1

ADCCMPR0

PBCMPR

PACMPR

PWMxU0

PWMxU1

PWMxU2

PWMxD0

PWMxD1

PWMxD2

Interrupt

(Can be used by ADC

trigger signal)

NOTES:

1. Switch of up side is low active and switch of down side is high active.

2. For 0% duty of upside, the rising/falling compare register must be set to ‘0’. For 100% duty of upside, the rising compare
register must be greater than TOPCMP value.

6-20

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC)

4.13 SAW-TOOTH WAVE (IMMODE = 1)

PWMSWAP = 0, PWMPOLU = 1 (High start), PWMPOLD = 0 (Low start)

TOPCMP

ADCCMPR2

PCCMPR

ADCCMPR1

ADCCMPR0

PBCMPR

PACMPR

PWMxU0

PWMxU1

PWMxU2

PWMxD0

PWMxD1

PWMxD2

Interrupt

(Can be used by ADC

trigger signal)

NOTES:

1. Switches of up side and down side are low active.

2. For 100% duty of upside, the rising/falling compare register must be set to ‘0’. For 0% duty of upside, the rising compare

register must be greater than TOPCMP value.

6-21