USER'S MANUAL ERRATA
This document contains the corrections of errors,
typos and omissions in the following document.
Samsung 8-bit CMOS S3C84E5/C84E9/P84E9 Microprocessor User's Manual
Document Number: 21.1-S3-C84E5/C84E9/P84E9-082005
Publication: August 2005
S3C84E5/C84E9/P84E9 USER’S MANUAL ERRATA
ERRATA (VER 1.1)
Samsung 8-bit CMOS S3C84E5/C84E9/P84E9 Microprocessor User’s Manual
Document Number: 21.1-S3-C84E5/C84E9/P84E9-082005
Publication: August 2005
1. Features (PAGE 1-2)
Built-in RESET circuit (LVR)
• Low-Voltage reset (LVR value: 2.9 V)
Operating Voltage Range
• V
to 5.5V
LVR
2. Low Voltage Reset (PAGE 16-1)
The on-chip Low Voltage Reset, features static reset when supply voltage is below a reference voltage value
(Typical 2.9 V).
1
USER’S MANUAL ERRATA S3C84E5/C84E9/P84E9
3. Low Voltage Reset (PAGE 16-2)
Watchdog RESET
nRESET
N.F
Longger than 1us
VDD
Internal System
RESET
VIN
+
Comparator
VREF
VDD
VREF
BGR
NOTES:
1. The target of voltage detection level is 2.9 V at VDD = 5 V
2. BGR is Band Gap voltage Reference
Longger than 1us
N.F
When the V
is lower than 2.9V
DD level
Figure 16-1. Low Voltage Reset Circuit
2
S3C84E5/C84E9/P84E9 USER’S MANUAL ERRATA
4. Table 17-3. D.C. Electrical Characteristics (PAGE 17-3)
(T
= – 25 °C to + 85 °C, V
A
DD
= V
to 5.5 V)
LVR
Parameter Symbol Conditions Min Typ. Max Unit
Input high voltage
V
V
IH1
DD
= V
to 5.5 V
LVR
0.8 VDD
–
VDD
All port and nRESET
Input low voltage
V
V
IH2
V
V
IL1
= V
DD
and XTIN
X
IN
= V
DD
(to 5.5 V
LVR
to 5.5 V
LVR
V
DD
– 0.5
– –
0.2VDD
All ports and nRESET
V
V
IL2
= V
DD
and XTIN
X
IN
to 5.5 V
LVR
0.4
V
V
3
USER’S MANUAL ERRATA S3C84E5/C84E9/P84E9
5. Table 17-3. D.C. Electrical Characteristics (PAGE 17-4)
(T
= – 25 °C to + 85 °C, V
A
DD
= V
to 5.5 V)
LVR
Parameter Symbol Conditions Min Typ. Max Unit
Pull-up resistor
R
P1
V
DD
= 5 V; V
= 0 V , T
IN
= 25°C
A
10 50 100
kΩ
All I/O pins except nRESET
V
DD
= 3 V; V
= 0 V, T
IN
= 25°C
A
20 100 400
All I/O pins except nRESET
R
P2
V
= 5 V; VIN = 0 V, T
DD
= 25°C
A
50 250 600
nRESET only
V
DD
= 3 V; V
= 0 V, T
IN
= 25°C
A
100 500 1000
nRESET only
Supply current
(1)
I
DD1
(2)
V
= 4.5V to 5.5V
DD
– 15 30 mA
RUN mode
12 MHz CPU clock
= V
V
DD
to 5.5 V
LVR
4 10
8 MHz CPU clock
V
I
DD2
= 4.5 V to 5.5 V
DD
3.4 7
Idle mode
12 MHz CPU clock
= V
V
DD
to 5.5 V
LVR
1 2.5
8 MHz CPU clock
I
DD3
Sub operating: main-osc stop
V
DD
= V
to 3.3 V
LVR
– 100 150 uA
32768 Hz crystal oscillator
I
DD4
Sub idle mode: main-osc stop
= V
V
DD
to 3.3 V
LVR
– 90 140
32768 Hz crystal oscillator
V
I
DD5
= 4.5 V to 5.5 V,
DD
T
= 25 °C
A
– 80 100
Stop mode
= V
V
DD
T
= 25 °C
A
to 3.3 V,
LVR
– 45 80
Stop mode
4
S3C84E5/C84E9/P84E9 USER’S MANUAL ERRATA
6. Table 17-4. A.C. Electrical Characteristics (PAGE 17-5)
(T
= – 25 °C to + 85 °C, V
A
DD
= V
to 5.5 V)
LVR
7. Table 17-5. Main Oscillator Frequency (PAGE 17-6)
(TA = – 25 °C + 85 °C, V
DD
= V
to 5.5 V)
LVR
Oscillator Clock Circuit Test Condition Min Typ. Max Unit
Main crystal or
ceramic
X
IN
C1 C2
= V
X
OUT
DD
to 5.5 V
LVR
1 – 12 MHz
V
External clock
(main system)
X
INXOUT
DD
= V
to 5.5 V
LVR
1 – 12
V
8. Table 17-6. Main Oscillator Clock Stabilization Time(PAGE 17-6)
(TA = – 25 °C + 85 °C, VDD = V
to 5.5 V)
LVR
9. Table 17-7. Sub Oscillator Frequency (PAGE 17-7)
(TA = –25 °C + 85 °C, V
Oscillator Clock Circuit Test Condition Min Typ. Max Unit
Crystal
= V
DD
XTINXT
to 5.5 V)
LVR
OUT
R
C1 C2
Crystal oscillation frequency
C1 = 100 pF, C2 = 100 pF
R = 330 Ω
XT
and XT
IN
are connected
OUT
with R and C by soldering.
32 32.768 34 kHz
5
USER’S MANUAL ERRATA S3C84E5/C84E9/P84E9
10. Table 17-8. Subsystem Oscillator (crystal) Stabilization Time (PAGE 17-7)
(T
= 25 °C)
A
Oscillator Test Condition Min Typ. Max Unit
Normal mode
Strong mode
V
DD
= V
V
DD
= 4.5 V to 5.5 V
V
DD
= V
V
DD
to 3.3 V
LVR
to 3.3 V
LVR
– 800 1600 ms
– 10 s
– 400 800 ms
– 150 300
= 4.5 V to 5.5 V
11. Table 17-9. Data Retention Supply Voltage in Stop Mode (PAGE 17-8)
(T
= – 25 °C to + 85 °C, V
A
DD
= V
to 5.5 V)
LVR
12. Table 17-10. UART Timing Characteristics in Mode 0 (PAGE 17-10)
(T
= – 25 °C to + 85 °C, V
A
DD
= V
Parameter Symbol Min Typ. Max Unit
Serial port clock cycle time
Output data setup to clock rising edge
Serial port clock High, Low level width
to 5.5 V, Load capacitance = 80 pF)
LVR
t
HIGH
t
SCK
t
S1
, t
LOW
500
300
200
t
CPU
t
CPU
t
CPU
× 6
× 5
× 3
700 ns
–
400
6
S3C84E5/C84E9/P84E9 USER’S MANUAL ERRATA
13. Table 17-11. A/D Converter Electrical Characteristics (PAGE 17-11)
(TA = – 25 °C to + 85 °C, VDD = V
to 5.5 V, VSS = 0 V)
LVR
14. Table 17-12. LVR (Low Voltage Reset) Circuit Characteristics (PAGE 17-12)
(T
= 25 °C)
A
Parameter Symbol Test Condition Min Typ Max Unit
LVR voltage level
V
LVR
= 25 °C
T
A
2.6 2.9 3.2 V
15. Figure 17-8. Operating Voltage Range(PAGE 17-12)
Main Oscillator Frequency
CPU Clock
12 MHz
8 MHz
1 MHz
1234567
VLVR 5.5 V
Supply Voltage (V)
Minimum instruction clock = 1/4 Oscillator clock
16. Table 19-2. Comparison of S3P84E9 and S3C84E5/C84E9 Features (PAGE 17-12)
Characteristic S3P84E9 S3C84E5/C84E9
Operating voltage (VDD) V
to 5.5 V V
LVR
LVR
to 5.5 V
7
S3C84E5/C84E9/P84E9
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.1
Important Notice
The information in this publication has been carefully
checked and is believed to be entirely accurate at the
time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.
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products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
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guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of any
product or circuit and specifically disclaims any and
all liability, including without limitation any
consequential or incidental damages.
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
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product.
S3C84E5/C84E9/P84E9 8-Bit CMOS Microcontrollers
User's Manual, Revision 1.1
Publication Number: 21.1-S3-C84E5/C84E9/P84E9-082005
© 2005 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any
form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written
consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are designed
and manufactured in accordance with the highest quality standards and objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 440-900
TEL: (82)-(31)-209-5238
FAX: (82)-(31)-209-6494
Home Page: http://www.samsung.com
Printed in the Republic of Korea
Preface
The S3C84E5/C84E9/P84E9 Microcontroller User's Manual is designed for application designers and programmers
who are using the S3C84E5/C84E9/P84E9 microcontroller for application development. It is organized in two main
parts:
Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming
model, instruction set, and interrupt structure. It has six chapters:
Chapter 1 Product Overview
Chapter 2 Address Spaces
Chapter 3 Addressing Modes
Chapter 1, "Product Overview, " is a high-level introduction to S3C84E5/C84E9/P84E9 with general product
descriptions, as well as detailed information about individual pin characteristics and pin circuit types.
Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack
operations.
Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
S3C8-series CPU.
Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values,
as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically
organized, register descriptions as a quick-reference source when writing programs.
Chapter 5, "Interrupt Structure," describes the S3C84E5/C84E9/P84E9 interrupt structure in detail and further
prepares you for additional information presented in the individual hardware module descriptions in Part II.
Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each
instruction are presented in a standard format. Each instruction description includes one or more practical examples
of how to use the instruction when writing an application program.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part
II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the first time,
we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information in Chapters
4, 5, and 6. Later, you can reference the information in Part I as necessary.
Chapter 4 Control Registers
Chapter 5 Interrupt Structure
Chapter 6 Instruction Set
Part II "hardware Descriptions," has detailed information about specific hardware components of the
S3C84E5/C84E9/P84E9 microcontroller. Also included in Part II are electrical, mechanical, OTP, and development
tools data. It has 14 chapters:
Chapter 7 Clock Circuit
Chapter 8 RESET and Power-Down
Chapter 9 I/O Ports
Chapter 10 Basic Timer
Chapter 11 8-bit Timer A/B
Chapter 12 16-bit Timer 1(0,1)
Chapter 13 UART
Two order forms are included at the back of this manual to facilitate customer order for S3C84E5/C84E9/P84E9
microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these
forms, fill them out, and then forward them to your loc al Samsung Sales Representative.
S3C84E5/C84E9/P84E9 MICROCONTROLLER iii
Chapter 14 Watch Timer
Chapter 15 A/D Converter
Chapter 16 Low Voltage Reset
Chapter 17 Electrical Data
Chapter 18 Mechanical Data
Chapter 19 S3P84E9 OTP version
Chapter 20 Development Tools
Table of Contents
Part I — Programming Model
Chapter 1 Product Overview
S3C8-SERIES Microcontrollers .............................................................................................................1-1
S3C84E5/C84E9/P84E9 Microcontroller................................................................................................1-1
Features.............................................................................................................................................1-2
Block Diagram ....................................................................................................................................1-3
Pin Assignment ...................................................................................................................................1-4
Pin Assignment...................................................................................................................................1-5
Pin Descriptions..................................................................................................................................1-6
Pin Circuits .........................................................................................................................................1-8
Chapter 2 Address Spaces
Overview.............................................................................................................................................2-1
Program Memory (ROM)......................................................................................................................2-2
Register Architecture...........................................................................................................................2-3
Register Page Pointer (PP)..........................................................................................................2-5
Register Set 1.............................................................................................................................2-7
Register Set 2.............................................................................................................................2-7
Prime Register Space..................................................................................................................2-8
Working Registers.......................................................................................................................2-9
Using the Register Pointers..........................................................................................................2-10
Register Addressing ............................................................................................................................2-12
Common Working Register Area (C0h–Cfh)....................................................................................2-14
4-Bit Working Register Addressing................................................................................................2-15
8-Bit Working Register Addressing................................................................................................2-17
System and User Stack .......................................................................................................................2-19
Chapter 3 Addressing Modes
Overview.............................................................................................................................................3-1
Register Addressing Mode (R)..............................................................................................................3-2
Indirect Register Addressing Mode (IR) ..................................................................................................3-3
Indexed Addressing Mode (X) ...............................................................................................................3-7
Direct Address Mode (DA)....................................................................................................................3-10
Indirect Address Mode (IA) ...................................................................................................................3-12
Relative Address Mode (RA).................................................................................................................3-13
Immediate Mode (IM)...........................................................................................................................3-14
S3C84E5/C84E9/P84E9 MICROCONTROLLER v
Table of Contents (Continued)
Chapter 4 Control Registers
Overview.............................................................................................................................................4-1
Chapter 5 Interrupt Structure
Overview.............................................................................................................................................5-1
Interrupt Types ............................................................................................................................5-2
S3C84E5/C84E9/P84E9 Interrupt Structure ...................................................................................5-3
Interrupt Vector Addresses...........................................................................................................5-5
Enable/Disable Interrupt Instructions (EI, DI) ..................................................................................5-7
System-Level Interrupt Control Registers .......................................................................................5-7
Interrupt Processing Control Points...............................................................................................5-8
Peripheral Interrupt Control Registers ............................................................................................5-9
System Mode Register (SYM)......................................................................................................5-10
Interrupt Mask Register (IMR).......................................................................................................5-11
Interrupt Priority Register (IPR) .....................................................................................................5-12
Interrupt Request Register (IRQ) ...................................................................................................5-14
Interrupt Pending Function Types..................................................................................................5-15
Interrupt Source Polling Sequence................................................................................................5-16
Interrupt Service Routines .............................................................................................................5-16
Generating Interrupt Vector Addresses ..........................................................................................5-17
Nesting of Vectored Interrupts.......................................................................................................5-17
Chapter 6 Instruction Set
Overview.............................................................................................................................................6-1
Data Types .................................................................................................................................6-1
Register Addressing ....................................................................................................................6-1
Addressing Modes .......................................................................................................................6-1
Flags Register (FLAGS)...............................................................................................................6-6
Flag Descriptions ........................................................................................................................6-7
Instruction Set Notation................................................................................................................6-8
Condition Codes..........................................................................................................................6-12
Instruction Descriptions ................................................................................................................6-13
vi S3C84E5/C84E9/P84E9 MICROCONTROLLER
Table of Contents (Continued)
Part II Hardware Descriptions
Chapter 7 Clock Circuit
Overview.............................................................................................................................................7-1
System Clock Circuit ...................................................................................................................7-1
Clock Status During Power-Down Modes.......................................................................................7-2
System Clock Control Register (CLKCON).....................................................................................7-3
Chapter 8 RESET and Power-Down
System Reset.....................................................................................................................................8-1
Overview.....................................................................................................................................8-1
Normal Mode RESET Operation....................................................................................................8-1
Hardware RESET Values .............................................................................................................8-2
Power-Down Modes.............................................................................................................................8-5
Stop Mode ..................................................................................................................................8-5
Idle Mode....................................................................................................................................8-6
Chapter 9 I/O Ports
Overview.............................................................................................................................................9-1
Port Data Registers .....................................................................................................................9-2
Port 0.........................................................................................................................................9-3
Port 1.........................................................................................................................................9-5
Port 2.........................................................................................................................................9-7
Port 3.........................................................................................................................................9-12
Port 4.........................................................................................................................................9-14
Chapter 10 Basic Timer
Overview.............................................................................................................................................10-1
Basic Timer (BT) .........................................................................................................................10-1
Basic Timer Control Register (BTCON)..........................................................................................10-1
Basic Timer Function Des cription..................................................................................................10-3
S3C84E5/C84E9/P84E9 MICROCONTROLLER vii
Table of Contents (Continued)
Chapter 11 8-bit Timer A/B
8-Bit Timer A.......................................................................................................................................11-1
Overview.....................................................................................................................................11-1
Function Description ....................................................................................................................11-2
Timer A Control Register (TACON)................................................................................................11-3
Block Diagram ............................................................................................................................11-4
8-Bit Timer B.......................................................................................................................................11-5
Overview.....................................................................................................................................11-5
Block Diagram ............................................................................................................................11-5
Timer B Control Register (TBCON)................................................................................................11-6
Timer B Pulse Width Calculations.................................................................................................11-7
Chapter 12 16-bit Timer 1(0, 1)
Overview.............................................................................................................................................12-1
Function Description ....................................................................................................................12-2
Timer 1(0,1) Control Register (T1CON0, T1CON1)...........................................................................12-3
Block Diagram ............................................................................................................................12-6
Chapter 13 UART
Overview.............................................................................................................................................13-1
Programming Procedure...............................................................................................................13-1
Uart Control Register (UARTCON) .................................................................................................13-2
Uart Interrupt Pending Register (UARTPND) ...................................................................................13-4
Uart Data Register (UDATA) .........................................................................................................13-5
Uart Baud Rate Data Register (BRDATAH, BRDATAL)....................................................................13-6
Baud Rate Calculations ................................................................................................................13-6
Block Diagram ....................................................................................................................................13-8
Uart Mode 0 Function Description.................................................................................................13-9
Uart Mode 1 Function Description.................................................................................................13-10
Uart Mode 2 Function Description.................................................................................................13-11
Serial Communication for Multiprocessor Configurations ..................................................................13-13
Chapter 14 Watch Timer
Overview.............................................................................................................................................14-1
Watch Timer Control Register (WTCON: R/W)...............................................................................14-2
Watch Timer Circuit Diagram........................................................................................................14-3
viii S3C84E5/C84E9/P84E9 MICROCONTROLLER
Table of Contents (Continued)
Chapter 15 8-bit Analog-to-Digital Converter
Overview.............................................................................................................................................15-1
Function Description ............................................................................................................................15-1
A/D Converter Control Register (ADCON) .......................................................................................15-2
Internal Reference Voltage Levels..................................................................................................15-4
Conversion Timing .......................................................................................................................15-4
Internal A/D Conversion Procedure................................................................................................15-5
Chapter 16 Low Voltage RESET
Overview.............................................................................................................................................16-1
Chapter 17 Electrical Data
Overview.............................................................................................................................................17-1
Chapter 18 Mechanical Data
Overview.............................................................................................................................................18-1
Chapter 19 S3P84E9 OTP Version
Overview.............................................................................................................................................19-1
Operating Mode Characteristics ....................................................................................................19-3
Chapter 20 Development Tools
Overview.............................................................................................................................................20-1
Shine .........................................................................................................................................20-1
Sasm.........................................................................................................................................20-1
Sama Assembler.........................................................................................................................20-1
HEX2ROM..................................................................................................................................20-1
Target Boards .............................................................................................................................20-2
Otp............................................................................................................................................20-2
Otp Programming Socket Adapter.................................................................................................20-2
TB84E5/84E9 Target Board..........................................................................................................20-3
Idle Led ......................................................................................................................................20-4
Stop Led.....................................................................................................................................20-4
Port (P0.0, P0.1) Selection (SUB -OSC or normal input)..................................................................20-4
S3C84E5/C84E9/P84E9 MICROCONTROLLER ix
List of Figures
Figure Title Page
Number Number
1-1 S3C84E5/C84E9/P84E9 Block Diagram................................................................1-3
1-2 S3C84E5/C84E9/P84E9 Pin Assignment (44-pin QFP)...........................................1-4
1-3 S3C84E5/C84E9/P84E9 Pin Assignment (42-pin SDIP) ..........................................1-5
1-4 Pin Circuit Type B (RESETB)...............................................................................1-8
1-5 Pin Circuit Type C...............................................................................................1-8
1-6 Pin Circuit Type D (P0.2-P0.7, P1, P4.3-P4.5) .......................................................1-9
1-7 Pin Circuit Type D-1 (P2, and P4.0-P4.2)...............................................................1-9
1-8 Pin Circuit Type E (P3) ........................................................................................1-10
1-9 Pin Circuit Type F (P0.0, P0.1).............................................................................1-10
2-1 Program Memory Address Space.........................................................................2-2
2-2 Internal Register File Organization.........................................................................2-4
2-3 Register Page Pointer (PP)..................................................................................2-5
2-4 Set 1, Set 2, Prime Area Register .........................................................................2-8
2-5 8-Byte Working Register Areas (Slices).................................................................2-9
2-6 Contiguous 16 Byte Working Register Block ..........................................................2-10
2-7 Non-Contiguous 16 Byte Working Register Block...................................................2-11
2-8 16-Bit Register Pair .............................................................................................2-12
2-9 Register File Addressing......................................................................................2-13
2-10 Common Working Register Area...........................................................................2-14
2-11 4-Bit Working Register Addressing........................................................................2-16
2-12 4-Bit Working Register Addressing Example..........................................................2-16
2-13 8-Bit Working Register Addressing........................................................................2-17
2-14 8-Bit Working Register Addressing Example..........................................................2-18
2-15 Stack Operations ................................................................................................2-19
3-1 Register Addressing ............................................................................................3-2
3-2 Working Register Addressing ...............................................................................3-2
3-3 Indirect Register Addressing to Register File ..........................................................3-3
3-4 Indirect Register Addressing to Program Memory ...................................................3-4
3-5 Indirect Working Register Addressing to Register File .............................................3-5
3-6 Indirect Working Register Addressing to Program or Data Memory ...........................3-6
3-7 Indexed Addressing to Register File......................................................................3-7
3-8 Indexed Addressing to Program or Data Memory with Short Offset...........................3-8
3-9 Indexed Addressing to Program or Data Memory....................................................3-9
3-10 Direct Addressing for Load Instructions..................................................................3-10
3-11 Direct Addressing for Call and Jump Instructions....................................................3-11
3-12 Indirect Addressing..............................................................................................3-12
3-13 Relative Addressing .............................................................................................3-13
3-14 Immediate Addressing .........................................................................................3-14
4-1 Register Description Format .................................................................................4-4
S3C84E5/C84E9/P84E9 MICROCONTROLLER xi
List of Figures (Continued)
Figure Title Page
Number Number
5-1 S3C8-Series Interrupt Types.................................................................................5-2
5-2 S3C84E5/C84E9/P84E9 Interrupt Structure ...........................................................5-4
5-3 ROM Vector Address Area ...................................................................................5-5
5-4 Interrupt Function Diagram ...................................................................................5-8
5-5 System Mode Register (SYM)..............................................................................5-10
5-6 Interrupt Mask Register (IMR)...............................................................................5-11
5-7 Interrupt Request Priority Groups ..........................................................................5-12
5-8 Interrupt Priority Register (IPR) .............................................................................5-13
5-9 Interrupt Request Register (IRQ) ...........................................................................5-14
6-1 System Flags Register (FLAGS)...........................................................................6-6
7-1 Main Oscillator Circuit (Crystal or Ceramic Oscillator) .............................................7-1
7-2 Sub-System Oscillator Circuit (Crystal Oscillator)...................................................7-1
7-3 System Clock Circuit Diagram ..............................................................................7-2
7-4 System Clock Control Register (CLKCON).............................................................7-3
7-5 Oscillator Control Register (OSCCON)...................................................................7-4
7-6 STOP Control Register (STPCON) ........................................................................7-4
9-1 Port 0 High Byte Control Register (P0CONH).........................................................9-3
9-2 Port 0 Low Byte Control Register (P0CONL) ..........................................................9-4
9-3 Port 1 High-Byte Control Register (P1CONH).........................................................9-5
9-4 Port 1 Low-Byte Control Register (P1CONL) ..........................................................9-6
9-5 Port 2 High-Byte Control Register (P2CONH).........................................................9-8
9-6 Port 2 Low-Byte Control Register (P2CONL) ..........................................................9-9
9-7 Port 2 Interrupt Pending Register (P2INTPND) ........................................................9-10
9-8 Port 2 Interrupt Control Register (P2INT) ................................................................9-11
9-9 Port 3 High-Byte Control Register (P3CONH).........................................................9-12
9-10 Port 3 Low-Byte Control Register (P3CONL)..........................................................9-13
9-11 Port 4 High-Byte Control Register (P4CONH) .........................................................9-15
9-12 Port 4 Low-Byte Control Register (P4CONL)..........................................................9-15
9-13 Port 4 Interrupt Pending Register (P4INTPND)........................................................9-16
9-14 Port 4 Interrupt Control Register (P4INT) ................................................................9-16
10-1 Basic Timer Control Register (BTCON) ..................................................................10-2
10-2 Basic Timer Block Diagram ..................................................................................10-4
11-1 Timer A Control Register (TACON) ........................................................................11-3
11-2 Timer A Functional Block Diagram ........................................................................11-4
11-3 Timer B Functional Block Diagram ........................................................................11-5
11-4 Timer B Control Register (TBCON) ........................................................................11-6
11-5 Timer B Data Registers (TBDATAH, TBDATAL)......................................................11-6
11-6 Timer B Output Flip Flop Waveforms in Repeat Mode .............................................11-8
xii S3C84E5/C84E9/P84E9 MICROCONTROLLER
List of Figures (Concluded)
Page Title Page
Number Number
12-1 Timer 1(0,1) Control Register (T1CON0, T1CON1)...................................................12-4
12-2 Timer A, Timer 1(0,1) Pending Register (TINTPND) .................................................12-5
12-3 Timer 1(0,1) Functional Block Diagram ..................................................................12-6
13-1 UART Control Register (UARTCON)......................................................................13-3
13-2 UART Interrupt Pending Register (UARTPND)........................................................13-4
13-3 UART Data Register (UDATA)...............................................................................13-5
13-4 UART Baud Rate Data Register (BRDATAH, BRDATAL) .........................................13-6
13-5 UART Functional Block Diagram ...........................................................................13-8
13-6 Timing Diagram for UART Mode 0 Operation ..........................................................13-9
13-7 Timing Diagram for UART Mode 1 Operation..........................................................13-10
13-8 Timing Diagram for UART Mode 2 Operation ..........................................................13-12
13-9 Connection Example for Multiprocessor Serial Data Communications.......................13-14
14-1 Watch Timer Circuit Diagram ................................................................................14-3
15-1 A/D Converter Control Register (ADCON)...............................................................15-2
15-2 A/D Converter Data Register (ADDATAH, ADDATAL)..............................................15-3
15-3 A/D Converter Circuit Diagram..............................................................................15-3
15-4 A/D Converter Timing Diagram ..............................................................................15-4
15-5 Recommended A/D Converter Circuit for Highest Absolute Accuracy........................15-5
16-1 Low Voltage Reset Circuit ....................................................................................16-2
17-1 Input Timing for External Interrupts (Ports 4 and 6)..................................................17-5
17-3 Clock Timing Measurement at XIN.........................................................................17-7
17-4 Stop Mode Release Timing Initiated by RESET......................................................17-8
17-5 Stop Mode (Main) Release Timing Initiated by Interrupts.........................................17-8
17-6 Stop Mode (Sub) Release Timing Initiated by Interrupts...........................................17-9
17-7 Waveform for UART Timing Characteristics ............................................................17-10
17-8 Operating Voltage Range.....................................................................................17-12
17-9 The Circuit Diagram to Improve EFT Characteristics................................................17-12
18-1 42-SDIP-600 Package Dimensions ........................................................................18-1
18-2 44-QFP-1010 Package Dimensions.......................................................................18-2
19-1 S3P84E9 Pin Assignments (42-SDIP Package).....................................................19-1
19-2 S3P84E9 Pin Assignments (44-QFP Package) ......................................................19-2
20-1 SMDS+ or SK-1000 Product Configuration .............................................................20-2
20-2 S3C84E5/S3C84E9/S3P84E9 Target Board Configuration.......................................20-3
20-3 44-Pin Connector pin assignment for TB84E5/84E9................................................20-5
20-4 TB84E5/84E9 Adapter Cable for 44pin Connector Package.....................................20-6
S3C84E5/C84E9/P84E9 MICROCONTROLLER xiii
List of Tables
Table Title Page
Number Number
1-1 S3C84E5/C84E9/P84E9 Pin Descriptions ..............................................................1-6
2-1 S3C84E5/C84E9/P84E9 Register Type Summary ..................................................2-3
4-1 Set 1 Registers ...................................................................................................4-1
4-2 Set 1, Bank 0 Registers.......................................................................................4-2
4-3 Set 1, Bank 1 Registers.......................................................................................4-3
5-1 Interrupt Vectors ..................................................................................................5-6
5-2 Interrupt Control Register Overview........................................................................5-7
5-3 Interrupt Source Control and Data Registers ...........................................................5-9
6-1 Instruction Group Summary..................................................................................6-2
6-2 Flag Notation Conventions....................................................................................6-8
6-3 Instruction Set Symbols .......................................................................................6-8
6-4 Instruction Notation Conventions ...........................................................................6-9
6-5 OPCODE Quick Reference...................................................................................6-10
6-6 Condition Codes..................................................................................................6-12
8-1 S3C84E5/C84E9/P84E9 Set 1 Register Values After RESET ..................................8-2
8-2 S3C84E5/C84E9/P84E9 Set 1, Bank 0 Register Values After RESET......................8-3
8-3 S3C84E5/C84E9/P84E9 Set 1, Bank 1 Register Values After RESET......................8-4
9-1 S3C84E5/C84E9/P84E9 Port Configuration Overview..............................................9-1
9-2 Port Data Register Summary................................................................................9-2
14-1 Watch Timer Control Register (WTCON): Set 1, Bank 0, FAH, R/W.........................14-2
17-1 Absolute Maximum Ratings..................................................................................17-2
17-2 Input/Output Capacitance.....................................................................................17-2
17-3 D.C. Electrical Characteristics..............................................................................17-3
17-4 A.C. Electrical Characteristics..............................................................................17-5
17-2 Input Timing for RESET........................................................................................17-5
17-5 Main Oscillator Frequency (f
17-6 Main Oscillator Clock Stabilization Time (t
17-7 Sub Oscillator Frequency (f
17-8 Subsystem Oscillator (crystal) Stabilization Time (t
17-9 Data Retention Supply Voltage in Stop Mode.........................................................17-8
17-10 UART Timing Characteristics in Mode 0 (10 MHz)..................................................17-10
17-11 A/D Converter Electrical Characteristics ................................................................17-11
17-12 LVR(Low Voltage Reset) Circuit Characteristics ...................................................17-12
).......................................................................17-6
OSC1
)......................................................17-6
ST1
) ........................................................................17-7
OSC2
).........................................17-7
ST2
S3C84E5/C84E9/P84E9 MICROCONTROLLER xv
List of Tables (Continued)
Table Title Page
Number Number
19-1 Descriptions of Pins Used to Read/Write the OTP..................................................19-3
19-2 Comparison of S3P84E9 and S3C84E5/C84E9 Features.........................................19-3
19-3 Operating Mode Selection Criteria.........................................................................19-3
20-1 Power Selection Settings for TB84E5/84E9............................................................20-4
20-2 Using Single Header Pins as the Input Path for External Trigger Sources..................20-4
20-3 The Port 0.0 and Port 0.1 selection setting............................................................20-5
xvi S3C84E5/C84E9/P84E9 MICROCONTROLLER
List of Programming Tips
Description Page
Number
Chapter 2: Address Spaces
Using the Page Pointer for RAM clear (Page 0, Page 1) ..........................................................................2-6
Setting the Register Pointers................................................................................................................2-10
Using the RPs to Calculate the Sum of a Series of Registers ..................................................................2-11
Addressing the Common Working Register Area....................................................................................2-15
Standard Stack Operations Using PUSH and POP .................................................................................2-20
Chapter 11: 8-bit Timer A/B
To Generate 38 kHz, 1/3duty signal through P4.3...................................................................................11-9
To generate a one pulse signal through P4.3..........................................................................................11-10
Using the Timer A................................................................................................................................11-11
Using the Timer B................................................................................................................................11-12
Chapter 12: 16-bit Timer 1(0,1)
Using the Timer 1(0) ............................................................................................................................12-7
Chapter 14: Watch Timer
Using the Watch Timer ........................................................................................................................14-4
Chapter 15: A/D Converter
Configuring A/D Converter.....................................................................................................................15-6
S3C84E5/C84E9/P84E9 MICROCONTROLLER xvii
List of Register Descriptions
Register Full Register Name Page
Identifier Number
ADCON A/D Converter Control Register F7H Set 1, Bank 0.................................................4-5
BTCON Basic Timer Control Register H Set 1 ....................................................................4-6
CLKCON System Clock Control Register D4H Set 1.............................................................4-7
FLAGS System Flags Register D5H Set 1........................................................................4-8
IMR Interrupt Mask Register DDH Set 1 .......................................................................4-9
IPH Instruction Pointer (High Byte) DAH Set 1..............................................................4-10
IPL Instruction Pointer (Low Byte) DBH Set 1..............................................................4-10
IPR Interrupt Priority Register FFH Set 1, Bank 0.........................................................4-11
IRQ Interrupt Request Register DCH Set 1...................................................................4-12
OSCCON Oscillator Control Register FBH Set 1,Bank 0 ......................................................4-13
P0CONH Port 0 Control Register (High Byte) E6H Set 1, Bank 0...........................................4-14
P0CONL Port 0 Control Register (Low Byte) E7H Set 1, Bank 0............................................4-15
P1CONH Port 1 Control Register (High Byte) E8H Set 1, Bank 0...........................................4-16
P1CONL Port 1 Control Register (Low Byte) E9H Set 1, Bank 0............................................4-17
P2CONH Port 2 Control Register (High Byte) EAH Set 1, Bank 0...........................................4-18
P2CONL Port 2 Control Register (Low Byte) EBH Set 1, Bank 0...........................................4-19
P2INT Port 2 Interrupt Control Register ECH Set 1, Bank 0 ...............................................4-20
P2INTPN D Port 2 Interrupt Pending Register EDH Set 1, Bank 0..............................................4-21
P3CONH Port 3 Control Register (High Byte) EEH Set 1, Bank 0...........................................4-22
P3CONL Port 3 Control Register (Low Byte) EFH Set 1, Bank 0............................................4-23
P4CONH Port 4 Control Register (High Byte) F0H Set 1, Bank 0...........................................4-24
P4CONL Port 4 Control Register (Low Byte) F1H Set 1, Bank 0 ............................................4-25
P4INT Port 4 Interrupt Control Register F2H Set 1, Bank 0................................................4-26
P4INTPND Port 4 Interrupt Pending Register F3H Set 1, Bank 0 ..............................................4-27
PP Register Page Pointer DFH Set 1..........................................................................4-28
RP0 Register Pointer 0 D6H Set 1................................................................................4-29
RP1 Register Pointer 1 D7H Set 1................................................................................4-29
SPH Stack Pointer (High Byte) D8H Set 1.....................................................................4-30
SPL Stack Pointer (Low Byte) D9H Set 1.....................................................................4-30
STPCON Stop Control Register E5H Set 1, Bank 0..............................................................4-31
SYM System Mode Register DEH Set 1........................................................................4-32
T1CON0 Timer 1(0) Control Register E8H Set 1, Bank 1.......................................................4-33
T1CON1 Timer 1(1) Control Register E9H Set 1, Bank 1.......................................................4-34
TACON Timer A Control Register E1H Set 1, Bank 1..........................................................4-35
TBCON Timer B Control Register D0H Set 1 ......................................................................4-36
TINTPND Timer A, Timer 1 Interrupt Pending Register E0H Set 1, Bank 1...............................4-37
UARTCON UART Control Register F6H Set 1, Bank 0.............................................................4-38
UARTPND UART Pending and parity control F4H Set 1, Bank 0..............................................4-40
WTCON Watch Timer Control Register FAH Set 1, Bank 0..................................................4-41
S3C84E5/C84E9/P84E9 MICROCONTROLLER xix
List of Instruction Descriptions
Instruction Full Register Name Page
Mnemonic Number
ADC Add with Carry ....................................................................................................6-14
ADD Add....................................................................................................................6-15
AND Logical AND........................................................................................................6-16
BAND Bit AND..............................................................................................................6-17
BCP Bit Compare........................................................................................................6-18
BITC Bit Complement ..................................................................................................6-19
BITR Bit Reset ............................................................................................................6-20
BITS Bit Set ................................................................................................................6-21
BOR Bit OR ................................................................................................................6-22
BTJRF Bit Test, Jump Relative on False...........................................................................6-23
BTJRT Bit Test, Jump Relative on True.............................................................................6-24
BXOR Bit XOR ..............................................................................................................6-25
CALL Call Procedure ....................................................................................................6-26
CCF Complement Carry Flag .......................................................................................6-27
CLR Clear..................................................................................................................6-28
COM Complement .......................................................................................................6-29
CP Compare.............................................................................................................6-30
CPIJE Compare, Increment, and Jump on Equal...............................................................6-31
CPIJNE Compare, Increment, and Jump on Non-Equal........................................................6-32
DA Decimal Adjust....................................................................................................6-33
DA Decimal Adjust....................................................................................................6-34
DEC Decrement..........................................................................................................6-35
DECW Decrement Word.................................................................................................6-36
DI Disable Interrupts ................................................................................................6-37
DIV Divide (Unsigned).................................................................................................6-38
DJNZ Decrement and Jump if Non-Zero ..........................................................................6-39
EI Enable Interrupts.................................................................................................6-40
ENTER Enter..................................................................................................................6-41
EXIT Exit ....................................................................................................................6-42
IDLE Idle Operation......................................................................................................6-43
INC Increment ...........................................................................................................6-44
INCW Increment Word...................................................................................................6-45
IRET Interrupt Return ...................................................................................................6-46
JP Jump..................................................................................................................6-47
JR Jump Relative ......................................................................................................6-48
LD Load...................................................................................................................6-49
LD Load...................................................................................................................6-50
LDB Load Bit..............................................................................................................6-51
S3C84E5/C84E9/P84E9 MICROCONTROLLER xxi
List of Instruction Descriptions (Continued)
Instruction Full Register Name Page
Mnemonic Number
LDC/LDE Load Memory......................................................................................................6-52
LDC/LDE Load Memory......................................................................................................6-53
LDCD/LDED Load Memory and Decrement...............................................................................6-54
LDCI/LDEI Load Memory and Increment ................................................................................6-55
LDCPD/LDEPD Load Memory with Pre-Decrement ........................................................................6-56
LDCPI/LDEPI Load Memory with Pre-Increment..........................................................................6-57
LDW Load Word ..........................................................................................................6-58
MULT Multiply (Unsigned) ..............................................................................................6-59
NEXT Next...................................................................................................................6-60
NOP No Operation.......................................................................................................6-61
OR Logical OR..........................................................................................................6-62
POP Pop from Stack...................................................................................................6-63
POPUD Pop User Stack (Decrementing)............................................................................6-64
POPUI Pop User Stack (Incrementing).............................................................................6-65
PUSH Push to Stack.....................................................................................................6-66
PUSHUD Push User Stack (Decrementing) ..........................................................................6-67
PUSHUI Push User Stack (Incrementing) ...........................................................................6-68
RCF Reset Carry Flag.................................................................................................6-69
RET Return................................................................................................................6-70
RL Rotate Left..........................................................................................................6-71
RLC Rotate Left through Carry .....................................................................................6-72
RR Rotate Right ........................................................................................................6-73
RRC Rotate Right through Carry ...................................................................................6-74
SB0 Select Bank 0 .....................................................................................................6-75
SB1 Select Bank 1 .....................................................................................................6-76
SBC Subtract with Carry..............................................................................................6-77
SCF Set Carry Flag.....................................................................................................6-78
SRA Shift Right Arithmetic ...........................................................................................6-79
SRP/SRP0/SRP1 Set Register Pointer ............................................................................................6-80
STOP Stop Operation....................................................................................................6-81
SUB Subtract .............................................................................................................6-82
SWAP Swap Nibbles......................................................................................................6-83
TCM Test Complement under Mask..............................................................................6-84
TM Test under Mask .................................................................................................6-85
WFI Wate for Interrupt.................................................................................................6-86
XOR Logical Exclusive OR ...........................................................................................6-87
xxii S3C84E5/C84E9/P84E9 MICROCONTROLLER
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLERS
Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. The major CPU features are:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode released by interrupt or reset
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight-interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to
specific interrupt levels.
S3C84E5/C84E9/P84E9 MICROCONTROLLER
The S3C84E5/C84E9/P84E9 single-chip CMOS microcontrollers are fabricated using the highly advanced CMOS
process technology based on Samsung’s latest CPU architecture.
The S3C84E5 is a microcontroller with a 16K-byte mask-programmable ROM embedded.
The S3C84E9 is a microcontroller with a 32K-byte mask-programmable ROM embedded.
The S3P84E9 is a microcontroller with a 32K-byte OTP ROM embedded.
Using a proven modular design approach, Samsung engineers have successfully developed the
S3C84E5/C84E9/P84E9 by integrating the following peripheral modules with the powerful SAM8 core:
— Five programmable I/O ports (42SDIP: 34pins, 44QFP: 36pins)
— Eleven bit-programmable pins for external interrupts.
— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).
— Two 8-bit timer/counter and Two 16-bit timer/counter with selectable operating modes.
— One asynchronous UART
— 10-bit 8-channel A/D converter
The S3C84E5/C84E9/P84E9 is versatile microcontroller for home appliances and ADC applications, etc. They are
currently available in 44-pin QFP and 42-pin SDIP package.
1-1
PRODUCT OVERVIEW S3C84E5/C84E9/P84E9
FEATURES
CPU
• SAM88RC CPU core
Memory
• 528-bytes internal register file
• 16K/32Kbytes internal program memory
(S3C84E5/C84E9:Mask ROM)
(S3P84E9:OTP)
Oscillation Sources
• Main clock oscillator (Crystal, Ceramic)
• CPU clock divider (1/1, 1/2, 1/8, 1/16)
• 32,768Hz Sub oscillator for watch timer
Instruction Set
• 78 instructions
• IDLE and STOP instructions added for power-
down modes
Instruction Execution Time
• 333 ns at 12-MHz f
(minimum)
OSC
Watch timer
• Real-time and interval time measurement
• Four-frequency outputs for buzzer sound
A/D Converter
• 10-bit resolution
• Eight-analog input channels
• 20us conversion speed at 10MHz f
ADC
clock.
Asynchronous UART
• One Asynchronous UART
• Programmable baud rate generator
• Supports serial data transmit/receive operations
with 8-bit, 9-bit in UART
Built-in RESET Circuit (LVR)
• Low-Voltage reset (LVR value: 2.9V)
Oscillation Frequency
• 1MHz to 12MHz external crystal oscillator
Interrupts
• 21 interrupt sources with 21 vectors.
• 8 level, 21 vector interrupt structure
I/O Ports
• Total 36 bit-programmable pins (44QFP)
Total 34 bit-programmable pins (42SDIP)
Timers and Timer/Counters
• One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
function.
• One 8-bit timer/counter (Timer A) with three
operating modes; Interval mode, capture mode
and PWM mode.
• One 8-bit timer (Timer B) with carrier frequency
(or PWM) generator.
• Two 16-bit timer/counter (Timer 10,11) with
three operating modes; Interval mode, Capture
mode, and PWM mode.
Operating Temperature Range
• –25°C to + 85°C
Operating Voltage Range
• V
to 5.5V
LVR
Package Type
• 42 pin SDIP, 44 pin QFP
1-2
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW
BLOCK DIAGRAM
Xin, XTin
Xout, XTout
nRESET
P1.0/TAOUT
P0.7/TACAP
P0.6 /T A C K
P4.3 /T B P WM
P1 .2 /T1OUT 0
P1 .1 /T1C K0
P0 .5 /T1C AP0
P0.4 /T 1OUT 1
P0.3 /T 1CK1
P0.2 /T 1CAP 1
P1.5/TxD
P1.4 /R x D
P1.3 /B Z O U T
OSC/nRESET
8-Bit
Basic Timer
8-Bit
Timer/Counter
A, B
16-Bit
Timer/Counter
10, 11
UART
Watch Timer
P0.0~P0.7
Port 0
I/O P o rt a n d In te rru p t C o n tro l
SAM88RC
CPU
16K/32K-Byte
ROM
P1.0~P1.5
528-Byte
RAM
Port 1
Port 2
Port 3
Port 4
A/D
P2.0~P2.7/
INT0 ~ IN T 7
P3.0~P3.7/
ADC0~ADC7
P4.0~P4.5
INT8 -IN T 1 0
ADC0~ADC7/
P3.0~P3.7
AV
REF
AVSS
Figure 1-1. S3C84E5/C84E9/P84E9 Block Diagram
1-3
PRODUCT OVERVIEW S3C84E5/C84E9/P84E9
PIN ASSIGNMENT
P4.4
P0.2/T1CAP1
P0.3/T1CK1
P0.4/T1OUT1
P0.5/T1CAP0
P0.6/TACK
P0.7/TACAP
P1.0/TAOUT
P1.1/T1CK0
P1.2/T1OUT0
P1.3/BZOUT
4443424140393837363534
XTout/P0.1
XTin/P0.0
TBPWM/P4.3
INT10/P4.2
VDD
VSS
Xout
Xin
TEST
INT9/P4.1
INT8/P4.0 AVss
1
2
3
4
5
6
7
8
9
10
11
S3C84E5
S3C84E9
S3P84E9
Top View
(44-QFP)
1213141516171819202122
33
32
31
30
29
28
27
26
25
24
23
P1.4/RXD
P1.5/TXD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
P4.5
AVref
nRESET
INT0/P2.0
INT1/P2.1
INT2/P2.2
INT3/P2.3
INT4/P2.4
INT5/P2.5
INT6/P2.6
INT7/P2.7
Figure 1-2. S3C84E5/C84E9/P84E9 Pin Assignment (44-pin QFP)
1-4
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW
PIN ASSIGNMENT
TACAP/P0.7
TACK/P0.6
T1CAP0/P0.5
T1OUT1/P0.4
T1CK1/P0.3
T1CAP1/P0.2
XTout/P0.1
XTin/P0.0
TBPWM/P4.3
INT10/P4.2
VDD
VSS
Xout
Xin
TEST
INT9/P4.1
INT8/P4.0
nRESET
INT0/P2.0
INT1/P2.1
INT2/P2.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3C84E5
S3C84E9
S3P84E9
Top View
(42-SDIP)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P1.0/TAOUT
P1.1/T1CK0
P1.2/T1OUT0
P1.3/BZOUT
P1.4/RXD
P1.5/TXD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AVss
AVref
P2.7/INT7
P2.6/INT6
P2.5/INT5
P2.4/INT4
P2.3/INT3
Figure 1-3. S3C84E5/C84E9/P84E9 Pin Assignment (42-pin SDIP)
1-5
PRODUCT OVERVIEW S3C84E5/C84E9/P84E9
PIN DESCRIPTIONS
Table 1-1. S3C84E5/C84E9/P84E9 Pin Descriptions
Pin
Name
Pin
Type
Pin
Description
P0.0–P0.7 I/O Bit programmable port; input or output mode
selected by software; input or push-pull output.
Software assignable pull-up resistor.
Alternately, can be used as I/O for Timer A,
Timer 1(0,1). P0.0 and P0.1 can alternately be
used for subsystem oscillator in/out mode
selected by software
P1.0–P1.5 I/O Bit programmable port; input or output mode
selected by software; input or push-pull output.
Software assignable pull-up resistor. Alternatively
can be used as Timer A, Timer 1(0), UART,
Watch Timer Buzzer output.
P2.0–P2.7 I/O Bit programmable port; input or output mode
selected by software; input or push-pull output.
Software assignable pull-up.
Alternately, can be used as inputs for external
interrupts INT0–INT7. (with noise filters and
interrupt controller)
P3.0–P3.7 I/O Bit programmable port; input or output mode
selected by software; input or push-pull output.
Software assignable pull-up.
Alternately, can be used as analog inputs for A/D
converter modules.
P4.0–P4.5 I/O Bit programmable port; input or output mode
selected by software; input or push-pull output.
Software assignable pull-up. Alternatively can be
used as Timer B, inputs for external interrupts
INT8–INT10. (with noise filters and interrupt
controller)
Circuit
Type
F
D
Pin
Number
1-2
38-43
(1-8)
D 32-37
(37-42)
D-1 13-20
(19-26)
E 24-31
(19-26)
D-1
D
10,11
3,4
44,21
(16-17)
(9-10)
Share
Pins
XTIN, XTOUT
TACAP
TACK
T1CAP0
T1OUT1
T1CK1
T1CAP1
TAOUT
T1CK0
T1OUT0
TXD
RXD
INT0–INT7
ADC0–ADC7
INT8–INT10
TBPWM
NOTE: Pin numbers shown in parentheses "( )" are for the 42-pin SDIP package.
1-6
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW
Table 1-1. S3C84E5/C84E9/P84E9 Pin Descriptions (Continued)
Pin
Name
INT0–INT10 I Input pins for external interrupt.
Pin
Type
Pin
Description
Alternatively used as general-purpose digital
input/output port 2,4.
Circuit
Type
Pin
Number
D-1 13-20, 4
10-11
(19-26)
Share
Pins
P2.0–P2.7
P4.0–P4.2
(10,16-17)
ADC0–ADC7 I Analog input pins for A/D converter module.
Alternatively used as general-purpose digital
E 24-31
P3.0–P3.7
(29-36)
input/output port 3.
AVREF, AVSS – A/D converter reference voltage and ground – 22, 23
–
(27, 28)
RxD I Serial data RxD pin for receive input and
transmit output (mode 0)
TxD O Serial data TxD pin for transmit output and
shift clock output (mode 0)
D 33
(38)
D 32
(37)
P1.4
P1.5
TACK I External clock input pins for timer A D 39(2) P0.6
TACAP I Capture input pins for timer A D 38(1) P0.7
TAOUT O Pulse width modulation output pins for timer A D 37(42) P1.0
BUZ O Buzzer output pin D 34(39) P1.3
TBPWM O Carrier frequency output pins for timer B D 3(9) P4.3
T1CK0 I External clock input pins for timer 1(0) D 36(41) P1.1
T1CAP0 I Capture input pins for timer 1(0) D 40(3) P0.5
T1OUT0 O Timer 1(0) 16-bit PWM mode output or
D 35(40) P1.2
counter match toggle output pins
T1CK1 I External clock input pins for timer 1(1) D 42(3) P0.3
T1CAP1 I Capture input pins for timer 1(1) D 43(5) P0.2
T1OUT1 O Timer 1(1) 16-bit PWM mode output or
D 41(4) P0.4
counter match toggle output pins
nRESET I System reset pin B 12(18) –
TEST I Pull-down resistor connected internally – 9(15) –
VDD, VSS – Power input pins – 5,6
–
(11,12)
XTIN, XTOUT I,O Subsystem oscillator pins – 1,2
P0.0, P0.1
(7,8)
Xin, Xout I,O Main oscillator pins – 7,8
–
(13,14)
NOTE: Pin numbers shown in parentheses "( )" are for the 42-pin SDIP package.
1-7
PRODUCT OVERVIEW S3C84E5/C84E9/P84E9
PIN CIRCUITS
V
DD
Pull-Up
Resistor
In
Schmitt Trigger
Figure 1-4. Pin Circuit Type B (nRESET)
Data
Output
Disable
Figure 1-5. Pin Circuit Type C
V
DD
P-Channel
N-Channel
Out
1-8
S3C84E5/C84E9/P84E9 PRODUCT OVERVIEW
V
DD
Pull-up
Enable
Data
Output
Pin Circuit
Type C
I/O
Disable
Figure 1-6. Pin Circuit Type D (P0.2-P0.7, P1, P4.3–P4.5)
V
DD
V
DD
Pull-up
Ext.INT
Input
Normal
Data
Output
Disable
Pin Circuit
Type C
Noise
Filter
Enable
I/O
Figure 1-7. Pin Circuit Type D-1 (P2, and P4.0–P4.2)
1-9
PRODUCT OVERVIEW S3C84E5/C84E9/P84E9
V
DD
Pull-up Resistor
Ω
(Typical Value: 47k
)
Pull-up
Enable
V
DD
Data
In/Out
Output
DIsable
Normal
Input
Analog
Input
Output Data
Output Disable
(Input Mode)
Digital Input
Figure 1-8. Pin Circuit Type E (P3)
V
DD
P-CH
N-CH
V
DD
Pull-up
enable
I/O
Alternative I/O Enable
XTin, XTout Oscillation circuit
Figure 1-9. Pin Circuit Type F (P0.0, P0.1)
1-10
S3C84E5/C84E9/P84E9 ADDRESS SPACES
2 ADDRESS SPACES
OVERVIEW
The S3C84E5/C84E9/P84E9 microcontroller has two types of address space:
— Internal program memory (ROM)
— Internal register file (RAM)
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data
between the CPU and the register file.
The S3C84E5/C84E9/P84E9 has an internal 16/32-Kbyte mask-programmable ROM / 32-Kbyte OTP ROM and 528byte RAM.
2-1
ADDRESS SPACES S3C84E5/C84E9/P84E9
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program codes or table data. The S3C84E5/84E9 has 16Kbytes and 32Kbytes of
internal mask programmable program memory. The program memory address range is therefore 0H–3FFFH and 0H7FFFH (see Figure 2-1).
The first 256 bytes of the ROM (0H-0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you use the vector address area to store a program code,
be careful not to overwrite the vector addresses stored in these locations.
The ROM address at which a program execution starts after a reset is 0100H.
(Decimal)
32,767
(Decimal)
16,383
255
32-KByte
16-KByte
Interrupt
Vector Area
(HEX)
7FFFH (S3C84E9/P84E9)
(HEX)
3FFFH (S3C84E5)
0FFH
0H0
Figure 2-1. Program Memory Address Space
2-2
S3C84E5/C84E9/P84E9 ADDRESS SPACES
REGISTER ARCHITECTURE
In the S3C84E5/C84E9/P84E9 implementation, the upper 64-byte area of register files is expanded two 64-byte
areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0
and bank 1), and the lower 32-byte area is a single 32-byte common area. set 2 is logically expanded 2 separately
addressable register pages, page 0–page 1.
In case of S3C84E5/C84E9/P84E9 the total number of addressable 8-bit registers is 590. Of these 590 registers, 16
bytes are for CPU and system control registers, 46 bytes are for peripheral control and data registers, 16 bytes are
used as a shared working registers, and 512 registers are for general-purpose use.
You can always address set 1 register location, regardless of which of the 2 register pages is currently selected. The
set 1 locations, however, can only be addressed using direct addressing modes.
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various
addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP).
Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2–1.
Table 2-1. S3C84E5/C84E9/P84E9 Register Type Summary
Register Type Number of Bytes
General-purpose registers (including 16-byte common
working register area, expanded 2 separat ely addressable
register pages (1Page occupies 192-byte prime register
area and the 64-byte set 2 area)
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers
Total Addressable Bytes 590
528
16
46
2-3
ADDRESS SPACES S3C84E5/C84E9/P84E9
64
Bytes
FFH
32
Bytes
E0H
DFH
D0H
CFH
C0H
Set1
Bank 1
Bank 0
System and
Peripheral Control Registers
(Register Addressing Mode)
System and
Peripheral Control Registers
(Register Addressing Mode)
General Purpose Register
(Register Addressing Mode)
FFH
E0H
192
Bytes
Page 1
Page 0
FFH
(Indirect Register, Indexed
Mode, and Stack Operations)
C0H
BFH
00H
Page 0
Page 0
Set 2
General-Purpose
Data Registers
Page 0
Page 0
Page 0
Prime
Data Registers
(All Addressing Modes)
Page 0
Page 0
Page 0
Page 0
256
Bytes
Figure 2-2. Internal Register File Organization
2-4
S3C84E5/C84E9/P84E9 ADDRESS SPACES
Register Page Pointer (PP)
REGISTER PAGE POINTER (PP)
The S3C8-series architecture supports the logical expansion of the physical 512-byte internal register file (using an
8-bit data bus) into as many as 2 separately addressable register pages. Page addressing is controlled by the
register page pointer (PP, DFH). In the S3C84E5/C84E9/P84E9 microcontroller, a paged register file expansion is
implemented for data registers, and the register page pointer must be changed to addres s other pages.
After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
"0000", automatically selecting page 0 as the source and destination page for register addressing.
DFH ,Set 1, R/W
LSBMSB .7 .6 .5 .4 .3 .2 .1 .0
Destination register page selection bits:
0000 0000
NOTE:
Destination: Page 0
Destination: Page 1 Source: Page 10001 0001
A hardware reset operation writes the 4-bit destination and source values shown
above to the register page pointer. These values should be modified to other
pages.
Figure 2-3. Register Page Pointer (PP)
Source register page selection bits:
Source: Page 0
2-5
ADDRESS SPACES S3C84E5/C84E9/P84E9
F PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1)
LD PP,#00H ; Destination ← 0, Source ← 0
SRP #0C0H
LD R0,#0FFH ; Page 0 RAM clear starts
RAMCL0: CLR @R0
DJNZ R0,RAMCL0
CLR @R0 ; R0 = 00H
LD PP,#10H ; Destination ← 1, Source ← 0
LD R0,#0FFH ; Page 1 RAM clear starts
RAMCL1: CLR @R0
DJNZ R0,RAMCL1
CLR @R0 ; R0 = 00H
2-6
S3C84E5/C84E9/P84E9 ADDRESS SPACES
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank
1. The set register bank ins tructions, SB0 or SB1, are used to address one bank or the other. A hardware reset
operation always selects bank 0 addressing.
The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 64 mapped system and peripheral
control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte common working
register area (C0H–CFH). You can use the common working register area as a “scratch” area for data operations
being performed in other areas of the register file.
Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing (For more information about working
register addressing, please refer to Chapter 3, “Addressing Modes.”)
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another 64
bytes of register space. This expanded area of the register file is called set 2. For S3C84E5/C84E9/P84E9, the set 2
address range (C0H–FFH) is accessible on pages 0-1.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.
The set 2 register area is commonly used for stack operations.
2-7
ADDRESS SPACES S3C84E5/C84E9/P84E9
PRIME REGISTER SPACE
The lower 192 bytes (00H–BFH) of the S3C84E5/C84E9/P84E9's two 256-byte register pages is called prime
register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3,
"Addressing Modes.")
The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers
on pages 0, or 1 you must set the register page pointer (PP) to the appropriate source and destination values.
FFH
Bank 0
F0H
E0H
D0H
C0H
CPU and system control
General-purpose
Peripheral and I/O
Set 1
Bank 1
FFH
C0H
BFH
00H
Figure 2-4. Set 1, Set 2, Prime Area Register
Page 1
Page 0
Set 2
Page 0
Prime
Space
2-8
S3C84E5/C84E9/P84E9 ADDRESS SPACES
WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When
4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that
consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except for the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)
— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)
All the registers in an 8-byte working register slice have the same binary value for their five most significant address
bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set
2. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).
1 1 1 1 1 X X X
RP1 (Registers R8-R15)
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16byte working register block.
0 0 0 0 0 X X X
RP0 (Registers R0-R7)
Figure 2-5. 8-Byte Working Register Areas (Slices)
Slice 32
Slice 31
~ ~
Slice 2
Slice 1
FFH
F8H
F7H
F0H
Set 1
Only
CFH
C0H
10H
FH
8H
7H
0H
2-9
ADDRESS SPACES S3C84E5/C84E9/P84E9
USING THE REGISTER POINTERS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte
working register slices in the register file. After a reset, RP# point to the working register common area: RP0 points
to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
To change a register pointer value, you load a new value to RP0 and or RP1 using an SRP or LD instruction.
(see Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set
2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing
modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice
(see Figure 2-6). ). In some cases, it may be necessary to define working register areas in different (non-contiguous)
areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly
define the working register area to support program requirements.
F PROGRAMMING TIP — Setting the Register Pointers
SRP #70H ; RP0 ← 70H, RP1 ← 78H
SRP1 #48H ; RP0 ← no change, RP1 ← 48H,
SRP0 #0A0H ; RP0 ← 0A0H, RP1 ← no change
CLR RP0 ; RP0 ← 00H, RP1 ← no change
LD RP1,#0F8H ; RP0 ← no change, RP1 ← 0F8H
Register File
Contains 32
8-Byte Slices
0 0 0 0 1 X X X
RP1
0 0 0 0 0 X X X
RP0
8-Byte Slice
8-Byte Slice
Figure 2-6. Contiguous 16-Byte Working Register Block
FH (R15)
8H
7H
0H (R0)
16-Byte Contiguous
Working Register
block
2-10
S3C84E5/C84E9/P84E9 ADDRESS SPACES
F7H (R7)
8-Byte Slice
F0H (R0)
Register File
1 1 1 1 0 X X X
RP0
0 0 0 0 0 X X X 8-Byte Slice
RP1
Contains 32
8-Byte Slices
7H (R15)
0H (R8)
16-byte Noncontiguous working
register block
Figure 2-7. Non-Contiguous 16-Byte Working Register Block
F PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H
contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:
SRP0 #80H ; RP0 ← 80H
ADD R0,R1 ; R0 ← R0 + R1
ADC R0,R2 ; R0 ← R0 + R2 + C
ADC R0,R3 ; R0 ← R0 + R3 + C
ADC R0,R4 ; R0 ← R0 + R4 + C
ADC R0,R5 ; R0 ← R0 + R5 + C
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example
takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate
the sum of these registers, the following instruction sequence would have to be used:
ADD 80H,81H ; 80H ← (80H) + (81H)
ADC 80H,82H ; 80H ← (80H) + (82H) + C
ADC 80H,83H ; 80H ← (80H) + (83H) + C
ADC 80H,84H ; 80H ← (80H) + (84H) + C
ADC 80H,85H ; 80H ← (80H) + (85H) + C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
2-11
ADDRESS SPACES S3C84E5/C84E9/P84E9
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair,
you can access any location in the register file except for set 2. With working register addressing, you use a register
pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair,
the address of the first 8-bit register is always an even number and the address of the next register is always an odd
number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least
significant byte is always stored in the next (+1) odd-numbered register.
Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8-byte
working register space in the internal register file and a specific 8-bit register within that space.
MSB
Rn
LSB
Rn+1
n = Even address
Figure 2-8. 16-Bit Register Pair
2-12
S3C84E5/C84E9/P84E9 ADDRESS SPACES
Special-Purpose Registers
Bank 1 Bank 0
FFH
Control
Registers
E0H
System
D0H
C0H
BFH
RP1
Register
Pointers
RP0
Each register pointer (RP) can independently point
to one of the 24 8-byte "slices" of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).
Registers
CFH
General-Purpose Register
FFH
Set 2
C0H
Prime
Registers
NOTE:
00H
In the S3C84E5/C84E9/P84E9 microcontroller,
pages 0-1 are implemented. Pages 0-1
contain all of the addressable registers
in the internal register file.
Register Addressing Only
Can be pointed by Register Pointer
Figure 2-9. Register File Addressing
Page 0-1
All
Addressing
Modes
Page 0-1
Indirect Register,
Indexed Addressing
Modes
2-13
ADDRESS SPACES S3C84E5/C84E9/P84E9
FFH
COMMON WORKING REGISTER AREA (C0H–CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–
CFH, as the active 16-byte working register block:
RP0 → C0H–C7H
RP1 → C8H–CFH
This 16-byte address range is called common area. That is, locations in this area can be used as working registers
by operations that address any location on any page in the register file. Typically, these working registers serve as
temporary buffers for data operations between different pages.
Page 1
FFH
Set 1
FFH
Page 0
F0H
E0H
D0H
C0H
Following a hardware reset, register
pointers RP0 and RP1 point to the
common working register area,
locations C0H-CFH.
RP0 =
RP1 =
1 1 0 0 0 0 0 0
1 1 0 0 1 0 0 0
Figure 2-10. Common Working Register Area
C0H
BFH
00H
Page 0
~ ~
Prime
Space
Set 2
~
2-14
S3C84E5/C84E9/P84E9 ADDRESS SPACES
F PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Examples 1:
1. LD 0C2H,40H ; Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H
LD R2,40H ; R2 (C2H) ← the value in location 40H
Example 2:
ADD 0C3H,#45H ; Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H
ADD R3,#45H ; R3 (C3H) ← R3 + 45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a
register pointer serves as an addressing "window" that makes it possible for instructions to access working registers
very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working
register area, the address bits are concatenated in the following way to form a complete 8-bit address:
— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).
— The five high-order bits in the register pointer select an 8-byte slice of the register space.
— The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-11, the res ult of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as the
address stored in the register pointer remains unchanged, the three bits from the address will always point to an
address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three
low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
2-15
ADDRESS SPACES S3C84E5/C84E9/P84E9
RP0
RP1
Selects
RP0 or RP1
Address OPCODE
Register pointer
provides five
high-order bits
Figure 2-11. 4-Bit Working Register Addressing
RP0
0 1 1 1 0 0 0 0
0 1 1 1 0 1 1 0
Together they create an
8-bit register address
0 1 1 1 1 0 0 0
Selects RP0
Register
address
(76H)
0 1 1 0 1 1 1 0
4-bit address
provides three
low-order bits
RP1
R6
OPCODE
Instruction
'INC R6'
Figure 2-12. 4-Bit Working Register Addressing Example
2-16
S3C84E5/C84E9/P84E9 ADDRESS SPACES
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register
addressing.
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing. Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address. The
three low-order bits of the complete address are provided by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address
(1100B) specify 8-bit working register addressing. Bit 3 ("1") selects RP1 and the five high-order bits in RP1
(10101B) become the five high-order bits of the register address. The three low-order bits of the register address
(011) are provided by the three low-order bits of the 8-bit instruction address. The five -address bits from RP1 and the
three address bits from the instruction are concatenated to form the complete register address, 0ABH (10101011B).
RP0
These address
bits indicate 8-bit
working register
addressing
Selects
RP0 or RP1
Address
1 1 0 0
Register pointer
provides five
high-order bits
8-bit physical address
Three low-order bits
Figure 2-13. 8-Bit Working Register Addressing
RP1
8-bit logical
address
2-17
ADDRESS SPACES S3C84E5/C84E9/P84E9
RP0
0 1 1 0 0 0 0 0
1 1 0 0 1 0 1 1
Specifies working
register addressing
Figure 2-14. 8-Bit Working Register Addressing Example
Selects RP1
R11
8-bit address
form instruction
'LD R11, R2'
RP1
1 0 1 0 1 0 0 0
1 0 1 0 1 0 1 1
Register
address
(0ABH)
2-18
S3C84E5/C84E9/P84E9 ADDRESS SPACES
SYSTEM AND USER STACK
The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH
and POP instructions are used to control system stack operations. The S3C84E5/C84E9/P84E architecture
supports stack operations in the internal register file.
Stack Operations
Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved
to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the
PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their
original locations. The stack address value is always decreased by one before a push operation and increased by
one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as
shown in Figure 2-15.
High Address
PCL
PCL
Top of
stack
PCH
Top of
stack
PCH
Flags
Stack contents
after a call
instruction
Low Address
Stack contents
after an
interrupt
Figure 2-15. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register fi le as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL, SPH)
Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations. The
most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least significant
byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.
Because only internal memory space is implemented in the S3C84E5/C84E9/P84E, the SPL must be initialized to
an 8-bit value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register,
if necessary.
When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register
file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition
occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack
operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data
that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH"
instead of "00H".
2-19
ADDRESS SPACES S3C84E5/C84E9/P84E9
F PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP
instructions:
LD SPL,#0FFH ; SPL ← FFH
; (Normally, the SPL is set to 0FFH by the initialization
; routine)
•
•
•
PUSH PP ; Stack address 0FEH ← PP
PUSH RP0 ; Stack address 0FDH ← RP0
PUSH RP1 ; Stack address 0FCH ← RP1
PUSH R3 ; Stack address 0FBH ← R3
•
•
•
POP R3 ; R3 ← Stack address 0FBH
POP RP1 ; RP1 ← Stack address 0FCH
POP RP0 ; RP0 ← Stack address 0FDH
POP PP ; PP ← Stack address 0FEH
2-20
S3C84E5/C84E9/P84E9 ADDRESSING MODES
3 ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction. The seven addressing modes and their symbols are:
— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Indirect Address (IA)
— Relative Address (RA)
— Immediate (IM)
3-1
ADDRESSING MODES S3C84E5/C84E9/P84E9
REGISTER ADDRESSING MODE (R)
In Register addressing mode (R), the operand value is the content of a specified register or register pair
(see Figure 3-1).
Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory Register File
8-bit Register
File Address
One-Operand
Instruction
(Example)
Sample Instruction:
dst
OPCODE
Point to One
OPERAND
Register in Register
File
Value used in
Instruction Execution
DEC CNTR ; Where CNTR is the label of an 8-bit register address
4-bit
Working Register
Two-Operand
Instruction
(Example)
Sample Instruction:
Figure 3-1. Register Addressing
Program Memory
dst
OPCODE
src
MSB Point to
RP0 ot RP1
3 LSBs
Point to the
Working Register
(1 of 8)
Register File
RP0 or RP1
Selected
RP points
to start
of working
register
block
OPERAND
ADD R1, R2 ; Where R1 and R2 are registers in the currently
selected working register area.
Figure 3-2. Working Register Addressing
3-2
S3C84E5/C84E9/P84E9 ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to program
memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly
address another memory location. Please note, however, that you cannot access locations C0H–FFH in set 1 using
the Indirect Register addressing mode.
Program Memory Register File
8-bit Register
File Address
One-Operand
Instruction
(Example)
dst
OPCODE
Point to One
ADDRESS
Register in Register
File
Address of Operand
used by Instruction
Value used in
Instruction Execution
Sample Instruction:
RL @SHIFT ; Where SHIFT is the label of an 8-bit register address
OPERAND
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES S3C84E5/C84E9/P84E9
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory
Example
Instruction
References
Program
Memory
Sample Instructions:
CALL @RR2
JP @RR2
REGISTER
dst
OPCODE
Points to
Register Pair
Value used in
Instruction
PAIR
Program Memory
OPERAND
Figure 3-4. Indirect Register Addressing to Program Memory
16-Bit
Address
Points to
Program
Memory
3-4
S3C84E5/C84E9/P84E9 ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
MSB Points to
4-bit
Working
Register
Address
Program Memory
dst
OPCODE
src
RP0 or RP1
3 LSBs
Point to the
Working Register
(1 of 8)
RP0 or RP1
~ ~
ADDRESS
Selected
RP points
to start fo
working register
block
~ ~
Sample Instruction:
OR R3, @R6
Figure 3-5. Indirect Working Register Addressing to Register File
Value used in
Instruction
OPERAND
3-5
ADDRESSING MODES S3C84E5/C84E9/P84E9
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
MSB Points to
4-bit Working
Register Address
Example Instruction
References either
Program Memory or
Data Memory
Program Memory
dst
OPCODE
src
RP0 or RP1
Next 2-bit Point
to Working
Register Pair
(1 of 4)
LSB Selects
Value used in
Instruction
RP0 or RP1
Register
Pair
Program Memory
or
Data Memory
OPERAND
Selected
RP points
to start of
working
register
block
16-Bit
address
points to
program
memory
or data
memory
Sample Instructions:
LCD R5,@RR6 ; Program memory access
LDE R3,@RR14 ; External data memory access
LDE @RR4, R8 ; External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
S3C84E5/C84E9/P84E9 ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate
the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the
internal register file or in ex ternal memory. Please note, however, that you cannot access locations C0H–FFH in
set 1 using indexed addressing mode.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to
+127. This applies to external memory accesses only (see Figure 3-8.)
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in
a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see
Figure 3-9).
The only instruction that supports indexed addressing mode for the internal register file is the Load instruction (LD).
The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data
memory, when implemented.
Two-Operand
Instruction
Example
Sample Instruction:
LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value
Program Memory
Base Address
dst/src
OPCODE
x
Value used in
Instruction
+
3 LSBs
Point to One of the
Woking Register
(1 of 8)
Register File
RP0 or RP1
~ ~
OPERAND
~ ~
INDEX
Selected RP
points to
start of
working
register
block
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES S3C84E5/C84E9/P84E9
INDEXED ADDRESSING MODE (Continued)
Register File
MSB Points to
4-bit Working
Register Address
Program Memory
OFFSET
dst/src
OPCODE
x
RP0 or RP1
NEXT 2 Bits
Point to Working
Register Pair
(1 of 4)
LSB Selects
RP0 or RP1
~ ~
Register
Pair
Program Memory
or
Data Memory
Selected
RP points
to start of
working
register
block
16-Bit
address
added to
offset
+
8-Bits
16-Bits
16-Bits
OPERAND
Sample Instructions:
LDC R4, #04H[RR2] ; The values in the program address (RR2 + 04H)
are loaded into register R4.
LDE R4,#04H[RR2] ; Identical operation to LDC example, except that
external program memory is accessed.
Value used in
Instruction
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
S3C84E5/C84E9/P84E9 ADDRESSING MODES
Register File
; The values in the program address (RR2 + 1000H)
INDEXED ADDRESSING MODE (Continued)
MSB Points to
4-bit Working
Register Address
Program Memory
OFFSET
OFFSET
dst/src
OPCODE
src
RP0 or RP1
NEXT 2 Bits
Point to Working
Register Pair
LSB Selects
RP0 or RP1
~ ~
Register
Pair
Program Memory
or
Data Memory
Selected
RP points
to start of
working
register
block
16-Bit
address
added to
offset
+
16-Bits
16-Bits
16-Bits
Sample Instructions:
LDC R4, #1000H[RR2]
are loaded into register R4.
LDE R4,#1000H[RR2] ; Identical operation to LDC example, except that
external program memory is accessed.
OPERAND
Value used in
Instruction
Figure 3-9. Indexed Addressing to Program or Data Memory
3-9
ADDRESSING MODES S3C84E5/C84E9/P84E9
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load
operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Memory
Program Memory
Address
Used
Upper Address Byte
Lower Address Byte
dst/src
Sample Instructions:
LDC R5,1234H; The values in the program address (1234H)
LDE R5,1234H; Identical operation to LDC example, except that
"0" or "1"
OPCODE
are loaded into register R5.
external program memory is accessed.
LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
Figure 3-10. Direct Addressing for Load Instructions
3-10
S3C84E5/C84E9/P84E9 ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Memory
Address
Used
Upper Address Byte
Lower Address Byte
OPCODE
Sample Instructions:
JP C,JOB1 ; Where JOB1 is a 16-bit immediate address
CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES S3C84E5/C84E9/P84E9
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed
to be all zeros.
Program Memory
Next Instruction
LSB Must be Zero
Current
Instruction
Lower Address Byte
Upper Address Byte
Sample Instruction:
CALL #40H ; The 16-bit value in program memory addresses 40H
and 41H is the subroutine start address.
dst
OPCODE
Program Memory
Locations 0-255
Figure 3-12. Indirect Addressing
3-12
S3C84E5/C84E9/P84E9 ADDRESSING MODES
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a twos -complement signed displacement between – 128 and + 127 is specified in
the instruction. The displacement value is then added to the current PC value. The result is the address of the next
instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately
following the current instruction.
Several program control instructions use the Relative Addres s mode to perform conditional jumps. The instructions
that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
Program Memory
Next OPCODE
Program Memory
Address Used
Current
Displacement
Current Instruction
Sample Instructions:
JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128
OPCODE
PC Value
Signed
Displacement Value
+
Figure 3-13. Relative Addressing
3-13
ADDRESSING MODES S3C84E5/C84E9/P84E9
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand
field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate
addressing mode is useful for loading constant values into registers.
Program Memory
OPERAND
OPCODE
(The Operand value is in the instruction)
Sample Instruction:
LD R0,#0AAH
Figure 3-14. Immediate Addressing
3-14
S3C84E5/C84E9/P84E9 CONTROL REGISTER
4 CONTROL REGISTERS
OVERVIEW
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in Part
II of this manual.
The locations and read/write characteristics of all mapped registers in the S3C84E5/C84E9/P84E9 register file are
listed in Table 4-1. The hardware Reset value for each mapped register is described in Chapter 8, RESET and
Power-Down."
Table 4-1. Set 1 Registers
Register Name Mnemonic Decimal Hex R/W
Timer B control register TBCON 208 D0H R/W
Timer B data register (High Byte) TBDATAH 209 D1H R/W
Timer B data register (Low Byte) TBDATAL 210 D2H R/W
Basic timer control register BTCON 211 D3H R/W
Clock control register CLKCON 212 D4H R/W
System flags register FLAGS 213 D5H R/W
Register pointer 0 RP0 214 D6H R/W
Register pointer 1 RP1 215 D7H R/W
Stack pointer (High Byte) SPH 216 D8H R/W
Stack pointer (Low Byte) SPL 217 D9H R/W
Instruction pointer (High Byte) IPH 218 DAH R/W
Instruction pointer (Low Byte) IPL 219 DBH R/W
Interrupt request register IRQ 220 DCH R
Interrupt mask register IMR 221 DDH R/W
System mode register SYM 222 DEH R/W
Register page pointer PP 223 DFH R/W
4-1
CONTROL REGISTERS S3C84E5/C84E9/P84E9
Table 4-2. Set 1, Bank 0 Registers
Register Name Mnemonic Decimal Hex R/W
Port 0 data register P0 224 E0H R/W
Port 1 data register P1 225 E1H R/W
Port 2 data register P2 226 E2H R/W
Port 3 data register P3 227 E3H R/W
Port 4 data register P4 228 E4H R/W
STOP control register STPCON 229 E5H R/W
Port 0 control register (High Byte) P0CONH 230 E6H R/W
Port 0 control register (Low Byte) P0CONL 231 E7H R/W
Port 1 control register (High Byte) P1CONH 232 E8H R/W
Port 1 control register (Low Byte) P1CONL 233 E9H R/W
Port 2 control register (High Byte) P2CONH 234 EAH R/W
Port 2 control register (Low Byte) P2CONL 235 EBH R/W
Port 2 interrupt control register P2INT 236 ECH R/W
Port 2 interrupt/pending register P2INTPND 237 EDH R/W
Port 3 control register (High Byte) P3CONH 238 EEH R/W
Port 3 control register (Low Byte) P3CONL 239 EFH R/W
Port 4 control register (High Byte) P4CONH 240 F0H R/W
Port 4 control register (Low Byte) P4CONL 241 F1H R/W
Port 4 interrupt control register P4INT 242 F2H R/W
Port 4 interrupt/pending register P4INTPND 243 F3H R/W
UART pending register UARTPND 244 F4H R/W
UART data register UDATA 245 F5H R/W
UART control register UARTCON 246 F6H R/W
A/D converter control register ADCON 247 F7H R/W
A/D converter data register (High Byte) ADDATAH 248 F8H R
A/D converter data register (Low Byte) ADDATAL 249 F9H R
Watch timer control register WTCON 250 FAH R/W
Oscillator control register OSCCON 251 FBH R/W
Location FCH is factory use only
Basic timer counter register BTCNT 253 FDH R
Location FEH is not mapped
Interrupt priority register IPR 255 FFH R/W
4-2
S3C84E5/C84E9/P84E9 CONTROL REGISTER
Table 4-3. Set 1, Bank 1 Registers
Register Name Mnemonic Decimal Hex R/W
Timer A, Timer 1 interrupt pending register TINTPND 224 E0H R/W
Timer A control register TACON 225 E1H R/W
Timer A data register TADATA 226 E2H R/W
Timer A counter register TACNT 227 E3H R
Timer 1(0) data register (High Byte) T1DATAH0 228 E4H R/W
Timer 1(0) data register (Low Byte) T1DATAL0 229 E5H R/W
Timer 1(1) data register (High Byte) T1DATAH1 230 E6H R/W
Timer 1(1) data register (Low Byte) T1DATAL1 231 E7H R/W
Timer 1(0) control register T1CON0 232 E8H R/W
Timer 1(1) control register T1CON1 233 E9H R/W
Timer 1(0) counter register (High Byte) T1CNTH0 234 EAH R
Timer 1(0) counter register (Low Byte) T1CNTL0 235 EBH R
Timer 1(1) counter register (High Byte) T1CNTH1 236 ECH R
Timer 1(1) counter register (Low Byte) T1CNTL1 237 EDH R
UART baud rate data register (High Byte) BRDATAH 238 EEH R/W
UART baud rate data register (Low Byte) BRDATAL 239 EFH R/W
Location F0H – FFH are not mapped
4-3
CONTROL REGISTERS S3C84E5/C84E9/P84E9
Bit number(s) that is/are appended to
the register name for bit addressing
Register nameRegister ID
FLAGS -
Bit Identifier
RESET
Read/Write
Bit Addressing
Mode
.7 Carry Flag (C)
.6
System Flags Register
.7 .6 .5
Value
R/W
Register addressing mode only
0 Operation does not generate a carry or borrow condition
0 Operation generates carry-out or borrow into high-order bit 7
Zero Flag (Z)
0 Operation result is a non-zero value
0 Operation result is zero
Name of individual
bit or related bits
Register address
(hexadecimal)
D5H
.4 .3 .2
x
x
R/WxR/WxR/WxR/WxR/W
Register location
in the internal
register file
Set 1
.1 .0
0
R
0
R/W
.5
R = Read-only
W = Write-only
R/W = Read/write
'-' = Not used
Type of addressing
that must be used to
address the bit
(1-bit, 4-bit, or 8-bit)
Sign Flag (S)
0 Operation generates positive number (MSB = "0")
0 Operation generates negative number (MSB = "1")
Description of the
effect of specific
bit settings
RESET
'-' = Not used
'x' = Undetermined value
'0' = Logic zero
'1' = Logic one
Figure 4-1. Register Description Format
value notation:
Bit number:
MSB = Bit 7
LSB = Bit 0
4-4
S3C84E5/C84E9/P84E9 CONTROL REGISTER
ADCON — A/D Converter Control Register F7H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write – R/W R/W R/W R R/W R/W R/W
Addressing Mode Register addressing mode only
.7 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.6–.4 A/D Input Pin Selection Bits
0 0 0 ADC0
0 0 1 ADC1
0 1 0 ADC2
0 1 1 ADC3
1 0 0 ADC4
1 0 1 ADC5
1 1 0 ADC6
1 1 1 ADC7
.3 End-of-Conversion Bit (Read-only)
0 A/D conversion operation is in progress
1 A/D conversion operation is complete
.2–.1 Clock Source Selection Bits
0 0 fxx/16
0 1 fxx/8
1 0 fxx/4
1 1 fxx
.0 Start or Enable Bit
0 Disable operation
1 Start operation
4-5
CONTROL REGISTERS S3C84E5/C84E9/P84E9
BTCON — Basic Timer Control Register D3H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Watchdog Timer Function Disable Code (for System Reset)
1 0 1 0 Disable watchdog timer function
Other Values Enable watchdog timer function
.3–.2 Basic Timer Input Clock Selection Bits
0 0
fxx/4096
0 1 fxx/1024
1 0 fxx/128
(3)
1 1 fxx/1 (Not used)
.1
Basic Timer Counter Clear Bit
(1)
0 No effect
1 Clear the basic timer counter value
.0
Clock Frequency Divider Clear Bit for Basic Timer
(2)
0 No effect
1 Clear both clock frequency dividers
NOTES:
1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write
operation, the BTCON.1 value is automatically cleared to “0”.
2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the
write operation, the BTCON.0 value is automatically cleared to "0".
3. The fxx is selected clock for system (main OSC. or sub OSC.).
4-6
S3C84E5/C84E9/P84E9 CONTROL REGISTER
CLKCON — System Clock Control Register D4H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write – – – R/W R/W – – –
Addressing Mode Register addressing mode only
.7–.5 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.4–.3
0 0 fxx/16
0 1 fxx/8
1 0 fxx/2
1 1 fxx/1 (non-divided)
CPU Clock (System Clock) Selection Bits
(note)
.2–.0 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load
the appropriate values to CLKCON.3 and CLKCON.4.
4-7
CONTROL REGISTERS S3C84E5/C84E9/P84E9
FLAGS — System Flags Register D5H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value x x x x x x 0 0
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Addressing Mode Register addressing mode only
.7 Carry Flag (C)
0 Operation does not generate a carry or underflow condition
1 Operation generates a carry-out or underflow into high-order bit 7
.6 Zero Flag (Z)
0 Operation result is a non-zero value
1 Operation result is zero
.5 Sign Flag (S)
0 Operation generates a positive number (MSB = "0")
1 Operation generates a negative number (MSB = "1")
.4 Overflow Flag (V)
0 Operation result is ≤ +127 or ≥ –128
1 Operation result is > +127 or < –128
.3 Decimal Adjust Flag (D)
0 Add operation completed
1 Subtraction operation completed
.2 Half-Carry Flag (H)
0 No carry -out of bit 3 or no underflow into bit 3 by addition or subtraction
1 Addition generated carry -out of bit 3 or subtraction generated underflow into bit 3
.1 Fast Interrupt Status Flag (FIS)
0 Interrupt return (IRET) in progress (when read)
1 Fast interrupt service routine in progress (when read)
.0 Bank Address Selection Flag (BA)
0 Bank 0 is selected
1 Bank 1 is selected
4-8
S3C84E5/C84E9/P84E9 CONTROL REGISTER
IMR — Interrupt Mask Register DDH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value x x x x x x x x
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 Interrupt Level 7 (IRQ7) Enable Bit
0 Disable (mask)
1 Enable (un-mask)
.6 Interrupt Level 6 (IRQ6) Enable Bit
0 Disable (mask)
1 Enable (un-mask)
.5 Interrupt Level 5 (IRQ5) Enable Bit
0 Disable (mask)
1 Enable (un-mask)
.4 Interrupt Level 4 (IRQ4) Enable Bit
0 Disable (mask)
1 Enable (un-mask)
.3 Interrupt Level 3 (IRQ3) Enable Bit
0 Disable (mask)
1 Enable (un-mask)
.2 Interrupt Level 2 (IRQ2) Enable Bit
0 Disable (mask)
1 Enable (un-mask)
.1 Interrupt Level 1 (IRQ1) Enable Bit
0 Disable (mask)
1 Enable (un-mask)
.0 Interrupt Level 0 (IRQ0) Enable Bit
0 Disable (mask)
1 Enable (un-mask)
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.
4-9
CONTROL REGISTERS S3C84E5/C84E9/P84E9
IPH — Instruction Pointer (High Byte) DAH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value x x x x x x x x
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Instruction Pointer Address (High Byte)
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).
IPL — Instruction Pointer (Low Byte) DBH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value x x x x x x x x
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Instruction Pointer Address (Low Byte)
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).
4-10
S3C84E5/C84E9/P84E9 CONTROL REGISTER
IPR — Interrupt Priority Register FFH Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value x x x x x x x x
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C
0 0 0 Group priority undefined
0 0 1 B > C > A
0 1 0 A > B > C
0 1 1 B > A > C
1 0 0 C > A > B
1 0 1 C > B > A
1 1 0 A > C > B
1 1 1 Group priority undefined
.6 Interrupt Subgroup C Priority Control Bit
0 IRQ6 > IRQ7
1 IRQ7 > IRQ6
.5 Interrupt Group C Priority Control Bit
0 IRQ5 > (IRQ6, IRQ7)
1 (IRQ6, IRQ7) > IRQ5
.3 Interrupt Subgroup B Priority Control Bit
0 IRQ3 > IRQ4
1 IRQ4 > IRQ3
.2 Interrupt Group B Priority Control Bit
0 IRQ2 > (IRQ3, IRQ4)
1 (IRQ3, IRQ4) > IRQ2
.0 Interrupt Group A Priority Control Bit
0 IRQ0 > IRQ1
1 IRQ1 > IRQ0
4-11
CONTROL REGISTERS S3C84E5/C84E9/P84E9
IRQ — Interrupt Request Register DCH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
Addressing Mode Register addressing mode only
.7 Interrupt Level 7 (IRQ7) Request Pending Bit
0 Not pending
1 Pending
.6 Interrupt Level 6 (IRQ6) Request Pending Bit
0 Not pending
1 Pending
.5 Interrupt Level 5 (IRQ5) Request Pending Bit
0 Not pending
1 Pending
.4 Interrupt Level 4 (IRQ4) Reque st Pending Bit
0 Not pending
1 Pending
.3 Interrupt Level 3 (IRQ3) Request Pending Bit
0 Not pending
1 Pending
.2 Interrupt Level 2 (IRQ2) Request Pending Bit
0 Not pending
1 Pending
.1 Interrupt Level 1 (IRQ1) Request Pending Bit
0 Not pending
1 Pending
.0 Interrupt Level 0 (IRQ0) Request Pending Bit
0 Not pending
1 Pending
4-12
S3C84E5/C84E9/P84E9 CONTROL REGISTER
OSCCON — Oscillator Control Register FBH Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write – – – R/W R/W R/W – R/W
Addressing Mode Register addressing mode only
.7–.5 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.4 Sub-system Oscillator Driving Ability Control Bit
0 Strong driving ability
1 Normal driving ability
.3 Main System Oscillator Control Bit
0 Main System Oscillator RUN
1 Main System Oscillator STOP
.2 Sub System Oscillator Control Bit
0 Sub system oscillator RUN
1 Sub system oscillator STOP
.1 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.0 System Clock Selection Bit
0 Main oscillator select
1 Subsystem oscillator select
4-13
CONTROL REGISTERS S3C84E5/C84E9/P84E9
P0CONH — Port 0 Control Register (High Byte) E6H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P0.7/TACAP Configuration Bits
0 0 Input mode with pull-up; TACAP input
0 1 Input mode; TACAP input
1 X Push-pull output mode
.5–.4 P0.6/TACK Configuration Bits
0 0 Input mode with pull-up; TACK input
0 1 Input mode; TACK input
1 X Push-pull output mode
.3–.2 P0.5/T1CAP0 Configuration Bits
0 0 Input mode with pull-up; T1CAP0 input
0 1 Input mode; T1CAP0 input
1 X Push-pull output mode
.1–.0 P0.4/T1OUT1 Configura tion Bits
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: T1OUT1 output
4-14
S3C84E5/C84E9/P84E9 CONTROL REGISTER
P0CONL — Port 0 Control Register (Low Byte) E7H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 1 .0
Reset Value 0 0 0 0 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P0.3/T1CK1 Configuration Bits
0 0 Input mode with pull-up; T1CK1 input
0 1 Input mode; T1CK1 input
1 X Push-pull output mode
.5–.4 P0.2/T1CAP1 Configuration Bits
0 0 Input mode with pull-up; T1CAP1 input
0 1 Input mode; T1CAP1 input
1 X Push-pull output mode
.3–.2 P0.1/XTout Configuration Bits
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: Sub oscillator output (XTout)
.1–.0 P0.0/XTin Configuration Bits
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: Sub oscillator input (XTin)
4-15
CONTROL REGISTERS S3C84E5/C84E9/P84E9
P1CONH — Port 1 Control Register (High Byte) E8H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write – – – – R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.3–.2 P1.5/TXD Configuration Bits
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: TXD output
.1–.0 P1.4/RXD Configuration Bits
0 0 Input mode with pull-up; RXD input
0 1 Input mode; RXD input
1 0 Push-pull output mode
1 1 Alternative function mode: RXD output
4-16
S3C84E5/C84E9/P84E9 CONTROL REGISTER
P1CONL — Port 1 Control Register (Low Byte) E9H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P1.3/BZOUT Configuration Bits
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: BZOUT output
.5–.4 P1.2/T1OUT0 Configuration Bits
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: T1OUT0 output
.3–.2 P1.1/T1CK0 Configuration Bits
0 0 Input mode with pull-up; T1CK0 input
0 1 Input mode; T1CK0 input
1 X Push-pull output mode
.1–.0 P1.0/TAOUT Configuration Bits
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: TAOUT output
4-17
CONTROL REGISTERS S3C84E5/C84E9/P84E9
P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P2.7/INT7
0 0 Input mode with pull-up; falling edge interrupt (INT7)
0 1 Input mode; falling edge interrupt (INT7)
1 0 Input mode; rising edge interrupt (INT7)
1 1 Push-pull output mode
.5-.4 P2.6/ INT6
0 0 Input mode with pull-up; falling edge interrupt (INT6)
0 1 Input mode; falling edge interrupt (INT6)
1 0 Input mode; rising edge interrupt (INT6)
1 1 Push-pull output mode
.3–.2 P2.5/ INT5
0 0 Input mode with pull-up; falling edge interrupt (INT5)
0 1 Input mode; falling edge interrupt (INT5)
1 0 Input mode; rising edge interrupt (INT5)
1 1 Push-pull output mode
.1–.0 P2.4/INT4
0 0 Input mode with pull-up; falling edge interrupt (INT4)
0 1 Input mode; falling edge interrupt (INT4)
1 0 Input mode; rising edge interrupt (INT4)
1 1 Push-pull output mode
4-18
S3C84E5/C84E9/P84E9 CONTROL REGISTER
P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P2.3/INT3
0 0 Input mode with pull-up; falling edge interrupt (INT3)
0 1 Input mode; falling edge interrupt (INT3)
1 0 Input mode; rising edge interrupt (INT3)
1 1 Push-pull output mode
.5–.4 P2.2/INT2
0 0 Input mode with pull-up; falling edge interrupt (INT2)
0 1 Input mode; falling edge interrupt (INT2)
1 0 Input mode; rising edge interrupt (INT2)
1 1 Push-pull output mode
.3–.2 P2.1/INT1
0 0 Input mode with pull-up; falling edge interrupt (INT1)
0 1 Input mode; falling edge interrupt (INT1)
1 0 Input mode; rising edge interrupt (INT1)
1 1 Push-pull output mode
.1–.0 P2.0/INT0
0 0 Input mode with pull-up; falling edge interrupt (INT0)
0 1 Input mode; falling edge interrupt (INT0)
1 0 Input mode; rising edge interrupt (INT0)
1 1 Push-pull output mode
4-19
CONTROL REGISTERS S3C84E5/C84E9/P84E9
P2INT — Port 2 Interrupt Control Register ECH Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P2.7 External Interrupt (INT7) Enable Bit
0 Disable interrupt
1 Enable interrupt
.6 P2.6 External Interrupt (INT6) Enable Bit
0 Disable interrupt
1 Enable interrupt
.5 P2.5 External Interrupt (INT5) Enable Bit
0 Disable interrupt
1 Enable interrupt
.4 P2.4 External Interrupt (INT4) Enable Bit
0 Disable interrupt
1 Enable interrupt
.3 P2.3 External Interrupt (INT3) Enable Bit
0 Disable interrupt
1 Enable interrupt
.2 P2.2 External Interrupt (INT2) Enable Bit
0 Disable interrupt
1 Enable interrupt
.1 P2.1 External Interrupt (INT1) Enable Bit
0 Disable interrupt
1 Enable interrupt
.0 P2.0 External Interrupt (INT0) Enable Bit
0 Disable interrupt
1 Enable interrupt
4-20
S3C84E5/C84E9/P84E9 CONTROL REGISTER
P2INTPND — Port 2 Interrupt Pending Register EDH Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P2.7/PND7 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.6 P2.6/PND6 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.5 P2.5/PND5 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.4 P2.4/PND4 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.3 P2.3/PND3 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.2 P2.2/PND2 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.1 P2.1/PND1 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.0 P2.0/PND0 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
4-21
CONTROL REGISTERS S3C84E5/C84E9/P84E9
P3CONH — Port 3 Control Register (High Byte) EEH Set 1, Bank 0
Bit Identifi er .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P3.7/ADC7
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: ADC7 input
.5–.4 P3.6/ADC6
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: ADC6 input
.3–.2 P3.5/ADC5
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: ADC5 input
.1–.0 P3.4/ADC4
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: ADC4 input
4-22
S3C84E5/C84E9/P84E9 CONTROL REGISTER
P3CONL — Port 3 Control Register (Low Byte) EFH Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P3.3/ADC3
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: ADC3 input
.5–.4 P3.2/ADC2
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: ADC2 input
.3–.3 P3.1/ADC1
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: ADC1 input
.1–.0 P3.0/ADC0
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: ADC0 input
4-23
CONTROL REGISTERS S3C84E5/C84E9/P84E9
P4CONH — Port 4 Control Register (High Byte) F0H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write – – – – R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.3–.2 P4.5
0 0 Input mode with pull-up
0 1 Input mode
1 X Push-pull output mode
.1–.0 P4.4
0 0 Input mode with pull-up
0 1 Input mode
1 X Push-pull output mode
4-24
S3C84E5/C84E9/P84E9 CONTROL REGISTER
P4CONL — Port 4 Control Register (Low Byte) F1H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.6 P4.3/TBPWM
0 0 Input mode with pull-up
0 1 Input mode
1 0 Push-pull output mode
1 1 Alternative function mode: TBPWM output
.5–.4 P4.2/INT10
0 0 Input mode with pull-up; falling edge interrupt (INT10)
0 1 Input mode; falling edge interrupt (INT10)
1 0 Input mode; rising edge interrupt (INT10)
1 1 Push-pull output mode
.3–.2 P4.1/INT9
0 0 Input mode with pull-up; falling edge interrupt (INT9)
0 1 Input mode; falling edge interrupt (INT9)
1 0 Input mode; rising edge interrupt (INT9)
1 1 Push-pull output mode
.1–.0 P4.0/INT8
0 0 Input mode with pull-up; falling edge interrupt (INT8)
0 1 Input mode; falling edge interrupt (INT8)
1 0 Input mode; rising edge interrupt (INT8)
1 1 Push-pull output mode
4-25
CONTROL REGISTERS S3C84E5/C84E9/P84E9
P4INT — Port 4 Interrupt Control Register F2H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write – – – – – R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.3 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.2 P4.2 External Interrupt (INT10) Enable Bit
0 Disable interrupt
1 Enable interrupt
.1 P4.1 External Interrupt (INT9) Enable Bit
0 Disable interrupt
1 Enable interrupt
.0 P4.0 External Interrupt (INT8) Enable Bit
0 Disable interrupt
1 Enable interrupt
4-26
S3C84E5/C84E9/P84E9 CONTROL REGISTER
P4INTPND — Port 4 Interrupt Pending Register F3H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write – – – – – R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.3 Not used for the S3C84E5/C84E9/P84E9 (must keep always 0)
.2 P4.2/PND10 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.1 P4.1/PND9 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
.0 P4.0/PND8 Interrupt Pending Bit
0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending
4-27
CONTROL REGISTERS S3C84E5/C84E9/P84E9
PP — Register Page Pointer DFH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Destination Register Page Selection Bits
0 0 0 0 Destination: page 0
0 0 0 1 Destination: page 1
Other values Don’t care
.3–.0 Source Register Page Selection Bits
0 0 0 0 Source: page 0
0 0 0 1 Source: page 1
Other values Don’t care
NOTE: In the S3C84E5/C84E9/P84E9 microcontroller, the internal register file is configured as two pages (Pages 0-1).
The pages 0-1 are used for the general-purpose register file and data register.
4-28
S3C84E5/C84E9/P84E9 CONTROL REGISTER
RP0 — Register Pointer 0 D6H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 1 1 0 0 0 – – –
Read/Write R/W R/W R/W R/W R/W – – –
Addressing Mode Register addressing only
.7–.3 Register Pointer 0 Address Value
Register pointer 0 can independently point to one of the 256-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select two
8-byte register slices at one time as active working register space. After a reset, RP0
points to address C0H in register set 1, selecting the 8-byte working register slice
C0H–C7H.
.2–.0 Not used for the S3C84E5/C84E9/P84E9
RP1 — Register Pointer 1 D7H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 1 1 0 0 1 – – –
Read/Write R/W R/W R/W R/W R/W – – –
Addressing Mode Register addressing only
.7–.3 Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 256-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select two
8-byte register slices at one time as active working register space. After a reset, RP1
points to address C8H in register set 1, selecting the 8-byte working register slice
C8H–CFH.
.2–.0 Not used for the S3C84E5/C84E9/P84E9
4-29
CONTROL REGISTERS S3C84E5/C84E9/P84E9
SPH — Stack Pointer (High Byte) D8H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value x x x x x x x x
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Stack Pointer Address (High Byte)
The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer
address (SP15–SP8). The lower byte of the stack pointer value is located in register
SPL (D9H). The SP value is undefined following a reset.
SPL — Stack Pointer (Low Byte) D9H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value x x x x x x x x
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Stack Pointer Address (Low Byte)
The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer
address (SP7–SP0). The upper byte of the stack pointer value is located in register
SPH (D8H). The SP value is undefined following a reset.
4-30
S3C84E5/C84E9/P84E9 CONTROL REGISTER
STPCON — Stop Control Register E5H Set 1, Bank 0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 STOP Control Bits
1 0 1 0 0 1 0 1 Enable stop instruction
Other values Disable stop instruction
NOTE: Before execute the STOP instruction, You must set this STPCON register as “10100101b”. Otherwise the STOP
instruction will not be executed.
4-31
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