SAMSUNG S3C44B0X User Manual
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S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
INTRODUCTION
SAMSUNG's S3C44B0X 16/32-bit RISC microprocessor is designed to provide a cost-effective and high performance
micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C44B0X
also provides the following: 8KB cache, optional internal SRAM, LCD controller, 2-channel UART with handshake, 4channel DMA, System manager (chip select logic, FP/ EDO/SDRAM controller), 5-channel timers with PWM, I/O
ports, RTC, 8-channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, Sync. SIO interface and PLL for clock.
The S3C44B0X was developed using a ARM7TDMI core, 0.25 um CMOS standard cells, and a memory compiler. Its
low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive
applications. Also S3C44B0X adopts a new bus architecture, SAMBA II (SAMSUNG ARM CPU embedded
Microcontroller Bus Architecture).
An outstanding feature of the S3C44B0X is its CPU core, a 16/32-bit ARM7TDMI RISC processor (66MHz) designed
by Advanced RISC Machines, Ltd. The architectural enhancements of ARM7TDMI include the Thumb decompressor, an on-chip ICE breaker debug support, and a 32-bit hardware multiplier.
By providing a complete set of common system peripherals, the S3C44B0X minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in this
document are as follows:
• 2.5V Static ARM7TDMI CPU core with 8KB cache . (SAMBA II bus architecture up to 66MHz)
• External memory controller. (FP/EDO/SDRAM Control, Chip Select logic)
• LCD controller (up to 256 color DSTN) with 1-ch LCD-dedicated DMA.
• 2-ch general DMAs / 2-ch peripheral DMAs with external request pins
• 2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO
• 1-ch multi-master IIC-BUS controller
• 1-ch IIS-BUS controller
• 5-ch PWM timers & 1-ch internal timer
• Watch Dog Timer
• 71 general purpose I/O ports / 8-ch external interrupt source
• Power control: Normal, Slow, Idle, and Stop mode
• 8-ch 10-bit ADC.
• RTC with calendar function.
• On-chip clock generator with PLL.
1-1
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
FEATURES
Architecture
• Integrated system for hand-held devices and
general embedded applications.
• 16/32-Bit RISC architecture and powerful
instruction set with ARM7TDMI CPU core.
• Thumb de-compressor maximizes code density
while maintaining performance.
• On-chip ICEbreaker debug support with JTAG-
based debugging solution.
• 32x8 bit hardware multiplier.
• New bus architecture to implement Low-Power
SAMBA II(SAMSUNG's ARM CPU embedded
Micro-controller Bus Architecture).
System Manager
• Little/Big endian support.
• Address space: 32Mbytes per each bank. (Total
256Mbyte)
• Supports programmable 8/16/32-bit data bus
width for each bank.
• Fixed bank start address and programmable bank
size for 7 banks.
• Programmable bank start address and bank size
for one bank.
• 8 memory banks.
- 6 memory banks for ROM, SRAM etc.
- 2 memory banks for ROM/SRAM/DRAM(Fast
Page, EDO, and Synchronous DRAM)
• Fully Programmable access cycles for all
memory banks.
• Supports external wait signal to expend the bus
cycle.
• Supports self-refresh mode in DRAM/SDRAM for
power-down.
• Supports asymmetric/symmetric address of
DRAM.
Cache Memory & internal SRAM
• 4-way set associative ID(Unified)-cache with
8Kbyte.
• The 0/4/8 Kbytes internal SRAM using unused
cache memory.
• Pseudo LRU(Least Recently Used) Replace
Algorithm.
• Write through policy to maintain the coherence
between main memory and cache content.
• Write buffer with four depth.
• Request data first fill technique when cache miss
occurs.
Clock & Power Manager
• Low power
• The on-chip PLL makes the clock for operating
MCU at maximum 66MHz.
• Clock can be fed selectively to each function
block by software.
• Power mode: Normal, Slow, Idle and Stop mode.
Normal mode: Normal operating mode.
Slow mode: Low frequency clock without PLL
Idle mode: Stop the clock for only CPU
Stop mode: All clocks are stopped
• Wake up by EINT[7:0] or RTC alarm interrupt from
Stop mode.
Interrupt Controller
• 30 Interrupt sources
( Watch-dog timer, 6 Timer, 6 UART, 8 External
interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO )
• Vectored IRQ interrupt mode to reduce interrupt
latency.
• Level/edge mode on the external interrupt sources
• Programmable polarity of edge and level
• Supports FIQ (Fast Interrupt request) for very
urgent interrupt request
FEATURES (Continued)
1-2
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Timer with PWM (Pulse Width Modulation)
• 5-ch 16-bit Timer with PWM / 1-ch 16-bit internal
timer with DMA-based or interrupt-based
operation
• Programmable duty cycle, frequency, and polarity
• Dead-zone generation.
• Supports external clock source.
RTC (Real Time Clock)
• Full clock feature: msec, sec, min, hour, day,
week, month, year.
• 32.768 KHz operation.
• Alarm interrupt for CPU wake-up.
• Time tick interrupt
General purpose input/output ports
• 8 external interrupt ports
• 71 multiplexed input/output ports
DMA Controller
• 2 channel general purpose Direct Memory Access
controller without CPU intervention.
• 2 channel Bridge DMA (peripheral DMA)
controller.
• Support IO to memory, memory to IO, IO to IO
with the Bridge DMA which has 6 type's DMA
requestor: Software, 4 internal function blocks
(UART, SIO, Timer, IIS), and External pins.
• Programmable priority order between DMAs (fixed
or round-robin mode)
• Burst transfer mode to enhance the transfer rate
on the FPDRAM, EDODRAM and SDRAM.
• Supports fly-by mode on the memory to external
device and external device to memory transfer
mode
A/D Converter
• 8-ch multiplexed ADC.
• Max. 100KSPS/10-bit.
UART
• 2-channel UART with DMA-based or interrupt-
based operation
• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit/receive
• Supports H/W handshaking during
transmit/receive
• Programmable baud rate
• Supports IrDA 1.0 (115.2kbps)
• Loop back mode for testing
• Each channel have two internal 32-byte FIFO for
Rx and Tx.
LCD Controller
• Supports color/monochrome/gray LCD panel
• Supports single scan and dual scan displays
• Supports virtual screen function
• System memory is used as display memory
• Dedicated DMA for fetching image data from
system memory
• Programmable screen size
• Gray level: 16 gray levels
• 256 Color levels
1-3
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
FEATURES (Continued)
Watchdog Timer
• 16-bit Watchdog Timer
• Interrupt request or system reset at time-out
IIC-BUS Interface
• 1-ch Multi-Master IIC-Bus with interrupt-bas ed
operation.
• Serial, 8-bit oriented, bi-directional data transfers
can be made at up to 100 Kbit/s in the standard
mode or up to 400 Kbit/s in the fast mode.
IIS-BUS Interface
• 1-ch IIS-bus for audio interface with DMA-based
operation.
• Serial, 8/16bit per channel data transfers
• Supports MSB-justified data format
SIO (Synchronous Serial I/O)
• 1-ch SIO with DMA-based or interrupt -based
operation.
• Programmable baud rates.
• Supports serial data transmit/receive operations
8-bit in SIO.
Operating Voltage Range
• Core : 2.5V I/O : 3.0 V to 3.6 V
Operating Frequency
• Up to 66 MHz
Package
• 160 LQFP / 160 FBGA
1-4
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
BLOCK DIAGRAM
Bus Arbiter
JTAG
Boundary Scan
ARM7TDMI TAP
Controller
Clock Generator
(PLL)
AIN[7:0]
CPU Unit
Write Buffer
ARM7TDMI
CPU Core
Cache 8K-byte
Power
Management
ADC
Watchdog Timer
S
y
s
t
e
m
B
u
s
System Bus Bridge & Arbitration /
BDMA (2-Ch)
P
e
r
i
p
h
e
r
a
l
Memory I/F
ROM/SRAM
DRAM/SDRAM
LCD
DMA
Interrupt CONT.
ZDMA (2-Ch)
(Controller)
UART 0,1 (Each
16byte FIFO)
LCD
CONT.
GPIO
I2C Bus
Controller
I2S Bus
Controller
G
e
n
e
r
a
l
P
u
r
p
o
s
e
I
/
O
32,768 Hz
B
RTC
(Real Time Clock)
u
s
Figure 1-1. S3C44B0X Block Diagram
Synchronout I/O
PWM Timer
0-4,5 (internal)
TCLK EXTCLK
SIOCK
1-5
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
PIN ASSIGNMENTS
DATA25/nXDREQ1/GPC9
DATA24/nXDACK1/GPC8
VSS
110
VDD
109
108
107
DATA26/nRTS1/GPC10
106
DATA22/VD5/GPC6
DATA23/VD4/GPC7
112
111
S3C44B0X
10
1112131415
DATA27/nCTS1/GPC11
DATA30/nRTS0/GPC14
DATA31/nCTS0/GPC15
DATA29/RxD1/GPC13
DATA28/TxD1/GPC12
VFRAME/GPD7
VLINE/GPD5
VD0/GPD0
VD1/GPD1
VD3/GPD3
VD2/GPD2
98
97
95
VCLK/GPD4
VM/GPD6
91
93
928990
94
VDDRTC
VSSIO
105
104
103
102
101
RxD0/GPE2
TxD0/GPE1
1009996
160-QFP
18
17
1620192221242326252827302932313433
EXTAL1
XTAL1
8788858384
VDDADC
AVCOM
AREFB
86
35
3638374039
AREFT
AIN7
82
AIN6
81
AIN5
80
AIN4
79
AIN3
78
AIN2
77
AIN1
76
AIN0
75
VSSADC
74
VSSIO
73
TOUT4/VD7/GPE7
72
TOUT3/VD6/GPE6
71
TOUT2/TCLK/GPE5
70
TOUT1/TCLK/GPE4
69
TOUT0/GPE3
68
EXTCLK
67
PLLCAP
66
EXTAL0
65
XTAL0
64
VSS
63
VDD
62
IICSCL/GPF0
61
IICSDA/GPF1
60
SIOTxD/nRTS1/IISLRCK/GPF5
59
SIORDY/TxD1/IISDO/GPF6
58
SIORxD/RxD1/IISDI/GPF7
57
SIOCLK/nCTS1/IISCLK/GPF8
56
ENDIAN/CODECLK/GPE8
55
OM3
54
OM2
53
OM1
52
OM0
51
nRESET
50
CLKout/GPE0
49
VSSIO
48
VDDIO
47
TDO
46
TDI
45
TMS
44
TCK
43
nTRST
42
ExINT7/IISLRCK/GPG7
41
DATA13
DATA12
DATA11
DATA10
VDDIO
VSSIO
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ADDR24/GPA9
VDD
VSS
ADDR23/GPA8
ADDR22/GPA7
ADDR21/GPA6
ADDR20/GPA5
ADDR19/GPA4
ADDR18/GPA3
ADDR17/GPA2
ADDR16/GPA1
ADDR15
ADDR14
ADDR13
ADDR12
VSSIO
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
DATA16/IISLRCK/GPC0
DATA19/IISCLK/GPC3
DATA17/IISDO/GPC1
DATA18/IISDI/GPC2
DATA20/VD7/GPC4
DATA21/VD6/GPC5
DATA14
DATA15
118
117
120
119
116
115
114
113
123456789
1-6
ADDR3
ADDR2
ADDR1
ADDR0/GPA0
nCAS0
nCAS1
nCAS2:nSCAS/GPB2
nCAS3:nSRAS/GPB3
VDDIO
VSSIO
nBE0:nWBE0:DQM0
nBE1:nWBE1:DQM1
nBE2:nWBE2:DQM2/GPB4
nGCS1/GPB6
nGCS0
nBE3:nWBE3:DQM3/GPB5
nOE
nWE
nGCS3/GPB8
nGCS2/GPB7
VSS
VDD
nGCS5/GPB10
nGCS4/GPB9
nGCS7:nSCS1:nRAS1
nGCS6:nSCS0:nRAS0
SCLK/GPB1
SCKE/GPB0
nXDREQ0/nXBREQ/GPF4
nWAIT/GPF2
ExINT0/VD4/GPG0
nXDACK0/nXBACK/GPF3
ExINT1/VD5/GPG1
Figure 1-2. S3C44B0X Pin Assignments (160 LQFP)
VDD
ExINT2/nCTS0/GPG2
VSS
ExINT3/nRTS0/GPG3
ExINT4/IISCLK/GPG4
ExINT5/IISDI/GPG5
ExINT6/IISDO/GPG6
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
P
N
M
L
K
J
H
G
Ball Pad A1
F
Corner Indicator
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Bottom View
Figure 1-3. S3C44B0X Pin Assignments (160 FBGA)
1-7
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-1. 160-Pin LQFP Pin Assignment
Pin
No.
Pin Name Default
Function
I/O State
(2)
@BUS REQ.
I/O State
@STOP
(2)
I/O State
@Initial
I/O TYPE
1 ADDR3 ADDR3 Hi-z Hi-z O phot8
2 ADDR2 ADDR2
3 ADDR1 ADDR1
4 ADDR0/GPA0 ADDR0 Hi-z/O Hi-z/O
5 nCAS0 nCAS0 Hi-z Low
6 nCAS1 nCAS1
7 nCAS2:nSCAS/GPB2 nSCAS High/Low/O
8 nCAS3:nSRAS/GPB3 nSRAS
9 VDDIO VDDIO
(3)
–
(3)
–
P vdd3op
10 VSSIO VSSIO vss3op
11 nBE0:nWBE0:DQM0 DQM0 Hi-z Hi-z O phot6
12 nBE1:nWBE1:DQM1 DQM1
13 nBE2:nWBE2:DQM2/GPB4 DQM2
14 nBE3:nWBE3:DQM3/GPB5 DQM3
15 nOE nOE phot8
(6)
16 nWE nWE phot6
17 nGCS0 nGCS0 phot8
18 nGCS1/GPB6 nGCS1 Hi-z/O Hi-z/O
19 nGCS2/GPB7 nGCS2
20 nGCS3/GPB8 nGCS3
21 VDD VDD − − P vdd2I
22 VSS VSS vss2I
23 nGCS4/GPB9 nGCS4 Hi-z/O Hi-z/O O phot8
24 nGCS5/GPB10 nGCS5
25 nGCS6:nSCS0:nRAS0 nSCS0 Hi-z High/High/Low
26 nGCS7:nSCS1:nRAS1 nSCS1
27 SCKE/GPB0 SCKE Hi-z/O Low/O phot6
28 SCLK/GPB1 SCLK High/O phot10
29 nWAIT/GPF2 GPF2 − − IO phbsu50ct8sm
30 nXDREQ0/nXBREQ/GPF4 GPF4
31 nXDACK0/nXBACK/GPF3 GPF3
32 ExINT0/VD4/GPG0 GPG0
33 ExINT1/VD5/GPG1 GPG1
1-8
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
1-9
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-1. 160-Pin LQFP Pin Assignment (Continued)
Pin
No.
Pin Name Default
Function
I/O State
@BUS REQ.
I/O State
@STOP
I/O State
@Initial
I/O TYPE
34 VDD VDD − − P vdd2i
35 VSS VSS vss2i
36 ExINT2/nCTS0/GPG2 GPG2 IO phbsu50ct8sm
37 ExINT3/nRTS0/GPG3 GPG3
38 ExINT4/IISCLK/GPG4 GPG4
39 ExINT5/IISDI/GPG5 GPG5
40 ExINT6/IISDO/GPG6 GPG6
41 ExINT7/IISLRCK/GPG7 GPG7
42 nTRST nTRST I phis
43 TCK TCK
44 TMS TMS
45 TDI TDI
46 TDO TDO O phot6
47 VDDIO VDDIO P vdd3op
48 VSSIO VSSIO vss3op
49 CLKout/GPE0 GPE0 IO phbsu50ct8sm
50 nRESET nRESET I phis
51 OM0 OM0
I
(1)
52 OM1 OM1
53 OM2 OM2
54 OM3 OM3
55 ENDIAN/CODECLK/GPE8 CODECLK
IO
(1)
phbsu50ct8sm
56 SIOCLK/nCTS1/IISCLK/GPF8 GPF8
57 SIORxD/RxD1/IISDI/GPF7 GPF7
58 SIORDY/TxD1/IISDO/GPF6 GPF6
59 SIOTxD/nRTS1/IISLRCK/GPF5 GPF5
60 IICSDA/GPF1 GPF1 phbsu50cd4sm
61 IICSCL/GPF0 GPF0
62 VDD VDD P vdd2i
63 VSS VSS vss2i
64 XTAL0 XTAL0
65 EXTAL0 EXTAL0
66 PLLCAP PLLCAP
AI
AO
AI
(5)
(5)
phsoscm16
(5)
phnc50_option
1-10
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-1. 160-Pin LQFP Pin Assignment (Continued)
Pin
No.
Pin Name Default
Function
I/O State
@BUS REQ.
I/O State
@STOP
I/O State
@Initial
I/O TYPE
67 EXTCLK EXTCLK − − I phis
68 TOUT0/GPE3 GPE3 IO phbsu50ct8sm
69 TOUT1/TCLK/GPE4 GPE4
70 TOUT2/TCLK/GPE5 GPE5
71 TOUT3/VD6/GPE6 GPE6
72 TOUT4/VD7/GPE7 GPE7
73 VSSIO VSSIO P vss3op
74 VSSADC VSSADC vss2t
75 AIN0 AIN0
(5) phnc50
AI
76 AIN1 AIN1
77 AIN2 AIN2
78 AIN3 AIN3
79 AIN4 AIN4
80 AIN5 AIN5
81 AIN6 AIN6
82 AIN7 AIN7
83 AREFT AREFT phnc50_option
84 AREFB AREFB
85 AVCOM AVCOM
86 VDDADC VDDADC P vdd2t
87 XTAL1 XTAL1 I phnc50
88 EXTAL1 EXTAL1 O
89 VDDRTC VDDRTC P vdd2t
90 VSSIO VSSIO vss3op
91 VFRAME/GPD7 GPD7 IO phbsu50ct8sm
92 VM/GPD6 GPD6
93 VLINE/GPD5 GPD5
94 VCLK/GPD4 GPD4
95 VD3/GPD3 GPD3
96 VD2/GPD2 GPD2
97 VD1/GPD1 GPD1
98 VD0/GPD0 GPD0
1-11
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-1. 160-Pin LQFP Pin Assignment (Continued)
Pin
No.
Pin Name Default
Function
I/O State
@BUS REQ.
I/O State
@STOP
I/O State
@Initial
I/O TYPE
99 RxD0/GPE2 GPE2 − − IO phbsu50ct8sm
100 TxD0/GPE1 GPE1
101 DATA31/nCTS0/GPC15 DATA31 Hi-z/IO Hi-z/IO I(Hi-z) phbsu50ct12sm
102 DATA30/nRTS0/GPC14 DATA30
103 DATA29/RxD1/GPC13 DATA29
104 DATA28/TxD1/GPC12 DATA28
105 DATA27/nCTS1/GPC11 DATA27
106 DATA26/nRTS1/GPC10 DATA26
107 DATA25/nXDREQ1/GPC9 DATA25
108 DATA24/nXDACK1/GPC8 DATA24
109 VDD VDD − − P vdd2i
110 VSS VSS vss2i
111 DATA23/VD4/GPC7 DATA23 Hi-z/IO Hi-z/IO I(Hi-z) phbsu50ct12sm
112 DATA22/VD5/GPC6 DATA22
113 DATA21/VD6/GPC5 DATA21
114 DATA20/VD7/GPC4 DATA20
115 DATA19/IISCLK/GPC3 DATA19
116 DATA18/IISDI/GPC2 DATA18
117 DATA17/IISDO/GPC1 DATA17
118 DATA16/IISLRCK/GPC0 DATA16
119 DATA15 DATA15 Hi-z Hi-z I(Hi-z)
120 DATA14 DATA14
121 DATA13 DATA13
122 DATA12 DATA12
123 DATA11 DATA11
124 DATA10 DATA10
125 VDDIO VDDIO − − P vdd3op
126 VSSIO VSSIO vss3op
127 DATA9 DATA9 Hi-z Hi-z I(Hi-z) phbsu50ct12sm
128 DATA8 DATA8
129 DATA7 DATA7
130 DATA6 DATA6
1-12
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-1. 160-Pin LQFP Pin Assignment (Concluded)
Pin
No.
Pin Name Default
Function
I/O State
@BUS REQ.
I/O State
@STOP
I/O State
@Initial
I/O TYPE
131 DATA5 DATA5 Hi-z Hi-z I(Hi-z) phbsu50ct12sm
132 DATA4 DATA4
133 DATA3 DATA3
134 DATA2 DATA2
135 DATA1 DATA1
136 DATA0 DATA0
137 ADDR24/GPA9 ADDR24 Hi-z/O Hi-z/O O phot8
138 VDD VDD − − P vdd2i
139 VSS VSS vss2i
140 ADDR23/GPA8 ADDR23 Hi-z/O Hi-z/O O phot8
141 ADDR22/GPA7 ADDR22
142 ADDR21/GPA6 ADDR21
143 ADDR20/GPA5 ADDR20
144 ADDR19/GPA4 ADDR19
145 ADDR18/GPA3 ADDR18
146 ADDR17/GPA2 ADDR17
147 ADDR16/GPA1 DATA16
148 ADDR15 ADDR15 Hi-z Hi-z
149 ADDR14 ADDR14
150 ADDR13 ADDR13
151 ADDR12 ADDR12
152 VSSIO VSSIO − − P vss3op
153 ADDR11 ADDR11 Hi-z Hi-z O phot8
154 ADDR10 ADDR10
155 ADDR9 ADDR9
156 ADDR8 ADDR8
157 ADDR7 ADDR7
158 ADDR6 ADDR6
159 ADDR5 ADDR5
160 ADDR4 ADDR4
1-13
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-2. 160-Pin FBGA Pin Assignment
Pin No. Pin Name Pin No. Pin Name
A1 ADDR4 C1 ADDR1
A2 ADDR5 C2 ADDR0/GPA0
A3 ADDR6 C3 nCAS0
A4 ADDR10 C4 ADDR8
A5 ADDR13 C5 VSSIO
A6 ADDR17/GPA2 C6 ADDR15
A7 ADDR20/GPA5 C7 ADDR21/GPA6
A8 ADDR23/GPA8 C8 ADDR22/GPA7
A9 DATA0 C9 ADDR24/GPA9
A10 DATA4 C10 DATA3
A11 DATA8 C11 DATA7
A12 DATA11 C12 VDDIO
A13 DATA12 C13 DATA17/IISDO/GPC1
A14 DATA14 C14 DATA16/IISLRCK/GPC0
B1 ADDR2 D1 nCAS3:nSRAS/GPB3
B2 ADDR3 D2 nCAS2:nSCAS/GPB2
B3 ADDR7 D3 VDDIO
B4 ADDR9 D4 nCAS1
B5 ADDR12 D5 ADDR11
B6 ADDR16/GPA1 D6 ADDR14
B7 ADDR19/GPA4 D7 ADDR18/GPA3
B8 VSS D8 VDD
B9 DATA1 D9 DATA2
B10 DATA5 D10 DATA6
B11 DATA9 D11 VSSIO
B12 DATA10 D12 DATA18/IISDI/GPC2
B13 DATA13 D13 DATA19/IISCLK/GPC3
B14 DATA15 D14 DATA20/VD7/GPC4
1-14
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-2. 160-Pin FBGA Pin Assignment (Continued)
Pin No. Pin Name Pin No. Pin Name
E1 nBE1:nWBE1:DQM1 H1 nGCS4/GPB9
E2 nBE0:nWBE0:DQM0 H2 nGCS5/GPB10
E3 nBE2:nWBE2:DQM2/GPB4 H3 VSS
E4 VSSIO H4 nGCS6:nSCS0:nRAS0
E11 DATA21/VD6/GPC5 H11 VD0/GPD0
E12 DATA22/VD5/GPC6 H12 DATA31/nCTS0/GPC15
E13 DATA23/VD4/GPC7 H13 RxD0/GPE2
E14 VSS H14 TxD0/GPE1
F1 nWE J1 nGCS7:nSCS1:nRAS1
F2 nOE J2 SCKE/GPB0
F3 nGCS0 J3 SCLK/GPB1
F4 nBE3:nWBE3:DQM3/GPB5 J4 nWAIT/GPF2
F11 VDD J11 VCLK/GPD4
F12 DATA24/nXDACK1/GPC8 J12 VD1/GPD1
F13 DATA25/nXDREQ1/GPC9 J13 VD3/GPD3
F14 DATA26/nRTS1/GPC10 J14 VD2/GPD2
G1 nGCS3/GPB8 K1 nXDREQ0/nXBREQ0/GPF4
G2 nGCS2/GPB7 K2 nXDACK0/nXBACK0/GPF3
G3 VDD K3 ExINT0/VD4/GPG0
G4 nGCS1/GPB6 K4 ExINT1/VD5/GPG1
G11 DATA27/nCTS1/GPC11 K11 VSSIO
G12 DATA30/nRTS0/GPC14 K12 VLINE/GPD5
G13 DATA28/TxD1/GPC12 K13 VFRAME/GPD7
G14 DATA29/RxD1/GPC13 K14 VM/GPD6
1-15
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-2. 160-Pin FBGA Pin Assignment (Continued)
Pin No. Pin Name Pin No. Pin Name
L1 VDD N1 ExINT5/IISDI/GPG5
L2 VSS N2 ExINT7/IISLRCK/GPG7
L3 ExINT2/nCTS0/GPG2 N3 TMS
L4 TDO N4 VDDIO
L5 nRESET N5 OM0
L6 OM3 N6 ENDIAN/CODECLK/GPE8
L7 SIORDY/TxD1/IISDO/GPF6 N7 SIOTxD/nRTS1/IISLRCK/GPF5
L8 EXTAL0 N8 XTAL0
L9 TOUT1/TCLK/GPE4 N9 EXTCLK
L10 VSSIO N10 TOUT3/VD6/GPE6
L11 VDDADC N11 AIN0
L12 VDDRTC N12 AIN2
L13 XTAL1 N13 AIN6
L14 EXTAL1 N14 AIN7
M1 ExINT4/IISCLK/GPG4 P1 ExINT6/IISDO/GPG6
M2 ExINT3/nRTS0/GPG3 P2 nTRST
M3 TDI P3 TCK
M4 CLKout/GPE0 P4 VSSIO
M5 OM2 P5 OM1
M6 SIORxD/RxD1/IISDI/GPF7 P6 SIOCLK/nCTS1/IISCLK/GPF8
M7 IICSCL/GPF0 P7 IICSDA/GPF1
M8 VDD P8 VSS
M9 TOUT0/GPE3 P9 PLLCAP
M10 TOUT4/VD7/GPE7 P10 TOUT2/TCLK/GPE5
M11 AIN1 P11 VSSADC
M12 AVCOM P12 AIN3
M13 AREFB P13 AIN4
M14 AREFT P14 AIN5
NOTES :
1. OM[3:0] and ENDIAN value are latched only at the rising edge of nRESET. Therefore, when nRESET is L, the pins of
OM[3:0] and ENDIAN are in input state. After nRESET becomes H, the pin of ENDIAN will be in output state.
2. The @BUS REQ. shows the pin states at the external bus, which is used by the other bus master. The @STOP shows
the pin states when S3C44B0X is in STOP mode.
3. ' − ' mark indicates the unchanged pin state at STOP mode or Bus released mode.
4. IICSDA,IICSCL pins are open-drain type.
5. AI/AO means analog input/output.
1-16
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
I/O Type Descriptions
vdd2i, vss2i 2.5V Vdd/Vss for internal logic
vdd3op, vss3op 3.3V Vdd/Vss for external interface logic
vdd2t, vss2t 2.5V Vdd/Vss for analog circuitry
phsoscm16 Oscillator cell with enable and feedback resistor
phbsu50ct12sm bi-directional pad, CMOS schmitt-trigger, 50K Ω pull-up resistor with control,
tri-state, Io=12mA
phbsu50ct8sm bi-directional pad, CMOS schmitt-trigger, 50K Ω pull-up resistor with control,
tri-state, Io=8mA
phbsu50cd4sm bi-directional pad, CMOS schmitt-trigger, 50K Ω pull-up resistor with control,
tri-state, Io=4mA
phot6 output pad, tri-state, Io=6mA
phot8 output pad, tri-state, Io=8mA
phot10 output pad, tri-state, Io=10mA
phis input pad, CMOS schmitt-trigger
phnc50, phnc50_option pad for analog pin
1-17
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
SIGNAL DESCRIPTIONS
Table 1-3. S3C44B0X Signal Descriptions
Signal I/O Description
BUS CONTROLLER
OM[1:0] I OM[1:0] sets S3C44B0X in the TEST mode, which is used only at fabrication. Also, it
determines the bus width of nGCS0. The logic level is determined by the pull-up/down
resistor during the RESET cycle.
00:8-bit 01:16-bit 10:32-bit 11:Test mode
ADDR[24:0] O ADDR[24:0] (Address Bus) outputs the memory address of the corresponding bank .
DATA[31:0] IO DATA[31:0] (Data Bus) inputs data during memory read and outputs data during
memory write. The bus width is programmable among 8/16/32-bit.
nGCS[7:0] O nGCS[7:0] (General Chip Select) are activated when the address of a memory is within
the address region of each bank. The number of access cycles and the bank size can
be programmed.
nWE O nWE (Write Enable) indicates that the current bus cycle is a write cycle.
nWBE[3:0] O Write Byte Enable
nBE[3:0] O Upper Byte/Lower Byte Enable(In case of SRAM)
nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle.
nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request control of the local
bus. BACK active indicates that bus control has been granted.
nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C44B0X has surrendered
control of the local bus to another bus master.
nWAIT I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus
cycle cannot be completed.
ENDIAN I It determines whether or not the data type is little endian or big endian. The logic level
is determined by the pull-up/down resistor during the RESET cycle.
0:little endian 1:big endian
DRAM/SDRAM/SRAM
nRAS[1:0] O Row Address Strobe
nCAS[3:0] O Column Address strobe
nSRAS O SDRAM Row Address Strobe
nSCAS O SDRAM Column Address Strobe
nSCS[1:0] O SDRAM Chip Select
DQM[3:0] O SDRAM Data Mask
SCLK O SDRAM Clock
SCKE O SDRAM Clock Enable
1-18
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-3. S3C44B0X Signal Descriptions (Continued)
Signal I/O Description
LCD CONTROL UNIT
VD[7:0] O LCD Data Bus
VFRAME O LCD Frame signal
VM O VM alternates the polarity of the row and column voltage
VLINE O LCD line signal
VCLK O LCD clock signal
TIMER/PWM
TOUT[4:0] O Timer output[4:0]
TCLK I External clock input
INTERRUPT CONTROL UNIT
EINT[7:0] I External Interrupt request
DMA
nXDREQ[1:0] I External DMA request
nXDACK[1:0] O External DMA acknowledge
UART
RxD[1:0] I UART receives data input
TxD[1:0] O UART transmits data output
nCTS[1:0] I UART clear to send input signal
nRTS[1:0] O UART request to send output signal
IIC-BUS
IICSDA IO IIC-bus data
IICSCL IO IIC-bus clock
IIS-BUS
IISLRCK IO IIS-bus channel select clock
IISDO O IIS-bus serial data output
IISDI I IIS-bus serial data input
IISCLK IO IIS-bus serial clock
CODECLK O CODEC system clock
SIO
SIORXD I SIO receives data input
SIOTXD O SIO transmits data output
SIOCK IO SIO clock
SIORDY IO SIO handshake signal when DMA completes the SIO operation
1-19
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-3. S3C44B0X Signal Descriptions (Continued)
Signal I/O Description
ADC
AIN[7:0] AI ADC input[7:0]
AREFT AI ADC Top Vref
AREFB AI ADC Bottom Vref
AVCOM AI ADC Common Vref
GENERAL PORT
P[70:0] IO General input/output ports (some ports are output mode only)
RESET & CLOCK
nRESET ST nRESET suspends any operation in progress and places S3C44B0X into a known reset
state. For a reset, nRESET must be held to L level for at least 4 MCLK after the
processor power has been stabilized.
OM[3:2] I OM[3:2] determines how the clock is made.
00 = Crystal(XTAL0,EXTAL0), PLL on 01 = EXTCLK, PLL on
10, 11 = Chip test mode.
EXTCLK I External clock source when OM[3:2] = 01b
If it isn't used, it has to be H (3.3V).
XTAL0 AI Crystal Input for internal osc circuit for system clock.
If it isn't used, XTAL0 has to be H (3.3V).
EXTAL0 AO Crystal Output for internal osc circuit for system clock. It is the inverted output of
XTAL0. If it isn't used, it has to be a floating pin.
PLLCAP AI Loop filter capacitor for system clock PLL. ( 700pF )
XTAL1 AI 32 KHz crystal input for RTC.
EXTAL1 AO 32 KHz crystal output for RTC. It is the inverted output of XTAL1.
CLKout O Fout or Fpllo clock
JTAG TEST LOGIC
nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start.
If debugger is used, A 10K pull-up resistor has to be connected.
If debugger(black ICE) is not used, nTRST pin must be at L or low active pulse.
TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's
states. A 10K pull-up resistor has to be connected to TMS pin.
TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.
A 10K pull-up resistor must be connected to TCK pin.
TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data.
A 10K pull-up resistor must be connected to TDI pin.
TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and data.
1-20
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-3. S3C44B0X Signal Descriptions (Concluded)
Signal I/O Description
POWER
VDD P S3C44B0X core logic VDD (2.5 V)
VSS P S3C44B0X core logic VSS
VDDIO P S3C44B0X I/O port VDD (3.3 V)
VSSIO P S3C44B0X I/O port VSS
RTCVDD P RTC VDD (2.5 V or 3.0 V, Not support 3.3V)
(This pin must be connected to power properly if RTC isn't used)
VDDADC P ADC VDD(2.5 V)
VSSADC P ADC VSS
1-21
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
S3C44B0X SPECIAL REGISTERS
Table 1-4. S3C44B0X Special Registers
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
CPU WRAPPER
SYSCFG 0x01c00000 ← W R/W System Configuration
NCACHBE0 0x01c00004 Non Cacheable Area 0
NCACHBE1 0x01c00008 Non Cacheable Area 1
SBUSCON 0x01c40000 System Bus Control
MEMORY CONTROLLER
BWSCON 0x01c80000 ← W R/W Bus Width & Wait Status Control
BANKCON0 0x01c80004 Boot ROM Control
BANKCON1 0x01c80008 BANK1 Control
BANKCON2 0x01c8000c BANK2 Control
BANKCON3 0x01c80010 BANK3 Control
BANKCON4 0x01c80014 BANK4 Control
BANKCON5 0x01c80018 BANK5 Control
BANKCON6 0x01c8001c BANK6 Control
BANKCON7 0x01c80020 BANK7 Control
REFRESH 0x01c80024 DRAM/SDRAM Refresh Control
BANKSIZE 0x01c80028 Flexible Bank Size
MRSRB6 0x01c8002c Mode register set for SDRAM
MRSRB7 0x01c80030 Mode register set for SDRAM
1-22
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-4. S3C44B0X Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
UART
ULCON0 0x01d00000 ← W R/W UART 0 Line Control
ULCON1 0x01d04000 UART 1 Line Control
UCON0 0x01d00004 UART 0 Control
UCON1 0x01d04004 UART 1 Control
UFCON0 0x01d00008 UART 0 FIFO Control
UFCON1 0x01d04008 UART 1 FIFO Control
UMCON0 0x01d0000c UART 0 Modem Control
UMCON1 0x01d0400c UART 1 Modem Control
UTRSTAT0 0x01d00010 R UART 0 Tx/Rx Status
UTRSTAT1 0x01d04010 UART 1 Tx/Rx Status
UERSTAT0 0x01d00014 UART 0 Rx Error Status
UERSTAT1 0x01d04014 UART 1 Rx Error Status
UFSTAT0 0x01d00018 UART 0 FIFO Status
UFSTAT1 0x01d04018 UART 1 FIFO Status
UMSTAT0 0x01d0001c UART 0 Modem Status
UMSTAT1 0x01d0401c UART 1 Modem Status
UTXH0 0x01d00023 0x01d00020 B W UART 0 Transmission Hold
UTXH1 0x01d04023 0x01d04020 UART 1 Transmission Hold
URXH0 0x01d00027 0x01d00024 R UART 0 Receive Buffer
URXH1 0x01d04027 0x01d04024 UART 1 Receive Buffer
UBRDIV0 0x01d00028 ← W R/W UART 0 Baud Rate Divisor
UBRDIV1 0x01d04028 UART 1 Baud Rate Divisor
SIO
SIOCON 0x01d14000 ← W R/W SIO Control
SIODAT 0x01d14004 SIO Data
SBRDR 0x01d14008 SIO Baud Rate Prescaler
ITVCNT 0x01d1400c SIO Interval Counter
DCNTZ 0x01d14010 SIO DMA Count Zero
1-23
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-4. S3C44B0X Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
IIS
IISCON 0x01d18000,02,03 0x01d18000 B,HW,W R/W IIS Control
IISMOD 0x01d18004,06 0x01d18004 HW,W IIS Mode
IISPSR 0x01d18008,0a,0b 0x01d18008 B,HW,W IIS Prescaler
IISFIFCON 0x01d1800c,0e 0x01d1800c HW,W IIS FIFO Control
IISFIF 0x01d18012 0x01d18010 HW IIS FIFO Entry
I/O PORT
PCONA 0x01d20000 ← W R/W Port A Control
PDATA 0x01d20004 Port A Data
PCONB 0x01d20008 Port B Control
PDATB 0x01d2000c Port B Data
PCONC 0x01d20010 Port C Control
PDATC 0x01d20014 Port C Data
PUPC 0x01d20018 Pull-up Control C
PCOND 0x01d2001c Port D Control
PDATD 0x01d20020 Port D Data
PUPD 0x01d20024 Pull-up Control D
PCONE 0x01d20028 Port E Control
PDATE 0x01d2002c Port E Data
PUPE 0x01d20030 Pull-up Control E
PCONF 0x01d20034 Port F Control
PDATF 0x01d20038 Port F Data
PUPF 0x01d2003c Pull-up Control F
PCONG 0x01d20040 Port G Control
PDATG 0x01d20044 Port G Data
PUPG 0x01d20048 Pull-up Control G
SPUCR 0x01d2004c Special Pull-up
EXTINT 0x01d20050 External Interrupt Control
EXTINPND 0x01d20054 External Interrupt Pending
WATCHDOG TIMER
WTCON 0x01d30000 ← W R/W Watchdog Timer Mode
WTDAT 0x01d30004 Watchdog Timer Data
WTCNT 0x01d30008 Watchdog Timer Count
1-24
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-4. S3C44B0X Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
A/D CONVERTER
ADCCON 0x01d40000,02,03 0x01d40000 B,HW,W R/W ADC Control
ADCPSR 0x01d40004,06,07 0x01d40004 ADC Prescaler
ADCDAT 0x01d40008,0a 0x01d40008 HW,W R Digitized 10 bit Data
PWM TIMER
TCFG0 0x01d50000 ← W R/W Timer Configuration
TCFG1 0x01d50004 Timer Configuration
TCON 0x01d50008 Timer Control
TCNTB0 0x01d5000c Timer Count Buffer 0
TCMPB0 0x01d50010 Timer Compare Buffer 0
TCNTO0 0x01d50014 R Timer Count Observation 0
TCNTB1 0x01d50018 R/W Timer Count Buffer 1
TCMPB1 0x01d5001c Timer Compare Buffer 1
TCNTO1 0x01d50020 R Timer Count Observation 1
TCNTB2 0x01d50024 R/W Timer Count Buffer 2
TCMPB2 0x01d50028 Timer Compare Buffer 2
TCNTO2 0x01d5002c R Timer Count Observation 2
TCNTB3 0x01d50030 R/W Timer Count Buffer 3
TCMPB3 0x01d50034 Timer Compare Buffer 3
TCNTO3 0x01d50038 R Timer Count Observation 3
TCNTB4 0x01d5003c R/W Timer Count Buffer 4
TCMPB4 0x01d50040 Timer Compare Buffer 4
TCNTO4 0x01d50044 R Timer Count Observation 4
TCNTB5 0x01d50048 R/W Timer Count Buffer 5
TCNTO5 0x01d5004c R Timer Count Observation 5
IIC
IICCON 0x01d60000 ← W R/W IIC Control
IICSTAT 0x01d60004 IIC Status
IICADD 0x01d60008 IIC Address
IICDS 0x01d6000c IIC Data Shift
1-25
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-4. S3C44B0X Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
RTC
RTCCON 0x01d70043 0x01d70040 B R/W RTC Control
RTCALM 0x01d70053 0x01d70050 RTC Alarm
ALMSEC 0x01d70057 0x01d70054 Alarm Second
ALMMIN 0x01d7005b 0x01d70058 Alarm Minute
ALMHOUR 0x01d7005f 0x01d7005c Alarm Hour
ALMDAY 0x01d70063 0x01d70060 Alarm Day
ALMMON 0x01d70067 0x01d70064 Alarm Month
ALMYEAR 0x01d7006b 0x01d70068 Alarm Year
RTCRST 0x01d7006f 0x01d7006c RTC Round Reset
BCDSEC 0x01d70073 0x01d70070 BCD Second
BCDMIN 0x01d70077 0x01d70074 BCD Minute
BCDHOUR 0x01d7007b 0x01d70078 BCD Hour
BCDDAY 0x01d7007f 0x01d7007c BCD Day
BCDDATE 0x01d70083 0x01d70080 BCD Date
BCDMON 0x01d70087 0x01d70084 BCD Month
Function
BCDYEAR 0x01d7008b 0x01d70088 BCD Year
TICINT 0x01D7008E 0x01D7008C Tick time count
CLOCK & POWER MANAGEMENT
PLLCON 0x01d80000 ← W R/W PLL Control
CLKCON 0x01d80004 Clock Control
CLKSLOW 0x01d80008 Slow clock Control
LOCKTIME 0x01d8000c PLL lock time Counter
1-26
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
Table 1-4. S3C44B0X Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
INTERRUPT CONTROLLER
INTCON 0x01e00000 ← W R/W Interrupt Control
INTPND 0x01e00004 R Interrupt Request Status
INTMOD 0x01e00008 R/W Interrupt Mode Control
INTMSK 0x01e0000c Interrupt Mask Control
I_PSLV 0x01e00010 IRQ Interrupt Previous Slave
I_PMST 0x01e00014 IRQ Interrupt Priority Master
I_CSLV 0x01e00018 R IRQ Interrupt Current Slave
I_CMST 0x01e0001c IRQ Interrupt Current Master
I_ISPR 0x01e00020 IRQ Interrupt Pending Status
I_ISPC 0x01e00024 W IRQ Interrupt Pending Clear
F_ISPR 0x01e00038 R FIQ Interrupt Pending
F_ISPC 0x01e0003c W FIQ Interrupt Pending Clear
LCD CONTROLLER
LCDCON1 0x01f00000 ← W R/W LCD Control 1
LCDCON2 0x01f00004 LCD Control 2
LCDCON3 0x01f00040 LCD Control 3
LCDSADDR1 0x01f00008 Frame Upper Buffer Start Address 1
LCDSADDR2 0x01f0000c Frame Lower Buffer Start Address 2
LCDSADDR3 0x01f00010 Virtual Screen Address
REDLUT 0x01f00014 RED Lookup Table
GREENLUT 0x01f00018 GREEN Lookup Table
BLUELUT 0x01f0001c BLUE Lookup Table
DP1_2 0x01f00020 Dithering Pattern duty 1/2
DP4_7 0x01f00024 Dithering Pattern duty 4/7
DP3_5 0x01f00028 Dithering Pattern duty 3/5
DP2_3 0x01f0002c Dithering Pattern duty 2/3
DP5_7 0x01f00030 Dithering Pattern duty 5/7
DP3_4 0x01f00034 Dithering Pattern duty 3/4
DP4_5 0x01f00038 Dithering Pattern duty 4/5
DP6_7 0x01f0003c Dithering Pattern duty 6/7
DITHMODE 0x01f00044 Dithering Mode
1-27
PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR
Table 1-4. S3C44B0X Special Registers (Concluded)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/W
rite
Function
DMA
ZDCON0 0x01e80000 ← W R/W ZDMA0 Control
ZDISRC0 0x01e80004 ZDMA 0 Initial Source Address
ZDIDES0 0x01e80008 ZDMA 0 Initial Destination Address
ZDICNT0 0x01e8000c ZDMA 0 Initial Transfer Count
ZDCSRC0 0x01e80010 R ZDMA 0 Current Source Address
ZDCDES0 0x01e80014 ZDMA 0 Current Destination Address
ZDCCNT0 0x01e80018 ZDMA 0 Current Transfer Count
ZDCON1 0x01e80020 R/W ZDMA 1 Control
ZDISRC1 0x01e80024 ZDMA 1 Initial Source Address
ZDIDES1 0x01e80028 ZDMA 1 Initial Destination Address
ZDICNT1 0x01e8002c ZDMA 1 Initial Transfer Count
ZDCSRC1 0x01e80030 R ZDMA 1 Current Source Address
ZDCDES1 0x01e80034 ZDMA 1 Current Destination Address
ZDCCNT1 0x01e80038 ZDMA 1 Current Transfer Count
BDCON0 0x01f80000 R/W BDMA 0 Control
BDISRC0 0x01f80004 BDMA 0 Initial Source Address
BDIDES0 0x01f80008 BDMA 0 Initial Destination Address
BDICNT0 0x01f8000c BDMA 0 Initial Transfer Count
BDCSRC0 0x01f80010 R BDMA 0 Current Source Address
BDCDES0 0x01f80014 BDMA 0 Current Destination Address
BDCCNT0 0x01f80018 BDMA 0 Current Transfer Count
BDCON1 0x01f80020 R/W BDMA 1 Control
BDISRC1 0x01f80024 BDMA 1 Initial Source Address
BDIDES1 0x01f80028 BDMA 1 Initial Destination Address
BDICNT1 0x01f8002c BDMA 1 Initial Transfer Count
BDCSRC1 0x01f80030 R BDMA 1 Current Source Address
BDCDES1 0x01f80034 BDMA 1 Current Destination Address
BDCCNT1 0x01f80038 BDMA 1 Current Transfer Count
1-28
S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW
IMPORTANT NOTES ABOUT S3C44B0X SPECIAL REGISTERS
1. In the little endian mode, L. endian address must be used. In the big endian mode, B. endian address must be
used.
2. The special registers have to be accessed by the recommended access unit.
3. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit) at
little/big endian.
4. It is very important that the ADC registers, RTC registers and UART registers be read/written by the specified
access unit and the specified address. Moreover, one must carefully consider which endian mode is used.
5. W: 32-bit register, which must be accessed by LDR/STR or int type pointer(int *).
HW: 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *).
B: 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char *).
1-29
S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL
2 PROGRAMMER'S MODEL
OVERVIEW
S3C44B0X has been developed using the advanced ARM7TDMI core, which has been designed by Advanced
RISC Machines, Ltd.
PROCESSOR OPERATING STATES
From the programmer's point of view, the ARM7TDMI can be in one of two states:
• ARM state which executes 32-bit, word-aligned ARM instructions.
• THUMB state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1
to select between alternate halfwords.
NOTE
Transition between these two states does not affect the processor mode or the contents of the registers.
SWITCHING STATE
Entering THUMB State
Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand
register.
Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT,
SWI etc.), if the exception was entered with the processor in THUMB state.
Entering ARM State
Entry into ARM state happens:
• On execution of the BX instruction with the state bit clear in the operand register.
• On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is
placed in the exception mode's link register, and execution commences at the exception's vector address.
MEMORY FORMATS
ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first
stored word, bytes 4 to 7 the second and so on. ARM7TDMI can treat words in memory as being stored either in
Big-Endian or Little-Endian format.
2-1
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