SAMSUNG S3C44B0X User Manual

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S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

INTRODUCTION

SAMSUNG's S3C44B0X 16/32-bit RISC microprocessor is designed to provide a cost-effective and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C44B0X also provides the following: 8KB cache, optional internal SRAM, LCD controller, 2-channel UART with handshake, 4channel DMA, System manager (chip select logic, FP/ EDO/SDRAM controller), 5-channel timers with PWM, I/O ports, RTC, 8-channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, Sync. SIO interface and PLL for clock.

The S3C44B0X was developed using a ARM7TDMI core, 0.25 um CMOS standard cells, and a memory compiler. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C44B0X adopts a new bus architecture, SAMBA II (SAMSUNG ARM CPU embedded Microcontroller Bus Architecture).

An outstanding feature of the S3C44B0X is its CPU core, a 16/32-bit ARM7TDMI RISC processor (66MHz) designed by Advanced RISC Machines, Ltd. The architectural enhancements of ARM7TDMI include the Thumb decompressor, an on-chip ICE breaker debug support, and a 32-bit hardware multiplier.

By providing a complete set of common system peripherals, the S3C44B0X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document are as follows:

• 2.5V Static ARM7TDMI CPU core with 8KB cache . (SAMBA II bus architecture up to 66MHz)

• External memory controller. (FP/EDO/SDRAM Control, Chip Select logic)

• LCD controller (up to 256 color DSTN) with 1-ch LCD-dedicated DMA.

• 2-ch general DMAs / 2-ch peripheral DMAs with external request pins

• 2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO

• 1-ch multi-master IIC-BUS controller

• 1-ch IIS-BUS controller

• 5-ch PWM timers & 1-ch internal timer

• Watch Dog Timer

• 71 general purpose I/O ports / 8-ch external interrupt source

• Power control: Normal, Slow, Idle, and Stop mode

• 8-ch 10-bit ADC.

• RTC with calendar function.

• On-chip clock generator with PLL.

1-1

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

FEATURES

Architecture

• Integrated system for hand-held devices and

general embedded applications.

• 16/32-Bit RISC architecture and powerful

instruction set with ARM7TDMI CPU core.

• Thumb de-compressor maximizes code density

while maintaining performance.

• On-chip ICEbreaker debug support with JTAG-

based debugging solution.

• 32x8 bit hardware multiplier.

• New bus architecture to implement Low-Power

SAMBA II(SAMSUNG's ARM CPU embedded Micro-controller Bus Architecture).

System Manager

• Little/Big endian support.

• Address space: 32Mbytes per each bank. (Total

256Mbyte)

• Supports programmable 8/16/32-bit data bus

width for each bank.

• Fixed bank start address and programmable bank

size for 7 banks.

• Programmable bank start address and bank size

for one bank.

• 8 memory banks.

- 6 memory banks for ROM, SRAM etc.

- 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM)

• Fully Programmable access cycles for all

memory banks.

• Supports external wait signal to expend the bus

cycle.

• Supports self-refresh mode in DRAM/SDRAM for

power-down.

• Supports asymmetric/symmetric address of

DRAM.

Cache Memory & internal SRAM

• 4-way set associative ID(Unified)-cache with

8Kbyte.

• The 0/4/8 Kbytes internal SRAM using unused

cache memory.

• Pseudo LRU(Least Recently Used) Replace

Algorithm.

• Write through policy to maintain the coherence

between main memory and cache content.

• Write buffer with four depth.

• Request data first fill technique when cache miss

occurs.

Clock & Power Manager

• Low power

• The on-chip PLL makes the clock for operating

MCU at maximum 66MHz.

• Clock can be fed selectively to each function

block by software.

• Power mode: Normal, Slow, Idle and Stop mode.

Normal mode: Normal operating mode. Slow mode: Low frequency clock without PLL Idle mode: Stop the clock for only CPU Stop mode: All clocks are stopped

• Wake up by EINT[7:0] or RTC alarm interrupt from

Stop mode.

Interrupt Controller

• 30 Interrupt sources

( Watch-dog timer, 6 Timer, 6 UART, 8 External interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO )

• Vectored IRQ interrupt mode to reduce interrupt

latency.

• Level/edge mode on the external interrupt sources

• Programmable polarity of edge and level

• Supports FIQ (Fast Interrupt request) for very

urgent interrupt request

FEATURES (Continued)

1-2

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Timer with PWM (Pulse Width Modulation)

• 5-ch 16-bit Timer with PWM / 1-ch 16-bit internal

timer with DMA-based or interrupt-based operation

• Programmable duty cycle, frequency, and polarity

• Dead-zone generation.

• Supports external clock source.

RTC (Real Time Clock)

• Full clock feature: msec, sec, min, hour, day,

week, month, year.

• 32.768 KHz operation.

• Alarm interrupt for CPU wake-up.

• Time tick interrupt

General purpose input/output ports

• 8 external interrupt ports

• 71 multiplexed input/output ports

DMA Controller

• 2 channel general purpose Direct Memory Access

controller without CPU intervention.

• 2 channel Bridge DMA (peripheral DMA)

controller.

• Support IO to memory, memory to IO, IO to IO

with the Bridge DMA which has 6 type's DMA requestor: Software, 4 internal function blocks (UART, SIO, Timer, IIS), and External pins.

• Programmable priority order between DMAs (fixed

or round-robin mode)

• Burst transfer mode to enhance the transfer rate

on the FPDRAM, EDODRAM and SDRAM.

• Supports fly-by mode on the memory to external

device and external device to memory transfer mode

A/D Converter

• 8-ch multiplexed ADC.

• Max. 100KSPS/10-bit.

UART

• 2-channel UART with DMA-based or interrupt-

based operation

• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data

transmit/receive

• Supports H/W handshaking during

transmit/receive

• Programmable baud rate

• Supports IrDA 1.0 (115.2kbps)

• Loop back mode for testing

• Each channel have two internal 32-byte FIFO for

Rx and Tx.

LCD Controller

• Supports color/monochrome/gray LCD panel

• Supports single scan and dual scan displays

• Supports virtual screen function

• System memory is used as display memory

• Dedicated DMA for fetching image data from

system memory

• Programmable screen size

• Gray level: 16 gray levels

• 256 Color levels

1-3

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

FEATURES (Continued)

Watchdog Timer

• 16-bit Watchdog Timer

• Interrupt request or system reset at time-out

IIC-BUS Interface

• 1-ch Multi-Master IIC-Bus with interrupt-bas ed

operation.

• Serial, 8-bit oriented, bi-directional data transfers

can be made at up to 100 Kbit/s in the standard mode or up to 400 Kbit/s in the fast mode.

IIS-BUS Interface

• 1-ch IIS-bus for audio interface with DMA-based

operation.

• Serial, 8/16bit per channel data transfers

• Supports MSB-justified data format

SIO (Synchronous Serial I/O)

• 1-ch SIO with DMA-based or interrupt -based

operation.

• Programmable baud rates.

• Supports serial data transmit/receive operations

8-bit in SIO.

Operating Voltage Range

• Core : 2.5V I/O : 3.0 V to 3.6 V

Operating Frequency

• Up to 66 MHz

Package

• 160 LQFP / 160 FBGA

1-4

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

BLOCK DIAGRAM

Bus Arbiter

JTAG

Boundary Scan

ARM7TDMI TAP

Controller

Clock Generator

(PLL)

AIN[7:0]

CPU Unit

Write Buffer

ARM7TDMI

CPU Core

Cache 8K-byte

Power

Management

ADC

Watchdog Timer

y s

B u

System Bus Bridge & Arbitration /

BDMA (2-Ch)

e r

i p h

e r

Memory I/F

ROM/SRAM

DRAM/SDRAM

LCD

DMA

Interrupt CONT.

ZDMA (2-Ch)

(Controller)

UART 0,1 (Each

16byte FIFO)

LCD

CONT.

GPIO

I2C Bus

Controller

I2S Bus

Controller

P u

r p o

s e

32,768 Hz

RTC

(Real Time Clock)

Figure 1-1. S3C44B0X Block Diagram

Synchronout I/O

PWM Timer

0-4,5 (internal)

TCLK EXTCLK

SIOCK

1-5

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

PIN ASSIGNMENTS

DATA25/nXDREQ1/GPC9

DATA24/nXDACK1/GPC8

VSS

110

VDD

109

108

107

DATA26/nRTS1/GPC10

106

DATA22/VD5/GPC6

DATA23/VD4/GPC7

112

111

S3C44B0X

1112131415

DATA27/nCTS1/GPC11

DATA30/nRTS0/GPC14

DATA31/nCTS0/GPC15

DATA29/RxD1/GPC13

DATA28/TxD1/GPC12

VFRAME/GPD7

VLINE/GPD5

VD0/GPD0

VD1/GPD1

VD3/GPD3

VD2/GPD2

VCLK/GPD4

VM/GPD6

928990

VDDRTC

VSSIO

105

104

103

102

101

RxD0/GPE2

TxD0/GPE1

1009996

160-QFP

1620192221242326252827302932313433

EXTAL1

XTAL1

8788858384

VDDADC

AVCOM

AREFB

3638374039

AREFT

AIN7

AIN6

AIN5

AIN4

AIN3

AIN2

AIN1

AIN0

VSSADC

VSSIO

TOUT4/VD7/GPE7

TOUT3/VD6/GPE6

TOUT2/TCLK/GPE5

TOUT1/TCLK/GPE4

TOUT0/GPE3

EXTCLK

PLLCAP

EXTAL0

XTAL0

VSS

VDD

IICSCL/GPF0

IICSDA/GPF1

SIOTxD/nRTS1/IISLRCK/GPF5

SIORDY/TxD1/IISDO/GPF6

SIORxD/RxD1/IISDI/GPF7

SIOCLK/nCTS1/IISCLK/GPF8

ENDIAN/CODECLK/GPE8

OM3

OM2

OM1

OM0

nRESET

CLKout/GPE0

VSSIO

VDDIO

TDO

TDI

TMS

TCK

nTRST

ExINT7/IISLRCK/GPG7

DATA13 DATA12 DATA11 DATA10

VDDIO

VSSIO DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

ADDR24/GPA9

VDD

VSS ADDR23/GPA8 ADDR22/GPA7 ADDR21/GPA6 ADDR20/GPA5 ADDR19/GPA4 ADDR18/GPA3 ADDR17/GPA2 ADDR16/GPA1

ADDR15 ADDR14 ADDR13 ADDR12

VSSIO ADDR11 ADDR10

ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4

121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160

DATA16/IISLRCK/GPC0

DATA19/IISCLK/GPC3

DATA17/IISDO/GPC1

DATA18/IISDI/GPC2

DATA20/VD7/GPC4

DATA21/VD6/GPC5

DATA14

DATA15

118

117

120

119

116

115

114

113

123456789

1-6

ADDR3

ADDR2

ADDR1

ADDR0/GPA0

nCAS0

nCAS1

nCAS2:nSCAS/GPB2

nCAS3:nSRAS/GPB3

VDDIO

VSSIO

nBE0:nWBE0:DQM0

nBE1:nWBE1:DQM1

nBE2:nWBE2:DQM2/GPB4

nGCS1/GPB6

nGCS0

nBE3:nWBE3:DQM3/GPB5

nOE

nWE

nGCS3/GPB8

nGCS2/GPB7

VSS

VDD

nGCS5/GPB10

nGCS4/GPB9

nGCS7:nSCS1:nRAS1

nGCS6:nSCS0:nRAS0

SCLK/GPB1

SCKE/GPB0

nXDREQ0/nXBREQ/GPF4

nWAIT/GPF2

ExINT0/VD4/GPG0

nXDACK0/nXBACK/GPF3

ExINT1/VD5/GPG1

Figure 1-2. S3C44B0X Pin Assignments (160 LQFP)

VDD

ExINT2/nCTS0/GPG2

VSS

ExINT3/nRTS0/GPG3

ExINT4/IISCLK/GPG4

ExINT5/IISDI/GPG5

ExINT6/IISDO/GPG6

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Ball Pad A1

Corner Indicator E

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Bottom View

Figure 1-3. S3C44B0X Pin Assignments (160 FBGA)

1-7

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-1. 160-Pin LQFP Pin Assignment

Pin No.

Pin Name Default

Function

I/O State

(2)

@BUS REQ.

I/O State

@STOP

(2)

I/O State

@Initial

I/O TYPE

1 ADDR3 ADDR3 Hi-z Hi-z O phot8 2 ADDR2 ADDR2 3 ADDR1 ADDR1 4 ADDR0/GPA0 ADDR0 Hi-z/O Hi-z/O 5 nCAS0 nCAS0 Hi-z Low 6 nCAS1 nCAS1 7 nCAS2:nSCAS/GPB2 nSCAS High/Low/O 8 nCAS3:nSRAS/GPB3 nSRAS 9 VDDIO VDDIO

(3)

–

(3)

–

P vdd3op

10 VSSIO VSSIO vss3op 11 nBE0:nWBE0:DQM0 DQM0 Hi-z Hi-z O phot6 12 nBE1:nWBE1:DQM1 DQM1 13 nBE2:nWBE2:DQM2/GPB4 DQM2 14 nBE3:nWBE3:DQM3/GPB5 DQM3 15 nOE nOE phot8

(6)

16 nWE nWE phot6 17 nGCS0 nGCS0 phot8 18 nGCS1/GPB6 nGCS1 Hi-z/O Hi-z/O 19 nGCS2/GPB7 nGCS2 20 nGCS3/GPB8 nGCS3 21 VDD VDD − − P vdd2I 22 VSS VSS vss2I 23 nGCS4/GPB9 nGCS4 Hi-z/O Hi-z/O O phot8 24 nGCS5/GPB10 nGCS5 25 nGCS6:nSCS0:nRAS0 nSCS0 Hi-z High/High/Low 26 nGCS7:nSCS1:nRAS1 nSCS1 27 SCKE/GPB0 SCKE Hi-z/O Low/O phot6 28 SCLK/GPB1 SCLK High/O phot10 29 nWAIT/GPF2 GPF2 − − IO phbsu50ct8sm 30 nXDREQ0/nXBREQ/GPF4 GPF4 31 nXDACK0/nXBACK/GPF3 GPF3 32 ExINT0/VD4/GPG0 GPG0 33 ExINT1/VD5/GPG1 GPG1

1-8

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

1-9

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-1. 160-Pin LQFP Pin Assignment (Continued)

Pin No.

Pin Name Default

Function

I/O State

@BUS REQ.

I/O State

@STOP

I/O State

@Initial

I/O TYPE

34 VDD VDD − − P vdd2i 35 VSS VSS vss2i 36 ExINT2/nCTS0/GPG2 GPG2 IO phbsu50ct8sm 37 ExINT3/nRTS0/GPG3 GPG3 38 ExINT4/IISCLK/GPG4 GPG4 39 ExINT5/IISDI/GPG5 GPG5 40 ExINT6/IISDO/GPG6 GPG6 41 ExINT7/IISLRCK/GPG7 GPG7 42 nTRST nTRST I phis 43 TCK TCK 44 TMS TMS 45 TDI TDI 46 TDO TDO O phot6 47 VDDIO VDDIO P vdd3op 48 VSSIO VSSIO vss3op 49 CLKout/GPE0 GPE0 IO phbsu50ct8sm 50 nRESET nRESET I phis 51 OM0 OM0

(1)

52 OM1 OM1 53 OM2 OM2 54 OM3 OM3 55 ENDIAN/CODECLK/GPE8 CODECLK

(1)

phbsu50ct8sm

56 SIOCLK/nCTS1/IISCLK/GPF8 GPF8 57 SIORxD/RxD1/IISDI/GPF7 GPF7 58 SIORDY/TxD1/IISDO/GPF6 GPF6 59 SIOTxD/nRTS1/IISLRCK/GPF5 GPF5 60 IICSDA/GPF1 GPF1 phbsu50cd4sm 61 IICSCL/GPF0 GPF0 62 VDD VDD P vdd2i 63 VSS VSS vss2i 64 XTAL0 XTAL0

65 EXTAL0 EXTAL0 66 PLLCAP PLLCAP

(5)

phsoscm16

(5)

phnc50_option

1-10

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 160-Pin LQFP Pin Assignment (Continued)

Pin No.

Pin Name Default

Function

I/O State

@BUS REQ.

I/O State

@STOP

I/O State

@Initial

I/O TYPE

67 EXTCLK EXTCLK − − I phis 68 TOUT0/GPE3 GPE3 IO phbsu50ct8sm 69 TOUT1/TCLK/GPE4 GPE4 70 TOUT2/TCLK/GPE5 GPE5 71 TOUT3/VD6/GPE6 GPE6 72 TOUT4/VD7/GPE7 GPE7 73 VSSIO VSSIO P vss3op 74 VSSADC VSSADC vss2t 75 AIN0 AIN0

(5) phnc50

AI 76 AIN1 AIN1 77 AIN2 AIN2 78 AIN3 AIN3 79 AIN4 AIN4 80 AIN5 AIN5 81 AIN6 AIN6 82 AIN7 AIN7 83 AREFT AREFT phnc50_option 84 AREFB AREFB 85 AVCOM AVCOM 86 VDDADC VDDADC P vdd2t 87 XTAL1 XTAL1 I phnc50 88 EXTAL1 EXTAL1 O 89 VDDRTC VDDRTC P vdd2t 90 VSSIO VSSIO vss3op 91 VFRAME/GPD7 GPD7 IO phbsu50ct8sm 92 VM/GPD6 GPD6 93 VLINE/GPD5 GPD5 94 VCLK/GPD4 GPD4 95 VD3/GPD3 GPD3 96 VD2/GPD2 GPD2 97 VD1/GPD1 GPD1 98 VD0/GPD0 GPD0

1-11

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-1. 160-Pin LQFP Pin Assignment (Continued)

Pin No.

Pin Name Default

Function

I/O State

@BUS REQ.

I/O State

@STOP

I/O State

@Initial

I/O TYPE

99 RxD0/GPE2 GPE2 − − IO phbsu50ct8sm 100 TxD0/GPE1 GPE1 101 DATA31/nCTS0/GPC15 DATA31 Hi-z/IO Hi-z/IO I(Hi-z) phbsu50ct12sm 102 DATA30/nRTS0/GPC14 DATA30 103 DATA29/RxD1/GPC13 DATA29 104 DATA28/TxD1/GPC12 DATA28 105 DATA27/nCTS1/GPC11 DATA27 106 DATA26/nRTS1/GPC10 DATA26 107 DATA25/nXDREQ1/GPC9 DATA25 108 DATA24/nXDACK1/GPC8 DATA24 109 VDD VDD − − P vdd2i 110 VSS VSS vss2i 111 DATA23/VD4/GPC7 DATA23 Hi-z/IO Hi-z/IO I(Hi-z) phbsu50ct12sm 112 DATA22/VD5/GPC6 DATA22 113 DATA21/VD6/GPC5 DATA21 114 DATA20/VD7/GPC4 DATA20 115 DATA19/IISCLK/GPC3 DATA19 116 DATA18/IISDI/GPC2 DATA18 117 DATA17/IISDO/GPC1 DATA17 118 DATA16/IISLRCK/GPC0 DATA16 119 DATA15 DATA15 Hi-z Hi-z I(Hi-z) 120 DATA14 DATA14 121 DATA13 DATA13 122 DATA12 DATA12 123 DATA11 DATA11 124 DATA10 DATA10 125 VDDIO VDDIO − − P vdd3op 126 VSSIO VSSIO vss3op 127 DATA9 DATA9 Hi-z Hi-z I(Hi-z) phbsu50ct12sm 128 DATA8 DATA8 129 DATA7 DATA7 130 DATA6 DATA6

1-12

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 160-Pin LQFP Pin Assignment (Concluded)

Pin No.

Pin Name Default

Function

I/O State

@BUS REQ.

I/O State

@STOP

I/O State

@Initial

I/O TYPE

131 DATA5 DATA5 Hi-z Hi-z I(Hi-z) phbsu50ct12sm 132 DATA4 DATA4 133 DATA3 DATA3 134 DATA2 DATA2 135 DATA1 DATA1 136 DATA0 DATA0 137 ADDR24/GPA9 ADDR24 Hi-z/O Hi-z/O O phot8 138 VDD VDD − − P vdd2i 139 VSS VSS vss2i 140 ADDR23/GPA8 ADDR23 Hi-z/O Hi-z/O O phot8 141 ADDR22/GPA7 ADDR22 142 ADDR21/GPA6 ADDR21 143 ADDR20/GPA5 ADDR20 144 ADDR19/GPA4 ADDR19 145 ADDR18/GPA3 ADDR18 146 ADDR17/GPA2 ADDR17 147 ADDR16/GPA1 DATA16 148 ADDR15 ADDR15 Hi-z Hi-z 149 ADDR14 ADDR14 150 ADDR13 ADDR13 151 ADDR12 ADDR12 152 VSSIO VSSIO − − P vss3op 153 ADDR11 ADDR11 Hi-z Hi-z O phot8 154 ADDR10 ADDR10 155 ADDR9 ADDR9 156 ADDR8 ADDR8 157 ADDR7 ADDR7 158 ADDR6 ADDR6 159 ADDR5 ADDR5 160 ADDR4 ADDR4

1-13

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-2. 160-Pin FBGA Pin Assignment

Pin No. Pin Name Pin No. Pin Name

A1 ADDR4 C1 ADDR1 A2 ADDR5 C2 ADDR0/GPA0 A3 ADDR6 C3 nCAS0 A4 ADDR10 C4 ADDR8 A5 ADDR13 C5 VSSIO A6 ADDR17/GPA2 C6 ADDR15 A7 ADDR20/GPA5 C7 ADDR21/GPA6 A8 ADDR23/GPA8 C8 ADDR22/GPA7

A9 DATA0 C9 ADDR24/GPA9 A10 DATA4 C10 DATA3 A11 DATA8 C11 DATA7 A12 DATA11 C12 VDDIO A13 DATA12 C13 DATA17/IISDO/GPC1 A14 DATA14 C14 DATA16/IISLRCK/GPC0

B1 ADDR2 D1 nCAS3:nSRAS/GPB3

B2 ADDR3 D2 nCAS2:nSCAS/GPB2

B3 ADDR7 D3 VDDIO

B4 ADDR9 D4 nCAS1

B5 ADDR12 D5 ADDR11

B6 ADDR16/GPA1 D6 ADDR14

B7 ADDR19/GPA4 D7 ADDR18/GPA3

B8 VSS D8 VDD

B9 DATA1 D9 DATA2 B10 DATA5 D10 DATA6 B11 DATA9 D11 VSSIO B12 DATA10 D12 DATA18/IISDI/GPC2 B13 DATA13 D13 DATA19/IISCLK/GPC3 B14 DATA15 D14 DATA20/VD7/GPC4

1-14

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. 160-Pin FBGA Pin Assignment (Continued)

Pin No. Pin Name Pin No. Pin Name

E1 nBE1:nWBE1:DQM1 H1 nGCS4/GPB9 E2 nBE0:nWBE0:DQM0 H2 nGCS5/GPB10 E3 nBE2:nWBE2:DQM2/GPB4 H3 VSS

E4 VSSIO H4 nGCS6:nSCS0:nRAS0 E11 DATA21/VD6/GPC5 H11 VD0/GPD0 E12 DATA22/VD5/GPC6 H12 DATA31/nCTS0/GPC15 E13 DATA23/VD4/GPC7 H13 RxD0/GPE2 E14 VSS H14 TxD0/GPE1

F1 nWE J1 nGCS7:nSCS1:nRAS1 F2 nOE J2 SCKE/GPB0 F3 nGCS0 J3 SCLK/GPB1

F4 nBE3:nWBE3:DQM3/GPB5 J4 nWAIT/GPF2 F11 VDD J11 VCLK/GPD4 F12 DATA24/nXDACK1/GPC8 J12 VD1/GPD1 F13 DATA25/nXDREQ1/GPC9 J13 VD3/GPD3 F14 DATA26/nRTS1/GPC10 J14 VD2/GPD2

G1 nGCS3/GPB8 K1 nXDREQ0/nXBREQ0/GPF4 G2 nGCS2/GPB7 K2 nXDACK0/nXBACK0/GPF3 G3 VDD K3 ExINT0/VD4/GPG0

G4 nGCS1/GPB6 K4 ExINT1/VD5/GPG1 G11 DATA27/nCTS1/GPC11 K11 VSSIO G12 DATA30/nRTS0/GPC14 K12 VLINE/GPD5 G13 DATA28/TxD1/GPC12 K13 VFRAME/GPD7 G14 DATA29/RxD1/GPC13 K14 VM/GPD6

1-15

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-2. 160-Pin FBGA Pin Assignment (Continued)

Pin No. Pin Name Pin No. Pin Name

L1 VDD N1 ExINT5/IISDI/GPG5 L2 VSS N2 ExINT7/IISLRCK/GPG7 L3 ExINT2/nCTS0/GPG2 N3 TMS L4 TDO N4 VDDIO L5 nRESET N5 OM0 L6 OM3 N6 ENDIAN/CODECLK/GPE8 L7 SIORDY/TxD1/IISDO/GPF6 N7 SIOTxD/nRTS1/IISLRCK/GPF5 L8 EXTAL0 N8 XTAL0

L9 TOUT1/TCLK/GPE4 N9 EXTCLK L10 VSSIO N10 TOUT3/VD6/GPE6 L11 VDDADC N11 AIN0 L12 VDDRTC N12 AIN2 L13 XTAL1 N13 AIN6 L14 EXTAL1 N14 AIN7

M1 ExINT4/IISCLK/GPG4 P1 ExINT6/IISDO/GPG6 M2 ExINT3/nRTS0/GPG3 P2 nTRST M3 TDI P3 TCK M4 CLKout/GPE0 P4 VSSIO M5 OM2 P5 OM1 M6 SIORxD/RxD1/IISDI/GPF7 P6 SIOCLK/nCTS1/IISCLK/GPF8 M7 IICSCL/GPF0 P7 IICSDA/GPF1 M8 VDD P8 VSS

M9 TOUT0/GPE3 P9 PLLCAP M10 TOUT4/VD7/GPE7 P10 TOUT2/TCLK/GPE5 M11 AIN1 P11 VSSADC M12 AVCOM P12 AIN3 M13 AREFB P13 AIN4 M14 AREFT P14 AIN5

NOTES :

1. OM[3:0] and ENDIAN value are latched only at the rising edge of nRESET. Therefore, when nRESET is L, the pins of OM[3:0] and ENDIAN are in input state. After nRESET becomes H, the pin of ENDIAN will be in output state.

2. The @BUS REQ. shows the pin states at the external bus, which is used by the other bus master. The @STOP shows the pin states when S3C44B0X is in STOP mode.

3. ' − ' mark indicates the unchanged pin state at STOP mode or Bus released mode.

4. IICSDA,IICSCL pins are open-drain type.

5. AI/AO means analog input/output.

1-16

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

I/O Type Descriptions

vdd2i, vss2i 2.5V Vdd/Vss for internal logic vdd3op, vss3op 3.3V Vdd/Vss for external interface logic vdd2t, vss2t 2.5V Vdd/Vss for analog circuitry phsoscm16 Oscillator cell with enable and feedback resistor phbsu50ct12sm bi-directional pad, CMOS schmitt-trigger, 50K Ω pull-up resistor with control,

tri-state, Io=12mA

phbsu50ct8sm bi-directional pad, CMOS schmitt-trigger, 50K Ω pull-up resistor with control,

tri-state, Io=8mA

phbsu50cd4sm bi-directional pad, CMOS schmitt-trigger, 50K Ω pull-up resistor with control,

tri-state, Io=4mA phot6 output pad, tri-state, Io=6mA phot8 output pad, tri-state, Io=8mA phot10 output pad, tri-state, Io=10mA phis input pad, CMOS schmitt-trigger phnc50, phnc50_option pad for analog pin

1-17

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

SIGNAL DESCRIPTIONS

Table 1-3. S3C44B0X Signal Descriptions

Signal I/O Description

BUS CONTROLLER

OM[1:0] I OM[1:0] sets S3C44B0X in the TEST mode, which is used only at fabrication. Also, it

determines the bus width of nGCS0. The logic level is determined by the pull-up/down resistor during the RESET cycle.

00:8-bit 01:16-bit 10:32-bit 11:Test mode ADDR[24:0] O ADDR[24:0] (Address Bus) outputs the memory address of the corresponding bank . DATA[31:0] IO DATA[31:0] (Data Bus) inputs data during memory read and outputs data during

memory write. The bus width is programmable among 8/16/32-bit. nGCS[7:0] O nGCS[7:0] (General Chip Select) are activated when the address of a memory is within

the address region of each bank. The number of access cycles and the bank size can

be programmed. nWE O nWE (Write Enable) indicates that the current bus cycle is a write cycle.

nWBE[3:0] O Write Byte Enable nBE[3:0] O Upper Byte/Lower Byte Enable(In case of SRAM) nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle.

nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request control of the local

bus. BACK active indicates that bus control has been granted. nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C44B0X has surrendered

control of the local bus to another bus master. nWAIT I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus

cycle cannot be completed. ENDIAN I It determines whether or not the data type is little endian or big endian. The logic level

is determined by the pull-up/down resistor during the RESET cycle.

0:little endian 1:big endian

DRAM/SDRAM/SRAM

nRAS[1:0] O Row Address Strobe nCAS[3:0] O Column Address strobe nSRAS O SDRAM Row Address Strobe nSCAS O SDRAM Column Address Strobe nSCS[1:0] O SDRAM Chip Select DQM[3:0] O SDRAM Data Mask SCLK O SDRAM Clock SCKE O SDRAM Clock Enable

1-18

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-3. S3C44B0X Signal Descriptions (Continued)

Signal I/O Description

LCD CONTROL UNIT

VD[7:0] O LCD Data Bus VFRAME O LCD Frame signal VM O VM alternates the polarity of the row and column voltage VLINE O LCD line signal VCLK O LCD clock signal

TIMER/PWM

TOUT[4:0] O Timer output[4:0] TCLK I External clock input

INTERRUPT CONTROL UNIT

EINT[7:0] I External Interrupt request

DMA

nXDREQ[1:0] I External DMA request nXDACK[1:0] O External DMA acknowledge

UART

RxD[1:0] I UART receives data input TxD[1:0] O UART transmits data output nCTS[1:0] I UART clear to send input signal nRTS[1:0] O UART request to send output signal

IIC-BUS

IICSDA IO IIC-bus data IICSCL IO IIC-bus clock

IIS-BUS

IISLRCK IO IIS-bus channel select clock IISDO O IIS-bus serial data output IISDI I IIS-bus serial data input IISCLK IO IIS-bus serial clock CODECLK O CODEC system clock

SIO

SIORXD I SIO receives data input SIOTXD O SIO transmits data output SIOCK IO SIO clock SIORDY IO SIO handshake signal when DMA completes the SIO operation

1-19

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-3. S3C44B0X Signal Descriptions (Continued)

Signal I/O Description

ADC

AIN[7:0] AI ADC input[7:0] AREFT AI ADC Top Vref AREFB AI ADC Bottom Vref AVCOM AI ADC Common Vref

GENERAL PORT

P[70:0] IO General input/output ports (some ports are output mode only)

RESET & CLOCK

nRESET ST nRESET suspends any operation in progress and places S3C44B0X into a known reset

state. For a reset, nRESET must be held to L level for at least 4 MCLK after the

processor power has been stabilized. OM[3:2] I OM[3:2] determines how the clock is made.

00 = Crystal(XTAL0,EXTAL0), PLL on 01 = EXTCLK, PLL on

10, 11 = Chip test mode. EXTCLK I External clock source when OM[3:2] = 01b

If it isn't used, it has to be H (3.3V). XTAL0 AI Crystal Input for internal osc circuit for system clock.

If it isn't used, XTAL0 has to be H (3.3V). EXTAL0 AO Crystal Output for internal osc circuit for system clock. It is the inverted output of

XTAL0. If it isn't used, it has to be a floating pin. PLLCAP AI Loop filter capacitor for system clock PLL. ( 700pF ) XTAL1 AI 32 KHz crystal input for RTC. EXTAL1 AO 32 KHz crystal output for RTC. It is the inverted output of XTAL1. CLKout O Fout or Fpllo clock

JTAG TEST LOGIC

nTRST I nTRST(TAP Controller Reset) resets the TAP controller at start.

If debugger is used, A 10K pull-up resistor has to be connected.

If debugger(black ICE) is not used, nTRST pin must be at L or low active pulse. TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's

states. A 10K pull-up resistor has to be connected to TMS pin. TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.

A 10K pull-up resistor must be connected to TCK pin. TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data.

A 10K pull-up resistor must be connected to TDI pin. TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and data.

1-20

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-3. S3C44B0X Signal Descriptions (Concluded)

Signal I/O Description

POWER

VDD P S3C44B0X core logic VDD (2.5 V) VSS P S3C44B0X core logic VSS VDDIO P S3C44B0X I/O port VDD (3.3 V) VSSIO P S3C44B0X I/O port VSS RTCVDD P RTC VDD (2.5 V or 3.0 V, Not support 3.3V)

(This pin must be connected to power properly if RTC isn't used) VDDADC P ADC VDD(2.5 V) VSSADC P ADC VSS

1-21

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

S3C44B0X SPECIAL REGISTERS

Table 1-4. S3C44B0X Special Registers

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

CPU WRAPPER

SYSCFG 0x01c00000 ← W R/W System Configuration NCACHBE0 0x01c00004 Non Cacheable Area 0 NCACHBE1 0x01c00008 Non Cacheable Area 1 SBUSCON 0x01c40000 System Bus Control

MEMORY CONTROLLER

BWSCON 0x01c80000 ← W R/W Bus Width & Wait Status Control BANKCON0 0x01c80004 Boot ROM Control BANKCON1 0x01c80008 BANK1 Control BANKCON2 0x01c8000c BANK2 Control BANKCON3 0x01c80010 BANK3 Control BANKCON4 0x01c80014 BANK4 Control BANKCON5 0x01c80018 BANK5 Control BANKCON6 0x01c8001c BANK6 Control BANKCON7 0x01c80020 BANK7 Control REFRESH 0x01c80024 DRAM/SDRAM Refresh Control BANKSIZE 0x01c80028 Flexible Bank Size MRSRB6 0x01c8002c Mode register set for SDRAM MRSRB7 0x01c80030 Mode register set for SDRAM

1-22

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C44B0X Special Registers (Continued)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

UART

ULCON0 0x01d00000 ← W R/W UART 0 Line Control ULCON1 0x01d04000 UART 1 Line Control UCON0 0x01d00004 UART 0 Control UCON1 0x01d04004 UART 1 Control UFCON0 0x01d00008 UART 0 FIFO Control UFCON1 0x01d04008 UART 1 FIFO Control UMCON0 0x01d0000c UART 0 Modem Control UMCON1 0x01d0400c UART 1 Modem Control UTRSTAT0 0x01d00010 R UART 0 Tx/Rx Status UTRSTAT1 0x01d04010 UART 1 Tx/Rx Status UERSTAT0 0x01d00014 UART 0 Rx Error Status UERSTAT1 0x01d04014 UART 1 Rx Error Status UFSTAT0 0x01d00018 UART 0 FIFO Status UFSTAT1 0x01d04018 UART 1 FIFO Status UMSTAT0 0x01d0001c UART 0 Modem Status UMSTAT1 0x01d0401c UART 1 Modem Status UTXH0 0x01d00023 0x01d00020 B W UART 0 Transmission Hold UTXH1 0x01d04023 0x01d04020 UART 1 Transmission Hold URXH0 0x01d00027 0x01d00024 R UART 0 Receive Buffer URXH1 0x01d04027 0x01d04024 UART 1 Receive Buffer UBRDIV0 0x01d00028 ← W R/W UART 0 Baud Rate Divisor UBRDIV1 0x01d04028 UART 1 Baud Rate Divisor

SIO

SIOCON 0x01d14000 ← W R/W SIO Control SIODAT 0x01d14004 SIO Data SBRDR 0x01d14008 SIO Baud Rate Prescaler ITVCNT 0x01d1400c SIO Interval Counter DCNTZ 0x01d14010 SIO DMA Count Zero

1-23

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-4. S3C44B0X Special Registers (Continued)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

IIS

IISCON 0x01d18000,02,03 0x01d18000 B,HW,W R/W IIS Control IISMOD 0x01d18004,06 0x01d18004 HW,W IIS Mode IISPSR 0x01d18008,0a,0b 0x01d18008 B,HW,W IIS Prescaler IISFIFCON 0x01d1800c,0e 0x01d1800c HW,W IIS FIFO Control IISFIF 0x01d18012 0x01d18010 HW IIS FIFO Entry

I/O PORT

PCONA 0x01d20000 ← W R/W Port A Control PDATA 0x01d20004 Port A Data PCONB 0x01d20008 Port B Control PDATB 0x01d2000c Port B Data PCONC 0x01d20010 Port C Control PDATC 0x01d20014 Port C Data PUPC 0x01d20018 Pull-up Control C PCOND 0x01d2001c Port D Control PDATD 0x01d20020 Port D Data PUPD 0x01d20024 Pull-up Control D PCONE 0x01d20028 Port E Control PDATE 0x01d2002c Port E Data PUPE 0x01d20030 Pull-up Control E PCONF 0x01d20034 Port F Control PDATF 0x01d20038 Port F Data PUPF 0x01d2003c Pull-up Control F PCONG 0x01d20040 Port G Control PDATG 0x01d20044 Port G Data PUPG 0x01d20048 Pull-up Control G SPUCR 0x01d2004c Special Pull-up EXTINT 0x01d20050 External Interrupt Control EXTINPND 0x01d20054 External Interrupt Pending

WATCHDOG TIMER

WTCON 0x01d30000 ← W R/W Watchdog Timer Mode WTDAT 0x01d30004 Watchdog Timer Data WTCNT 0x01d30008 Watchdog Timer Count

1-24

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C44B0X Special Registers (Continued)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

A/D CONVERTER

ADCCON 0x01d40000,02,03 0x01d40000 B,HW,W R/W ADC Control ADCPSR 0x01d40004,06,07 0x01d40004 ADC Prescaler ADCDAT 0x01d40008,0a 0x01d40008 HW,W R Digitized 10 bit Data

PWM TIMER

TCFG0 0x01d50000 ← W R/W Timer Configuration TCFG1 0x01d50004 Timer Configuration TCON 0x01d50008 Timer Control TCNTB0 0x01d5000c Timer Count Buffer 0 TCMPB0 0x01d50010 Timer Compare Buffer 0 TCNTO0 0x01d50014 R Timer Count Observation 0 TCNTB1 0x01d50018 R/W Timer Count Buffer 1 TCMPB1 0x01d5001c Timer Compare Buffer 1 TCNTO1 0x01d50020 R Timer Count Observation 1 TCNTB2 0x01d50024 R/W Timer Count Buffer 2 TCMPB2 0x01d50028 Timer Compare Buffer 2 TCNTO2 0x01d5002c R Timer Count Observation 2 TCNTB3 0x01d50030 R/W Timer Count Buffer 3 TCMPB3 0x01d50034 Timer Compare Buffer 3 TCNTO3 0x01d50038 R Timer Count Observation 3 TCNTB4 0x01d5003c R/W Timer Count Buffer 4 TCMPB4 0x01d50040 Timer Compare Buffer 4 TCNTO4 0x01d50044 R Timer Count Observation 4 TCNTB5 0x01d50048 R/W Timer Count Buffer 5 TCNTO5 0x01d5004c R Timer Count Observation 5

IIC

IICCON 0x01d60000 ← W R/W IIC Control IICSTAT 0x01d60004 IIC Status IICADD 0x01d60008 IIC Address IICDS 0x01d6000c IIC Data Shift

1-25

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-4. S3C44B0X Special Registers (Continued)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

RTC

RTCCON 0x01d70043 0x01d70040 B R/W RTC Control RTCALM 0x01d70053 0x01d70050 RTC Alarm ALMSEC 0x01d70057 0x01d70054 Alarm Second ALMMIN 0x01d7005b 0x01d70058 Alarm Minute ALMHOUR 0x01d7005f 0x01d7005c Alarm Hour ALMDAY 0x01d70063 0x01d70060 Alarm Day ALMMON 0x01d70067 0x01d70064 Alarm Month ALMYEAR 0x01d7006b 0x01d70068 Alarm Year RTCRST 0x01d7006f 0x01d7006c RTC Round Reset BCDSEC 0x01d70073 0x01d70070 BCD Second BCDMIN 0x01d70077 0x01d70074 BCD Minute BCDHOUR 0x01d7007b 0x01d70078 BCD Hour BCDDAY 0x01d7007f 0x01d7007c BCD Day BCDDATE 0x01d70083 0x01d70080 BCD Date BCDMON 0x01d70087 0x01d70084 BCD Month

Function

BCDYEAR 0x01d7008b 0x01d70088 BCD Year TICINT 0x01D7008E 0x01D7008C Tick time count

CLOCK & POWER MANAGEMENT

PLLCON 0x01d80000 ← W R/W PLL Control CLKCON 0x01d80004 Clock Control CLKSLOW 0x01d80008 Slow clock Control LOCKTIME 0x01d8000c PLL lock time Counter

1-26

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C44B0X Special Registers (Continued)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

INTERRUPT CONTROLLER

INTCON 0x01e00000 ← W R/W Interrupt Control INTPND 0x01e00004 R Interrupt Request Status INTMOD 0x01e00008 R/W Interrupt Mode Control INTMSK 0x01e0000c Interrupt Mask Control I_PSLV 0x01e00010 IRQ Interrupt Previous Slave I_PMST 0x01e00014 IRQ Interrupt Priority Master I_CSLV 0x01e00018 R IRQ Interrupt Current Slave I_CMST 0x01e0001c IRQ Interrupt Current Master I_ISPR 0x01e00020 IRQ Interrupt Pending Status I_ISPC 0x01e00024 W IRQ Interrupt Pending Clear F_ISPR 0x01e00038 R FIQ Interrupt Pending F_ISPC 0x01e0003c W FIQ Interrupt Pending Clear

LCD CONTROLLER

LCDCON1 0x01f00000 ← W R/W LCD Control 1 LCDCON2 0x01f00004 LCD Control 2 LCDCON3 0x01f00040 LCD Control 3 LCDSADDR1 0x01f00008 Frame Upper Buffer Start Address 1 LCDSADDR2 0x01f0000c Frame Lower Buffer Start Address 2 LCDSADDR3 0x01f00010 Virtual Screen Address REDLUT 0x01f00014 RED Lookup Table GREENLUT 0x01f00018 GREEN Lookup Table BLUELUT 0x01f0001c BLUE Lookup Table DP1_2 0x01f00020 Dithering Pattern duty 1/2 DP4_7 0x01f00024 Dithering Pattern duty 4/7 DP3_5 0x01f00028 Dithering Pattern duty 3/5 DP2_3 0x01f0002c Dithering Pattern duty 2/3 DP5_7 0x01f00030 Dithering Pattern duty 5/7 DP3_4 0x01f00034 Dithering Pattern duty 3/4 DP4_5 0x01f00038 Dithering Pattern duty 4/5 DP6_7 0x01f0003c Dithering Pattern duty 6/7 DITHMODE 0x01f00044 Dithering Mode

1-27

PRODUCT OVERVIEW S3C44B0X RISC MICROPROCESSOR

Table 1-4. S3C44B0X Special Registers (Concluded)

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/W

rite

Function

DMA

ZDCON0 0x01e80000 ← W R/W ZDMA0 Control ZDISRC0 0x01e80004 ZDMA 0 Initial Source Address ZDIDES0 0x01e80008 ZDMA 0 Initial Destination Address ZDICNT0 0x01e8000c ZDMA 0 Initial Transfer Count ZDCSRC0 0x01e80010 R ZDMA 0 Current Source Address ZDCDES0 0x01e80014 ZDMA 0 Current Destination Address ZDCCNT0 0x01e80018 ZDMA 0 Current Transfer Count ZDCON1 0x01e80020 R/W ZDMA 1 Control ZDISRC1 0x01e80024 ZDMA 1 Initial Source Address ZDIDES1 0x01e80028 ZDMA 1 Initial Destination Address ZDICNT1 0x01e8002c ZDMA 1 Initial Transfer Count ZDCSRC1 0x01e80030 R ZDMA 1 Current Source Address ZDCDES1 0x01e80034 ZDMA 1 Current Destination Address ZDCCNT1 0x01e80038 ZDMA 1 Current Transfer Count BDCON0 0x01f80000 R/W BDMA 0 Control BDISRC0 0x01f80004 BDMA 0 Initial Source Address BDIDES0 0x01f80008 BDMA 0 Initial Destination Address BDICNT0 0x01f8000c BDMA 0 Initial Transfer Count BDCSRC0 0x01f80010 R BDMA 0 Current Source Address BDCDES0 0x01f80014 BDMA 0 Current Destination Address BDCCNT0 0x01f80018 BDMA 0 Current Transfer Count BDCON1 0x01f80020 R/W BDMA 1 Control BDISRC1 0x01f80024 BDMA 1 Initial Source Address BDIDES1 0x01f80028 BDMA 1 Initial Destination Address BDICNT1 0x01f8002c BDMA 1 Initial Transfer Count BDCSRC1 0x01f80030 R BDMA 1 Current Source Address BDCDES1 0x01f80034 BDMA 1 Current Destination Address BDCCNT1 0x01f80038 BDMA 1 Current Transfer Count

1-28

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW

IMPORTANT NOTES ABOUT S3C44B0X SPECIAL REGISTERS

1. In the little endian mode, L. endian address must be used. In the big endian mode, B. endian address must be used.

2. The special registers have to be accessed by the recommended access unit.

3. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit) at little/big endian.

4. It is very important that the ADC registers, RTC registers and UART registers be read/written by the specified

access unit and the specified address. Moreover, one must carefully consider which endian mode is used.

5. W: 32-bit register, which must be accessed by LDR/STR or int type pointer(int *).

HW: 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *). B: 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char *).

1-29

S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL

2 PROGRAMMER'S MODEL

OVERVIEW

S3C44B0X has been developed using the advanced ARM7TDMI core, which has been designed by Advanced RISC Machines, Ltd.

PROCESSOR OPERATING STATES

From the programmer's point of view, the ARM7TDMI can be in one of two states:

• ARM state which executes 32-bit, word-aligned ARM instructions.

• THUMB state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1

to select between alternate halfwords.

NOTE

Transition between these two states does not affect the processor mode or the contents of the registers.

SWITCHING STATE Entering THUMB State

Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand register.

Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the processor in THUMB state.

Entering ARM State

Entry into ARM state happens:

• On execution of the BX instruction with the state bit clear in the operand register.

• On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is

placed in the exception mode's link register, and execution commences at the exception's vector address.

MEMORY FORMATS

ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM7TDMI can treat words in memory as being stored either in Big-Endian or Little-Endian format.

2-1

PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR

BIG-ENDIAN FORMAT

In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.

Higher Address

Lower Address

31 8

4 0

Most significant byte is at lowest address. Word is addressed by byte address of most significant byte.

24 1516

9 5 1

10 6 2

8 7 0

11 7 3

Word Address

8 4 0

Figure 2-1. Big-Endian Addresses of Bytes within Words

LITTLE-ENDIAN FORMAT

In Little-Endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0.

Higher Address

31 23 8 7 0

24 1516

Word Address

8 4 0

Lower Address

11 7 3

Least significant byte is at lowest address. Word is addressed by byte address of least significant byte.

10 6 2

9 5 1

8 4 0

Figure 2-2. Little-Endian Addresses of Bytes whthin Words

INSTRUCTION LENGTH

Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).

Data Types

ARM7TDMI supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to fourbyte boundaries and half words to two-byte boundaries.

2-2

S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL

OPERATING MODES

ARM7TDMI supports seven modes of operation:

• User (usr): The normal ARM program execution state

• FIQ (fiq): Designed to support a data transfer or channel process

• IRQ (irq): Used for general-purpose interrupt handling

• Supervisor (svc): Protected mode for the operating system

• Abort mode (abt): Entered after a data or instruction prefetch abort

• System (sys): A privileged user mode for the operating system

• Undefined (und): Entered when an undefined instruction is executed

Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes' known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources.

REGISTERS

ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer.

The ARM State Register Set

In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (nonUser) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle.

The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information.

and Link (BL) instruction is executed. At all other times it may be treated as a general-purpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when Branch and Link instructions are executed within interrupt or exception routines.

[31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC.

and the current mode bits.

FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.

2-3

PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR

ARM State General Registers and Program Counter

System & User

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC)

CPSR CPSR

FIQ

R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC)

Supervisor IRQAbort Undefined

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC)

ARM State Program Status Registers

CPSR

SPSR_abt

SPSR_fiq

CPSR

SPSR_svc

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC)

CPSR

SPSR_irq

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC)

CPSR

SPSR_und

2-4

= banked register

Figure 2-3. Register Organization in ARM State

S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL

The THUMB State Register Set

The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4.

THUMB State General Registers and Program Counter

System & User

R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC

CPSR CPSR

= banked register

FIQ

R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC

Supervisor IRQAbort Undefined

R0 R1 R2 R3 R4 R5 R6 R7 SP_svc LR_svc PC

R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt PC

THUMB State Program Status Registers

SPSR_fiq

CPSR

SPSR_svc

CPSR

SPSR_abt

R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC

CPSR

SPSR_irq

R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC

CPSR

SPSR_und

Figure 2-4. Register Organization in THUMB State

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PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR

Lo-registersHi-registers

The relationship between ARM and THUMB state registers

The THUMB state registers relate to the ARM state registers in the following way:

• THUMB state R0-R7 and ARM state R0-R7 are identical

• THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical

• THUMB state SP maps onto ARM state R13

• THUMB state LR maps onto ARM state R14

• The THUMB state Program Counter maps onto the ARM state Program Counter (R15)

This relationship is shown in Figure 2-5.

THUMB state ARM state

R0 R1 R2 R3 R4 R5 R6 R7

Stack Pointer (SP)

Link register (LR)

Program Counter (PC)

CPSR SPSR

R0 R1 R2 R3 R4 R5 R6 R7 R8

R9 R10 R11 R12

Stack Pointer (R13)

Link register (R14)

Program Counter (R15)

CPSR SPSR

2-6

Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers

S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL

Accessing Hi-Registers in THUMB State

In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage.

A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register, and from a Hi register to a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions. For more information, refer to Figure 3-34.

THE PROGRAM STATUS REGISTERS

The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These register's functions are:

• Hold information about the most recently performed ALU operation

• Control the enabling and disabling of interrupts

• Set the processor operating mode

The arrangement of bits is shown in Figure 2-6.

Condition Code Flags

30 29 2728 26 25 24 23 8 7 6 5 4 3 2 1 0

N Z C V I F T M4 M3 M2 M1 M0

Overflow Carry/Borrow/Extend Zero Negative/Less Than

(Reserved) Control Bits

Mode bits State bit FIQ disable IRQ disable

Figure 2-6. Program Status Register Format

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PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR

The Condition Code Flags

The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed.

In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details.

The Control Bits

The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will be changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software.

The T bit

This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal.

Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state.

Interrupt disable bits

The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively.

The mode bits

The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor's operating mode, as shown in Table 2-1. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied.

Reserved bits The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits,

you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.

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S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL

Table 2-1. PSR Mode Bit Values

M[4:0] Mode Visible THUMB state registers Visible ARM state registers

10000 User R7..R0,

LR, SP

R14..R0, PC, CPSR

PC, CPSR

10001 FIQ R7..R0,

LR_fiq, SP_fiq PC, CPSR, SPSR_fiq

10010 IRQ R7..R0,

LR_irq, SP_irq PC, CPSR, SPSR_irq

10011 Supervisor R7..R0,

LR_svc, SP_svc, PC, CPSR, SPSR_svc

10111 Abort R7..R0,

LR_abt, SP_abt, PC, CPSR, SPSR_abt

11011 Undefined R7..R0

LR_und, SP_und, PC, CPSR, SPSR_und

11111 System R7..R0,

LR, SP

R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq

R12..R0, R14_irq, R13_irq, PC, CPSR, SPSR_irq

R12..R0, R14_svc, R13_svc, PC, CPSR, SPSR_svc

R12..R0, R14_abt, R13_abt, PC, CPSR, SPSR_abt

R12..R0, R14_und, R13_und, PC, CPSR

R14..R0, PC, CPSR

PC, CPSR

Reserved bits The remaining bits in the PSR's are reserved. When changing a PSR's flag or control bits,

you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.

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PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR

EXCEPTIONS

Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished.

It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order. See Exception Priorities on page 2-14.

Action on Entering an Exception

When handling an exception, the ARM7TDMI:

1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from THUMB state, then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception. This means that the exception handler need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC, R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state.

2. Copies the CPSR into the appropriate SPSR

3. Forces the CPSR mode bits to a value which depends on the exception

4. Forces the PC to fetch the next instruction from the relevant exception vector

It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions. If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the

PC is loaded with the exception vector address.

Action on Leaving an Exception

On completion, the exception handler:

1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the type of exception.)

2. Copies the SPSR back to the CPSR

3. Clears the interrupt disable flags, if they were set on entry

NOTE

An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception.

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S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL

Exception Entry/Exit Summary

Table 2-2 summarises the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler.

Table 2-2. Exception Entry/Exit

Return Instruction Previous State Notes

ARM R14_x THUMB R14_x

BL MOV PC, R14 PC + 4 PC + 2 1 SWI MOVS PC, R14_svc PC + 4 PC + 2 1 UDEF MOVS PC, R14_und PC + 4 PC + 2 1 FIQ SUBS PC, R14_fiq, #4 PC + 4 PC + 4 2 IRQ SUBS PC, R14_irq, #4 PC + 4 PC + 4 2 PABT SUBS PC, R14_abt, #4 PC + 4 PC + 4 1 DABT SUBS PC, R14_abt, #8 PC + 8 PC + 8 3 RESET NA – – 4

NOTES:

1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort.

2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority.

3. Where PC is the address of the Load or Store instruction which generated the data abort.

4. The value saved in R14_svc upon reset is unpredictable.

FIQ

The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM state has sufficient private registers to remove the need for register saving (thus minimising the overhead of context switching).

FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow.

Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt by executing

SUBS PC,R14_fiq,#4

FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is clear, ARM7TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction.

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PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR

IRQ

The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode.

Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the interrupt by executing

SUBS PC,R14_irq,#4

Abort

An abort indicates that the current memory access cannot be completed. It can be signalled by the external ABORT input. ARM7TDMI checks for the abort exception during memory access cycles.

There are two types of abort:

• Prefetch abort: occurs during an instruction prefetch.

• Data abort: occurs during a data access.

If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. If the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place.

If a data abort occurs, the action taken depends on the instruction type:

• Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be

aware of this.

• The swap instruction (SWP) is aborted as though it had not been executed.

• Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the

instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last register to be transferred) is preserved in an aborted LDM instruction.

The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. The application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort.

After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb):

SUBS PC,R14_abt,#4 ; for a prefetch abort, or SUBS PC,R14_abt,#8 ; for a data abort

This restores both the PC and the CPSR, and retries the aborted instruction.

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S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL

Software Interrupt

The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb):

MOV PC,R14_svc

This restores the PC and CPSR, and returns to the instruction following the SWI.

NOTE

nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM7TDMI CPU core.

Undefined Instruction

When ARM7TDMI comes across an instruction which it cannot handle, it takes the undefined instruction trap. This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation.

After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or Thumb):

MOVS PC,R14_und

This restores the CPSR and returns to the instruction following the undefined instruction.

Exception Vectors

The following table shows the exception vector addresses.

Table 2-3. Exception Vectors

Address Exception Mode in Entry

0x00000000 Reset Supervisor 0x00000004 Undefined instruction Undefined 0x00000008 Software Interrupt Supervisor

0x0000000C Abort (prefetch) Abort

0x00000010 Abort (data) Abort 0x00000014 Reserved Reserved 0x00000018 IRQ IRQ

0x0000001C FIQ FIQ

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PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR

Exception Priorites

When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled:

Highest priority:

1. Reset

2. Data abort

3. FIQ

4. IRQ

5. Prefetch abort

Lowest priority:

6. Undefined Instruction, Software interrupt.

Not All Exceptions Can Occur at Once:

Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decodings of the current instruction.

If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM7TDMI enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations.

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S3C44B0X RISC MICROPROCESSOR PROGRAMMER'S MODEL

INTERRUPT LATENCIES

The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM7TDMI will be executing the instruction at 0x1C.

Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser (Tsyncmin) plus Tfiq. This is 4 processor cycles.

RESET

When the nRESET signal goes LOW, ARM7TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses.

When nRESET goes HIGH again, ARM7TDMI:

1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined.

2. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit.

3. Forces the PC to fetch the next instruction from address 0x00.

4. Execution resumes in ARM state.

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PROGRAMMER'S MODEL S3C44B0X RISC MICROPROCESSOR

NOTES

2-16

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

3 INSTRUCTION SET

INSTRUCTION SET SUMMAY

This chapter describes the ARM instruction set and the THUMB instruction set in the ARM7TDMI core.

FORMAT SUMMARY

The ARM instruction set formats are shown below.

27 26 25 24 23 22 2120191817 16 15 1314 12 11 1031 30 29 28 9 8 7 6 5 4 3 2 1 0

Cond Rn Data/Processing/

Cond Cond Cond Cond Cond

Cond

Cond Cond Cond Cond Cond

Cond

0 0 I S

0 0 0 0 00 A S

0 0 0 0 0 01 B

0 0 0 P U 0 W L

0 0 0 P U 1 W L

0 1 I P U B W L 0 1 I 1 0 0 P U B W L 1 0 L1 1 1 0 P U B W L

1 1 01

1 1 01 L

1 1 11

Opcode

1 00 010 0 0

CP Opc

Opc

A SU10 0 00

RdHi RdLo

11 11 1 1 11

CRn

Offset

CRd

Ignored by processor

Operand2

Rs Rn

Offset

CP#

PSR Transfer

Offset

CRm

Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer:

immendiate offset Single Data Transfer

Undefined Block Data Transfer Branch Coprocessor Data Transfer

Coprocessor Data Operation

Coprocessor Register Transfer

Software Interrupt

27 26 25 24 23 22 21 20 19 18 17 16 15 1314 12 11 1031 30 29 28 9 8 7 6 5 4 3 2 1 0

Figure 3-1. ARM Instruction Set Format

3-1

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

NOTE

Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations.

INSTRUCTION SUMMARY

Table 3-1. The ARM Instruction Set

Mnemonic Instruction Action

ADC Add with carry Rd: = Rn + Op2 + Carry ADD Add Rd: = Rn + Op2 AND AND Rd: = Rn AND Op2 B Branch R15: = address BIC Bit Clear Rd: = Rn AND NOT Op2 BL Branch with Link R14: = R15, R15: = address BX Branch and Exchange R15: = Rn, T bit: = Rn[0] CDP Coprocessor Data Processing (Coprocessor-specific) CMN Compare Negative CPSR flags: = Rn + Op2 CMP Compare CPSR flags: = Rn - Op2 EOR Exclusive OR Rd: = (Rn AND NOT Op2)

OR (Op2 AND NOT Rn) LDC Load coprocessor from memory Coprocessor load LDM Load multiple registers Stack manipulation (Pop) LDR Load register from memory Rd: = (address) MCR Move CPU register to coprocessor

cRn: = rRn {<op>cRm}

MLA Multiply Accumulate

Rd: = (Rm × Rs) + Rn MOV Move register or constant Rd: = Op2

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

Table 3-1. The ARM Instruction Set (Continued)

Mnemonic Instruction Action

MRC Move from coprocessor register to

Rn: = cRn {<op>cRm}

CPU register MRS Move PSR status/flags to register Rn: = PSR MSR Move register to PSR status/flags PSR: = Rm MUL Multiply MVN Move negative register

Rd: = Rm × Rs

Rd: = 0 × FFFFFFFF EOR Op2 ORR OR Rd: = Rn OR Op2 RSB Reverse Subtract Rd: = Op2 - Rn RSC Reverse Subtract with Carry Rd: = Op2 - Rn - 1 + Carry SBC Subtract with Carry Rd: = Rn - Op2 - 1 + Carry STC Store coprocessor register to memory address: = CRn STM Store Multiple Stack manipulation (Push) STR Store register to memory <address>: = Rd SUB Subtract Rd: = Rn - Op2 SWI Software Interrupt OS call SWP Swap register with memory Rd: = [Rn], [Rn] := Rm TEQ Test bitwise equality CPSR flags: = Rn EOR Op2 TST Test bits CPSR flags: = Rn AND Op2

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

THE CONDITION FIELD

In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored.

There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which means the Branch will only be taken if the Z flag is set.

In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved, and must not be used.

In the absence of a suffix, the condition field of most instructions is set to "Always" (suffix AL). This means the instruction will always be executed regardless of the CPSR condition codes.

Table 3-2. Condition Code Summary

Code Suffix Flags Meaning

0000 EQ Z set equal 0001 NE Z clear not equal 0010 CS C set unsigned higher or same 0011 CC C clear unsigned lower 0100 MI N set negative 0101 PL N clear positive or zero 0110 VS V set overflow 0111 VC V clear no overflow 1000 HI C set and Z clear unsigned higher 1001 LS C clear or Z set unsigned lower or same 1010 GE N equals V greater or equal 1011 LT N not equal to V less than 1100 GT Z clear AND (N equals V) greater than 1101 LE Z set OR (N not equal to V) less than or equal 1110 AL (ignored) always

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

BRANCH AND EXCHANGE (BX)

This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter,

PC. The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the instruction stream will be decoded as ARM or THUMB instructions.

31 2427 19 15 8 7 0

28 16 111223 20 4 3

Cond Rn

00 0 1 10 0 0 11 1 1 11 1 1 11 1 1 00 0 1

[3:0] Operand Register

If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions If bit0 of Rn =0, subsequent instructions decoded as ARM instructions

[31:28] Condition Field

Figure 3-2. Branch and Exchange Instructions

INSTRUCTION CYCLE TIMES

The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and nonsequential (N-cycle), respectively.

ASSEMBLER SYNTAX

BX - branch and exchange. BX {cond} Rn

{cond} Two character condition mnemonic. See Table 3-2. Rn is an expression evaluating to a valid register number.

USING R15 AS AN OPERAND

If R15 is used as an operand, the behavior is undefined.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

Examples

ADR R0, Into_THUMB + 1 ; Generate branch target address

; and set bit 0 high - hence ; arrive in THUMB state.

BX R0 ; Branch and change to THUMB

; state. CODE16 ; Assemble subsequent code as Into_THUMB ; THUMB instructions

•

ADR R5, Back_to_ARM ; Generate branch target to word aligned address

; - hence bit 0 is low and so change back to ARM state. BX R5 ; Branch and change back to ARM state.

•

ALIGN ; Word align CODE32 ; Assemble subsequent code as ARM instructions Back_to_ARM

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

BRANCH AND BRANCH WITH LINK (B, BL)

The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below.

31 2427

28 23

Cond Offset

101

[24] Link bit

0 = Branch 1 = Branch with link

[31:28] Condition Field

Figure 3-3. Branch Instructions

Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction.

Branches beyond +/- 32Mbytes must use an offset or absolute destination which has been previously loaded into a register. In this case the PC should be manually saved in R14 if a Branch with Link type operation is required.

THE LINK BIT

Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the PC and R14[1:0] are always cleared.

To return from a routine called by Branch with Link use MOV PC,R14 if the link register is still valid or LDM Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn.

INSTRUCTION CYCLE TIMES

Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S and N are defined as sequential (S-cycle) and internal (I-cycle).

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

ASSEMBLER SYNTAX

Items in {} are optional. Items in <> must be present. B{L}{cond} <expression> {L} Used to request the Branch with Link form of the instruction. If absent, R14 will not be

affected by the instruction.

{cond} A two-character mnemonic as shown in Table 3-2. If absent then AL (ALways) will be

used.

<expression> The destination. The assembler calculates the offset.

EXAMPLES

here BAL here ; Assembles to 0xEAFFFFFE (note effect of PC offset).

B there ; Always condition used as default. CMP R1,#0 ; Compare R1 with zero and branch to fred

; if R1 was zero, otherwise continue. BEQ fred ; Continue to next instruction. BL sub+ROM ; Call subroutine at computed address. ADDS R1,#1 ; Add 1 to register 1, setting CPSR flags

; on the result then call subroutine if BLCC sub ; the C flag is clear, which will be the

; case unless R1 held 0xFFFFFFFF.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

DATA PROCESSING

The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4.

31 2427 19 15

28 16 111221

26 25

Cond Operand2

00 L20OpCode S Rn Rd

[15:12] Destination register

0 = Branch 1 = Branch with link

[19:16] 1st operand register

0 = Branch 1 = Branch with link

[20] Set condition codes

0 = Do not after condition codes 1 = Set condition codes

[24:21] Operation codes

0000 = AND-Rd: = Op1 AND Op2 0001 = EOR-Rd: = Op1 EOR Op2 0010 = SUB-Rd: = Op1-Op2 0011 = RSB-Rd: = Op2-Op1 0100 = ADD-Rd: = Op1+Op2 0101 = ADC-Rd: = Op1+Op2+C 0110 = SBC-Rd: = OP1-Op2+C-1 0111 = RSC-Rd: = Op2-Op1+C-1 1000 = TST-set condition codes on Op1 AND Op2 1001 = TEO-set condition codes on OP1 EOR Op2 1010 = CMP-set condition codes on Op1-Op2 1011 = SMN-set condition codes on Op1+Op2 1100 = ORR-Rd: = Op1 OR Op2 1101 = MOV-Rd: =Op2 1110 = BIC-Rd: = Op1 AND NOT Op2 1111 = MVN-Rd: = NOT Op2

[25] Immediate operand

0 = Operand 2 is a register 1 = Operand 2 is an immediate value

[11:0] Operand 2 type selection

311 04

Shift

[3:0] 2nd operand register [11:4] Shift applied to Rm

811 07

Rotate

[7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm

Imm

[31:28] Condition field

Figure 3-4. Data Processing Instructions

3-9

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn).

The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the S bit in the instruction.

Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in Table 3-3.

3-10

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

CPSR FLAGS

The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result.

Table 3-3. ARM Data Processing Instructions

Assembler Mnemonic OP Code Action

AND 0000 Operand1 AND operand2 EOR 0001 Operand1 EOR operand2

WUB 0010 Operand1 - operand2

RSB 0011 Operand2 operand1 ADD 0100 Operand1 + operand2 ADC 0101 Operand1 + operand2 + carry SBC 0110 Operand1 - operand2 + carry - 1 RSC 0111 Operand2 - operand1 + carry - 1

TST 1000 As AND, but result is not written

TEQ 1001 As EOR, but result is not written CMP 1010 As SUB, but result is not written CMN 1011 As ADD, but result is not written ORR 1100 Operand1 OR operand2 MOV 1101 Operand2 (operand1 is ignored)

BIC 1110 Operand1 AND NOT operand2 (Bit clear)

MVN 1111 NOT operand2 (operand1 is ignored)

The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed).

3-11

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

SHIFTS

When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than R15). The encoding for the different shift types is shown in Figure 3-5.

456711

[6:5] Shift type

00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right

[11:7] Shift amount

5 bit unsigned integer

0RS

[6:5] Shift type

00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right

[11:8] Shift register

Shift amount specified in bottom-byte of Rs

456711 8

Figure 3-5. ARM Shift Operations

Instruction specified shift amount

When the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. A logical shift left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class (see above). For example, the effect of LSL #5 is shown in Figure 3-6.

31 27 26

Contents of Rm

carry out

Value of Operand 2

Figure 3-6. Logical Shift Left

NOTE

LSL #0 is a special case, where the shifter carry out is the old value of the CPSR C flag. The contents of Rm are used directly as the second operand. A logical shift right (LSR) is similar, but the contents of Rm are moved to less significant positions in the result. LSR #5 has the effect shown in Figure 3-7.

3-12

000000

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

Contents of Rm

00000

Value of Operand 2

carry out

Figure 3-7. Logical Shift Right

The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified.

An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown in Figure 3-8.

4530

Contents of Rm

Value of Operand 2

carry out

Figure 3-8. Arithmetic Shift Right

The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to the value of bit 31 of Rm.

3-13

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9.

Contents of Rm

Value of Operand 2

carry out

Figure 3-9. Rotate Right

The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3-10.

Contents of Rm

carry out

3-14

Value of Operand 2

Figure 3-10. Rotate Right Extended

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15.

If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output.

If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation.

If the value in the byte is 32 or more, the result will be a logical extension of the shift described above:

1. LSL by 32 has result zero, carry out equal to bit 0 of Rm.

2. LSL by more than 32 has result zero, carry out zero.

3. LSR by 32 has result zero, carry out equal to bit 31 of Rm.

4. LSR by more than 32 has result zero, carry out zero.

5. ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm.

6. ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm.

7. ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above.

NOTE

The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction.

3-15

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

IMMEDIATE OPERAND ROTATES

The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. This enables many common constants to be generated, for example all powers of 2.

WRITING TO R15

When Rd is a register other than R15, the condition code flags in the CPSR may be updated from the ALU flags as described above.

When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected.

When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR. This allows state changes which atomically restore both PC and CPSR. This form of instruction should not be used in User mode.

USING R15 AS AN OPERANDY

If R15 (the PC) is used as an operand in a data processing instruction the register is used directly. The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift

amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount the PC will be 12 bytes ahead.

TEQ, TST, CMP AND CMN OPCODES

NOTE

TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in the CPSR. An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic.

The TEQP form of the TEQ instruction used in earlier ARM processors must not be used: the PSR transfer operations should be used instead.

The action of TEQP in the ARM7TDMI is to move SPSR_<mode> to the CPSR if the processor is in a privileged mode and to do nothing if in User mode.

INSTRUCTION CYCLE TIMES

Data Processing instructions vary in the number of incremental cycles taken as follows:

Table 3-4. Incremental Cycle Times

Processing Type Cycles

Normal data processing 1S Data processing with register specified shift 1S + 1I Data processing with PC written 2S + 1N Data processing with register specified shift and PC written 2S + 1N +1I

NOTE: S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively.

3-16

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

ASSEMBLER SYNTAX

•• MOV,MVN (single operand instructions).

•• CMP,CMN,TEQ,TST (instructions which do not produce a result).

•• AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC

where: <Op2> Rm{,<shift>} or,<#expression> {cond} A two-character condition mnemonic. See Table 3-2. {S} Set condition codes if S present (implied for CMP, CMN, TEQ, TST). Rd, Rn and Rm Expressions evaluating to a register number. <#expression> If this is used, the assembler will attempt to generate a shifted immediate 8-bit field to

match the expression. If this is impossible, it will give an error.

<shift> <Shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit with

extend).

<shiftname>s ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL, they assemble to the same

code.)

EXAMPLES

ADDEQ R2,R4,R5 ; If the Z flag is set make R2:=R4+R5 TEQS R4,#3 ; Test R4 for equality with 3.

; (The S is in fact redundant as the ; assembler inserts it automatically.)

SUB R4,R5,R7,LSR R2 ; Logical right shift R7 by the number in

; the bottom byte of R2, subtract result

; from R5, and put the answer into R4. MOV PC,R14 ; Return from subroutine. MOVS PC,R14 ; Return from exception and restore CPSR

; from SPSR_mode.

3-17

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

PSR TRANSFER (MRS, MSR)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are

implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11.

These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the CPSR or SPSR_<mode> to be moved to a general register. The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR_<mode> register.

The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags (N,Z,C and V) of CPSR or SPSR_<mode> without affecting the control bits. In this case, the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR.

OPERAND RESTRICTIONS

•• In user mode, the control bits of the CPSR are protected from change, so only the condition code flags of the

CPSR can be changed. In other (privileged) modes the entire CPSR can be changed.

•• Note that the software must never change the state of the T bit in the CPSR. If this happens, the processor

will enter an unpredictable state.

•• The SPSR register which is accessed depends on the mode at the time of execution. For example, only

SPSR_fiq is accessible when the processor is in FIQ mode.

•• You must not specify R15 as the source or destination register.

•• Also, do not attempt to access an SPSR in User mode, since no such register exists.

3-18

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

MRS (transfer PSR contents to a register)

31 2227 1528 16 11122123

Cond 000000000000

00010 Rd

001111

[15:21] Destination Register [19:16] Source PSR

0 = CPSR 1 = SPSR_<current mode>

[31:28] Condition Field

MRS (transfer register contents to PSR)

31 222728 11122123

Cond 00000000

00010

101001111

4 3 0

[3:0] Source Register [22] Destination PSR

0 = CPSR 1 = SPSR_<current mode>

[31:28] Condition Field

MRS (transfer register contents or immediate value to PSR flag bits only)

31 222728 11122123

Cond Source operand

26 25 24 0

I 1000

101001111

[22] Destination PSR

0 = CPSR 1 = SPSR_<current mode>

[25] Immediate Operand

0 = Source operand is a register 1 = SPSR_<current mode>

[11:0] Source Operand

11 4 3 0

00000000 Rm

[3:0] Source Register [11:4] Source operand is an immediate value

11 08 7

Rotate Imm

[7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm

[31:28] Condition Field

Figure 3-11. PSR Transfer

3-19

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

RESERVED BITS

Only twelve bits of the PSR are defined in ARM7TDMI (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits.

To ensure the maximum compatibility between ARM7TDMI programs and future processors, the following rules should be observed:

• The reserved bits should be preserved when changing the value in a PSR.

• Programs should not rely on specific values from the reserved bits when checking the PSR status, since they

may read as one or zero in future processors.

A read-modify-write strategy should therefore be used when altering the control bits of any PSR register; this involves transferring the appropriate PSR register to a general register using the MRS instruction, changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction.

EXAMPLES

The following sequence performs a mode change:

MRS R0,CPSR ; Take a copy of the CPSR. BIC R0,R0,#0x1F ; Clear the mode bits. ORR R0,R0,#new_mode ; Select new mode MSR CPSR,R0 ; Write back the modified CPSR.

When the aim is simply to change the condition code flags in a PSR, a value can be written directly to the flag bits without disturbing the control bits. The following instruction sets the N,Z,C and V flags:

MSR CPSR_flg,#0xF0000000 ; Set all the flags regardless of their previous state

; (does not affect any control bits).

No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits.

INSTRUCTION CYCLE TIMES

PSR transfers take 1S incremental cycles, where S is defined as Sequential (S-cycle).

3-20

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

ASSEMBLY SYNTAX

•• MRS - transfer PSR contents to a register

MRS{cond} Rd,<psr>

•• MSR - transfer register contents to PSR

MSR{cond} <psr>,Rm

•• MSR - transfer register contents to PSR flag bits only

MSR{cond} <psrf>,Rm

The most significant four bits of the register contents are written to the N,Z,C & V flags respectively.

•• MSR - transfer immediate value to PSR flag bits only

MSR{cond} <psrf>,<#expression>

The expression should symbolise a 32 bit value of which the most significant four bits are written to the N,Z,C and V flags respectively.

Key:

{cond} Two-character condition mnemonic. See Table 3-2.. Rd and Rm Expressions evaluating to a register number other than R15 <psr> CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are synonyms as are SPSR

and SPSR_all) <psrf> CPSR_flg or SPSR_flg <#expression> Where this is used, the assembler will attempt to generate a shifted immediate 8-bit field

to match the expression. If this is impossible, it will give an error.

EXAMPLES

In User mode the instructions behave as follows:

MSR CPSR_all,Rm ; CPSR[31:28] <- Rm[31:28] MSR CPSR_flg,Rm ; CPSR[31:28] <- Rm[31:28] MSR CPSR_flg,#0xA0000000 ; CPSR[31:28] <- 0xA (set N,C; clear Z,V) MRS Rd,CPSR ; Rd[31:0] <- CPSR[31:0]

In privileged modes the instructions behave as follows:

MSR CPSR_all,Rm ; CPSR[31:0] <- Rm[31:0] MSR CPSR_flg,Rm ; CPSR[31:28] <- Rm[31:28] MSR CPSR_flg,#0x50000000 ; CPSR[31:28] <- 0x5 (set Z,V; clear N,C) MSR SPSR_all,Rm ; SPSR_<mode>[31:0]<- Rm[31:0] MSR SPSR_flg,Rm ; SPSR_<mode>[31:28] <- Rm[31:28] MSR SPSR_flg,#0xC0000000 ; SPSR_<mode>[31:28] <- 0xC (set N,Z; clear C,V) MRS Rd,SPSR ; Rd[31:0] <- SPSR_<mode>[31:0]

3-21

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12.

The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication.

31 27 19 15

28 16 111221 20

Cond

S Rd Rn

8 7 4 3 0

Rs RmA00 0 0 0 0

1 0 0 1

[15:12][11:8][3:0] Operand Registers [19:16] Destination Register

[20] Set Condition Code

0 = Do not after condition codes 1 = Set condition codes

[21] Accumulate

0 = Multiply only 1 = Multiply and accumulate

[31:28] Condition Field

Figure 3-12. Multiply Instructions

The multiply form of the instruction gives Rd:=Rm*Rs. Rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. The multiply-accumulate form gives Rd:=Rm*Rs+Rn, which can save an explicit ADD instruction in some circumstances. Both forms of the instruction work on operands which may be considered as signed (2's complement) or unsigned integers.

The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical. As these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies.

For example consider the multiplication of the operands: Operand A Operand B Result 0xFFFFFFF6 0x0000001 0xFFFFFF38

3-22

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

If the Operands Are Interpreted as Signed

Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38.

If the Operands Are Interpreted as Unsigned

Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38.

Operand Restrictions

The destination register Rd must not be the same as the operand register Rm. R15 must not be used as an operand or as the destination register.

All other register combinations will give correct results, and Rd, Rn and Rs may use the same register when required.

3-23

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

CPSR FLAGS

Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero). The C (Carry) flag is set to a meaningless value and the V (oVerflow) flag is unaffected.

INSTRUCTION CYCLE TIMES

MUL takes 1S + mI and MLA 1S + (m+1)I cycles to execute, where S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively.

m The number of 8 bit multiplier array cycles is required to complete the multiply, which is

controlled by the value of the multiplier operand specified by Rs. Its possible values are

as follows 1 If bits [32:8] of the multiplier operand are all zero or all one. 2 If bits [32:16] of the multiplier operand are all zero or all one. 3 If bits [32:24] of the multiplier operand are all zero or all one. 4 In all other cases.

ASSEMBLER SYNTAX

MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn

{cond} Two-character condition mnemonic. See Table 3-2.. {S} Set condition codes if S present Rd, Rm, Rs and Rn Expressions evaluating to a register number other than R15.

EXAMPLES

MUL R1,R2,R3 ; R1:=R2*R3 MLAEQS R1,R2,R3,R4 ; Conditionally R1:=R2*R3+R4, Setting condition codes.

3-24

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13.

The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. Signed and unsigned multiplication each with optional accumulate give rise to four variations.

31 27 19 15

28 16 11122123

Cond

00 0 0 1

S RdHi RdLo

[11:8][3:0] Operand Registers [19:16][15:12] Source Destination Registers

[20] Set Condition Code

0 = Do not alter condition codes 1 = Set condition codes

[21] Accumulate

0 = Multiply only 1 = Multiply and accumulate

[22] Unsigned

0 = Unsigned 1 = Signed

[31:28] Condition Field

Figure 3-13. Multiply Long Instructions

8 7 4 3 0

Rs RmA

1 0 0 1

The multiply forms (UMULL and SMULL) take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs. The lower 32 bits of the 64 bit result are written to RdLo, the upper 32 bits of the result are written to RdHi.

The multiply-accumulate forms (UMLAL and SMLAL) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi,RdLo := Rm * Rs + RdHi,RdLo. The lower 32 bits of the 64 bit number to add is read from RdLo. The upper 32 bits of the 64 bit number to add is read from RdHi. The lower 32 bits of the 64 bit result are written to RdLo. The upper 32 bits of the 64 bit result are written to RdHi.

The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. The SMULL and SMLAL instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result.

3-25

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

OPERAND RESTRICTIONS

•• R15 must not be used as an operand or as a destination register.

•• RdHi, RdLo, and Rm must all specify different registers.

CPSR FLAGS

Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero). Both the C and V flags are set to meaningless values.

INSTRUCTION CYCLE TIMES

MULL takes 1S + (m+1)I and MLAL 1S + (m+2)I cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by Rs.

Its possible values are as follows:

For Signed INSTRUCTIONS SMULL, SMLAL:

•• If bits [31:8] of the multiplier operand are all zero or all one.

•• If bits [31:16] of the multiplier operand are all zero or all one.

•• If bits [31:24] of the multiplier operand are all zero or all one.

•• In all other cases.

For Unsigned Instructions UMULL, UMLAL:

•• If bits [31:8] of the multiplier operand are all zero.

•• If bits [31:16] of the multiplier operand are all zero.

•• If bits [31:24] of the multiplier operand are all zero.

•• In all other cases.

S and I are defined as sequential (S-cycle) and internal (I-cycle), respectively.

3-26

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

ASSEMBLER SYNTAX

Table 3-5. Assembler Syntax Descriptions

Mnemonic Description Purpose

UMULL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply Long 32 x 32 = 64 UMLAL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply & Accumulate Long 32 x 32 + 64 = 64 SMULL{cond}{S} RdLo,RdHi,Rm,Rs Signed Multiply Long 32 x 32 = 64 SMLAL{cond}{S} RdLo,RdHi,Rm,Rs Signed Multiply & Accumulate Long 32 x 32 + 64 = 64

where: {cond} Two-character condition mnemonic. See Table 3-2. {S} Set condition codes if S present RdLo, RdHi, Rm, Rs Expressions evaluating to a register number other than R15.

EXAMPLES

UMULL R1,R4,R2,R3 ; R4,R1:=R2*R3 UMLALS R1,R5,R2,R3 ; R5,R1:=R2*R3+R5,R1 also setting condition codes

3-27

ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

SINGLE DATA TRANSFER (LDR, STR)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14.

The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.

The result of this calculation may be written back into the base register if auto-indexing is required.

31 27 19 15 0

28 16 11122123

Cond

26 2425

01 I P U OffsetW

B20L Rn Rd

[15:12] Source/Destination Registers [19:16] Base Register [20] Load/Store Bit

0 = Store to memory 1 = Load from memory

[21] Write-back Bit

0 = No write-back 1 = Write address into base

[22] Byte/Word Bit

0 = Transfer word quantity 1 = Transfer byte quantity

[23] Up/Down Bit

0 = Down: subtract offset from base 1 = Up: add offset to base

[24] Pre/Post Indexing Bit

0 = Post: add offset after transfer 1 = Pre: add offset before transfer

3-28

[25] Immediate Offset

0 = Offset is an immediate value

[11:0] Offset

Immediate

[11:0] Unsigned 12-bit immediate offset

Shift

[3:0] Offset register[11:4] Shift applied to Rm

4 3 0

[31:28] Condition Field

Figure 3-14. Single Data Transfer Instructions

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

OFFSETS AND AUTO-INDEXING

The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (post-indexed, P=0) the base is used as the transfer address.

The W bit gives optional auto increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base value may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The only use of the W bit in a post-indexed data transfer is in privileged mode code, where setting the W bit forces nonprivileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware.

SHIFTED REGISTER OFFSET

The 8 shift control bits are described in the data processing instructions section. However, the register specified shift amounts are not available in this instruction class. See Figure 3-5.

BYTES AND WORDS

This instruction class may be used to transfer a byte (B=1) or a word (B=0) between an ARM7TDMI register and memory.

The action of LDR(B) and STR(B) instructions is influenced by the BIGEND control signal of ARM7TDMI core. The two possible configurations are described below.

Little-Endian Configuration

A byte load (LDRB) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. Please see Figure 2-2.

A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. The external memory system should activate the appropriate byte subsystem to store the data.

A word load (LDR) will normally use a word aligned address. However, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. This means that half-words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. Two shift operations are then required to clear or to sign extend the upper 16 bits.

A word store (STR) should generate a word aligned address. The word presented to the data bus is not affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data bus output 31.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

A+3 A+2 A+1

memory

LDR from word aligned address

memory

LDR from address offset by 2

Figure 3-15. Little-Endian Offset Addressing

Big-Endian Configuration

A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. Please see Figure 2-1.

A word load (LDR) should generate a word aligned address. An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. This means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. A shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

USE OF R15

Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction.

R15 must not be specified as the register offset (Rm). When R15 is the source register (Rd) of a register store (STR) instruction, the stored value will be address of the

instruction plus 12.

RESTRICTION ON THE USE OF BASE REGISTER

When configured for late aborts, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value.

After an abort, the following example code is difficult to unwind as the base register, Rn, gets updated before the abort handler starts. Sometimes it may be impossible to calculate the initial value.

EXAMPLE:

LDR R0,[R1],R1

Therefore a post-indexed LDR or STR where Rm is the same register as Rn should not be used.

DATA ABORTS

A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued.

INSTRUCTION CYCLE TIMES

Normal LDR instructions take 1S + 1N + 1I and LDR PC take 2S + 2N +1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STR instructions take 2N incremental cycles to execute.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

ASSEMBLER SYNTAX

<LDR|STR>{cond}{B}{T} Rd,<Address> where: LDR Load from memory into a register

STR Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. {B} If B is present then byte transfer, otherwise word transfer {T} If T is present the W bit will be set in a post-indexed instruction, forcing non-privileged

mode for the transfer cycle. T is not allowed when a pre-indexed addressing mode is

specified or implied. Rd An expression evaluating to a valid register number. Rn and Rm Expressions evaluating to a register number. If Rn is R15 then the assembler will

subtract 8 from

the offset value to allow for ARM7TDMI pipelining. In this case base write-back should

not be specified.

<Address>can be: 1 An expression which generates an address:

The assembler will attempt to generate an instruction using the PC as a base and a

corrected immediate offset to address the location given by evaluating the expression.

This will be a PC relative, pre-indexed address. If the address is out of range, an error

will be generated.

2 A pre-indexed addressing specification:

[Rn] offset of zero

[Rn,<#expression>]{!} offset of <expression> bytes

[Rn,{+/-}Rm{,<shift>}]{!} offset of +/- contents of index register, shifted

by <shift>

3 A post-indexed addressing specification:

[Rn],<#expression> offset of <expression> bytes

[Rn],{+/-}Rm{,<shift>} offset of +/- contents of index register, shifted as

by <shift>.

<shift> General shift operation (see data processing instructions) but you cannot specify the shift

amount by a register.

{!} Writes back the base register (set the W bit) if! is present.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

EXAMPLES

STR R1,[R2,R4]! ; Store R1 at R2+R4 (both of which are registers)

; and write back address to R2. STR R1,[R2],R4 ; Store R1 at R2 and write back R2+R4 to R2. LDR R1,[R2,#16] ; Load R1 from contents of R2+16, but don't write back. LDR R1,[R2,R3,LSL#2] ; Load R1 from contents of R2+R3*4. LDREQB R1,[R6,#5] ; Conditionally load byte at R6+5 into

; R1 bits 0 to 7, filling bits 8 to 31 with zeros. STR R1,PLACE ; Generate PC relative offset to address PLACE. PLACE

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16.

These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if auto-indexing is required.

31 27 19 15

28 16 11122123

Cond

2425

000 P U 0000W

L Rn Rd

[3:0] Offset Register [6][5] S H

0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 = Signed byte 1 1 = Signed halfword

[15:12] Source/Destination Register [19:16] Base Register [20] Load/Store

0 = Store to memory 1 = Load from memory

[21] Write-back

0 = No write-back 1 = Write address into base

[23] Up/Down

0 = Down: subtract offset from base 1 = Up: add offset to base

8 7 6 5 4 3 0

1 RmS H 1

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[24] Pre/Post Indexing

0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer

[31:28] Condition Field

Figure 3-16. Halfword and Signed Data Transfer with Register Offset

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

31 27 19 15

28 16 11122123

Cond

2425

000 P U OffsetW

L Rn Rd

[3:0] Immediate Offset (Low Nibble) [6][5] S H

0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 = Signed byte 1 1 = Signed halfword

[11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store

0 = Store to memory 1 = Load from memory

[21] Write-back

0 = No write-back 1 = Write address into base

8 7 6 5 4 3 0

1 OffsetS H 1

[23] Up/Down

0 = Down: subtract offset from base 1 = Up: add offset to base

[24] Pre/Post Indexing

0 = Post: add/subtract offset after transfer 1 = Pre: add/subtract offset bofore transfer

[31:28] Condition Field

Figure 3-17. Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing

OFFSETS AND AUTO-INDEXING

The offset from the base may be either a 8-bit unsigned binary immediate value in the instruction, or a second register. The 8-bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word, such that bit 11 becomes the MSB and bit 0 becomes the LSB. The offset may be added to (U=1) or subtracted from (U=0) the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after (postindexed, P=0) the base register is used as the transfer address.

The W bit gives optional auto-increment and decrement addressing modes. The modified base value may be written back into the base (W=1), or the old base may be kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained if necessary by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base.

The Write-back bit should not be set high (W=1) when post-indexed addressing is selected.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

HALFWORD LOAD AND STORES

Setting S=0 and H=1 may be used to transfer unsigned Half-words between an ARM7TDMI register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible

configurations are described in the section below.

SIGNED BYTE AND HALFWORD LOADS

The S bit controls the loading of sign-extended data. When S=1 the H bit selects between Bytes (H=0) and Halfwords (H=1). The L bit should not be set low (Store) when Signed (S=1) operations have been selected.

The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7, the sign bit.

The LDRSH instruction loads the selected Half-word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15, the sign bit.

The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the following section.

ENDIANNESS AND BYTE/HALFWORD SELECTION Little-Endian Configuration

A signed byte load (LDRSB) expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary, on data bus inputs 15 through to 8 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-2.

A halfword load (LDRSH or LDRH) expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a halfword boundary, (A[1]=1).The supplied address should always be on a halfword boundary. If bit 0 of the supplied address is HIGH then the ARM7TDMI will load an unpredictable value. The selected halfword is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the halfword.

A halfword store (STRH) repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0. The external memory system should activate the appropriate halfword subsystem to store the data. Note that the address must be halfword aligned, if bit 0 of the address is HIGH this will cause unpredictable behaviour.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

Big-Endian Configuration

A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte. Please see Figure 2-1.

A halfword load (LDRSH or LDRH) expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary, (A[1]=1). The supplied address should always be on a halfword boundary. If bit 0 of the supplied address is HIGH then the ARM7TDMI will load an unpredictable value. The selected halfword is placed in the bottom 16 bits of the destination register. For unsigned half-words (LDRH), the top 16 bits of the register are filled with zeros and for signed half-words (LDRSH) the top 16 bits are filled with the sign bit, bit 15 of the halfword.

USE OF R15

Write-back should not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction.

R15 should not be specified as the register offset (Rm). When R15 is the source register (Rd) of a Half-word store (STRH) instruction, the stored address will be address

of the instruction plus 12.

DATA ABORTS

A transfer to or from a legal address may cause problems for a memory management system. For instance, in a system which uses virtual memory the required data may be absent from the main memory. The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued.

INSTRUCTION CYCLE TIMES

Normal LDR(H,SH,SB) instructions take 1S + 1N + 1I. LDR(H,SH,SB) PC take 2S + 2N + 1I incremental cycles. S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STRH instructions take 2N incremental cycles to execute.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

ASSEMBLER SYNTAX

<LDR|STR>{cond}<H|SH|SB> Rd,<address> LDR Load from memory into a register

STR Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2.. H Transfer halfword quantity SB Load sign extended byte (Only valid for LDR) SH Load sign extended halfword (Only valid for LDR) Rd An expression evaluating to a valid register number.

<address> can be: 1 An expression which generates an address:

The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression. This will be a PC relative, pre-indexed address. If the address is out of range, an error will be generated.

2 A pre-indexed addressing specification:

[Rn] offset of zero [Rn,<#expression>]{!} offset of <expression> bytes [Rn,{+/-}Rm]{!} offset of +/- contents of index register

3 A post-indexed addressing specification:

[Rn],<#expression> offset of <expression> bytes [Rn],{+/-}Rm offset of +/- contents of index register.

4 Rn and Rm are expressions evaluating to a register number. If Rn is R15 then the

assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining. In this case base write-back should not be specified.

{!} Writes back the base register (set the W bit) if ! is present.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

EXAMPLES

LDRH R1,[R2,-R3]! ; Load R1 from the contents of the halfword address

; contained in R2-R3 (both of which are registers)

; and write back address to R2 STRH R3,[R4,#14] ; Store the halfword in R3 at R14+14 but don't write back. LDRSB R8,[R2],#-223 ; Load R8 with the sign extended contents of the byte

; address contained in R2 and write back R2-223 to R2. LDRNESH R11,[R0] ; Conditionally load R11 with the sign extended contents

; of the halfword address contained in R0. HERE ; Generate PC relative offset to address FRED. STRH R5, [PC,#(FRED-HERE-8)]; Store the halfword in R5 at address FRED FRED

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

BLOCK DATA TRANSFER (LDM, STM)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18.

Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory.

THE REGISTER LIST

The instruction can cause the transfer of any registers in the current bank (and non-user mode programs can also transfer to and from the user bank, see below). The register list is a 16 bit field in the instruction, with each bit corresponding to a register. A 1 in bit 0 of the register field will cause R0 to be transferred, a 0 will cause it not to be transferred; similarly bit 1 controls the transfer of R1, and so on.

Any subset of the registers, or all the registers, may be specified. The only restriction is that the register list should not be empty.

Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12.

31 27 19 15

28 162123

Cond

2425

24 0

100 P U W

L Rn

[19:16] Base Register [20] Load/Store Bit

0 = Store to memory 1 = Load from memory

[21] Write-back Bit

0 = No write-back 1 = Write address into base

[22] PSR & Force User Bit

0 = Do not load PSR or user mode 1 = Load PSR or force user mode

[23] Up/Down Bit

0 = Down: subtract offset from base 1 = Up: add offset to base

[24] Pre/Post Indexing Bit

0 = Post: add offset after transfer 1 = Pre: add offset bofore transfer

3-40

[31:28] Condition Field

Figure 3-18. Block Data Transfer Instructions

S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

ADDRESSING MODES

The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of the modified base is required (W=1). Figure 3.19-22 show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed.

In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value.

ADDRESS ALIGNMENT

The address should normally be a word aligned quantity and non-word aligned addresses do not affect the instruction. However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system.

0x100C

Rn R1

1 2

R5 R1

3 4

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

R7 R5 R1

Figure 3-19. Post-Increment Addressing

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

0x100C

0x1000

0x0FF4

0x100C R5 R1

0x1000

0x0FF4

R7Rn R5 R1

Figure 3-20. Pre-Increment Addressing

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

R5 R1

0x100C

0x1000

0x0FF4

R7 R5 R1

Figure 3-21. Post-Decrement Addressing

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

0x100C

0x1000

R7 R5 R1

R5 R1

0x0FF4

0x100C

0x1000

0x0FF4

Figure 3-22. Pre-Decrement Addressing

0x100C

0x1000

0x0FF4

0x100C

0x1000

0x0FF4

USE OF THE S BIT

When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode.

LDM with R15 in Transfer List and S Bit Set (Mode Changes)

If the instruction is a LDM then SPSR_<mode> is transferred to CPSR at the same time as R15 is loaded.

STM with R15 in Transfer List and S Bit Set (User Bank Transfer)

The registers transferred are taken from the User bank rather than the bank corresponding to the current mode. This is useful for saving the user state on process switches. Base write-back should not be used when this mechanism is employed.

R15 not in List and S Bit Set (User Bank Transfer)

For both LDM and STM instructions, the User bank registers are transferred rather than the register bank corresponding to the current mode. This is useful for saving the user state on process switches. Base write-back should not be used when this mechanism is employed.

When the instruction is LDM, care must be taken not to read from a banked register during the following cycle (inserting a dummy instruction such as MOV R0, R0 after the LDM will ensure safety).

USE OF R15 AS THE BASE

R15 should not be used as the base register in any LDM or STM instruction.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

INCLUSION OF THE BASE IN THE REGISTER LIST

When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value. A LDM will always overwrite the updated base if the base is in the list.

DATA ABORTS

Some legal addresses may be unacceptable to a memory management system, and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH. This can happen on any transfer during a multiple register load or store, and must be recoverable if ARM7TDMI is to be used in a virtual memory system.

Abort during STM Instructions

If the abort occurs during a store multiple instruction, ARM7TDMI takes little action until the instruction completes, whereupon it enters the data abort trap. The memory manager is responsible for preventing erroneous writes to the memory. The only change to the internal state of the processor will be the modification of the base register if write-back was specified, and this must be reversed by software (and the cause of the abort resolved) before the instruction may be retried.

Aborts during LDM Instructions

When ARM7TDMI detects a data abort during a load multiple instruction, it modifies the operation of the instruction to ensure that recovery is possible.

• Overwriting of registers stops when the abort happens. The aborting load will not take place but earlier ones

may have overwritten registers. The PC is always the last register to be written and so will always be preserved.

• The base register is restored, to its modified value if write-back was requested. This ensures recoverability in

the case where the base register is also in the transfer list, and may have been overwritten before the abort occurred.

The data abort trap is taken when the load multiple has completed, and the system software must undo any base modification (and resolve the cause of the abort) before restarting the instruction.

INSTRUCTION CYCLE TIMES

Normal LDM instructions take nS + 1N + 1I and LDM PC takes (n+1)S + 2N + 1I incremental cycles, where S,N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively. STM instructions take (n-1)S + 2N incremental cycles to execute, where n is the number of words transferred.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

ASSEMBLER SYNTAX

<LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^} where: {cond} Two character condition mnemonic. See Table 3-2.

Rn An expression evaluating to a valid register number <Rlist> A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}). {!} If present requests write-back (W=1), otherwise W=0. {^} If present set S bit to load the CPSR along with the PC, or force transfer of user bank

when in privileged mode.

Addressing Mode Names

There are different assembler mnemonics for each of the addressing modes, depending on whether the instruction is being used to support stacks or for other purposes. The equivalence between the names and the values of the bits in the instruction are shown in the following table 3-6.

Table 3-6. Addressing Mode Names

Name Stack Other L bit P bit U bit

Pre-Increment Load LDMED LDMIB 1 1 1 Post-Increment Load LDMFD LDMIA 1 0 1 Pre-Decrement Load LDMEA LDMDB 1 1 0 Post-Decrement Load LDMFA LDMDA 1 0 0 Pre-Increment Store STMFA STMIB 0 1 1 Post-Increment Store STMEA STMIA 0 0 1 Pre-Decrement Store STMFD STMDB 0 1 0 Post-Decrement Store STMED STMDA 0 0 0

FD, ED, FA, EA define pre/post indexing and the up/down bit by reference to the form of stack required. The F and E refer to a "full" or "empty" stack, i.e. whether a pre-index has to be done (full) before storing to the stack. The A and D refer to whether the stack is ascending or descending. If ascending, a STM will go up and LDM down, if descending, vice-versa.

IA, IB, DA, DB allow control when LDM/STM are not being used for stacks and simply mean Increment After, Increment Before, Decrement After, Decrement Before.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

EXAMPLES

LDMFD SP!,{R0,R1,R2} ; Unstack 3 registers. STMIA R0,{R0-R15} ; Save all registers. LDMFD SP!,{R15} ; R15 ← (SP), CPSR unchanged. LDMFD SP!,{R15}^ ; R15 ← (SP), CPSR <- SPSR_mode

; (allowed only in privileged modes).

STMFD R13,{R0-R14}^ ; Save user mode regs on stack

; (allowed only in privileged modes).

These instructions may be used to save state on subroutine entry, and restore it efficiently on return to the calling routine:

STMED SP!,{R0-R3,R14} ; Save R0 to R3 to use as workspace

; and R14 for returning. BL somewhere ; This nested call will overwrite R14 LDMED SP!,{R0-R3,R15} ; Restore workspace and return.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

SINGLE DATA SWAP (SWP)

31 19 15

28 16 11122123

27 8 7 4 3 0

Cond

00010 0000 Rm1001

B2000 Rn Rd

[3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit

0 = Swap word quantity 1 = Swap word quantity

[31:28] Condition Field

Figure 3-23. Swap Instruction

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-23.

The data swap instruction is used to swap a byte or word quantity between a register and external memory. This instruction is implemented as a memory read followed by a memory write which are "locked" together (the processor cannot be interrupted until both operations have completed, and the memory manager is warned to treat them as inseparable). This class of instruction is particularly useful for implementing software semaphores.

The swap address is determined by the contents of the base register (Rn). The processor first reads the contents of the swap address. Then it writes the contents of the source register (Rm) to the swap address, and stores the old memory contents in the destination register (Rd). The same register may be specified as both the source and destination.

The LOCK output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together, and should be allowed to complete without interruption. This is important in multi-processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores; control of the memory must not be removed from a processor while it is performing a locked operation.

BYTES AND WORDS

This instruction class may be used to swap a byte (B=1) or a word (B=0) between an ARM7TDMI register and memory. The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers. In particular, the description of Big and Little Endian configuration applies to the SWP instruction.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

USE OF R15

Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction.

DATA ABORTS

If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued.

INSTRUCTION CYCLE TIMES

Swap instructions take 1S + 2N +1I incremental cycles to execute, where S,N and I are defined as sequential (S-cycle), non-sequential, and internal (I-cycle), respectively.

ASSEMBLER SYNTAX

<SWP>{cond}{B} Rd,Rm,[Rn] {cond} Two-character condition mnemonic. See Table 3-2.

{B} If B is present then byte transfer, otherwise word transfer Rd,Rm,Rn Expressions evaluating to valid register numbers

EXAMPLES

SWP R0,R1,[R2] ; Load R0 with the word addressed by R2, and

; store R1 at R2. SWPB R2,R3,[R4] ; Load R2 with the byte addressed by R4, and

; store bits 0 to 7 of R3 at R4. SWPEQ R0,R0,[R1] ; Conditionally swap the contents of the

; word addressed by R1 with R0.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

SOFTWARE INTERRUPT (SWI)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below.

31 2427

28 23

Cond Comment Field (Ignored by Processor)

1111

[31:28] Condition Field

Figure 3-24. Software Interrupt Instruction

The software interrupt instruction is used to enter Supervisor mode in a controlled manner. The instruction causes the software interrupt trap to be taken, which effects the mode change. The PC is then forced to a fixed value (0x08) and the CPSR is saved in SPSR_svc. If the SWI vector address is suitably protected (by external memory management hardware) from modification by the user, a fully protected operating system may be constructed.

RETURN FROM THE SUPERVISOR

The PC is saved in R14_svc upon entering the software interrupt trap, with the PC adjusted to point to the word after the SWI instruction. MOVS PC,R14_svc will return to the calling program and restore the CPSR.

Note that the link mechanism is not re-entrant, so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR.

COMMENT FIELD

The bottom 24 bits of the instruction are ignored by the processor, and may be used to communicate information to the supervisor code. For instance, the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions.

INSTRUCTION CYCLE TIMES

Software interrupt instructions take 2S + 1N incremental cycles to execute, where S and N are defined as sequential (S-cycle) and non-sequential (N-cycle).

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

ASSEMBLER SYNTAX

SWI{cond} <expression> {cond} Two character condition mnemonic, Table 3-2.

<expression> Evaluated and placed in the comment field (which is ignored by ARM7TDMI).

EXAMPLES

SWI ReadC ; Get next character from read stream. SWI WriteI+"k” ; Output a "k" to the write stream. SWINE 0 ; Conditionally call supervisor with 0 in comment field.

Supervisor code

The previous examples assume that suitable supervisor code exists, for instance:

0x08 B Supervisor ; SWI entry point EntryTable ; Addresses of supervisor routines DCD ZeroRtn DCD ReadCRtn DCD WriteIRtn

• • •

Zero EQU 0

ReadC EQU 256 WriteI EQU 512

Supervisor ; SWI has routine required in bits 8-23 and data (if any) in

; bits 0-7. Assumes R13_svc points to a suitable stack STMFD R13,{R0-R2,R14} ; Save work registers and return address. LDR R0,[R14,#-4] ; Get SWI instruction. BIC R0,R0,#0xFF000000 ; Clear top 8 bits. MOV R1,R0,LSR#8 ; Get routine offset. ADR R2,EntryTable ; Get start address of entry table. LDR R15,[R2,R1,LSL#2] ; Branch to appropriate routine. WriteIRtn ; Enter with character in R0 bits 0-7.

• • •

LDMFD R13,{R0-R2,R15}^ ; Restore workspace and return,

; restoring processor mode and flags.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

COPROCESSOR DATA OPERATIONS (CDP)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25.

This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back to ARM7TDMI, and it will not wait for the operation to complete. The coprocessor could contain a queue of such instructions awaiting execution, and their execution can overlap other activity, allowing the coprocessor and ARM7TDMI to perform independent tasks in parallel.

COPROCESSOR INSTRUCTIONS

The S3C44B0X, unlike some other ARM-based processors, does not have an external coprocessor interface. It does not have a on-chip coprocessor also.

So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C44B0X. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the S3C44B0X, the coprocessor instructions are still described here in full for completeness. (Remember that any external coprocessor described in this section is a software emulation.)

31 2427 19 15

28 16 111223 20

Cond CRm

8 7 5 4 3 0

CpCp#CRdCRn1110 CP Opc

[3:0] Coprocessor operand register [7:5] Coprocessor information [11:8] Coprocessor number [15:12] Coprocessor destination register [19:16] Coprocessor operand register [23:20] Coprocessor operation code

[31:28] Condition Field

Figure 3-25. Coprocessor Data Operation Instruction

Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM7TDMI. The remaining bits are used by coprocessors. The above field names are used by convention, and particular coprocessors may redefine the use of all fields except CP# as appropriate. The CP# field is used to contain an identifying number (in the range 0 to

15) for each coprocessor, and a coprocessor will ignore any instruction which does not contain its number in the CP# field.

The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field (and possibly in the CP field) on the contents of CRn and CRm, and place the result in CRd.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

INSTRUCTION CYCLE TIMES

Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop.

S and I are defined as sequential (S-cycle) and internal (I-cycle).

ASSEMBLER SYNTAX

CDP{cond} p#,<expression1>,cd,cn,cm{,<expression2>} {cond} Two character condition mnemonic. See Table 3-2.

p# The unique number of the required coprocessor <expression1> Evaluated to a constant and placed in the CP Opc field cd, cn and cm Evaluate to the valid coprocessor register numbers CRd, CRn and CRm respectively <expression2> Where present is evaluated to a constant and placed in the CP field

EXAMPLES

CDP p1,10,c1,c2,c3 ; Request coproc 1 to do operation 10

; on CR2 and CR3, and put the result in CR1. CDPEQ p2,5,c1,c2,c3,2 ; If Z flag is set request coproc 2 to do operation 5 (type 2)

; on CR2 and CR3, and put the result in CR1.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

COPROCESSOR DATA TRANSFERS (LDC, STC)

The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26.

This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors's registers directly to memory. ARM7TDMI is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred.

31 27 19 15

28 16 11122123

Cond

2425

110 P U CP#W

N20L Rn CRd

[7:0] Unsigned 8 Bit Immediate Offset [11:8] Coprocessor Number [15:12] Coprocessor Source/Destination Register [19:16] Base Register [20] Load/Store Bit

0 = Store to memory 1 = Load from memory

[21] Write-back Bit

0 = No write-back 1 = Write address into base

[22] Transfer Length [23] Up/Down Bit

0 = Down: subtract offset from base 1 = Up: add offset to base

[24] Pre/Post Indexing Bit

0 = Post: add offset after transfer 1 = Pre: add offset before transfer

8 7 0

Offset

[31:28] Condition Field

Figure 3-26. Coprocessor Data Transfer Instructions

THE COPROCESSOR FIELDS

The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field.

The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors, but by convention CRd is the register to be transferred (or the first register where more than one is to be transferred), and the N bit is used to choose one of two transfer length options. For instance N=0 could select the transfer of a single register, and N=1 could select the transfer of all the registers for context switching.

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ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR

ADDRESSING MODES

ARM7TDMI is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. Note, however, that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and specify byte offsets for single data transfers.

The 8 bit unsigned immediate offset is shifted left 2 bits and either added to (U=1) or subtracted from (U=0) the base register (Rn); this calculation may be performed either before (P=1) or after (P=0) the base is used as the transfer address. The modified base value may be overwritten back into the base register (if W=1), or the old value of the base may be preserved (W=0). Note that post-indexed addressing modes require explicit setting of the W bit, unlike LDR and STR which always write-back when post-indexed.

The value of the base register, modified by the offset in a pre-indexed instruction, is used as the address for the transfer of the first word. The second word (if more than one is transferred) will go to or come from an address one word (4 bytes) higher than the first transfer, and the address will be incremented by one word for each subsequent transfer.

ADDRESS ALIGNMENT

The base address should normally be a word aligned quantity. The bottom 2 bits of the address will appear on

A[1:0] and might be interpreted by the memory system.

USE OF R15

If Rn is R15, the value used will be the address of the instruction plus 8 bytes. Base write-back to R15 must not be specified.

DATA ABORTS

If the address is legal but the memory manager generates an abort, the data trap will be taken. The write-back of the modified base will take place, but all other processor state will be preserved. The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved, and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried.

INSTRUCTION CYCLE TIMES

Coprocessor data transfer instructions take (n-1)S + 2N + bI incremental cycles to execute, where: n The number of words transferred.

b The number of cycles spent in the coprocessor busy-wait loop.

S, N and I are defined as sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle), respectively.

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S3C44B0X RISC MICROPROCESSOR ARM INSTRUCTION SET

ASSEMBLER SYNTAX

<LDC|STC>{cond}{L} p#,cd,<Address> LDC Load from memory to coprocessor

STC Store from coprocessor to memory {L} When present perform long transfer (N=1), otherwise perform short transfer (N=0) {cond} Two character condition mnemonic. See Table 3-2.. p# The unique number of the required coprocessor cd An expression evaluating to a valid coprocessor register number that is placed in the

CRd field

<Address> can be: 1 An expression which generates an address:

2 A pre-indexed addressing specification:

[Rn] offset of zero [Rn,<#expression>]{!} offset of <expression> bytes

3 A post-indexed addressing specification:

[Rn],<#expression offset of <expression> bytes {!} write back the base register (set the W bit) if! is present Rn is an expression evaluating to a valid

ARM7TDMI register number.

NOTE

If Rn is R15, the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining.

EXAMPLES

LDC p1,c2,table ; Load c2 of coproc 1 from address

; table, using a PC relative address.

STCEQL p2,c3,[R5,#24]! ; Conditionally store c3 of coproc 2

; into an address 24 bytes up from R5, ; write this address back to R5, and use ; long transfer option (probably to store multiple words).

NOTE

Although the address offset is expressed in bytes, the instruction offset field is in words. The assembler will adjust the offset appropriately.

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