SAMSUNG S3C3410X User Guide

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USER'S MANUAL

22-S3-C3410X-062001

S3C3410X

16-Bit CMOS

Microcontrollers

Revision 2

NOTIFICATION OF REVISIONS

ORIGINATOR: Samsung Electronics, SOC Development Group, Ki-Heung, South Korea

PRODUCT NAME: S3C3410X RISC Microcontroller

DOCUMENT NAME: S3C3410X User's Manual, Revision 2

DOCUMENT NUMBER: 22-S3-C3410X-06-2001

EFFECTIVE DATE: June, 2001

SUMMARY: As a result of additional product testing and evaluation, to correct the errata and

to add more detailed explanations, some specifications published in the S3C3410X User's Manual, Revision 1, have been changed. These changes for S3C3410X microcontroller, which are described in detail in the Revision Descriptions section below, are related to the followings:

— Chapter 1. Pin Descriptions — Chapter 4. EXTCONx, EXTPORT, EXTDATx and Timing Diagrams — Chapter 5. Cache Disable Operation

— Chapter 7. Port 7 and Port 9 Control Registers — Chapter 11. Interrupt Priority Register (INTPRIx) — Chapter 14. Multi-Master IIC-Bus Status Register (IICSTAT)

DIRECTIONS: Please note the changes in your copy (copies) of the S3C3410X User's Manual,

Revision 1. Or, simply attach the Revision Descriptions of the next page to S3C3410X User's Manual, Revision 1.

REVISION HISTORY

Revision Date Remark

0 – There is no preliminary spec. 1 August, 2000 Reviewed by Gwang-Su Han. 2 June, 2001 Reviewed by Gwang-Su Han.

REVISION DESCRIPTIONS

1. PIN DESCRIPTIONS:

1) Pin descriptions about A[23:0], D[15:0], nCS[7:0] nECS[1:0], nWAIT and nWREXP, are changed and the content of RP[7:0] are added.

S3C3410X User's Manual reference: Table 1-3, page 1-11

2) The following errata should be corrected: RXD → URXD, TXD → UTXD, SIOCK[1:0] → SIOCLK[1:0], EXTAI0 → EXTAL0, SYSCFG0 → SYSCFG, MEMCONx → BANKCONx, EDVCONx → EXTCONx, EXTDATAx → EXTDATx , UTXHW → UTXH_W, URXHW → URXH_W, IICADD(0xe002) → IICADD(0xe003), IICDS(0xe003) → IICDS(0xe002)

S3C3410X User's Manual reference: Table 1-3, page 1-11

2. EXTCONX, EXTPORT, EXTDATX AND TIMING DIAGRAMS:

1) Contents about EXTCONx, EXTPORT, and EXTDATx are changed. S3C3410X User's Manual reference: page 4-14 and page 4-15

2) "Multiplexed Address Mode Timing Diagrams", "nCS Timing Diagram with nWAIT", and “ nECS Timing Diagram with nWAIT" are added.

3) External Device Interface Diagram is changed.

S3C3410X User's Manual reference: Figure 4-21, page 4-30

3. CACHE DISABLE OPERATION:

1) More detailed explanations about the internal SRAM address (when the cache is disabled) is added. S3C3410X User's Manual reference: page 5-4

4. PORT 7 AND PORT 9 CONTROL REGISTERS:

1) The contents of P7BR(0xB00B) is added in PORT 7 and the pin descriptions of P7.x are changed to P7.x (RPx).

S3C3410X User's Manual reference: page 7-20

2) More detailed explanations about P9.0(LP) and P9.1(DCLK) are added. S3C3410X User's Manual reference: page 7-25

(Continued to the next page)

5. INTERRUPT PRIORITY REGISTER:

1) The contents about the INTPRIx are changed . S3C3410X User's Manual reference: page 11-10

6. MULTI-MASTER IIC-BUS STATUS REGISTER:

1) The contents of INTFLAG is added to IICSTAT register. S3C3410X User's Manual reference: page 14-7

2) The prescaler value (4 × (prescaler value + 1)) is changed to (16 × (prescaler value + 1)) in IICPS. S3C3410X User’s Manual reference: page 14-9

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

INTRODUCTION

Samsung's S3C3410X 16/32-bit RISC microcontroller is a cost-effective and high-performance microcontroller solution for PDA and general purpose application.

An outstanding feature of the S3C3410X is its CPU core, a 16/32-bit RISC processor(ARM7TDMI) designed by Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose, microprocessor macrocell, which was developed for the use in application-specific and customer-specific integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive application.

The S3C3410X has been developed by using the ARM7TDMI core, CMOS standard cell, and a data path compiler. Most of the on-chip function blocks have been designed using an HDL synthesizer. The S3C3410X has been fully verified in SAMSUNG ASIC test environment including the internal Qualification Assurance Process.

By providing a complete set of common system peripherals, the S3C3410X can minimize the overall system cost and eliminates the need to configure additional components, externally.

The integrated on-chip functions which are described in this document include:

• Integrated external memory controller (ROM/SRAM and FP/EDO DRAM/SDRAM controller)

• 2-channel general DMA controller

• Internal 4K-byte memory can be configured as (4KB Cache only), (2KB Cache and 2KB SRAM), or (4KB

SRAM only).

• 1-channel UART with IrDA 1.0, 1-channel IIC, and 2-channel SIO(Synchronous serial IO)

• 3-channel 16-bit timers and 2-channel 8-bit timers

• Real time clock with calendar function.

• Crystal/Ceramic oscillator or external clock can be used as the clock source.

• Power control: Normal, Idle, and Stop mode

• 1-channel 8-bit basic timer and 3-bit watch-dog timer

• Interrupt controller: 35 interrupt sources, interrupt priority control logic and interrupt vector generation by H/W.

• 8-channel 10-bit ADC

• 10 programmable I/O port group (Total 74 I/O ports including the multiplexed I/O)

1-1

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

FEATURES

Architecture

• Integrated system for hand-held and general embedded application.

• Fully 16/32-bit RISC architecture(32-bit ARM instruction as well as 16-bit Thumb instruction).

• ARM7TDMI CPU core, supporting the efficient and powerful instruction set.

• On-chip ICEBreakerTM debug support by JTAG- based solution.

• 4KB Unified Cache (Instruction/Data Cache Memory)

System Manager

• Address space: 16Mbytes per each bank (Total 128Mbyte)

• Support 8-bit/16-bit data bus width for external memory/device access.

• The bank can support ROM/SRAM/Flash, External I/O device or FP/EDO/SDRAM.

• Among total 8 memory banks, bank0,1,2,3,4 and 5 can be mapped to ROM/SRAM/Flash, while bank6 and 7 can be mapped to FP/EDO/SDRAM as well as ROM/SRAM/Flash.

• Fully programmable access cycle for all memory banks

DMA Controller

• Two-channel general purposed DMA(Direct Memory Access) controller.

• The data transfer of Memory-to-memory, serial port-to-memory, memory-to-serial port, memoryto-SFR(Special Function Register), SFR-tomemory, internal SRAM-to-memory, and memory-to-internal SRAM without CPU intervention

• Initiated by the software or external DMA request

• Increment or decrement source or destination addresses.

• Supports 8-bit(byte), 16-bit(half-word), and 32bit(word) of data transfer size.

I/O Ports

• 10 Programmable Input, Output, and I/O port group (74 I/O ports including the multiplexed I/O)

• One programmable Output port (2-bit multiplexed output ports)

• One programmable Input port(8-bit multiplexed input ports)

• Eight programmable I/O port group.

• Supports self-refresh/auto-refresh mode to

retain the data in the DRAM.

• Two external I/O banks can be mapped to the SFR (Special Function Register) region.

Unified(Instruction/Data) Cache Memory & Internal SRAM

• Two-way set associative 4KB cache.

• Pseudo LRU (Least Recently Used)

replacement policy.

• Four depth write buffer.

• Programmable configuration of

(4KB cache, only), (2KB cache and 2KB SRAM), or (4KB SRAM, only).

1-2

16-bit Timer/Counters (T0, T1, T2)

• Three-channel programmable 16-bit timer/counter

• Interval, capture, match & overflow, or DMA mode operation

• Internal or external clock source

8-bit Timer/Counters (T3, T4)

• Two-channel programmable 8-bit timer/counter

• Interval, capture, PWM, or DMA mode operation

(T4 PWM with 5-byte FIFO buffer, which can provide the sound generation capability)

• Internal or external clock source

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

UART & SIO

• One-channel UART with DMA-based or interrupt-based operation

• Programmable baud rates

• Supports 5-bit, 6-bit, 7-bit and 8-bit serial data

transmit/receive frame in UART

• Programmable accessible 8-byte transmitter FIFO and 8-byte receiver FIFO in UART

• Two-channel synchronous SIO with DMA-based or interrupt-based operation

• Support the serial data transmit/receive operation by 8-bit frame.

Interrupt Controller

• 35 interrupt sources (12 External interrupt, 2 DMA, 3 UART, 11 Timer, ADC, IIC, 2 SIO, Basic Timer, 2 RTC)

• H/W interrupt priority logic and vector generation

• Normal or fast interrupt modes (IRQ, FIQ)

IIC Bus Interface

• One-channel multi-master IIC-bus

• Support 8-bit, bi-directional, and serial data

transfer up to 100kbit/s.

RTC (Real Time Clock)

• Full clock function : second, minute, hours, day, week, month, and year

• 32.768KHz operation

• Alarm interrupt for CPU wake-up

Power Down Mode

• Power mode: Idle, Slow and Stop mode

• System clock division ratio in slow mode: 1, 1/2,

1/8, 1/16, and 1/1024

Operating Voltage Range

• 3.0 V to 3.6 V

Temperature Range

A/D Converter

• Eight-channel multiplexed ADC

• Successive approximation conversion

• 10-bit ADC

WDT(Watch-Dog Timer) and Basic Timer

• 8-bit Counter (Basic Timer) and 3-bit counter (Watchdog Timer)

• The overflow signal of 8-bit counter can generate a basic timer interrupt and should be input clock for 3-bit counter(Watchdog Timer).

• The overflow signal of 3-bit counter makes a system reset

• 0oC to 70oC

Operating Frequency

• up to 40MHz

Package Type

• 128-pin QFP

1-3

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

General Purpose I/O Ports

BLOCK DIAGRAM

CPU Unit

Write

Buffer

ARM7TDMI

CPU Core

Cache

4 Kbyte

General Purpose I/O Ports

DMA0,1

UART

SYSTEM BUS

System Clock

Circuit

Basic Timer

WDT

A/D

Converter

Interrupt

Controller

Real Time Clock

Generator

Crystal/ Ceramic Oscillator

Timer 0,1,2,3,4

Serial I/O 0,1

GPIO

Controller

SYSTEM BUS CONTROLLER BUS ARBITRATION

BUS

INTERFACE

Figure 1-1. S3C3410X Block Diagram

ROM/

FLASH/SRAM

CONTROLLER

IIC BUS

FP/DRAM/

SDRAM

CONTROLLER

1-4

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

nCS6:nRAS0:nSCS0/P2.5

nCS7:nRAS1:nSCS1/P2.6

nWBE0:nBE0:DQM0/P3.0

nWBE1:nBE1:DQM1/P3.1

PIN ASSIGNMENTS

AIN3/P8.3

AIN2/P8.2

AIN1/P8.1

AIN0/P8.0

AVREF

ADCVSS

EXTAL1

XTAL1

RTCVDD

TEST1

TEST0

nRESET

EXTAL0

XTAL0

RP7/P7.7

RP6/P7.6

VDD

VSS

RP5/P7.5

TDO/RP4/P7.4

nTRST/RP3/P7.3

TDI/RP2/P7.2

TMS/RP1/P7.1

TCK/RP0/P7.0

EINT3/P6.7

SIOTXD1/P6.6

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

AIN4/EINT8/P8.4

AIN5/EINT9/P8.5 AIN6/EINT10/P8.6 AIN7/EINT11/P8.7

ADCVDD TCLK0/TCAP0/P0.0 TCLK1/TCAP1/P0.1

TCLK2/TCAP2P0.2

VSS

VDD TCLK3/P0.3 TCLK4/P0.4

TCAP3/TOUT3/PWM0/P0.5 TCAP4/TOUT4/PWM1/P0.6

EINT0/nWREXP/P0.7

A0 A1 A2

VSS

VDD

A3 A4 A5 A6

A7 A8/A16 A9/A17

A10/A18

VSS

VDD A11/A19 A12/A20 A13/A21 A14/A22 A15/A23

A16/P1.0 A17/P1.1 A18/P1.2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

39404142434445464748495051525354555657585960616263

S3C3410X

(128-QFP-1420)

102 101 100

SIOCLK1/P6.5 SIORXD1/P6.4 SIORDY/nWAIT/P6.3 SIOTXD0/P6.2

SIOCLK0/P6.1

SIORXD0/P6.0

UTXD/P5.7

URXD/P5.6

VDD

VSS

IICSCK/P5.5

IICSDA/P5.4

nDACK1/P5.3

nDREQ1/P5.2

nDACK0/P5.1

nDREQ0/P5.0

D15/A23/P4.7

D14/A22/P4.6

VDD

VSS

D13/A21/P4.5

D12/A20/P4.4

D11/A19/P4.3

D10/A18/P4.2

D9/A17/P4.1

D8/A16/P4.0

VDD

VSS

DCLK/P9.1

LP/P9.0

VSS

A19/P1.3

A20/EINT4/P1.4

A21/EINT5/P1.5

A22/EINT6/P1.6

A23/EINT7/P1.7

nCS0

nCS1/P2.0

nCS2/P2.1

nCS3/P2.2

nCS4/P2.3

nCS5/P2.4

VDD

nAS

nOE

EINT1/nECS0/P2.7

Figure 1-2. S3C3410X Pin Assignments

nWE/P3.4

SCLK/P3.6

SCKE/P3.5

nCAS0:nSRAS/P3.2

nCAS1:nSCAS/P3.3

EINT2/nECS1/P3.7

1-5

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

Table 1-1. 128-Pin QFP Pin Assignment

Pin No Function I/O State @Initial I/O Type Reset

1 AIN4/EINT8/P8.4 I piseuc P8.4 2 AIN5/EINT9/P8.5 I piseuc P8.5 3 AIN6/EINT10/P8.6 I piseuc P8.6 4 AIN7/EINT11/P8.7 I piseuc P8.7 5 ADCVDD P vddt 6 TCLK0/TCAP0/P0.0 IO pbseuct4 P0.0 7 TCLK1/TCAP1/P0.1 IO pbseuct4 P0.1 8 TCLK2/TCAP2/P0.2 IO pbseuct4 P0.2

9 VSS P vss 10 VDD P vdd 11 TCLK3/P0.3 IO pbseuct4 P0.3 12 TCLK4/P0.4 IO pbseuct4 P0.4 13 TCAP3/TOUT3/PWM0/P0.5 IO pbseuct4 P0.5 14 TCAP4/TOUT4/PWM1/P0.6 IO pbseuct4 P0.6 15 EINT0/nWREXP/P0.7 IO pbseuct8 P0.7 16 A0 O pob8 A0 17 A1 O pob8 A1 18 A2 O pob8 A2 19 VSS P vss 20 VDD P vdd 21 A3 O pob8 A3 22 A4 O pob8 A4 23 A5 O pob8 A5 24 A6 O pob8 A6 25 A7 O pob8 A7 26 A8/A16 O pob8 A8 27 A9/A17 O pob8 A9 28 A10/A18 O pob8 A10 29 VSS P vss 30 VDD P vdd 31 A11/A19 O pob8 A11 32 A12/A20 O pob8 A12

1-6

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 128-Pin QFP Pin Assignment (Continued)

Pin No Function I/O State @Initial I/O Type Reset

33 A13/A21 O pob8 A13 34 A14/A22 O pob8 A14 35 A15/A23 O pob8 A15 36 A16/P1.0 IO pbcedct8 P1.0 37 A17/P1.1 IO pbcedct8 P1.1 38 A18/P1.2 IO pbcedct8 P1.2 39 A19/P1.3 IO pbcedct8 P1.3 40 A20/EINT4/P1.4 IO pbsedct8 P1.4 41 A21/EINT5/P1.5 IO pbsedct8 P1.5 42 A22/EINT6/P1.6 IO pbsedct8 P1.6 43 A23/EINT7/P1.7 IO pbsedct8 P1.7 44 nCS0 O pob8 nCS0 45 nCS1/P2.0 IO pbceuct8 P2.0 46 nCS2/P2.1 IO pbceuct8 P2.1 47 nCS3/P2.2 IO pbceuct8 P2.2 48 nCS4/P2.3 IO pbceuct8 P2.3 49 nCS5/P2.4 IO pbceuct8 P2.4 50 nCS6:nRAS0:nSCS0/P2.5 IO pbceuct8 P2.5 51 VSS P vss 52 VDD P vdd 53 nCS7:nRAS1:nSCS1/P2.6 IO pbceuct8 P2.6 54 EINT1/nECS0/P2.7 IO pbseuct8 P2.7 55 nOE O pob8 nOE 56 nAS O pob8 nAS 57 nWBE0:nBE0:DQM0/P3.0 IO pbceuct8 P3.0 58 nWBE1:nBE1:DQM1/P3.1 IO pbceuct8 P3.1 59 nCAS0:nSRAS/P3.2 IO pbceuct8 P3.2 60 nCAS1:nSCAS/P3.3 IO pbceuct8 P3.3 61 nWE/P3.4 IO pbceuct8 P3.4 62 SCKE/P3.5 IO pbceuct8 P3.5 63 SCLK/P3.6 IO pbceuct8 P3.6 64 EINT2/nECS1/P3.7 IO pbseuct8 P3.7

1-7

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

Table 1-1. 128-Pin QFP Pin Assignment (Continued)

Pin No Function I/O State @Initial I/O Type Reset

65 LP/P9.0 O pob8 LP 66 DCLK/P9.1 O pob8 DCLK 67 D0 IO pbcedct8 D0 68 D1 IO pbcedct8 D1 69 D2 IO pbcedct8 D2 70 D3 IO pbcedct8 D3 71 D4 IO pbcedct8 D4 72 D5 IO pbcedct8 D5 73 VSS P vss 74 VDD P vdd 75 D6 IO pbcedct8 D6 76 D7 IO pbsedct8 D7 77 D8/A16/P4.0 IO pbcedct8 P4.0 78 D9/A17/P4.1 IO pbcedct8 P4.1 79 D10/A18/P4.2 IO pbcedct8 P4.2 80 D11/A19/P4.3 IO pbcedct8 P4.3 81 D12/A20/P4.4 IO pbcedct8 P4.4 82 D13/A21/P4.5 IO pbcedct8 P4.5 83 VSS P vss 84 VDD P vdd 85 D14/A22/P4.6 IO pbcedct8 P4.6 86 D15/A23/P4.7 IO pbcedct8 P4.7 87 nDREQ0/P5.0 IO pbceuct4 P5.0 88 nDACK0/P5.1 IO pbceuct4 P5.1 89 nDREQ1/P5.2 IO pbceuct4 P5.2 90 nDACK1/P5.3 IO pbceuct4 P5.3 91 IICSDA/P5.4 IO pbceuct8 P5.4 92 IICSCK/P5.5 IO pbceuct8 P5.5 93 VSS P vss 94 VDD P vdd 95 URXD/P5.6 IO pbceuct4 P5.6 96 UTXD/P5.7 IO pbceuct4 P5.7

1-8

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 128-Pin QFP Pin Assignment (Continued)

Pin No Function I/O State @Initial I/O Type Reset

97 SIORXD0/P6.0 IO pbseuct4 P6.0 98 SIOCLK0/P6.1 IO pbseuct4 P6.1

99 SIOTXD0/P6.2 IO pbseuct4 P6.2 100 SIORDY/nWAIT/P6.3 IO pbseuct4 P6.3 101 SIORXD1/P6.4 IO pbseuct4 P6.4 102 SIOCLK1/P6.5 IO pbseuct4 P6.5 103 SIOTXD1/P6.6 IO pbseuct4 P6.6 104 EINT3/P6.7 IO pbseuct4 P6.7 105 TCK/RP0/P7.0 IO pbceuct4 P7.0 106 TMS/RP1/P7.1 IO pbceuct4 P7.1 107 TDI/RP2/P7.2 IO pbceuct4 P7.2 108 nTRST/RP3/P7.3 IO pbceuct4 P7.3 109 TDO/RP4/P7.4 IO pbceuct4 P7.4 110 RP5/P7.5 IO pbceuct4 P7.5 111 VSS P vss 112 VDD P vdd 113 RP6/P7.6 IO pbceuct4 P7.6 114 RP7/P7.7 IO pbceuct4 P7.7 115 XTAL0 I oscm XTAL0 116 EXTAL0 O oscm EXTAL0 117

RESET

I pisu

RESET

118 TEST0 I pis TEST0 119 TEST1 I pis TEST1 120 RTCVDD P vddt 121 XTAL1 I oscm XTAL1 122 EXTAL1 O oscm EXTAL1 123 ADCVSS P vsst 124 AVREF A apad AVREF 125 AIN0/P8.0 I piseuc P8.0 126 AIN1/P8.1 I piseuc P8.1 127 AIN2/P8.2 I piseuc P8.2 128 AIN3/P8.3 I piseuc P8.3

1-9

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

Table 1-2. I/O Type Description

I/O Type Description

vdd, vss 3.3V Vdd/Vss vddt, vsst 3.3V Vdd/Vss for analog circuitry pbceuct4 bi-direction pad, CMOS level, pull-up resister with control, tri-state, Io = 4mA pbseuct4 bi-direction pad, CMOS schmitt-trigger, pull-up resister with control, tri-state, Io = 4mA pbceuct8 bi-direction pad, CMOS level, pull-up resister with control, tri-state, Io = 8mA pbseuct8 bi-direction pad, CMOS schmitt-trigger, pull-up resister with control, tri-state, Io = 8mA pbcedct8 bi-direction pad, CMOS level, pull-down resister with control, tri-state, Io = 8mA pbsedct8 bi-direction pad, CMOS schmitt-trigger, pull-down resister with control, tri-state, Io = 8mA pob8 output pad, Io = 8mA pis input pad, CMOS schmitt-trigger pisu input pad, CMOS schmitt-trigger, pull-up resister piceuc input pad, CMOS level, pull-up resister with control piseuc input pad, CMOS schmitt-trigger, pull-up resister with control apad pad for analog pin oscm pad for x-tal oscillation

1-10

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-3. S3C3410X Pin Descriptions

Pin I/O Description

BUS CONTROLLER

TEST[1:0] I The TEST[1:0] can configure the data bus size for bank 0 in normal or MDS mode.

The normal mode is for CPU to start its operation by fetching the instruction from external memory. The MDS mode is for CPU to be debugged by the external Emulator, EmbeddedICE, etc. 00 = Normal mode with 8-bit data bus size for bank 0 access. 01 = Normal mode with 16-bit data bus size for bank 0 access. 10 = MDS mode with 8-bit data bus size for bank 0 access.

11 = MDS mode with 16-bit data bus size for bank 0 access. A[23:0] O A[23:0] (address bus) generate the address when external memory access. D[15:0] I/O D[15:0] (Data bus) input the data during memory read and output the data during

memory write. The data bus width can be programmable for 8-bit or 16-bit by the

BANKCONx register option. nCS[7:0] O nCS[7:0] (Chip Select) selectively generate the chip select signal of each bank when

the external memory access address is within the address range of each bank. The

number of access cycle and the bank size can be programmable by the BANKCONx

extra device (External I/O device). nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle. nWE O nWE (Write Enable for x16 SRAM or SDRAM) indicates that the current bus cycle is

a write cycle. To support the byte write to external memory, the byte to be accessed

can be determined by nBE[1:0], which is the selection on upper byte or lower byte.

For example, in case of 16-bit SRAM, nBE[1:0] should play it role as UB(Upper

Byte)/LB(Lower Byte) to select the upper byte or lower byte. In case of SDRAM,

nWBE[1:0] should play it role as DQM[1:0] to select the upper byte or lower byte. For

16-bit access, not 8-bit access, both nWBE[1:0] should be activated at same time. In

certain case, no more byte access is needed. For example, x16 Flash Memory does

not need byte access through 16-bit bus when user need the programming in the

flash memory. In this case, please use nWBE[0] instead of nWE to indicate that the

current bus cycle is a write cycle. Summarizing, nWE should be used to indicate the

write bus cycle in case of x16 SRAM and x16/x8 SDRAM. In case of x16 with two x8

SRAM, nWBE[0] and nWBE[1] should be connected to the WE of SRAM,

respectively. For more detail information, please refer the chapter 4. nWBE[1:0] O nWBE[1:0] (Write Byte Enable). In case of Flash or ROM access, nWBE[0] should

be connected to the WE of memory. For the access to the non-volatile memory, we

do not need the selection on bytes because the 8-bit write cycle via 16-bit bus is no

more necessary. To program the data into the non-volatile memory, we should

always use the 16-bit access. In this configuration, please use nWBE[0] instead of

nWE to indicate that the current bus cycle is a write cycle. Summarizing, nWBE[0]

should be used to indicate the current write bus cycle in case of x8 SRAM, x8/x16

ROM, EDODRAM or Flash memory. For more detail information, please refer the

chapter 4.

1-11

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

Table 1-3. S3C3410X Signal Descriptions (Continued)

Pin I/O Description

nAS O nAS generates an address strobe signal for latch device in multiplexed address

mode which generate A[23:16] and A[15:8] address in A[15:8] pins.

nWAIT I nWAIT receives request signal to prolong a current bus cycle. As long as nWAIT is

"Low", the current bus cycle cannot be completed.

nWREXP O nWREXP outputs write strobe signal for external device, when you write any data

into EXTPORT register to interface external device.

DRAM/SDRAM

nRAS[1:0] O Row Address Strobe nCAS[1:0] O Column Address Strobe nSCS[1:0] O SDRAM Chip Select nSRAS O SDRAM Row Address Strobe nSCAS O SDRAM Column Address Strobe DQM[1:0] O SDRAM Data Mask SCLK O SDRAM Clock SCKE O SDRAM Clock Enable

16-bit/8-bit Timer

TCLK[4:0] I External clock input for Timer TCAP[4:0] I Capture input for Timer TOUT[4:3] O Timer 3, 4 output or PWM output

DMA

nDREQ[1:0] I External DMA request nDACK[1:0] O External DMA acknowledge

Interrupt Controller

EINT[12:0] I External interrupt request

UART

URXD I UART receives data input UTXD O UART transmits data output

SIO

SIOCLK[1:0] I/O SIO external clock SIORXD[1:0] I SIO receives data input SIOTXD[1:0] O SIO transmits data output SIORDY I/O SIO handshakes signal when SIO operation is done by DMA

IIC-BUS

IICSDA I/O IIC-bus data IICSCK I/O IIC-bus Clock

1-12

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-3. S3C3410X Signal Descriptions (Continued)

Pin I/O Description

ADC

AIN[7:0] A ADC input AVREF A ADC Vref

General Purpose I/O

Pn.x I/O General purpose input/output ports RP[7:0] O Real time buffer output ports (refer to P7)

RESET & Clock

RESET

RESET is the global reset input for the S3C3410X. For a system reset, RESET must

be held to "Low" level for at least 1us. XTAL0 A Crystal input for internal oscillation circuit for system clock EXTAL0 A Crystal output for internal oscillation circuit for system clock. It's the inverted output

of XTAL0. XTAL1 A 32.768KHz crystal input for RTC EXTAL1 A 32.768KHz crystal output for RTC. It's the inverted output of XTAL1.

LCD Interface

LP O LCD Line Pulse (Inversion of nECS0) DCLK O LCD Clock (Inversion of nWREXP)

JTAG Test Logic

nTRST I nTRST (TAP Controller Reset) can reset the TAP controller at power-up. A 100K

pull-up resistor is connected to nTRST pin, internally. If the debugger(BlackICE) is

not used, nTRST pin should be "Low" level or low active pulse should be applied

before CPU running. For example, RESET signal can be tied with nTRST. TMS I TMS (TAP Controller Mode Select) can control the sequence of the state diagram of

TAP controller. A 100K pull-up resistor is connected to TMS pin, internally. TCK I TCK (TAP Controller Clock) can provide the clock input for the JTAG logic. A 100K

pull-up resistor is connected to TCK pin, internally. TDI I TDI (TAP Controller Data Input) is the serial input for JTAG port. A 100K pull-up

resistor is connected to TDI pin, internally. TDO O TDO (TAP Controller Data Output) is the serial output for JTAG port.

POWER

VDD P Power supply pin VSS P Ground pin RTCVDD P RTC power supply ADCVDD P ADC power supply ADCVSS P ADC ground & RTC ground

1-13

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

S3C3410X SPECIAL FUNCTION REGISTER

Table 1-4. S3C3410X Special Function Register

Group Register Offset R/W Description AccessReset Value

System SYSCFG0 0x1000 R/W System Configuration Register W 0xfff1

Manager BANKCON0 0x2000 R/W Memory Bank 0 Control Register W 0x00200070

BANKCON1 0x2004 R/W Memory Bank 1 Control Register W 0x0 BANKCON2 0x2008 R/W Memory Bank 2 Control Register W 0x0 BANKCON3 0x200c R/W Memory Bank 3 Control Register W 0x0 BANKCON4 0x2010 R/W Memory Bank 4 Control Register W 0x0 BANKCON5 0x2014 R/W Memory Bank 5 Control Register W 0x0 BANKCON6 0x2018 R/W Memory Bank 6 Control Register W 0x0 BANKCON7 0x201c R/W Memory Bank 7 Control Register W 0x0

REFCON 0x2020 R/W DRAM Refresh Control Register W 0x1 EXTCON0 0x2030 R/W Extra device control register 0 W 0x0 EXTCON1 0x2034 R/W Extra device control register 1 W 0x0 EXTPORT 0x203e R/W External port data register B/H 0x0

EXTDAT0 0x202c R/W Extra chip selection data register 0 B/H 0x0 EXTDAT1 0x202e R/W Extra chip selection data register 1 B/H 0x0

DMA DMACON0 0x300c R/W DMA 0 control register W 0x0

DMASRC0 0x3000 R/W DMA 0 source address register W 0x0 DMADST0 0x3004 R/W DMA 0 destination address register W 0x0 DMACNT0 0x3008 R/W DMA 0 transfer count register W 0x0

DMACON1 0x400c R/W DMA 1 Control Register W 0x0

DMASRC1 0x4000 R/W DMA 1 source address register W 0x0 DMADST1 0x4004 R/W DMA 1 destination address register W 0x0 DMACNT1 0x4008 R/W DMA 1 transfer count register W 0x0

I/O Port PDAT0 0xb000 R/W Port 0 data register B 0x0

PDAT1 0xb001 R/W Port 1 data register B 0x0 PDAT2 0xb002 R/W Port 2 data register B 0x0 PDAT3 0xb003 R/W Port 3 data register B 0x0 PDAT4 0xb004 R/W Port 4 data register B 0x0 PDAT5 0xb005 R/W Port 5 data register B 0x0 PDAT6 0xb006 R/W Port 6 data register B 0x0 PDAT7 0xb007 R/W Port 7 data register B 0x0 PDAT8 0xb008 R Port 8 data register B 0x0

1-14

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C3410X Special Function Register (Continued)

Group Register Offset R/W Description Access Reset Value

I/O Port PDAT9 0xb009 R/W Port 9 data register B 0x0

P7BR 0xb00b R/W Port 7 buffer register B 0x0 PCON0 0xb010 R/W Port 0 control register H 0x0 PCON1 0xb012 R/W Port 1 control register H 0x0 PCON2 0xb014 R/W Port 2 control register H 0x0 PCON3 0xb016 R/W Port 3 control register H 0x0 PCON4 0xb018 R/W Port 4 control register H 0x0 PCON5 0xb01c R/W Port 5 control register W 0x0 PCON6 0xb020 R/W Port 6 control register W 0x0 PCON7 0xb024 R/W Port 7 control register H 0x0 PCON8 0xb026 R/W Port 8 control register B 0x0 PCON9 0xb027 R/W Port 9 control register B 0x0

PUR0 0xb028 R/W Port 0 pull-up control register B 0x80

PDR1 0xb029 R/W Port 1 pull-down control register B 0xff

PUR2 0xb02a R/W Port 2 pull-up control register B 0xff

PUR3 0xb02b R/W Port 3 pull-up control register B 0xff

PDR4 0xb02c R/W Port 4 pull-down control register B 0xff

PUR5 0xb02d R/W Port 5 pull-up control register B 0x0

PUR6 0xb02e R/W Port 6 pull-up control register B 0x0

PUR7 0xb02f R/W Port 7 pull-up control register B 0x0

PUR8 0xb03c R/W Port 8 pull-up control register B 0x0

EINTPND 0xb031 R/W External interrupt pending register B 0x0 EINTCON 0xb032 R/W External interrupt control register H 0x0

EINTMOD 0xb034 R/W External interrupt mode register W 0x0

Timer 0 TDAT0 0x9000 R/W Timer 0 data register H 0xffff

TPRE0 0x9002 R/W Timer 0 prescaler register B 0x0

TCON0 0x9003 R/W Timer 0 control register B 0x0

TCNT0 0x9006 R Timer 0 counter register H 0x0

Timer 1 TDAT1 0x9010 R/W Timer 1 data register H 0xffff

TPRE1 0x9012 R/W Timer 1 prescaler register B 0x0

TCON1 0x9013 R/W Timer 1 control register B 0x0

TCNT1 0x9016 R Timer 1 counter register H 0x0

1-15

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

Table 1-4. S3C3410X Special Function Register (Continued)

Group Register Offset R/W Description Access Reset Value

Timer 2 TDAT2 0x9020 R/W Timer 2 data register H 0xffff

TPRE2 0x9022 R/W Timer 2 prescaler register B 0x0

TCON2 0x9023 R/W Timer 2 control register B 0x0

TCNT2 0x9026 R Timer 2 counter register H 0x0

Timer 3 TDAT3 0x9031 R/W Timer 3 data register B 0xff

TPRE3 0x9032 R/W Timer 3 prescaler register B 0x0

TCON3 0x9033 R/W Timer 3 control register B 0x0

TCNT3 0x9037 R Timer 3 counter register B 0x0

Timer 4 TDAT4 0x9041 R/W Timer 4 data register B 0xff

TPRE4 0x9042 R/W Timer 4 prescaler register B 0x0

TCON4 0x9043 R/W Timer 4 control register B 0x0

TCNT4 0x9047 R Timer 4 counter register B 0x0

TFCON 0x904f R/W FIFO control register of Timer 4 B 0x0

TFSTAT 0x904e R FIFO status register of Timer 4 B 0x0

TFB4 0x904b R/W Timer 4 FIFO register @ byte B 0x0

TFHW4 0x904a R/W Timer 4 FIFO register @ half-word H 0x0

TFW4 0x9048 R/W Timer 4 FIFO register @ word W 0x0

UART ULCON 0x5003 R/W UART line control register B 0x0

UCON 0x5007 R/W UART control register B 0x0

USTAT 0x500b R UART status register B 0x0

UFCON 0x500f R/W UART FIFO control register B 0x0

UFSTAT 0x5012 R UART FIFO status register B 0x0

UTXH 0x5017 R/W UART transmit holding register B 0x0

UTXH_B 0x5017 R/W UART transmit FIFO register @ byte B 0x0

UTXH_HW 0x5016 R/W UART transmit FIFO register

H 0x0

@ half-word

UTXH_W 0x5014 R/W UART transmit FIFO register @ word W 0x0

URXH 0x501b R/W UART receive buffer register B 0x0

URXH_B 0x501b R/W UART receive FIFO register @ byte B 0x0

URXH_HW 0x501a R/W UART receive FIFO register

H 0x0

@ half-word

URXH_W 0x5018 R/W UART receive FIFO register @ word W 0x0

UBRDIV 0x501e R/W Baud rate divisor register for UART H 0x0

1-16

S3C3410X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C3410X Special Function Register (Continued)

Group Register Offset R/W Description Access Reset Value

SIO 0 ITVCNT0 0x6000 R/W SIO 0 interval counter register B 0x0

SBRDR0 0x6001 R/W SIO 0 baud rate prescaler register B 0x0 SIODAT0 0x6002 R/W SIO 0 data register B 0x0 SIOCON0 0x6003 R/W SIO 0 control register B 0x0

SIO 1 ITVCNT1 0x7000 R/W SIO 1 interval counter register B 0x0

SBRDR1 0x7001 R/W SIO 1 baud rate prescaler register B 0x0 SIODAT1 0x7002 R/W SIO 1 data register B 0x0 SIOCON1 0x7003 R/W SIO 1 control register B 0x0

Interrupt INTMOD 0xc000 R/W Interrupt mode register W 0x0

INTPND 0xc004 R/W Interrupt pending register W 0x0 INTMSK 0xc008 R/W Interrupt mask register W 0x0 INTPRI0 0xc00c R/W Interrupt priority register 0 W 0x03020100 INTPRI1 0xc010 R/W Interrupt priority register 1 W 0x07060504 INTPRI2 0xc014 R/W Interrupt priority register 2 W 0x0b0a0908 INTPRI3 0xc018 R/W Interrupt priority register 3 W 0x0f0e0d0c INTPRI4 0xc01c R/W Interrupt priority register 4 W 0x13121110 INTPRI5 0xc020 R/W Interrupt priority register 5 W 0x17161514 INTPRI6 0xc024 R/W Interrupt priority register 6 W 0x1b1a1918 INTPRI7 0xc028 R/W Interrupt priority register 7 W 0x1f1e1d1c

ADC ADCCON 0x8002 R/W A/D Converter control register H 0x140

ADCDAT 0x8006 R A/D Converter data register H 0x0

Basic BTCON 0xa002 R/W Basic Timer control register H 0x0

Timer BTCNT 0xa007 R Basic Timer count register B 0x0

IIC IICCON 0xe000 R/W IIC-bus control register B 0x0

IICSTAT 0xe001 R/W IIC-bus status register B 0x0

IICDS 0xe002 R/W IIC-Bus transmit/receive data shift

B 0x0

IICADD 0xe003 R/W IIC-Bus transmit/receive address

B 0x0

IICPS 0xe004 R/W IIC-Bus Prescaler register B 0x0

IICPCNT 0xe005 R/W IIC-Bus Prescaler Counter register B 0x0

SYSON 0xd003 R/W System control register B 0x0

1-17

PRODUCT OVERVIEW S3C3410X RISC MICROPROCESSOR

Table 1-4. S3C3410X Special Function Register (Continued)

Group Register Offset R/W Description Access Reset Value

RTC RTCCON 0xa013 R/W RTC control register B 0x0

RTCALM 0xa012 R/W RTC alarm control register B 0x0 ALMSEC 0xa033 R/W Alarm second data register B 0x59

ALMMIN 0xa032 R/W Alarm minute data register B 0x59

ALMHOUR 0xa031 R/W Alarm hour data register B 0x23

ALMDAY 0xa037 R/W Alarm day data register B 0x31

ALMMON 0xa036 R/W Alarm month data register B 0x12

ALMYEAR 0xa035 R/W Alarm year data register B 0x99

BCDSEC 0xa023 R/W BCD second data register B –

BCDMIN 0xa022 R/W BCD minute data register B –

BCDHOUR 0xa021 R/W BCD hour data register B –

BCDDAY 0xa027 R/W BCD day data register B –

BCDDATE 0xa020 R/W BCD date data register B –

BCDMON 0xa026 R/W BCD month data register B –

BCDYEAR 0xa025 R/W BCD year data register B –

RINTPND 0xa010 R/W RTC time interrupt pending register B 0x0

RINTCON 0xa011 R/W RTC time interrupt control register B 0x0

1-18

S3C3410X RISC MICROPROCESSOR PROGRAMMER'S MODEL

2 PROGRAMMER'S MODEL

OVERVIEW

S3C3410X was developed using the advanced ARM7TDMI core designed by Advanced RISC Machines, Ltd. ARM7TDMI supports big-endian and little-endian memory formats, but the S3C3410X supports only the bigendian memory format.

PROCESSOR OPERATING STATES

From the programmer's point of view, the ARM7TDMI can be in one of two states:

• ARM state which executes 32-bit, word-aligned ARM instructions.

• THUMB state which operates with 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit

1 to select between alternate halfwords.

NOTE

Transition between these two states does not affect the processor mode or the contents of the registers.

SWITCHING STATE Entering THUMB State

Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand register.

Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the processor in THUMB state.

Entering ARM State

Entry into ARM state happens:

• On execution of the BX instruction with the state bit clear in the operand register.

• On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is

placed in the exception mode's link register, and execution commences at the exception's vector address.

MEMORY FORMATS

ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM7TDMI can treat words in memory as being stored either in Big-Endian or Little-Endian format.

2-1

PROGRAMMER'S MODEL S3C3410X RISC MICROPROCESSOR

BIG-ENDIAN FORMAT

In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.

Higher Address

Lower Address

31 8

4 0

Most significant byte is at lowest address. Word is addressed by byte address of most significant byte.

24 1516

9 5 1

10 6 2

8 7 0

11 7 3

Word Address

8 4 0

Figure 2-1. Big-Endian Addresses of Bytes within Words

LITTLE-ENDIAN FORMAT

In Little-Endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0.

Higher Address

31 23 8 7 0

24 1516

Word Address

8 4 0

Lower Address

11 7 3

Least significant byte is at lowest address. Word is addressed by byte address of least significant byte.

10 6 2

9 5 1

8 4 0

Figure 2-2. Little-Endian Addresses of Bytes whthin Words

INSTRUCTION LENGTH

Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).

Data Types

ARM7TDMI supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to fourbyte boundaries and half words to two-byte boundaries.

2-2

S3C3410X RISC MICROPROCESSOR PROGRAMMER'S MODEL

OPERATING MODES

ARM7TDMI supports seven modes of operation:

• User (usr): The normal ARM program execution state

• FIQ (fiq): Designed to support a data transfer or channel process

• IRQ (irq): Used for general-purpose interrupt handling

• Supervisor (svc): Protected mode for the operating system

• Abort mode (abt): Entered after a data or instruction prefetch abort

• System (sys): A privileged user mode for the operating system

• Undefined (und): Entered when an undefined instruction is executed

Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes' known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources.

REGISTERS

ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer.

The ARM State Register Set

In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (nonUser) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle.

The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information.

and Link (BL) instruction is executed. At all other times it may be treated as a general-purpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when Branch and Link instructions are executed within interrupt or exception routines.

[31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC.

and the current mode bits.

FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.

2-3

PROGRAMMER'S MODEL S3C3410X RISC MICROPROCESSOR

ARM State General Registers and Program Counter

User/System

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC)

CPSR CPSR

FIQ

R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC)

Supervisor IRQAbort Undefined

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC)

ARM State Program Status Registers

CPSR

SPSR_abt

SPSR_fiq

CPSR

SPSR_svc

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC)

CPSR

SPSR_irq

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC)

CPSR

SPSR_und

2-4

= banked register

Figure 2-3. Register Organization in ARM State

S3C3410X RISC MICROPROCESSOR PROGRAMMER'S MODEL

The THUMB State Register Set

The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4.

THUMB State General Registers and Program Counter

User/System

R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC

CPSR CPSR

= banked register

FIQ

R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC

Supervisor IRQAbort Undefined

R0 R1 R2 R3 R4 R5 R6 R7 SP_svc LR_svc PC

R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt PC

THUMB State Program Status Registers

SPSR_fiq

CPSR

SPSR_svc

CPSR

SPSR_abt

R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC

CPSR

SPSR_irq

R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC

CPSR

SPSR_und

Figure 2-4. Register Organization in THUMB state

2-5

PROGRAMMER'S MODEL S3C3410X RISC MICROPROCESSOR

Lo-registersHi-registers

The relationship between ARM and THUMB state registers

The THUMB state registers relate to the ARM state registers in the following way:

• THUMB state R0-R7 and ARM state R0-R7 are identical

• THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical

• THUMB state SP maps onto ARM state R13

• THUMB state LR maps onto ARM state R14

• The THUMB state Program Counter maps onto the ARM state Program Counter (R15)

This relationship is shown in Figure 2-5.

THUMB state ARM state

R0 R1 R2 R3 R4 R5 R6 R7

Stack Pointer (SP)

Link register (LR)

Program Counter (PC)

CPSR SPSR

R0 R1 R2 R3 R4 R5 R6 R7 R8

R9 R10 R11 R12

Stack Pointer (R13)

Link register (R14)

Program Counter (R15)

CPSR SPSR

2-6

Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers

S3C3410X RISC MICROPROCESSOR PROGRAMMER'S MODEL

Accessing Hi-Registers in THUMB State

In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage.

A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register, and from a Hi register to a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions. For more information, refer to Figure 3-34.

THE PROGRAM STATUS REGISTERS

The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These register's functions are:

• Hold information about the most recently performed ALU operation

• Control the enabling and disabling of interrupts

• Set the processor operating mode

The arrangement of bits is shown in Figure 2-6.

Condition Code Flags

30 29 2728 26 25 24 23 8 7 6 5 4 3 2 1 0

N Z C V I F T M4 M3 M2 M1 M0

Overflow Carry/Borrow/Extend Zero Negative/Less Than

(Reserved) Control Bits

Mode bits State bit FIQ disable IRQ disable

Figure 2-6. Program Status Register Format

2-7

PROGRAMMER'S MODEL S3C3410X RISC MICROPROCESSOR

The Condition Code Flags

The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed.

In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details.

The Control Bits

The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will be changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software.

The T bit

This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal.

Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state.

Interrupt disable bits

The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively.

The mode bits

The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor's operating mode, as shown in Table 2-1. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied.

Reserved bits The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits,

you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.

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