SAMSUNG S3C2501X User Guide
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S3C2501X
32-BIT RISC
MICROPROCESSOR
USER'S MANUAL
Revision 1
Important Notice
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S3C2501X RISC Microprocessor
User's Manual, Revision 1
Publication Number: 21-S3-C2501X-122002
© 2002 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
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certification (BSI Certificate No. FM24653). All semiconductor products are designed
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Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Kiheung-Eup
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Printed in the Republic of Korea
Table of Contents
Chapter 1 Product Overview
1.1 Overview...........................................................................................................................................1-1
1.2 Features ............................................................................................................................................ 1-2
1.3 Block Diagram...................................................................................................................................1-4
1.4 Package Diagram ..............................................................................................................................1-5
1.5 Pin Assignment ..................................................................................................................................1-6
1.6 Signal Description..............................................................................................................................1-12
1.7 Pad Type...........................................................................................................................................1-26
1.8 Special Registers...............................................................................................................................1-27
Chapter 2 Programmer's Model
2.1 Overview...........................................................................................................................................2-1
2.2 Switching State..................................................................................................................................2-1
2.2.1 Entering THUMB State...........................................................................................................2-1
2.2.2 Entering ARM State................................................................................................................2-1
2.3 Memory Formats................................................................................................................................2-2
2.3.1 Big-Endian Format..................................................................................................................2-2
2.3.2 Little-Endian Format...............................................................................................................2-2
2.4 Instruction Length .............................................................................................................................. 2-3
2.5 Data Types ........................................................................................................................................2-3
2.6 Operating Modes ............................................................................................................................... 2-3
2.7 Registers ...........................................................................................................................................2-4
2.7.3 The Relationship Between ARM and THUMB State Registers.................................................2-7
2.7.4 Accessing Hi-Registers in THUMB State.................................................................................2-8
2.8 The Program Status Registers...........................................................................................................2-8
2.8.1 The Condition Code Flags ......................................................................................................2-9
2.8.2 The Control Bits...................................................................................................................... 2-9
2.9 Exceptions.........................................................................................................................................2-11
2.9.1 Action on Entering an Exception.............................................................................................2-11
2.9.2 Action on Leaving an Exception..............................................................................................2-11
2.9.3 Exception Entry/Exit Summary...............................................................................................2-12
2.9.4 FIQ.........................................................................................................................................2-12
2.9.5 IRQ.........................................................................................................................................2-13
2.9.6 Abort ......................................................................................................................................2-13
2.9.7 Software Interrupt...................................................................................................................2-14
2.9.8 Undefined Instruction ..............................................................................................................2-14
2.10 Exception Vectors............................................................................................................................2-14
2.10.1 Exception Priorities ...............................................................................................................2-15
2.10.2 Not All Exceptions Can Occur at Once: ................................................................................2-15
2.11 Interrupt Latencies ...........................................................................................................................2-16
2.12 Reset...............................................................................................................................................2-16
2.13 Introduction for ARM940T................................................................................................................2-17
2.14 ARM940T Block Diagram.................................................................................................................2-18
2.15 About The ARM940T Programmer's Model......................................................................................2-19
2.15.1 Data Abort Model.................................................................................................................. 2-20
2.15.2 Instruction Set Extension Spaces.......................................................................................... 2-20
2.16 ARM940T CP15 Registers...............................................................................................................2-21
2.16.1 CP15 Register Map Summary ..............................................................................................2-21
S3C2501X iii
Table of Contents (Continued)
Chapter 3 Instruction Set
3.1 Instruction Set Summay.................................................................................................................... 3-1
3.1.1 Format Summary................................................................................................................... 3-1
3.1.2 Instruction Summary .............................................................................................................. 3-2
3.2 The Condition Field ........................................................................................................................... 3-4
3.3 Branch and Exchange (BX)............................................................................................................... 3-5
3.3.1 Instruction Cycle Times.......................................................................................................... 3-5
3.3.2 Assembler Syntax .................................................................................................................. 3-5
3.3.3 Using R15 as an Operand...................................................................................................... 3-5
3.4 Branch and Branch with Link (B, BL)................................................................................................. 3-7
3.4.1 The Link Bit ........................................................................................................................... 3-7
3.4.2 Instruction Cycle Times.......................................................................................................... 3-7
3.4.3 Assembler Syntax .................................................................................................................. 3-8
3.5 Data Processing ................................................................................................................................ 3-9
3.5.1 CPSR Flags ........................................................................................................................... 3-11
3.5.2 Shifts..................................................................................................................................... 3-12
3.5.3 Immediate Operand Rotates.................................................................................................. 3-16
3.5.4 Writing to R15........................................................................................................................ 3-16
3.5.5 Using R15 as an Operand...................................................................................................... 3-16
3.5.6 Teq, Tst, Cmp and CMN Opcodes......................................................................................... 3-16
3.5.7 Instruction Cycle Times.......................................................................................................... 3-17
3.6.8 Assembler Syntax .................................................................................................................. 3-17
3.6 PSR Transfer (MRS, MSR)............................................................................................................... 3-19
3.6.1 Operand Restrictions ............................................................................................................. 3-19
3.6.2 Reserved Bits........................................................................................................................ 3-21
3.6.3 Instruction Cycle Times.......................................................................................................... 3-21
3.6.4 Assembler Syntax .................................................................................................................. 3-22
3.7 Multiply and Multiply-Accumulate (MUL, MLA).................................................................................. 3-23
3.7.1 CPSR Flags ........................................................................................................................... 3-24
3.7.2 Instruction Cycle Times.......................................................................................................... 3-24
3.7.3 Assembler Syntax .................................................................................................................. 3-24
3.8 Multiply Long and Multiply-Accumulate Long (MULL, MLAL)............................................................. 3-25
3.8.1 Operand Restrictions ............................................................................................................. 3-25
3.8.2 CPSR Flags ........................................................................................................................... 3-26
3.8.3 Instruction Cycle Times.......................................................................................................... 3-26
3.8.4 Assembler Syntax .................................................................................................................. 3-27
3.9 Single Data Transfer (LDR, STR)...................................................................................................... 3-28
3.9.1 Offsets and Auto-Indexing ..................................................................................................... 3-29
3.9.2 Shifted Register Offset........................................................................................................... 3-29
3.9.3 Bytes and Words ................................................................................................................... 3-29
3.9.4 Use of R15............................................................................................................................. 3-31
3.9.5 Restriction on the Use of Base Register................................................................................. 3-31
3.9.6 Data Aborts............................................................................................................................ 3-31
3.9.7 Instruction Cycle Times.......................................................................................................... 3-31
3.9.8 Assembler Syntax .................................................................................................................. 3-32
iv S3C2501X
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.10 Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH).................................................3-34
3.10.1 Offsets and Auto-Indexing .................................................................................................... 3-35
3.10.2 Half-Word Load and Stores ..................................................................................................3-36
3.10.3 Signed Byte and Half-Word Loads........................................................................................3-36
3.10.4 Endianness and Byte/Half-Word Selection............................................................................ 3-36
3.10.5 Use of R15 ...........................................................................................................................3-37
3.10.6 Data Aborts...........................................................................................................................3-37
3.10.7 Instruction Cycle Times ........................................................................................................3-37
3.10.8 Assembler Syntax................................................................................................................. 3-38
3.11 Block Data Transfer (LDM, STM).....................................................................................................3-40
3.11.1 The Register List...................................................................................................................3-40
3.11.2 Addressing Modes ................................................................................................................3-41
3.11.3 Address Alignment................................................................................................................3-41
3.11.4 Use of the S Bit ....................................................................................................................3-43
3.11.5 Use of R15 as the Base........................................................................................................3-43
3.11.6 Inclusion of the Base in the Register List...............................................................................3-44
3.11.7 Data Aborts...........................................................................................................................3-44
3.11.8 Instruction Cycle Times ........................................................................................................3-44
3.11.9 Assembler Syntax................................................................................................................. 3-45
3.12 Single Data Swap (SWP).................................................................................................................3-47
3.12.1 Bytes and Words ..................................................................................................................3-47
3.12.2 Use of R15 ...........................................................................................................................3-47
3.12.3 Data Aborts...........................................................................................................................3-48
3.12.4 Instruction Cycle Times ........................................................................................................3-48
3.12.5 Assembler Syntax................................................................................................................. 3-48
3.13 Software Interrupt (SWI)..................................................................................................................3-49
3.13.1 Return from the Supervisor................................................................................................... 3-49
3.13.2 Comment Field.....................................................................................................................3-49
3.13.3 Instruction Cycle Times ........................................................................................................3-49
3.13.4 Assembler Syntax................................................................................................................. 3-50
3.14 Coprocessor Data Operations (CDP)................................................................................................3-51
3.14.1 Coprocessor Instructions.......................................................................................................3-51
3.14.2 The Coprocessor Fields........................................................................................................3-51
3.14.3 Instruction Cycle Times ........................................................................................................3-52
3.14.4 Assembler Syntax................................................................................................................. 3-52
3.15 Coprocessor Data Transfers (LDC, STC) ......................................................................................... 3-53
3.15.1 The Coprocessor Fields........................................................................................................3-53
3.15.2 Addressing Modes ................................................................................................................3-54
3.15.3 Address Alignment................................................................................................................3-54
3.15.4 Use of R15 ...........................................................................................................................3-54
3.15.5 Data Aborts...........................................................................................................................3-54
3.15.6 Instruction Cycle Times ........................................................................................................3-54
3.15.7 Assembler Syntax................................................................................................................. 3-55
S3C2501X v
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.16 Coprocessor Register Transfers (MRC, MCR)................................................................................. 3-56
3.16.1 The Coprocessor Fields....................................................................................................... 3-56
3.16.2 Transfers to R15.................................................................................................................. 3-57
3.16.3 Transfers from R15.............................................................................................................. 3-57
3.16.4 Instruction Cycle Times........................................................................................................ 3-57
3.16.5 Assembler Syntax................................................................................................................ 3-57
3.17 Undefined Instruction ...................................................................................................................... 3-58
3.17.1 Instruction Cycle Times........................................................................................................ 3-58
3.17.2 Assembler Syntax................................................................................................................ 3-58
3.18 Instruction Set Examples................................................................................................................. 3-59
3.18.1 Using The Conditional Instructions....................................................................................... 3-59
3.18.2 Pseudo-Random Binary Sequence Generator...................................................................... 3-61
3.18.3 Multiplication by Constant Using The Barrel Shifter.............................................................. 3-61
3.18.4 Loading a Word From an Unknown Alignment..................................................................... 3-63
3.19 Thumb Instruction Set Format......................................................................................................... 3-64
3.19.1 Format Summary ................................................................................................................. 3-64
3.19.2 Opcode Summary ................................................................................................................ 3-65
3.20 Format 1: Move Shifted Register..................................................................................................... 3-67
3.20.1 Operation............................................................................................................................. 3-67
3.20.2 Instruction Cycle Times........................................................................................................ 3-67
3.21 Format 2: Add/Subtract................................................................................................................... 3-68
3.21.1 Operation............................................................................................................................. 3-68
3.21.2 Instruction Cycle Times........................................................................................................ 3-69
3.22 Format 3: Move/Compare/Add/Subtract Immediate......................................................................... 3-70
3.22.1 Operations........................................................................................................................... 3-70
3.22.2 Instruction Cycle Times........................................................................................................ 3-70
3.23 Format 4: ALU Operations .............................................................................................................. 3-71
3.23.1 Operation............................................................................................................................. 3-71
3.23.2 Instruction Cycle Times........................................................................................................ 3-72
3.24 Format 5: Hi-Register Operations/Branch Exchange ....................................................................... 3-73
3.24.1 Operation............................................................................................................................. 3-73
3.24.2 Instruction Cycle Times........................................................................................................ 3-74
3.24.3 The Bx Instruction ................................................................................................................ 3-74
3.24.4 Using R15 as an Operand.................................................................................................... 3-75
3.25 Format 6: PC-Relative Load............................................................................................................ 3-76
3.25.1 Operation............................................................................................................................. 3-76
3.25.2 Instruction Cycle Times........................................................................................................ 3-76
3.26 Format 7: Load/Store With Register Offset...................................................................................... 3-77
3.26.1 Operation............................................................................................................................. 3-77
3.26.2 Instruction Cycle Times........................................................................................................ 3-78
3.27 Format 8: Load/Store Sign-Extended Byte/Half-Word ..................................................................... 3-79
3.27.1 Operation............................................................................................................................. 3-79
3.27.2 Instruction Cycle Times........................................................................................................ 3-80
vi S3C2501X
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.28 Format 9: Load/Store with Immediate Offset....................................................................................3-81
3.28.1 Operation..............................................................................................................................3-81
3.28.2 Instruction Cycle Times ........................................................................................................3-82
3.29 Format 10: Load/Store Half-Word....................................................................................................3-83
3.29.1 Operation..............................................................................................................................3-83
3.29.2 Instruction Cycle Times ........................................................................................................3-83
3.30 Format 11: SP-Relative Load/Store .................................................................................................3-84
3.30.1 Operation..............................................................................................................................3-84
3.30.2 Instruction Cycle Times ........................................................................................................3-84
3.31 Format 12: Load Addres...................................................................................................................3-85
3.31.1 Operation..............................................................................................................................3-85
3.31.2 Instruction Cycle Times ........................................................................................................3-86
3.32 Format 13: Add Offset to Stack Pointer............................................................................................ 3-87
3.32.1 Operation..............................................................................................................................3-87
3.32.2 Instruction Cycle Times ........................................................................................................3-87
3.33 Format 14: Push/Pop Registers........................................................................................................3-88
3.33.1 Operation..............................................................................................................................3-88
3.33.2 Instruction Cycle Times ........................................................................................................3-89
3.34 Format 15: Multiple Load/Store........................................................................................................3-90
3.34.1 Operation..............................................................................................................................3-90
3.34.2 Instruction Cycle Times ........................................................................................................3-90
3.35 Format 16: Conditional Branch.........................................................................................................3-91
3.35.1 Operation..............................................................................................................................3-91
3.35.2 Instruction Cycle Times ........................................................................................................3-92
3.36 Format 17: Software Interrupt .......................................................................................................... 3-93
3.36.1 Operation..............................................................................................................................3-93
3.36.2 Instruction Cycle Times ........................................................................................................3-93
3.37 Format 18: Unconditional Branch.....................................................................................................3-94
3.37.1 Operation..............................................................................................................................3-94
3.38 Format 19: Long Branch With Link ...................................................................................................3-95
3.38.1 Operation..............................................................................................................................3-95
3.38.2 Instruction Cycle Times ........................................................................................................3-96
3.39 Instruction Set Examples ................................................................................................................. 3-97
3.39.1 Multiplication by a Constant Using Shifts and Adds ...............................................................3-97
3.39.2 General Purpose Signed Divide............................................................................................3-98
3.39.3 Division by a Constant..........................................................................................................3-100
S3C2501X vii
Table of Contents (Continued)
Chapter 4 System Configuration
4.1 Overview .......................................................................................................................................... 4-1
4.2 Features............................................................................................................................................ 4-1
4.3 Address Map..................................................................................................................................... 4-2
4.4 Remap of Memory Space ................................................................................................................. 4-3
4.5 External Address Translation ............................................................................................................ 4-3
4.6 Arbitration Scheme ........................................................................................................................... 4-4
4.6.1 Problem Solvings with Programmable Round-Robin.............................................................. 4-7
4.7 Clock Configuration........................................................................................................................... 4-9
4.8 System Configuration Special Registers............................................................................................ 4-15
4.8.1 System Configuration Register............................................................................................... 4-16
4.8.2 Product Code and Revision Number Register........................................................................ 4-18
4.8.3 Clock Control Register........................................................................................................... 4-19
4.8.4 Peripheral Clock Disable Register .......................................................................................... 4-20
4.8.5 Clock Status Register ............................................................................................................ 4-21
4.8.6 AHB Bus Master Priority Register .......................................................................................... 4-21
4.8.7 Core PLL Control Register..................................................................................................... 4-22
4.8.8 System Bus PLL Control Register.......................................................................................... 4-23
4.8.9 PHY PLL Control Register ..................................................................................................... 4-24
Chapter 5 Memory Controller
5.1 Overview .......................................................................................................................................... 5-1
5.2 Features............................................................................................................................................ 5-2
5.3 Memory Map ..................................................................................................................................... 5-3
5.4 Bus Interface Signals........................................................................................................................ 5-5
5.5 Endian Modes................................................................................................................................... 5-7
5.6 Ext I/O Bank Controller..................................................................................................................... 5-13
5.6.1 Features ................................................................................................................................ 5-13
5.6.2 External Device Connection................................................................................................... 5-14
5.6.3 Ext. I/O Bank Controller Special Register............................................................................... 5-21
5.6.4 Timing Diagram..................................................................................................................... 5-29
5.7 SDRAM Controller ............................................................................................................................ 5-38
5.7.1 Features ................................................................................................................................ 5-38
5.7.2 SDRAM Size and Configuration............................................................................................. 5-39
5.7.3 Address Mapping................................................................................................................... 5-42
5.7.4 SDRAM Commands............................................................................................................... 5-44
5.7.5 External Data Bus Width........................................................................................................ 5-45
5.7.6 Merging Write Buffer ............................................................................................................. 5-45
5.7.7 Self Refresh........................................................................................................................... 5-45
5.7.8 Basic Operation..................................................................................................................... 5-46
5.7.9 SDRAM Special Registers ..................................................................................................... 5-47
5.7.10 SDRAM Controller Timing.................................................................................................... 5-54
viii S3C2501X
Table of Contents (Continued)
Chapter 6 I2C Bus Controller
6.1 Overview...........................................................................................................................................6-1
6.2 Features ............................................................................................................................................ 6-1
6.3 Functional Description .......................................................................................................................6-2
6.4 I2C Concepts .....................................................................................................................................6-3
6.4.1 Basic Operation......................................................................................................................6-3
6.4.2 General Characteristics .......................................................................................................... 6-4
6.4.3 Bit Transfers...........................................................................................................................6-4
6.4.4 Data Validity...........................................................................................................................6-5
6.4.5 Start and Stop Conditions.......................................................................................................6-5
6.4.6 Data Transfer Operations .......................................................................................................6-6
6.5 I2C Special Registers.........................................................................................................................6-8
6.5.1 Control Status Register ...........................................................................................................6-8
6.5.2 Shift Buffer Register...............................................................................................................6-10
6.5.3 Prescaler Register..................................................................................................................6-10
6.5.4 Prescaler Counter Register.....................................................................................................6-11
6.5.5 Interrupt Pending Register......................................................................................................6-11
Chapter 7 Ethernet Controller
7.1 Overview...........................................................................................................................................7-1
7.2 Features ............................................................................................................................................ 7-2
7.3 MAC Function Blocks.........................................................................................................................7-3
7.3.1 Media Independent Interface (MII)..........................................................................................7-3
7.3.2 Physical Layer Entity (PHY) ....................................................................................................7-4
7.3.3 Buffered Dma Interface (BDI).................................................................................................7-4
7.3.4 The MAC Transmitter Block.................................................................................................... 7-4
7.3.5 The MAC Receiver Block........................................................................................................7-6
7.3.6 Flow Control Block..................................................................................................................7-7
7.3.7 Buffered DMA (BDMA) Overview ...........................................................................................7-7
7.4 Ethernet Controller Special Registers.................................................................................................7-13
7.4.1 BDMA Relative Special Register ............................................................................................7-15
7.4.2 MAC Relative Special Register ...............................................................................................7-24
7.5 Ethernet Operations...........................................................................................................................7-37
7.5.1 MAC Frame Format................................................................................................................ 7-37
7.5.2 The MII Station Manager ........................................................................................................7-45
7.5.3 Full-Duplex Pause Operations................................................................................................7-46
7.5.4 Error Signalling .......................................................................................................................7-48
7.5.5 Timing Parameters for MII Transactions.................................................................................7-50
S3C2501X ix
Table of Contents (Continued)
Chapter 8 DES/3DES
8.1 Overview .......................................................................................................................................... 8-1
8.2 Feature............................................................................................................................................. 8-1
8.3 DES/3DES Special Registers............................................................................................................ 8-3
8.3.1 DES/3DES Control Register................................................................................................... 8-4
8.3.2 DES/3DES Status Register.................................................................................................... 8-5
8.3.3 DES/3DES Interrupt Enable Register..................................................................................... 8-6
8.3.4 DES/3DES Run Enable Register............................................................................................ 8-6
8.3.5 DES/3DES Key1 Left/Right Side Register .............................................................................. 8-6
8.3.6 DES/3DES Key 2 Left/Right Side Register ............................................................................. 8-7
8.3.7 DES/3DES Key 3 Left Side Register...................................................................................... 8-7
8.3.8 DES/3DES IV Left/Right Side Register .................................................................................. 8-7
8.3.9 DES/3DES Input/Output Data FIFO Register......................................................................... 8-8
8.4 DES/3DES Operation........................................................................................................................ 8-9
8.5 Performance Calculation Guide ........................................................................................................ 8-10
Chapter 9 GDMA Controller
9.1 Overview .......................................................................................................................................... 9-1
9.2 Feature............................................................................................................................................. 9-1
9.3 GDMA Special Registers................................................................................................................... 9-3
9.3.1 GDMA Programmable Priority Registers................................................................................ 9-4
9.3.2 GDMA Control Registers........................................................................................................ 9-9
9.3.3 GDMA Source/Destination Address Registers........................................................................ 9-12
9.3.4 GDMA Transfer Count Registers............................................................................................ 9-13
9.3.5 GDMA Run Enable Registers................................................................................................. 9-14
9.3.6 GDMA Interrupt Pending Register .......................................................................................... 9-15
9.4 GDMA Mode Operation..................................................................................................................... 9-16
9.4.1 Software Mode....................................................................................................................... 9-16
9.4.2 External GDMA Request Mode.............................................................................................. 9-16
9.4.3 HUART Mode ........................................................................................................................ 9-16
9.4.4 DES Mode............................................................................................................................. 9-17
9.5 GDMA Function Description.............................................................................................................. 9-17
9.5.1 GDMA Transfers .................................................................................................................... 9-17
9.5.2 Starting/Ending GDMA Transfers........................................................................................... 9-17
9.5.3 Data Transfer Modes ............................................................................................................. 9-18
9.6 GDMA Transfer Timing Data............................................................................................................. 9-19
9.6.1 Single and One Data Burst Mode .......................................................................................... 9-20
9.6.2 Single and Four Data Burst Mode.......................................................................................... 9-21
9.6.3 Block and One Data Burst Mode............................................................................................ 9-22
9.6.4 Block and Four Data Burst..................................................................................................... 9-23
x S3C2501X
Table of Contents (Continued)
Chapter 10 Serial I/O (Console UART)
10.1 Overview .........................................................................................................................................10-1
10.2 Features ..........................................................................................................................................10-1
10.3 Console UART Special Registers.....................................................................................................10-3
10.3.1 Console UART Control Registers..........................................................................................10-4
10.3.2 Console UART Status Registers ...........................................................................................10-8
10.3.3 Console UART Interrupt Enable Register..............................................................................10-11
10.3.4 UART Transmit Data Register ..............................................................................................10-13
10.3.5 UART Receive Data Register ............................................................................................... 10-14
10.3.6 UART Baud Rate Divisor Register........................................................................................10-15
10.3.7 Console UART Baud Rate Examples....................................................................................10-16
10.3.8 UART Control Character Register 1 and 2 ............................................................................ 10-17
Chapter 11Serial I/O (High-Speed UART)
11.1 Overview .........................................................................................................................................11-1
11.2 Features ..........................................................................................................................................11-1
11.3 High-Speed UART Special Registers...............................................................................................11-3
11.3.1 High-Speed UART Control Registers....................................................................................11-4
11.3.2 High-Speed UART Status Registers......................................................................................11-9
11.3.3 High-Speed UART Interrupt Enable Register ........................................................................11-14
11.3.4 High-Speed UART Transmit Buffer Register.........................................................................11-16
11.3.5 High-Speed UART Receive Buffer Register..........................................................................11-17
11.3.6 High-Speed UART Baud Rate Divisor Register.....................................................................11-18
11.3.7 High-Speed UART Baud Rate Examples..............................................................................11-19
11.3.8 High-Speed UART Control Character 1 Register................................................................... 11-20
11.3.9 High-Speed UART Control Character 2 Register................................................................... 11-21
11.3.10 High-Speed UART Autoband Boundary Register.................................................................11-22
11.3.11 High-Speed UART Autobaud Table Regsiter.......................................................................11-23
11.4 High-Speed UART Operation...........................................................................................................11-24
11.4.1 FIFO Operation ....................................................................................................................11-24
11.4.2 Hardware Flow Control ......................................................................................................... 11-24
11.4.3 Software Flow Control...........................................................................................................11-26
11.4.4 Auto Baud Rate Detection.....................................................................................................11-26
Chapter 12I/O Ports
12.1 Overview .........................................................................................................................................12-1
12.2 Features ..........................................................................................................................................12-1
12.3 I/O Port Special Register..................................................................................................................12-2
12.3.1 I/O Port Mode Select Register .............................................................................................. 12-2
12.3.2 I/O Port Function Control Register........................................................................................12-4
12.3.3 I/O Port Control Register for GDMA......................................................................................12-7
12.3.4 I/O Port Control Register for External Interrupt .....................................................................12-8
12.3.5 I/O Port External Interrupt Clear Register..............................................................................12-10
12.3.6 I/O Port Data Register ..........................................................................................................12-11
12.3.7 I/O Port Drive Control Register.............................................................................................12-11
S3C2501X xi
Table of Contents (Concluded)
Chapter 13Interrupt Controller
13.1 Overview ........................................................................................................................................ 13-1
13.2 Features.......................................................................................................................................... 13-1
13.3 Interrupt Sources............................................................................................................................. 13-2
13.4 Interrupt Controller Special Registers.............................................................................................. 13-3
13.4.1 Interrupt Mode Registers ...................................................................................................... 13-3
13.4.2 Interrupt Mask Registers...................................................................................................... 13-5
12.4.3 Interrupt Priority Registers ................................................................................................... 13-8
13.4.4 Interrupt Offset Register....................................................................................................... 13-9
13.4.5 Interrupt by Priority Register ................................................................................................ 13-12
13.4.6 Interrupt Test Register ......................................................................................................... 13-12
Chapter 1432-bit Timers
14.1 Overview ........................................................................................................................................ 14-1
14.2 Feature ........................................................................................................................................... 14-1
14.3 Interval Mode Operation.................................................................................................................. 14-2
14.4 Toggle Mode Operation................................................................................................................... 14-2
14.5 Timer Operation Guidelines ............................................................................................................ 14-3
14.6 Timer Special Register .................................................................................................................... 14-4
14.6.1 Timer Mode Register ........................................................................................................... 14-4
14.6.2 Timer Data Registers........................................................................................................... 14-6
14.6.3 Timer Count Registers......................................................................................................... 14-7
14.6.4 Timer Interrupt Clear Registers............................................................................................ 14-8
14.6.5 Watchdog Timer Register.................................................................................................... 14-9
Chapter 15Electrical Data
15.1 Overview ........................................................................................................................................ 15-1
15.2 Absolute Maximum Ratings............................................................................................................. 15-1
15.3 Recommended Operating Conditions.............................................................................................. 15-1
15.4 DC Electrical Specifications ............................................................................................................ 15-2
15.5 AC Electrical Characteristics........................................................................................................... 15-4
Chapter 16Mechanical Data
16.1 Overview ........................................................................................................................................ 16-1
xii S3C2501X
List of Figures
Figure Title Page
Number Number
1-1 S3C2501X Block Diagram......................................................................................1-4
1-2 S3C2501X Pin Assignment Diagram ...................................................................... 1-5
2-1 Big-Endian Addresses of Bytes within Words..........................................................2-2
2-2 Little-Endian Addresses of Bytes Words.................................................................2-2
2-3 Register Organization in ARM State.......................................................................2-5
2-4 Register Organization in THUMB State ..................................................................2-6
2-5 Mapping of THUMB State Registers onto ARM State Registers ..............................2-7
2-6 Program Status Register Format............................................................................2-8
2-7 ARM940T Block Diagram.......................................................................................2-18
3-1 ARM Instruction Set Format ...................................................................................3-1
3-2 Branch and Exchange Instructions..........................................................................3-5
3-3 Branch Instructions .................................................................................................3-7
3-4 Data Processing Instructions .................................................................................. 3-9
3-5 ARM Shift Operations.............................................................................................3-12
3-6 Logical Shift Left .................................................................................................... 3-12
3-7 Logical Shift Right..................................................................................................3-13
3-8 Arithmetic Shift Right .............................................................................................3-13
3-9 Rotate Right...........................................................................................................3-14
3-10 Rotate Right Extended ........................................................................................... 3-14
3-11 PSR Transfer ......................................................................................................... 3-20
3-12 Multiply Instructions ................................................................................................3-23
3-13 Multiply Long Instructions.......................................................................................3-25
3-14 Single Data Transfer Instructions............................................................................ 3-28
3-15 Little-Endian Offset Addressing ..............................................................................3-30
3-16 Half-word and Signed Data Transfer with Register Offset.......................................3-34
3-17 Half-word and Signed Data Transfer with Immediate Offset and Auto-Indexing......3-35
3-18 Block Data Transfer Instructions.............................................................................3-40
3-19 Post-Increment Addressing.....................................................................................3-41
3-20 Pre-Increment Addressing......................................................................................3-42
3-21 Post-Decrement Addressing...................................................................................3-42
3-22 Pre-Decrement Addressing.....................................................................................3-43
3-23 Swap Instruction.....................................................................................................3-47
3-24 Software Interrupt Instruction.................................................................................. 3-49
3-25 Coprocessor Data Operation Instruction .................................................................3-51
3-26 Coprocessor Data Transfer Instructions..................................................................3-53
3-27 Coprocessor Register Transfer Instructions ............................................................ 3-56
3-28 Undefined Instruction..............................................................................................3-58
3-29 THUMB Instruction Set Formats.............................................................................3-64
S3C2501X xiii
List of Figures (Continued)
Figure Title Page
Number Number
3-30 Format 1................................................................................................................ 3-67
3-31 Format 2................................................................................................................ 3-68
3-32 Format 3................................................................................................................ 3-70
3-33 Format 4................................................................................................................ 3-71
3-34 Format 5................................................................................................................ 3-73
3-35 Format 6................................................................................................................ 3-76
3-36 Format 7................................................................................................................ 3-77
3-37 Format 8................................................................................................................ 3-79
3-38 Format 9................................................................................................................ 3-81
3-39 Format 10.............................................................................................................. 3-83
3-40 Format 11.............................................................................................................. 3-84
3-41 Format 12.............................................................................................................. 3-85
3-42 Format 13.............................................................................................................. 3-87
3-43 Format 14.............................................................................................................. 3-88
3-44 Format 15.............................................................................................................. 3-90
3-45 Format 16.............................................................................................................. 3-91
3-46 Format 17.............................................................................................................. 3-93
3-47 Format 18.............................................................................................................. 3-94
3-48 Format 19.............................................................................................................. 3-95
4-1 S3C2501X Address map after resest..................................................................... 4-2
4-2 External Address Bus Diagram.............................................................................. 4-4
4-3 Priority Groups of S3C2501X................................................................................. 4-5
4-4 AHB Programmable Priority Registers................................................................... 4-6
4-5 Shows the Clock Generation Logic of the S3C2501X ............................................. 4-14
4-6 Divided System Clock Timing Diagram.................................................................. 4-19
5-1 Memory Bank Address map................................................................................... 5-4
5-2 Memory Controller Bus Signals.............................................................................. 5-6
5-3 8-bit ROM, SRAM and Flash Basic Connection ..................................................... 5-14
5-4 8-bit ROM, SRAM and Flash Basic Connection (8-bit Memory x 2)........................ 5-15
5-5 16-bit SRAM Basic Connection .............................................................................. 5-16
5-6 16-bit ROM and Flash Basic Connection ............................................................... 5-17
5-7 16-bit ROM Basic Connection 2 ............................................................................. 5-18
5-8 16-bit SRAM Basic Connection 2........................................................................... 5-19
5-9 ROM & SRAM with Muxed Address & Data Bus Connection.................................. 5-20
5-10 BnCON.................................................................................................................. 5-22
5-11 Bank n Control (BnCON) Register Configuration.................................................... 5-24
5-12 Muxed Bus Control (MUXBCON) Register Configuration....................................... 5-26
5-13 Wait Control (WAITCON) Register Configuration .................................................. 5-28
xiv S3C2501X
List of Figures (Continued)
Figure Title Page
Number Number
5-14 Read Timing Diagram 1 .........................................................................................5-29
5-15 Write Timing Diagram 1 .........................................................................................5-30
5-16 Read Timing Diagram 2 .........................................................................................5-31
5-17 Write Timing Diagram 2 .........................................................................................5-32
5-18 Read after Write at the Same Bank (COHDIS = 1).................................................5-33
5-19 Read Timing Diagram (Muxed Bus)........................................................................5-34
5-20 Write Timing Diagram (Muxed Bus) .......................................................................5-35
5-21 Write Timing Diagram (nEWAIT)............................................................................5-36
5-22 Write Timing Diagram (nREADY)...........................................................................5-37
5-23 SDRAM Configuration Register 0 ...........................................................................5-49
5-24 SDRAM Command Register...................................................................................5-51
5-25 SDRAM Refresh Timer Register .............................................................................5-52
5-26 SDRAM Write Buffer Time-out Register.................................................................5-53
5-27 Single Read Operation (CAS Latency=2)................................................................5-54
5-28 Single Read Operation (CAS Latency=3)................................................................5-55
5-29 Single Write Operation...........................................................................................5-56
5-30 Burst Read Operation (CAS Latency = 2)...............................................................5-57
5-31 Burst Read Operation (CAS Latency = 3)...............................................................5-58
5-32 Burst Write Operation............................................................................................. 5-59
6-1 I2C Block Diagram.................................................................................................. 6-1
6-2 Master Transmitter and Slave Receiver..................................................................6-3
6-3 Master Receiver and Slave Transmitter..................................................................6-4
6-4 Start and Stop Conditions .......................................................................................6-5
6-5 Data Transfer Format.............................................................................................6-7
6-6 I2C Control Status Register.....................................................................................6-10
7-1 Ethernet Diagram...................................................................................................7-1
7-2 Data Structure of Tx Buffer Descriptor.................................................................... 7-10
7-3 Data Structure of Rx Buffer Descriptor ................................................................... 7-11
7-4 Data Structure of the Receive Frame .....................................................................7-12
7-5 Fields of an IEEE802.3/Ethernet Frame ................................................................. 7-38
7-6 CSMA/CD Transmit Operation ...............................................................................7-40
7-7 Timing for Transmission without Collision ...............................................................7-41
7-8 Timing for Transmission with Collision in Preamble................................................7-42
7-9 Receiving Frame without Error...............................................................................7-43
7-10 Receiving Frame with Error....................................................................................7-43
7-11 CSMA/CD Receive Operation ................................................................................ 7-44
7-12 MAC Control Frame Format...................................................................................7-46
7-13 Timing Relationship of Transmission Signals at MII................................................7-50
7-14 Timing Relationship of Reception Signals at MII .....................................................7-50
7-15 MDIO Sourced by PHY...........................................................................................7-50
7-16 MDIO Sourced by STA...........................................................................................7-50
8-1 DES/3DES Block Diagram .....................................................................................8-2
S3C2501X xv
List of Figures (Continued)
Figure Title Page
Number Number
9-1 GDMA Controller Block Diagram........................................................................... 9-2
9-2 GDMA Programmable Priority Registers................................................................ 9-5
9-3 GDMA Control Register......................................................................................... 9-11
9-4 GDMA Source/Destination Address Register ......................................................... 9-12
9-5 GDMA Transfer Count Register............................................................................. 9-13
9-6 GDMA Run Enable Register.................................................................................. 9-14
9-7 GDMA Interrupt Pending Register.......................................................................... 9-15
9-8 External GDMA Requests (Single Mode)............................................................... 9-18
9-9 External GDMA Requests (Block Mode)................................................................ 9-18
9-10 External GDMA Requests Detailed Timing ............................................................ 9-19
9-11 Single and One Data Burst Mode Timing............................................................... 9-20
9-12 Single and Four Data Burst Mode Timing .............................................................. 9-21
9-13 Block and One Data Burst Mode Timing................................................................ 9-22
9-14 Block and Four Data Burst Timing......................................................................... 9-23
10-1 Console UART Block Diagram............................................................................... 10-2
10-2 Console UART Control Register ............................................................................ 10-6
10-3 Console UART Control Register ............................................................................ 10-7
10-4 Console UART Status Register .............................................................................. 10-10
10-5 Console UART Interrupt Enable Register ............................................................... 10-12
10-6 Console UART Transmit Data Register.................................................................. 10-13
10-7 Console UART Receive Data Register................................................................... 10-14
10-8 Console UART Baud Rate Divisor Register ........................................................... 10-15
10-9 Console UART Baud Rate Generator (BRG).......................................................... 10-16
10-10 Console UART Control Character 1 Register......................................................... 10-17
10-11 Console UART Control Character 2 Register......................................................... 10-17
10-12 Interrupt-Based Serial I/O Transmit and Receive Timing Diagram......................... 10-18
10-13 Serial I/O Frame Timing Diagram (Normal Console UART)................................... 10-19
10-14 Infra-Red Transmit Mode Frame Timing Diagram.................................................. 10-19
10-15 Infra-Red Receive Mode Frame Timing Diagram................................................... 10-20
11-1 High-Speed UART Block Diagram......................................................................... 11-2
11-2 High-Speed UART Control Register....................................................................... 11-7
11-3 High-Speed UART Status Register........................................................................ 11-12
11-4 High-Speed UART Interrupt Enable Register......................................................... 11-15
11-5 High-Speed UART Transmit Buffer Register .......................................................... 11-16
11-6 High-Speed UART Receive Buffer Register........................................................... 11-17
11-7 High-Speed UART Baud Rate Divisor Register...................................................... 11-18
11-8 High-Speed UART Baud Rate Generator (BRG).................................................... 11-19
11-9 High-Speed UART Control Character 1 Register.................................................... 11-20
11-10 High-Speed UART Control Character 2 Register.................................................... 11-21
xvi S3C2501X
List of Figures (Concluded)
Figure Title Page
Number Number
11-11 AutoBaud Boundary Register Range ...................................................................... 11-22
11-12 High-Speed UART AutoBaud Boundary Register.................................................... 11-22
11-13 Example of AutoBaud Table Register Setting.........................................................11-23
11-14 High-Speed UART AutoBaud Table Register ..........................................................11-23
11-15 When CTS Signal Level is High During Transmit Operation...................................11-25
11-16 When CTS Signal Level is Low During Transmit Operation....................................11-25
11-17 Normal Received Rx Data......................................................................................11-26
11-18 DCD Lost During Rx Data Receive.........................................................................11-26
11-19 Interrupt-Based Serial I/O Transmit and Receive Timing Diagram ..........................11-27
11-20 DMA-Based Serial I/O Timing Diagram (Tx Only)...................................................11-28
11-21 DMA-Based Serial I/O Timing Diagram (Rx Only) ..................................................11-28
11-22 Serial I/O Frame Timing Diagram (Normal High-Speed UART)..............................11-29
11-23 Infra-Red Transmit Mode Frame Timing Diagram...................................................11-29
11-24 Infra-Red Receive Mode Frame Timing Diagram ...................................................11-30
12-1 I/O Port Mode Registers 1/2 ...................................................................................12-3
12-2 I/O Function Control Register 1 ..............................................................................12-5
12-3 I/O Function Control Register 2 ..............................................................................12-6
12-4 I/O Port Control Register for GDMA........................................................................12-7
12-5 I/O Port Control Register for External Interrupt.......................................................12-9
12-6 I/O Port External Interrupt Clear Register...............................................................12-10
13-1 Internal Interrupt Mode Register .............................................................................13-4
13-2 External Interrupt Mode Register............................................................................13-5
13-3 Internal Interrupt Mask Register.............................................................................. 13-6
13-4 External Interrupt Mask Register ............................................................................13-7
13-5 Interrupt Priority Register........................................................................................13-8
14-1 Timer Output Signal Timing....................................................................................14-2
14-2 32-Bit Timer Block Diagram ...................................................................................14-3
14-3 Timer Mode Register..............................................................................................14-5
14-4 Timer Data Registers..............................................................................................14-6
14-5 Timer Count Registers............................................................................................14-7
14-6 Timer Interrupt Clear Register................................................................................14-8
14-7 Watchdog Timer Register....................................................................................... 14-9
16-1 272-BGA-2727-AN Package Dimensions................................................................ 16-2
S3C2501X xvii
List of Tables
Table Title Page
Number Number
1-1 S3C2501X Signal Descriptions...............................................................................1-12
1-2 S3C2501X Pad Type and Feature..........................................................................1-26
1-3 S3C2501X System Configuration ........................................................................... 1-27
1-4 S3C2501X Memory Controller................................................................................1-27
1-5 S3C2501X SDRAM Controller................................................................................1-27
1-6 S3C2501X IIC Controller........................................................................................1-28
1-7 S3C2501X Ethernet Controller 0.............................................................................1-28
1-8 S3C2501X Ethernet Controller 1.............................................................................1-29
1-9 S3C2501X DES Controller......................................................................................1-30
1-10 S3C2501X GDMA Controller..................................................................................1-31
1-11 S3C2501X Console UART Controller......................................................................1-32
1-12 S3C2501X High speed UART Controller................................................................. 1-32
1-13 S3C2501X I/O Port Controller.................................................................................1-33
1-14 S3C2501X Interrupt Controller................................................................................ 1-33
1-15 S3C2501X Timer Controller....................................................................................1-34
2-1 PSR Mode. Bit Values............................................................................................2-10
2-2 Exception Entry/Exit...............................................................................................2-12
2-3 Exception Vectors .................................................................................................. 2-14
2-4 ARM9TDMI Implementation Option........................................................................2-19
2-5 CP15 Register Map................................................................................................2-21
2-6 ID Code Register....................................................................................................2-21
2-7 Cache Type Register Format.................................................................................. 2-22
2-8 CP15 Register 1.....................................................................................................2-23
2-9 Clocking Modes ......................................................................................................2-23
2-10 Cacheable Register Format....................................................................................2-24
2-11 Write Buffer Control Register .................................................................................2-25
2-12 Protection Space Register Format..........................................................................2-26
2-13 Permission Encoding ..............................................................................................2-26
2-14 CP15 Data Protection Region Registers.................................................................2-27
2-15 CP15 Instruction Protection Region Registers ........................................................2-27
2-16 CP15 Protection Region Register Format...............................................................2-28
2-17 Area Size Encoding................................................................................................2-28
2-18 Cache Operations Writing to Register 7..................................................................2-29
2-19 CP15 Register 7 Index/Segment Data Format........................................................2-30
2-20 CP15 Register 7 Prefetch Address Format.............................................................2-30
2-21 Lockdown Register Format.....................................................................................2-31
2-22 CP15 Register 15...................................................................................................2-32
S3C2501X xix
List of Tables (Continued)
Table Title Page
Number Number
3-1 The ARM Instruction Set........................................................................................ 3-2
3-2 Condition Code Summary...................................................................................... 3-4
3-3 ARM Data Processing Instructions ......................................................................... 3-11
3-4 Incremental Cycle Times....................................................................................... 3-17
3-5 Assembler Syntax Descriptions ............................................................................. 3-27
3-6 Addressing Mode Names ....................................................................................... 3-45
3-7 THUMB Instruction Set Opcodes........................................................................... 3-65
3-8 Summary of Format 1 Instructions ......................................................................... 3-67
3-9 Summary of Format 2 Instructions ......................................................................... 3-68
3-10 Summary of Format 3 Instructions ......................................................................... 3-70
3-11 Summary of Format 4 Instructions ......................................................................... 3-71
3-12 Summary of Format 5 Instructions ......................................................................... 3-74
3-13 Summary of PC-Relative Load Instruction............................................................. 3-76
3-14 Summary of Format 7 Instructions ......................................................................... 3-77
3-15 Summary of format 8 instructions.......................................................................... 3-79
3-16 Summary of Format 9 Instructions ......................................................................... 3-81
3-17 Half-word Data Transfer Instructions...................................................................... 3-83
3-18 SP-Relative Load/Store Instructions ...................................................................... 3-84
3-19 Load Address ........................................................................................................ 3-85
3-20 The ADD SP Instruction......................................................................................... 3-87
3-21 PUSH and POP Instructions.................................................................................. 3-88
3-22 The Multiple Load/Store Instructions ...................................................................... 3-90
3-23 The Conditional Branch Instructions ...................................................................... 3-91
3-24 The SWI Instruction ............................................................................................... 3-92
3-25 Summary of Branch Instruction.............................................................................. 3-93
3-26 The BL Instruction ................................................................................................. 3-94
4-1 The Base Address of Remapped Memory.............................................................. 4-3
4-2 AHB Bus Priorities for Arbitration ........................................................................... 4-4
4-3 Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins.... 4-9
4-4 P, M, S values of the S3C2501X PLL .................................................................... 4-13
4-5 System Configuration Registers............................................................................. 4-15
xx S3C2501X
List of Tables (Continued)
Table Title Page
Number Number
5-1 Base Address of Each Bank ...................................................................................5-3
5-2 Bus Interface Signals..............................................................................................5-5
5-3 External 32-bit Datawidth Store Operation with Big-Endian.....................................5-7
5-4 External 32-bit Datawidth Load Operation with Big-Endian.....................................5-7
5-5 External 16-bit Datawidth Store Operation with Big-Endian.....................................5-8
5-6 External 16-bit Datawidth Load Operation with Big-Endian.....................................5-8
5-7 External 8-bit Datawidth Store Operation with Big-Endian ......................................5-9
5-8 External 8-bit Datawidth Load Operation with Big-Endian.......................................5-9
5-9 External 32-bit Datawidth Store Operation with Little-Endian..................................5-10
5-10 External 32-bit Datawidth Load Operation with Little-Endian ...................................5-10
5-11 External 16-bit Datawidth Store Operation with Little-Endian..................................5-11
5-12 External 16-bit Datawidth Load Operation with Little-Endian ...................................5-11
5-13 External 8-bit Datawidth Store Operation with Little-Endian....................................5-12
5-14 External 8-bit Datawidth Load Operation with Little-Endian..................................... 5-12
5-15 Ext. I/O Bank Controller Special Registers .............................................................5-21
5-16 Bank n Control (BnCON) Register..........................................................................5-23
5-17 Muxed Bus Control Register...................................................................................5-25
5-18 WAIT Control Register ........................................................................................... 5-27
5-19 Supported SDRAM Configuration of 32-bit External Bus.........................................5-40
5-20 Supported SDRAM Configuration of 16-bit External Bus.........................................5-41
5-21 SDRAM Address Mapping of 32-bit External Bus ...................................................5-42
5-22 SDRAM address mapping of 16-bit external bus.....................................................5-43
5-23 SDRAM commands................................................................................................5-44
5-24 SDRAM Special Registers......................................................................................5-47
5-25 SDRAM Configuration Register..............................................................................5-47
5-26 SDRAM Command Register...................................................................................5-50
5-27 SDRAM Refresh Timer Register .............................................................................5-52
5-28 SDRAM Write Buffer Time-out Register.................................................................5-53
6-1 Control Status Register...........................................................................................6-8
6-2 IICCON Register Description..................................................................................6-8
6-3 IICBUF Register.....................................................................................................6-10
6-4 IICPS Register .......................................................................................................6-10
6-5 IICCNT Register.....................................................................................................6-11
6-6 IICPND Register .....................................................................................................6-11
S3C2501X xxi
List of Tables (Continued)
Table Title Page
Number Number
7-1 MAC Function Block Descriptions.......................................................................... 7-3
7-2 ETHERNET 0 Special Registers............................................................................ 7-13
7-3 ETHERNET 1 Special Registers............................................................................ 7-14
7-4 BDMATXCON Register.......................................................................................... 7-15
7-5 BDMA RXCON Register........................................................................................ 7-16
7-6 BDMATXDPTR Register ........................................................................................ 7-17
7-7 BDMARXDPTR Register ....................................................................................... 7-17
7-8 BTXBDCNT Register............................................................................................. 7-18
7-9 BRXBDCNT Register............................................................................................. 7-18
7-10 BMTXINTEN Register............................................................................................ 7-19
7-11 BMTXSTAT Register............................................................................................. 7-20
7-12 BMRXINTEN Register ........................................................................................... 7-21
7-13 BMRXSTAT Register ............................................................................................. 7-22
7-14 BDMARXLEN Register.......................................................................................... 7-23
7-15 CFTXSTAT Register.............................................................................................. 7-24
7-16 MACCON Register ................................................................................................ 7-25
7-17 CAMCON Register ................................................................................................ 7-26
7-18 MACTXCON Register............................................................................................ 7-27
7-19 MACTXSTAT Register........................................................................................... 7-28
7-20 MACRXCON Register............................................................................................ 7-29
7-21 MACRXSTAT Register .......................................................................................... 7-30
7-22 STADATA Register................................................................................................ 7-31
7-23 STACON Register................................................................................................. 7-32
7-24 CAMEN Register................................................................................................... 7-33
7-25 MISSCNT Register................................................................................................ 7-34
7-26 PZCNT Register.................................................................................................... 7-35
7-27 RMPZCNT Register............................................................................................... 7-35
7-28 CAM Register........................................................................................................ 7-36
7-29 MAC Frame Format Description............................................................................ 7-37
7-30 STA Frame Structure Description.......................................................................... 7-45
xxii S3C2501X
List of Tables (Continued)
Table Title Page
Number Number
8-1 DES/3DES Special Registers Overview ................................................................. 8-3
8-2 DES/3DES Control Register Description................................................................. 8-4
8-3 DES/3DES Status Register Description..................................................................8-5
8-4 DES/3DES Interrupt Enable Register Description...................................................8-6
8-5 DES/3DES Run Enable Register Description ..........................................................8-6
8-6 DES/3DES Key1 Left Side Register Description.....................................................8-6
8-7 DES/3DES Key 1 Right Side Register Description..................................................8-6
8-8 DES/3DES Key 2 Left Side Register Description....................................................8-7
8-9 DES/3DES Key 2 Right Side Register Description..................................................8-7
8-10 DES/3DES Key 3 Left Side Register Description....................................................8-7
8-11 DES/3DES Key 3 Right Side Register Description..................................................8-7
8-12 DES/3DES IV Left Side Register Description.......................................................... 8-7
8-13 DES/3DES IV Right Side Register Description .......................................................8-7
8-14 DES/3DES Input Data FIFO Description................................................................. 8-8
8-15 DES/3DES Output Data FIFO Description..............................................................8-8
9-1 GDMA Special Registers Overview........................................................................9-3
9-2 GDMA Programmable Priority Registers ................................................................9-4
9-3 DCON0/1/2/3/4/5 Registers....................................................................................9-9
9-4 GDMA Control Register Description .......................................................................9-9
9-5 DSAR0/1/2/3/4/5 and DDAR0/1/2/3/4/5 Registers................................................... 9-12
9-6 DTCR0/1/2/3/4/5 Registers .....................................................................................9-13
9-7 DRER0/1/2/3/4/5 Registers.....................................................................................9-14
9-8 DIPR0/1/2/3 Registers............................................................................................9-15
S3C2501X xxiii
List of Tables (Continued)
Table Title Page
Number Number
10-1 Console UART Special Registers Overview........................................................... 10-3
10-2 CUCON Registers ................................................................................................. 10-4
10-3 Console UART Control Register Description.......................................................... 10-4
10-4 CUSTAT Registers................................................................................................ 10-8
10-5 Console UART Status Register Description ........................................................... 10-8
10-6 CUINT Registers ................................................................................................... 10-11
10-7 Console UART Interrupt Enable Register Description ............................................ 10-11
10-8 CUTXBUF Registers.............................................................................................. 10-13
10-9 Console UART Transmit Register Description........................................................ 10-13
10-10 CURXBUF Registers ............................................................................................. 10-14
10-11 Console UART Receive Register Description ........................................................ 10-14
10-12 CUBRD Registers .................................................................................................. 10-15
10-13 Typical Baud Rates Examples of Console UART................................................... 10-16
10-14 CUCHAR 1, 2 Registers ........................................................................................ 10-17
11-1 High-Speed UART Special Registers Overview..................................................... 11-3
11-2 High-Speed UART Control Register...................................................................... 11-4
11-3 High-Speed UART Control Register Description .................................................... 11-4
11-4 High-Speed UART Status Register........................................................................ 11-9
11-5 High-Speed UART Status Register Description...................................................... 11-9
11-6 High-Speed UART Interrupt Enable Register......................................................... 11-14
11-7 High-Speed UART Interrupt Enable Register Description....................................... 11-14
11-8 High-Speed UART Transmit Register .................................................................... 11-16
11-9 High-Speed UART Transmit Register Description.................................................. 11-16
11-10 High-Speed UART Receive Register..................................................................... 11-17
11-11 High-Speed UART Receive Register Description ................................................... 11-17
11-12 High-Speed UART Transmit Register .................................................................... 11-18
11-13 Typical Baud Rates Examples of High-Speed UART............................................. 11-19
11-14 High-Speed UART Control Charater 1 Register ..................................................... 11-20
11-15 High-Speed UART Control Character 2 Register.................................................... 11-21
11-16 High-Speed UART AutoBaud Boundary Register................................................... 11-22
11-17 High-Speed UART AutoBaud Table Register......................................................... 11-23
12-1 I/O Port Special Registers ..................................................................................... 12-2
12-2 IOPMODE1/2 Registers......................................................................................... 12-2
12-3 IOPCON1/2 Register............................................................................................. 12-4
12-4 IOPGDMA Register............................................................................................... 12-7
12-5 IOPEXTINT Register ............................................................................................. 12-8
12-6 IOPEXTINTPND Register...................................................................................... 12-10
12-7 IOPDATA1/2 Register............................................................................................ 12-11
12-8 IOPDRV1/2 Register.............................................................................................. 12-11
xxiv S3C2501X
List of Tables (Concluded)
Table Title Page
Number Number
13-1 S3C2501X Internal Interrupt Sources......................................................................13-2
13-2 S3C2501X External Interrupt Sources ....................................................................13-3
13-3 INTMOD, EXTMOD Register..................................................................................13-3
13-4 INTMASK, EXTMASK Register .............................................................................. 13-5
13-5 Interrupt Priority Register........................................................................................13-8
13-6 INTOFFSET_FIQ, INTOFFSET_IRQ Register .......................................................13-9
13-7 Index Value of Interrupt Sources ............................................................................ 13-10
13-8 IPRIORHI, IPRIORLO Register ..............................................................................13-12
13-9 INTTSTHI, INTTSTLO Register ..............................................................................13-12
14-1 TMOD Register ......................................................................................................14-4
14-2 TDATA0 - TDATA5 Registers.................................................................................14-6
14-3 TCNT0 - TCNT5 Registers .....................................................................................14-7
14-4 Timer Interrupt Clear Registers...............................................................................14-8
14-5 WDT Register ........................................................................................................14-9
14-6 Watchdog Timer Timeout Value.............................................................................14-10
15-1 Absolute Maximum Ratings....................................................................................15-1
15-2 Recommended Operating Conditions.....................................................................15-1
15-3 D.C Electric Characteristics....................................................................................15-2
15-4 Operating Frequency ..............................................................................................15-4
15-5 Clock AC timing specification-................................................................................15-4
15-6 AC Electrical Characteristics for S3C2501X............................................................15-5
S3C2501X xxv
S3C2501X PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
1.1 OVERVIEW
Samsung's S3C2501X 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
solution for Ethernet-based systems, for example, SOHO router, internet gateway, WLAN AP, etc.
A variety of communication features are embedded into S3C2501X required in many communication areas,
including two Ethernet MACs, a high speed UART, and a console UART. A security feature is also supported by
DES/3DES accelerator.
This highly integrated microcontroller enables customers to save system costs and increase performance
over other 32-bit microcontroller.
The S3C2501X is built based on an outstanding CPU core: The ARM940T cached processor is a member of the
ARM9 Thumb family of high-performance 32-bit system-on-a-chip processor solutions.
It provides a complete high performance CPU subsystem, including ARM9TDMI RISC integer CPU, 4KB
instruction/data caches, write buffer, and protection unit, with an AMBA bus interface.
The ARM9TDMI core within the ARM940T executes both the 32-bit ARM and 16-bit Thumb instruction sets,
allowing the user to trade off between high performance and high code density.
It is binary compatible with ARM7TDMI, ARM10TDMI, and Strong ARM processors, and is supported by a wide
range of tools, operating systems, and application software.
The following integrated on-chip functions are described in detail in this user's manual :
• ARM940T cached processor
• Ethernet Controller
• GDMA Controller
• UART Controller
• I2C Controller
• Programmable I/O ports
• Interrupt Controller
1-1
PRODUCT OVERVIEW S3C2501X
1.2 FEATURES
ARM940T Core processor
• Fully 16/32-bit RISC architecture.
• Harvard cache architecture with separate 4KB
Instruction and Data cache
• Protection unit to partition memory and set
individual protection attributes for each partition
• AMBA Bus architecture
• Up to 166MHz operating frequency
Memory Controller
• 24-bit External Address Pins
• 2 Banks for SDRAM with 16/32 bit external bus.
• 8 Banks for Flash/ROM/SRAM/External I/O with
8/16/32-bit external bus.
• One External Bus Master with Bus
Request/Acknowledge Pins
Ethernet Controllers
• Buffered DMA (BDMA) engine using burst mode
• BDMA Tx/Rx buffers (256-byte/256-byte)
• MAC Tx/Rx FIFOs (80-byte/16-byte) to support
re-transmit after collision without DMA request
• Data alignment logic
• Support for old and new media (compatible with
existing 10M-bit/s networks)
On-chip CAM (21 addresses)
• Full-duplex mode for doubled bandwidth
• Pause operation hardware support for full-
duplex flow control
• Long packet mode for specialized environments
• Short packet mode for fast testing
• PAD generation for ease of processing and
reduced processing time
Universal Asynchronous Receiver Transmitter
(UART)
• Programmable baud rates
• 32-byte Transmit FIFO and 32-byte Receive
FIFO
• UART source clock selectable (Internal clock
:PCLK2, External clock: EXT_CLK)
• Auto baud rate detection
• Infra-red (IR) transmit/receive
• Insertion of one or two Stop bits per frame
• Selectable 5-bit, 6-bit, 7-bit, or 8-bit data
transfers
• Parity checking
DES/3DES Accelerator
• DES or Triple DES mode
• 10/100 Mbps operation to increase
price/performance options and to support
phased conversions
• Full IEEE 802.3 compatibility for existing
applications
• Media Independent interface (MII) or 7-wire
interface
• Station management (STA) signaling for
external physical layer configuration and link
negotiation
1-2
• ECB or CBC mode
• Encryption or decryption support
• General DMA support
S3C2501X PRODUCT OVERVIEW
1.2 FEATURES (Continue)
General DMA Channels
• Six GDMA channels
• Memory to memory data transfer
• Memory to peripheral data transfer (high-speed
UART and DES)
• Support for four external GDMA requests from
GDMA request pins
(xGDMA_Req0 - xGDMA_Req3).
Six Programmable Timers
• Interval or toggle mode operation
Hardware Watchdog Timer
• Useful for periodic reset or interrupts
Programmable Interrupt Controller
• 28 programmable interrupt sources
• 22 internal sources and 6 external sources
• programmable priority control
I2C Controller
• Master mode operation only
• Baud rate generator for serial clock
Three PLLs for System, Core and PHY Clock
Each
PLL0 for ARM940T
• The Input frequency is 10MHz.
• Provide up to 166MHz output to ARM940T
PLL1 for system clock
• The Input frequency is 10MHz.
• Provide up to 133MHz output to system
PLL2 for PHY
• The input frequency is 10MHz
• Provide 20 MHz or 25MHz output to external
PHY chip
Programmable I/O port Controller
• 64 programmable I/O ports
• Individually configurable to input, output, or I/O
mode for dedicated signals
• 6 external interrupt request
• 4 external GDMA request
• 4 external GDMA acknowledge
• 6 timer outputs
• 7 UART signals
Operating Voltage Range
• Internal Power: 1.8 V ± 5 %
• I/O Power: 3.3 V ± 5 %
Operating temperature range
• -40 °C – 85 °C
Package Type
• 272 BGA
1-3
PRODUCT OVERVIEW S3C2501X
1.3 BLOCK DIAGRAM
2-bank
SDRAM
8-bank
Flash/ROM/
SRAM/Ext
I/O
10/100
Ethernet
MAC
10/100
Ethernet
MAC
Controller
Memory
DMA
DMA
133
MHz
AHB
BUS
A
H
B
I/F
APB
Bridge
Sys. Bus
Arbiter
Six
GDMA
4KB
D-Cache
ARM940T
(166 MHz)
4KB
D-Cache
Interrupt
Controller
DES/3DES
WDT
Six
Timers
133
MHz
APB
BUS
High
Speed
UART
Console
UART
I2C
GPIOs
Bus Master
1-4
External
REQ/ACK
Clock Gen.
&
Reset Drv. with 4
PLLs
10 MHz
OSC.
20 MHz or
Figure 1-1. S3C2501X Block Diagram
25 MHz
S3C2501X PRODUCT OVERVIEW
1.4 PACKAGE DIAGRAM
TOP View
A1 ball pad corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ABCDEFGHJKLMNPRTUVWY
Figure 1-2. S3C2501X Pin Assignment Diagram
1-5
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