SAMSUNG S3C2500B User Guide
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USER'S MANUAL
21-S3C2500B-032003
S3C2500B
32-Bit RISC
Microprocessor
Revision 1
S3C2500B
32-BIT RISC
MICROPROCESSOR
USER'S MANUAL
Revision 1
Important Notice
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S3C2500B RISC Microprocessor
User's Manual, Revision 1.0
Publication Number: 21.0-S3-C2500B-052003
2003 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
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certification (BSI Certificate No. FM24653). All semiconductor products are designed
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Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Kiheung-Eup
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Printed in the Republic of Korea
Table of Contents
Chapter 1 Product Overview
1.1 Overview...........................................................................................................................................1-1
1.2 Features ............................................................................................................................................ 1-2
1.3 Block Diagram...................................................................................................................................1-5
1.4 Package Diagram ..............................................................................................................................1-6
1.5 Pin Assignment ..................................................................................................................................1-7
1.6 Signal Description..............................................................................................................................1-13
1.7 Pad Type...........................................................................................................................................1-31
1.8 Special Registers...............................................................................................................................1-32
Chapter 2 Programmer's Model
2.1 Overview...........................................................................................................................................2-1
2.2 Switching State..................................................................................................................................2-1
2.2.1 Entering THUMB State...........................................................................................................2-1
2.2.2 Entering ARM State................................................................................................................2-1
2.3 Memory Formats................................................................................................................................2-2
2.3.1 Big-Endian Format..................................................................................................................2-2
2.3.2 Little-Endian Format...............................................................................................................2-2
2.4 Instruction Length .............................................................................................................................. 2-3
2.5 Data Types ........................................................................................................................................2-3
2.6 Operating Modes ............................................................................................................................... 2-3
2.7 Registers ...........................................................................................................................................2-4
2.7.3 The Relationship Between ARM and THUMB State Registers.................................................2-7
2.7.4 Accessing Hi-Registers in THUMB State.................................................................................2-8
2.8 The Program Status Registers...........................................................................................................2-8
2.8.1 The Condition Code Flags ......................................................................................................2-9
2.8.2 The Control Bits...................................................................................................................... 2-9
2.9 Exceptions.........................................................................................................................................2-11
2.9.1 Action on Entering an Exception.............................................................................................2-11
2.9.2 Action on Leaving an Exception..............................................................................................2-11
2.9.3 Exception Entry/Exit Summary...............................................................................................2-12
2.9.4 FIQ.........................................................................................................................................2-12
2.9.5 IRQ.........................................................................................................................................2-13
2.9.6 Abort ......................................................................................................................................2-13
2.9.7 Software Interrupt...................................................................................................................2-14
2.9.8 Undefined Instruction ..............................................................................................................2-14
2.10 Exception Vectors............................................................................................................................2-14
2.10.1 Exception Priorities ...............................................................................................................2-15
2.10.2 Not All Exceptions Can Occur at Once: ................................................................................2-15
2.11 Interrupt Latencies ...........................................................................................................................2-16
2.12 Reset...............................................................................................................................................2-16
2.13 Introduction for ARM940T................................................................................................................2-17
2.14 ARM940T Block Diagram.................................................................................................................2-18
2.15 About The ARM940T Programmer's Model......................................................................................2-19
2.15.1 Data Abort Model.................................................................................................................. 2-20
2.15.2 Instruction Set Extension Spaces.......................................................................................... 2-20
2.16 ARM940T CP15 Registers...............................................................................................................2-21
2.16.1 CP15 Register Map Summary ..............................................................................................2-21
S3C2500B RISC MICROCONTROLLER iii
Table of Contents (Continued)
Chapter 3 Instruction Set
3.1 Instruction Set Summay.................................................................................................................... 3-1
3.1.1 Format Summary................................................................................................................... 3-1
3.1.2 Instruction Summary .............................................................................................................. 3-2
3.2 The Condition Field ........................................................................................................................... 3-4
3.3 Branch and Exchange (BX)............................................................................................................... 3-5
3.3.1 Instruction Cycle Times.......................................................................................................... 3-5
3.3.2 Assembler Syntax .................................................................................................................. 3-5
3.3.3 Using R15 as an Operand...................................................................................................... 3-5
3.4 Branch and Branch with Link (B, BL)................................................................................................. 3-7
3.4.1 The Link Bit ........................................................................................................................... 3-7
3.4.2 Instruction Cycle Times.......................................................................................................... 3-7
3.4.3 Assembler Syntax .................................................................................................................. 3-8
3.5 Data Processing ................................................................................................................................ 3-9
3.5.1 CPSR Flags ........................................................................................................................... 3-11
3.5.2 Shifts..................................................................................................................................... 3-12
3.5.3 Immediate Operand Rotates.................................................................................................. 3-16
3.5.4 Writing to R15........................................................................................................................ 3-16
3.5.5 Using R15 as an Operand...................................................................................................... 3-16
3.5.6 Teq, Tst, Cmp and CMN Opcodes......................................................................................... 3-16
3.5.7 Instruction Cycle Times.......................................................................................................... 3-17
3.6.8 Assembler Syntax .................................................................................................................. 3-17
3.6 PSR Transfer (MRS, MSR)............................................................................................................... 3-19
3.6.1 Operand Restrictions ............................................................................................................. 3-19
3.6.2 Reserved Bits........................................................................................................................ 3-21
3.6.3 Instruction Cycle Times.......................................................................................................... 3-21
3.6.4 Assembler Syntax .................................................................................................................. 3-22
3.7 Multiply and Multiply-Accumulate (MUL, MLA).................................................................................. 3-23
3.7.1 CPSR Flags ........................................................................................................................... 3-24
3.7.2 Instruction Cycle Times.......................................................................................................... 3-24
3.7.3 Assembler Syntax .................................................................................................................. 3-24
3.8 Multiply Long and Multiply-Accumulate Long (MULL, MLAL)............................................................. 3-25
3.8.1 Operand Restrictions ............................................................................................................. 3-25
3.8.2 CPSR Flags ........................................................................................................................... 3-26
3.8.3 Instruction Cycle Times.......................................................................................................... 3-26
3.8.4 Assembler Syntax .................................................................................................................. 3-27
3.9 Single Data Transfer (LDR, STR)...................................................................................................... 3-28
3.9.1 Offsets and Auto-Indexing ..................................................................................................... 3-29
3.9.2 Shifted Register Offset........................................................................................................... 3-29
3.9.3 Bytes and Words ................................................................................................................... 3-29
3.9.4 Use of R15............................................................................................................................. 3-31
3.9.5 Restriction on the Use of Base Register................................................................................. 3-31
3.9.6 Data Aborts............................................................................................................................ 3-31
3.9.7 Instruction Cycle Times.......................................................................................................... 3-31
3.9.8 Assembler Syntax .................................................................................................................. 3-32
iviv S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.10 Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH).................................................3-34
3.10.1 Offsets and Auto-Indexing .................................................................................................... 3-35
3.10.2 Half-Word Load and Stores ..................................................................................................3-36
3.10.3 Signed Byte and Half-Word Loads........................................................................................3-36
3.10.4 Endianness and Byte/Half-Word Selection............................................................................ 3-36
3.10.5 Use of R15 ...........................................................................................................................3-37
3.10.6 Data Aborts...........................................................................................................................3-37
3.10.7 Instruction Cycle Times ........................................................................................................3-37
3.10.8 Assembler Syntax................................................................................................................. 3-38
3.11 Block Data Transfer (LDM, STM).....................................................................................................3-40
3.11.1 The Register List...................................................................................................................3-40
3.11.2 Addressing Modes ................................................................................................................3-41
3.11.3 Address Alignment................................................................................................................3-41
3.11.4 Use of the S Bit ....................................................................................................................3-43
3.11.5 Use of R15 as the Base........................................................................................................3-43
3.11.6 Inclusion of the Base in the Register List...............................................................................3-44
3.11.7 Data Aborts...........................................................................................................................3-44
3.11.8 Instruction Cycle Times ........................................................................................................3-44
3.11.9 Assembler Syntax................................................................................................................. 3-45
3.12 Single Data Swap (SWP).................................................................................................................3-47
3.12.1 Bytes and Words ..................................................................................................................3-47
3.12.2 Use of R15 ...........................................................................................................................3-47
3.12.3 Data Aborts...........................................................................................................................3-48
3.12.4 Instruction Cycle Times ........................................................................................................3-48
3.12.5 Assembler Syntax................................................................................................................. 3-48
3.13 Software Interrupt (SWI)..................................................................................................................3-49
3.13.1 Return from the Supervisor................................................................................................... 3-49
3.13.2 Comment Field.....................................................................................................................3-49
3.13.3 Instruction Cycle Times ........................................................................................................3-49
3.13.4 Assembler Syntax................................................................................................................. 3-50
3.14 Coprocessor Data Operations (CDP)................................................................................................3-51
3.14.1 Coprocessor Instructions.......................................................................................................3-51
3.14.2 The Coprocessor Fields........................................................................................................3-51
3.14.3 Instruction Cycle Times ........................................................................................................3-52
3.14.4 Assembler Syntax................................................................................................................. 3-52
3.15 Coprocessor Data Transfers (LDC, STC) ......................................................................................... 3-53
3.15.1 The Coprocessor Fields........................................................................................................3-53
3.15.2 Addressing Modes ................................................................................................................3-54
3.15.3 Address Alignment................................................................................................................3-54
3.15.4 Use of R15 ...........................................................................................................................3-54
3.15.5 Data Aborts...........................................................................................................................3-54
3.15.6 Instruction Cycle Times ........................................................................................................3-54
3.15.7 Assembler Syntax................................................................................................................. 3-55
S3C2500B RISC MICROCONTROLLER v
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.16 Coprocessor Register Transfers (MRC, MCR)................................................................................. 3-56
3.16.1 The Coprocessor Fields....................................................................................................... 3-56
3.16.2 Transfers to R15.................................................................................................................. 3-57
3.16.3 Transfers from R15.............................................................................................................. 3-57
3.16.4 Instruction Cycle Times........................................................................................................ 3-57
3.16.5 Assembler Syntax................................................................................................................ 3-57
3.17 Undefined Instruction ...................................................................................................................... 3-58
3.17.1 Instruction Cycle Times........................................................................................................ 3-58
3.17.2 Assembler Syntax................................................................................................................ 3-58
3.18 Instruction Set Examples................................................................................................................. 3-59
3.18.1 Using The Conditional Instructions....................................................................................... 3-59
3.18.2 Pseudo-Random Binary Sequence Generator...................................................................... 3-61
3.18.3 Multiplication by Constant Using The Barrel Shifter.............................................................. 3-61
3.18.4 Loading a Word From an Unknown Alignment..................................................................... 3-63
3.19 Thumb Instruction Set Format......................................................................................................... 3-64
3.19.1 Format Summary ................................................................................................................. 3-64
3.19.2 Opcode Summary ................................................................................................................ 3-65
3.20 Format 1: Move Shifted Register..................................................................................................... 3-67
3.20.1 Operation............................................................................................................................. 3-67
3.20.2 Instruction Cycle Times........................................................................................................ 3-67
3.21 Format 2: Add/Subtract................................................................................................................... 3-68
3.21.1 Operation............................................................................................................................. 3-68
3.21.2 Instruction Cycle Times........................................................................................................ 3-69
3.22 Format 3: Move/Compare/Add/Subtract Immediate......................................................................... 3-70
3.22.1 Operations........................................................................................................................... 3-70
3.22.2 Instruction Cycle Times........................................................................................................ 3-70
3.23 Format 4: ALU Operations .............................................................................................................. 3-71
3.23.1 Operation............................................................................................................................. 3-71
3.23.2 Instruction Cycle Times........................................................................................................ 3-72
3.24 Format 5: Hi-Register Operations/Branch Exchange ....................................................................... 3-73
3.24.1 Operation............................................................................................................................. 3-73
3.24.2 Instruction Cycle Times........................................................................................................ 3-74
3.24.3 The Bx Instruction ................................................................................................................ 3-74
3.24.4 Using R15 as an Operand.................................................................................................... 3-75
3.25 Format 6: PC-Relative Load............................................................................................................ 3-76
3.25.1 Operation............................................................................................................................. 3-76
3.25.2 Instruction Cycle Times........................................................................................................ 3-76
3.26 Format 7: Load/Store With Register Offset...................................................................................... 3-77
3.26.1 Operation............................................................................................................................. 3-77
3.26.2 Instruction Cycle Times........................................................................................................ 3-78
3.27 Format 8: Load/Store Sign-Extended Byte/Half-Word ..................................................................... 3-79
3.27.1 Operation............................................................................................................................. 3-79
3.27.2 Instruction Cycle Times........................................................................................................ 3-80
vivi S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.28 Format 9: Load/Store with Immediate Offset....................................................................................3-81
3.28.1 Operation..............................................................................................................................3-81
3.28.2 Instruction Cycle Times ........................................................................................................3-82
3.29 Format 10: Load/Store Half-Word....................................................................................................3-83
3.29.1 Operation..............................................................................................................................3-83
3.29.2 Instruction Cycle Times ........................................................................................................3-83
3.30 Format 11: SP-Relative Load/Store .................................................................................................3-84
3.30.1 Operation..............................................................................................................................3-84
3.30.2 Instruction Cycle Times ........................................................................................................3-84
3.31 Format 12: Load Addres...................................................................................................................3-85
3.31.1 Operation..............................................................................................................................3-85
3.31.2 Instruction Cycle Times ........................................................................................................3-86
3.32 Format 13: Add Offset to Stack Pointer............................................................................................ 3-87
3.32.1 Operation..............................................................................................................................3-87
3.32.2 Instruction Cycle Times ........................................................................................................3-87
3.33 Format 14: Push/Pop Registers........................................................................................................3-88
3.33.1 Operation..............................................................................................................................3-88
3.33.2 Instruction Cycle Times ........................................................................................................3-89
3.34 Format 15: Multiple Load/Store........................................................................................................3-90
3.34.1 Operation..............................................................................................................................3-90
3.34.2 Instruction Cycle Times ........................................................................................................3-90
3.35 Format 16: Conditional Branch.........................................................................................................3-91
3.35.1 Operation..............................................................................................................................3-91
3.35.2 Instruction Cycle Times ........................................................................................................3-92
3.36 Format 17: Software Interrupt .......................................................................................................... 3-93
3.36.1 Operation..............................................................................................................................3-93
3.36.2 Instruction Cycle Times ........................................................................................................3-93
3.37 Format 18: Unconditional Branch.....................................................................................................3-94
3.37.1 Operation..............................................................................................................................3-94
3.38 Format 19: Long Branch With Link ...................................................................................................3-95
3.38.1 Operation..............................................................................................................................3-95
3.38.2 Instruction Cycle Times ........................................................................................................3-96
3.39 Instruction Set Examples ................................................................................................................. 3-97
3.39.1 Multiplication by a Constant Using Shifts and Adds ...............................................................3-97
3.39.2 General Purpose Signed Divide............................................................................................3-98
3.39.3 Division by a Constant..........................................................................................................3-100
S3C2500B RISC MICROCONTROLLER vii
Table of Contents (Continued)
Chapter 4 System Configuration
4.1 Overview .......................................................................................................................................... 4-1
4.2 Features............................................................................................................................................ 4-1
4.3 Address Map..................................................................................................................................... 4-2
4.4 Remap of Memory Space ................................................................................................................. 4-3
4.5 External Address Translation ............................................................................................................ 4-3
4.6 Arbitration Scheme ........................................................................................................................... 4-4
4.6.1 Problem Solvings with Programmable Round-Robin.............................................................. 4-7
4.7 Clock Configuration........................................................................................................................... 4-9
4.8 External Bus Master .......................................................................................................................... 4-14
4.9 System Configuration Special Registers............................................................................................ 4-15
4.9.1 System Configuration Register............................................................................................... 4-16
4.9.2 Product Code and Revision Number Register........................................................................ 4-18
4.9.3 Clock Control Register........................................................................................................... 4-19
4.9.4 Peripheral Clock Disable Register .......................................................................................... 4-20
4.9.5 Clock Status Register ............................................................................................................ 4-21
4.9.6 AHB Bus Master Priority Register .......................................................................................... 4-21
4.9.7 Core PLL Control Register..................................................................................................... 4-22
4.9.8 System Bus PLL Control Register.......................................................................................... 4-23
4.9.9 USB PLL Control Register ..................................................................................................... 4-24
4.9.10 PHY PLL Control Register.................................................................................................... 4-24
Chapter 5 Memory Controller
5.1 Overview .......................................................................................................................................... 5-1
5.2 Features............................................................................................................................................ 5-2
5.3 Memory Map ..................................................................................................................................... 5-3
5.4 Bus Interface Signals........................................................................................................................ 5-5
5.5 Endian Modes................................................................................................................................... 5-7
5.6 Ext I/O Bank Controller..................................................................................................................... 5-13
5.6.1 Features ................................................................................................................................ 5-13
5.6.2 External Device Connection................................................................................................... 5-14
5.6.3 Ext. I/O Bank Controller Special Register............................................................................... 5-21
5.6.4 Timing Diagram..................................................................................................................... 5-29
5.7 SDRAM Controller ............................................................................................................................ 5-38
5.7.1 Features ................................................................................................................................ 5-38
5.7.2 SDRAM Size and Configuration............................................................................................. 5-39
5.7.3 Address Mapping................................................................................................................... 5-42
5.7.4 SDRAM Commands............................................................................................................... 5-44
5.7.5 External Data Bus Width........................................................................................................ 5-45
5.7.6 Merging Write Buffer ............................................................................................................. 5-45
5.7.7 Self Refresh........................................................................................................................... 5-45
5.7.8 Basic Operation..................................................................................................................... 5-46
5.7.9 SDRAM Special Registers ..................................................................................................... 5-47
5.7.10 SDRAM Controller Timing.................................................................................................... 5-54
viiiviii S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 6 I2C Controller
6.1 Overview...........................................................................................................................................6-1
6.2 Features ............................................................................................................................................ 6-1
6.3 Functional Description .......................................................................................................................6-2
6.4 I2C Concepts .....................................................................................................................................6-3
6.4.1 Basic Operation......................................................................................................................6-3
6.4.2 General Characteristics .......................................................................................................... 6-4
6.4.3 Bit Transfers...........................................................................................................................6-4
6.4.4 Data Validity...........................................................................................................................6-5
6.4.5 Start And Stop Conditions.......................................................................................................6-5
6.4.6 Data Trsansfer Operations ......................................................................................................6-6
6.5 I2C Special Registers.........................................................................................................................6-9
6.5.1 Control Status Register ...........................................................................................................6-9
6.5.2 Shift Buffer Register...............................................................................................................6-11
6.5.3 Prescaler Register..................................................................................................................6-11
6.5.4 Prescaler Counter Register.....................................................................................................6-12
6.5.5 Interrupt Pending Register......................................................................................................6-12
Chapter 7 Ethernet Controller
7.1 Overview...........................................................................................................................................7-1
7.2 Features ............................................................................................................................................ 7-2
7.3 MAC Function Blocks.........................................................................................................................7-3
7.3.1 Media Independent Interface (MII)..........................................................................................7-3
7.3.2 Physical Layer Entity (PHY) ....................................................................................................7-4
7.3.3 Buffered Dma Interface (BDI).................................................................................................7-4
7.3.4 The MAC Transmitter Block.................................................................................................... 7-4
7.3.5 The MAC Receiver Block........................................................................................................7-6
7.3.6 Flow Control Block..................................................................................................................7-7
7.3.7 Buffered DMA (BDMA) Overview ...........................................................................................7-7
7.4 Ethernet Controller Special Registers.................................................................................................7-13
7.4.1 BDMA Relative Special Register ............................................................................................7-15
7.4.2 MAC Relative Special Register ...............................................................................................7-24
7.5 Ethernet Operations...........................................................................................................................7-37
7.5.1 MAC Frame Format................................................................................................................ 7-37
7.5.2 The MII Station Manager ........................................................................................................7-45
7.5.3 Full-Duplex Pause Operations................................................................................................7-46
7.5.4 Error Signalling .......................................................................................................................7-48
7.5.5 Timing Parameters for MII Transactions.................................................................................7-50
S3C2500B RISC MICROCONTROLLER ix
Table of Contents (Continued)
Chapter 8 HDLC Controller
8.1 Overview .......................................................................................................................................... 8-1
8.2 Features............................................................................................................................................ 8-2
8.3 Function Descriptions........................................................................................................................ 8-3
8.3.1 HDLC Frame Format............................................................................................................. 8-4
8.4 Protocol Features.............................................................................................................................. 8-6
8.4.1 Invalid Frame ........................................................................................................................ 8-6
8.4.2 Zero Insertion and Zero Deletion............................................................................................ 8-6
8.4.3 Abort...................................................................................................................................... 8-6
8.4.4 Idle and Time Fill................................................................................................................... 8-6
8.4.5 FIFO Structure....................................................................................................................... 8-7
8.4.6 Two-Channel DMA Engine ..................................................................................................... 8-7
8.4.7 Baud Rate Generator............................................................................................................. 8-7
8.4.8 Digital Phase-Locked Loop (DPLL) ........................................................................................ 8-9
8.4.9 Clock Usage Method.............................................................................................................. 8-9
8.5 HDLC Operational Description .......................................................................................................... 8-11
8.5.1 HDLC Initialization................................................................................................................. 8-11
8.5.2 HDLC Data Encoding/Decoding............................................................................................. 8-12
8.5.3 HDLC Data Setup and Hold Timing with Clock....................................................................... 8-13
8.5.4 HDLC Transmitter Operation ................................................................................................. 8-14
8.5.5 HDLC Receiver Operation ..................................................................................................... 8-16
8.5.6 Hardware Flow Control .......................................................................................................... 8-17
8.5.7 Memory Data Structure .......................................................................................................... 8-19
8.5.8 Data Buffer Descriptor ........................................................................................................... 8-20
8.6 Buffer Descriptor............................................................................................................................... 8-21
8.6.1 Transmit Buffer Descriptor..................................................................................................... 8-21
8.6.2 Receive Buffer Descriptor...................................................................................................... 8-22
8.7 HDLC Special Registers.................................................................................................................... 8-24
8.7.1 HDLC Global Mode Register .................................................................................................. 8-27
8.7.2 HDLC Control Register .......................................................................................................... 8-30
8.7.3 HDLC Status Register ........................................................................................................... 8-36
8.7.4 Summary............................................................................................................................... 8-36
8.7.5 HDLC Interrupt Enable Register ............................................................................................. 8-42
8.7.6 HDLC Tx Fifo......................................................................................................................... 8-44
8.7.7 HDLC Rx Fifo........................................................................................................................ 8-45
8.7.8 HDLC Brg Time Constant Registers ....................................................................................... 8-46
8.7.9 HDLC Preamble Constant Register ........................................................................................ 8-47
8.7.10 HDLC Station Address Registers and Hmask Register......................................................... 8-48
8.7.11 Dma Tx Buffer Descriptor Pointer Register .......................................................................... 8-49
8.7.12 Dma Rx Buffer Descriptor Pointer Register.......................................................................... 8-50
8.7.13 Maximum Frame Length Register........................................................................................ 8-50
8.7.14 Receive Buffer Size Register............................................................................................... 8-51
8.7.15 Synchronization Register ..................................................................................................... 8-51
8.7.16 Transparent Control Register............................................................................................... 8-52
8.7.17 Tx Buffer Descriptor Count Register..................................................................................... 8-53
8.7.18 Rx Buffer Descriptor Count Register.................................................................................... 8-53
8.7.19 Tx Buffer Descriptor Maximum Count Register.................................................................... 8-54
8.7.20 Rx Buffer Descriptor Maximum Count Register .................................................................... 8-54
xx S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 9 IOM2 & TSA Controller
9.1 Overview...........................................................................................................................................9-1
9.2 Features ............................................................................................................................................ 9-1
9.3 IOM2 Bus...........................................................................................................................................9-2
9.3.1 B Channels.............................................................................................................................9-3
9.3.2 D Channel .............................................................................................................................. 9-3
9.3.3 Monitor Channels....................................................................................................................9-3
9.3.4 Command and Indicate Channels...........................................................................................9-3
9.3.5 Intercommunication Channels.................................................................................................9-3
9.3.6 TIC Bus..................................................................................................................................9-3
9.3.7 Channel Operation..................................................................................................................9-4
9.4 TSA (Time Slot Assigner) ..................................................................................................................9-9
9.4.1 Overview................................................................................................................................9-9
9.4.2 TSA Block Diagram................................................................................................................9-9
9.4.3 HDLC External Pin Multiplexed Signals..................................................................................9-10
9.4.4 Operation ...............................................................................................................................9-10
9.5 IOM2 Special Registers ..................................................................................................................... 9-11
9.5.1 IOM2CON Register.................................................................................................................9-12
9.5.2 IOM2 Status Register .............................................................................................................9-14
9.5.3 IOM2 Interrupt Enable Register ..............................................................................................9-16
9.5.4 IOM2 TIC Bus Address Register.............................................................................................9-18
9.5.5 IOM2 IC Channel Transmit Data Register...............................................................................9-19
9.5.6 IOM2 C/I0 Channel Transmit Data Register............................................................................9-20
9.5.7 IOM2 C/I1 Channel Transmit Data Register............................................................................9-21
9.5.8 IOM2 C/I1 Channel Receive Data Register.............................................................................9-21
9.5.9 IOM2 Monitor Channel Transmit Data Register....................................................................... 9-22
9.5.10 IOM2 Monitor Channel Receive Data Register...................................................................... 9-22
9.5.11 TSA A Control Register.........................................................................................................9-23
9.5.12 TSA B Control Register.........................................................................................................9-24
9.5.13 TSA C Control Register ........................................................................................................ 9-25
9.5.14 IOM2STRB (Strobe Register) ...............................................................................................9-26
S3C2500B RISC MICROCONTROLLER xi
Table of Contents (Continued)
Chapter 10USB Controller
10.1 Overview ........................................................................................................................................ 10-1
10.2 Features.......................................................................................................................................... 10-2
10.3 Function Descriptions ...................................................................................................................... 10-3
10.3.1 USB Bus Topology and Physical Connection ....................................................................... 10-3
10.3.2 Frame Generation................................................................................................................ 10-3
10.3.3 Packet Formats.................................................................................................................... 10-4
10.3.4 Bit Stuffing and NRZI Coding............................................................................................... 10-5
10.3.5 Bulk Transactions ................................................................................................................ 10-5
10.3.6 Control Transactions............................................................................................................ 10-6
10.3.7 Isochronous Transactions .................................................................................................... 10-6
10.3.8 Interrupt Transactions.......................................................................................................... 10-6
10.4 USB Block Descriptions .................................................................................................................. 10-7
10.4.1 USB Block Overview ........................................................................................................... 10-7
10.4.2 SIE (Serial Interface Engine) Block...................................................................................... 10-7
10.5 USB Special Registers.................................................................................................................... 10-9
10.5.1 USB Function Address Register........................................................................................... 10-10
10.5.2 USB Power Management Register....................................................................................... 10-12
10.5.3 USB Interrupt Register......................................................................................................... 10-14
10.5.4 USB Interrupt Enable Register............................................................................................. 10-17
10.5.5 USB Frame Number Register .............................................................................................. 10-19
10.5.6 USB Disconnect Timer Register........................................................................................... 10-20
10.5.7 USB Endpoint 0 Common Status Register........................................................................... 10-22
10.5.8 USB Endpoint 1 Common Status Register........................................................................... 10-25
10.5.9 USB Endpoint 2 Common Status Register........................................................................... 10-30
10.5.10 USB Endpoint 3 Common Status Register ......................................................................... 10-35
10.5.11 USB Endpoint 4 Common Status Register ......................................................................... 10-40
10.5.12 USB Write Count for Endpoint 0 Register........................................................................... 10-45
10.5.13 USB Write Count for Endpoint 1 Register........................................................................... 10-47
10.5.14 USB Write Count for Endpoint 2 Register........................................................................... 10-49
10.5.15 USB Write Count for Endpoint 3 Register........................................................................... 10-51
10.5.16 USB Write Count for Endpoint 4 Register........................................................................... 10-53
10.5.17 USB Endpoint 0/1/2/3/4 FIFO Register............................................................................... 10-55
xiixii S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 11DES/3DES
11.1 Overview .........................................................................................................................................11-1
11.2 Feature............................................................................................................................................11-1
11.3 DES/3DES Special Registers ...........................................................................................................11-3
11.3.1 DES/3DES Control Register .................................................................................................11-4
11.3.2 DES/3DES Status Register...................................................................................................11-5
11.3.3 DES/3DES Interrupt Enable Register....................................................................................11-6
11.3.4 DES/3DES Run Enable Register...........................................................................................11-6
11.3.5 DES/3DES Key1 Left/Right Side Register............................................................................. 11-6
11.3.6 DES/3DES Key 2 Left/Right Side Register............................................................................ 11-7
11.3.7 DES/3DES Key 3 Left Side Register.....................................................................................11-7
11.3.8 DES/3DES IV Left/Right Side Register .................................................................................11-7
11.3.9 DES/3DES Input/Output Data FIFO Register........................................................................11-8
11.4 DES/3DES Operation.......................................................................................................................11-9
11.5 Performance Calculation Guide ....................................................................................................... 11-10
Chapter 12GDMA Controller
12.1 Overview .........................................................................................................................................12-1
12.2 Feature............................................................................................................................................12-1
12.3 GDMA Special Registers..................................................................................................................12-3
12.3.1 GDMA Programmable Priority Registers ...............................................................................12-4
12.3.2 GDMA Control Registers.......................................................................................................12-9
12.3.3 GDMA Source/Destination Address Registers .......................................................................12-12
12.3.4 GDMA Transfer Count Registers...........................................................................................12-13
12.3.5 GDMA Run Enable Registers................................................................................................12-14
12.3.6 GDMA Interrupt Pending Register......................................................................................... 12-15
12.4 GDMA Mode Operation....................................................................................................................12-16
12.4.1 Software Mode .....................................................................................................................12-16
12.4.2 External GDMA Request Mode.............................................................................................12-16
12.4.3 HUART Mode.......................................................................................................................12-16
12.4.4 DES Mode............................................................................................................................12-17
12.5 GDMA Function Description .............................................................................................................12-17
12.5.1 GDMA Transfers................................................................................................................... 12-17
12.5.2 Starting/Ending GDMA Transfers ..........................................................................................12-17
12.5.3 Data Transfer Modes............................................................................................................12-18
12.6 GDMA Transfer Timing Data............................................................................................................12-19
12.6.1 Single and One Data Burst Mode.......................................................................................... 12-20
12.6.2 Single and Four Data Burst Mode.........................................................................................12-21
12.6.3 Block and One Data Burst Mode...........................................................................................12-22
12.6.4 Block and Four Data Burst....................................................................................................12-23
S3C2500B RISC MICROCONTROLLER xiii
Table of Contents (Continued)
Chapter 13 Serial I/O (Console UART)
13.1 Overview ........................................................................................................................................ 13-1
13.2 Features.......................................................................................................................................... 13-1
13.3 Console UART Special Registers.................................................................................................... 13-3
13.3.1 Console UART Control Registers......................................................................................... 13-4
13.3.2 Console UART Status Registers .......................................................................................... 13-8
13.3.3 Console UART Interrupt Enable Register............................................................................. 13-11
13.3.4 UART Transmit Data Register.............................................................................................. 13-13
13.3.5 UART Receive Data Register............................................................................................... 13-14
13.3.6 UART Baud Rate Divisor Register ....................................................................................... 13-15
13.3.7 Console UART Baud Rate Examples................................................................................... 13-16
13.3.8 UART Control Character Register 1 and 2............................................................................ 13-17
Chapter 14Serial I/O (High-Speed UART)
14.1 Overview ........................................................................................................................................ 14-1
14.2 Features.......................................................................................................................................... 14-1
14.3 High-Speed UART Special Registers .............................................................................................. 14-3
14.3.1 High-Speed UART Control Registers ................................................................................... 14-4
14.3.2 High-Speed UART Status Registers ..................................................................................... 14-9
14.3.3 High-Speed UART Interrupt Enable Register ....................................................................... 14-14
14.3.4 High-Speed UART Transmit Buffer Register........................................................................ 14-16
14.3.5 High-Speed UART Receive Buffer Register......................................................................... 14-17
14.3.6 High-Speed UART Baud Rate Divisor Register.................................................................... 14-18
14.3.7 High-Speed UART Baud Rate Examples ............................................................................. 14-19
14.3.8 High-Speed UART Control Character 1 Register.................................................................. 14-20
14.3.9 High-Speed UART Control Character 2 Register.................................................................. 14-21
14.3.10 High-Speed UART Autoband Boundary Register................................................................ 14-22
14.3.11 High-Speed UART Autobaud Table Regsiter ...................................................................... 14-23
14.4 High-Speed UART Operation.......................................................................................................... 14-24
14.4.1 FIFO Operation.................................................................................................................... 14-24
14.4.2 Hardware Flow Control......................................................................................................... 14-24
14.4.3 Software Flow Control.......................................................................................................... 14-26
14.4.4 Auto Baud Rate Detection.................................................................................................... 14-26
Chapter 15I/O Ports
15.1 Overview ........................................................................................................................................ 15-1
15.2 Features.......................................................................................................................................... 15-1
15.3 I/O Port Special Register................................................................................................................. 15-2
15.3.1 I/O Port Mode Select Register.............................................................................................. 15-3
15.3.2 I/O Port Function Control Register ....................................................................................... 15-5
15.3.3 I/O Port Control Register for GDMA..................................................................................... 15-8
15.3.4 I/O Port Control Register for External Interrupt..................................................................... 15-9
15.3.5 I/O Port External Interrupt Clear Register............................................................................. 15-11
15.3.6 I/O Port Data Register.......................................................................................................... 15-12
15.3.7 I/O Port Drive Control Register ............................................................................................ 15-12
xivxiv S3C2500B RISC MICROCONTROLLER
Table of Contents (Concluded)
Chapter 16Interrupt Controller
16.1 Overview .........................................................................................................................................16-1
16.2 Features ..........................................................................................................................................16-1
16.3 Interrupt Sources .............................................................................................................................16-2
16.4 Interrupt Controller Special Registers...............................................................................................16-3
16.4.1 Interrupt Mode Registers.......................................................................................................16-3
16.4.2 Interrupt Mask Registers.......................................................................................................16-5
16.4.3 Interrupt Priority Registers ....................................................................................................16-8
16.4.4 Interrupt Offset Register .......................................................................................................16-9
16.4.5 Interrupt by Priority Register .................................................................................................16-12
16.4.6 Interrupt Test Register..........................................................................................................16-12
Chapter 1732-bit Timers
17.1 Overview .........................................................................................................................................17-1
17.2 Feature............................................................................................................................................17-1
17.3 Interval Mode Operation ..................................................................................................................17-2
17.4 Toggle Mode Operation ...................................................................................................................17-2
17.5 Timer Operation Guidelines.............................................................................................................17-3
17.6 Timer Special Register.....................................................................................................................17-4
17.6.1 Timer Mode Register............................................................................................................17-4
17.6.2 Timer Data Registers............................................................................................................17-6
17.6.3 Timer Count Registers..........................................................................................................17-7
17.6.4 Timer Interrupt Clear Registers.............................................................................................17-8
17.6.5 Watchdog Timer Register.....................................................................................................17-9
Chapter 18Electrical Data
18.1 Overview .........................................................................................................................................18-1
18.2 Absolute Maximum Ratings .............................................................................................................18-1
18.3 Recommended Operating Conditions............................................................................................... 18-1
18.4 DC Electrical Specifications.............................................................................................................18-2
18.5 Max Power Consumption.................................................................................................................18-4
18.6 AC Electrical Characteristics............................................................................................................18-5
Chapter 19Mechanical Data
19.1 Overview .........................................................................................................................................19-1
S3C2500B RISC MICROCONTROLLER xv
List of Figures
Figure Title Page
Number Number
1-1 S3C2500B Block Diagram......................................................................................1-5
1-2 S3C2500B Pin Assignment Diagram ......................................................................1-6
2-1 Big-Endian Addresses of Bytes within Words..........................................................2-2
2-2 Little-Endian Addresses of Bytes Words.................................................................2-2
2-3 Register Organization in ARM State.......................................................................2-5
2-4 Register Organization in THUMB State ..................................................................2-6
2-5 Mapping of THUMB State Registers onto ARM State Registers ..............................2-7
2-6 Program Status Register Format............................................................................2-8
2-7 ARM940T Block Diagram.......................................................................................2-18
3-1 ARM Instruction Set Format ...................................................................................3-1
3-2 Branch and Exchange Instructions..........................................................................3-5
3-3 Branch Instructions .................................................................................................3-7
3-4 Data Processing Instructions .................................................................................. 3-9
3-5 ARM Shift Operations.............................................................................................3-12
3-6 Logical Shift Left .................................................................................................... 3-12
3-7 Logical Shift Right..................................................................................................3-13
3-8 Arithmetic Shift Right .............................................................................................3-13
3-9 Rotate Right...........................................................................................................3-14
3-10 Rotate Right Extended ........................................................................................... 3-14
3-11 PSR Transfer ......................................................................................................... 3-20
3-12 Multiply Instructions ................................................................................................3-23
3-13 Multiply Long Instructions.......................................................................................3-25
3-14 Single Data Transfer Instructions............................................................................ 3-28
3-15 Little-Endian Offset Addressing ..............................................................................3-30
3-16 Half-word and Signed Data Transfer with Register Offset.......................................3-34
3-17 Half-word and Signed Data Transfer with Immediate Offset and Auto-Indexing......3-35
3-18 Block Data Transfer Instructions.............................................................................3-40
3-19 Post-Increment Addressing.....................................................................................3-41
3-20 Pre-Increment Addressing......................................................................................3-42
3-21 Post-Decrement Addressing...................................................................................3-42
3-22 Pre-Decrement Addressing.....................................................................................3-43
3-23 Swap Instruction.....................................................................................................3-47
3-24 Software Interrupt Instruction.................................................................................. 3-49
3-25 Coprocessor Data Operation Instruction .................................................................3-51
3-26 Coprocessor Data Transfer Instructions..................................................................3-53
3-27 Coprocessor Register Transfer Instructions ............................................................ 3-56
3-28 Undefined Instruction..............................................................................................3-58
3-29 THUMB Instruction Set Formats.............................................................................3-64
S3C2500B RISC MICROCONTROLLER xvii
List of Figures (Continued)
Figure Title Page
Number Number
3-30 Format 1................................................................................................................ 3-67
3-31 Format 2................................................................................................................ 3-68
3-32 Format 3................................................................................................................ 3-70
3-33 Format 4................................................................................................................ 3-71
3-34 Format 5................................................................................................................ 3-73
3-35 Format 6................................................................................................................ 3-76
3-36 Format 7................................................................................................................ 3-77
3-37 Format 8................................................................................................................ 3-79
3-38 Format 9................................................................................................................ 3-81
3-39 Format 10.............................................................................................................. 3-83
3-40 Format 11.............................................................................................................. 3-84
3-41 Format 12.............................................................................................................. 3-85
3-42 Format 13.............................................................................................................. 3-87
3-43 Format 14.............................................................................................................. 3-88
3-44 Format 15.............................................................................................................. 3-90
3-45 Format 16.............................................................................................................. 3-91
3-46 Format 17.............................................................................................................. 3-93
3-47 Format 18.............................................................................................................. 3-94
3-48 Format 19.............................................................................................................. 3-95
4-1 S3C2500B Address map after resest..................................................................... 4-2
4-2 External Address Bus Diagram.............................................................................. 4-4
4-3 Priority Groups of S3C2500B................................................................................. 4-5
4-4 AHB Programmable Priority Registers................................................................... 4-6
4-5 Shows the Clock Generation Logic of the S3C2500B............................................. 4-14
4-6 Divided System Clock Timing Diagram.................................................................. 4-19
5-1 Memory Bank Address map................................................................................... 5-4
5-2 Memory Controller Bus Signals.............................................................................. 5-6
5-3 8-bit ROM, SRAM and Flash Basic Connection ..................................................... 5-14
5-4 8-bit ROM, SRAM and Flash Basic Connection (8-bit Memory x 2)........................ 5-15
5-5 16-bit SRAM Basic Connection .............................................................................. 5-16
5-6 16-bit ROM and Flash Basic Connection ............................................................... 5-17
5-7 16-bit ROM Basic Connection 2 ............................................................................. 5-18
5-8 16-bit SRAM Basic Connection 2........................................................................... 5-19
5-9 ROM & SRAM with Muxed Address & Data Bus Connection.................................. 5-20
5-10 BnCON.................................................................................................................. 5-22
5-11 Bank n Control (BnCON) Register Configuration.................................................... 5-24
5-12 Muxed Bus Control (MUXBCON) Register Configuration....................................... 5-26
5-13 Wait Control (WAITCON) Register Configuration .................................................. 5-28
xviiixviii S3C2500B RISC MICROCONTROLLER
List of Figures (Continued)
Figure Title Page
Number Number
5-14 Read Timing Diagram 1 .........................................................................................5-29
5-15 Write Timing Diagram 1 .........................................................................................5-30
5-16 Read Timing Diagram 2 .........................................................................................5-31
5-17 Write Timing Diagram 2 .........................................................................................5-32
5-18 Read after Write at the Same Bank (COHDIS = 1).................................................5-33
5-19 Read Timing Diagram (Muxed Bus)........................................................................5-34
5-20 Write Timing Diagram (Muxed Bus) .......................................................................5-35
5-21 Write Timing Diagram (nEWAIT)............................................................................5-36
5-22 Write Timing Diagram (nREADY)...........................................................................5-37
5-23 SDRAM Configuration Register 0 ...........................................................................5-49
5-24 SDRAM Command Register...................................................................................5-51
5-25 SDRAM Refresh Timer Register .............................................................................5-52
5-26 SDRAM Write Buffer Time-out Register.................................................................5-53
5-27 Single Read Operation (CAS Latency=2).................................... 5-54
5-28 Single Read Operation (CAS Latency=3).................................... 5-55
5-29 Single Write Operation ................................................... 5-56
5-30 Burst Read Operation (CAS Latency = 2) ................................... 5-57
5-31 Burst Read Operation (CAS Latency = 3) ................................... 5-58
5-32 Burst Write Operation............................................................................................. 5-59
6-1 I2C Block Diagram.................................................................................................. 6-1
6-2 Master Transmitter and Slave Receiver..................................................................6-3
6-3 Master Receiver and Slave Transmitter..................................................................6-4
6-4 Start and Stop Conditions .......................................................................................6-5
6-5 Data Transfer Format.............................................................................................6-7
6-6 I2C Control Status Register.....................................................................................6-10
7-1 Ethernet Diagram...................................................................................................7-1
7-2 Data Structure of Tx Buffer Descriptor.................................................................... 7-10
7-3 Data Structure of Rx Buffer Descriptor ................................................................... 7-11
7-4 Data Structure of the Receive Frame .....................................................................7-12
7-5 Fields of an IEEE802.3/Ethernet Frame ................................................................. 7-38
7-6 CSMA/CD Transmit Operation ...............................................................................7-40
7-7 Timing for Transmission without Collision ...............................................................7-41
7-8 Timing for Transmission with Collision in Preamble................................................7-42
7-9 Receiving Frame without Error...............................................................................7-43
7-10 Receiving Frame with Error....................................................................................7-43
7-11 CSMA/CD Receive Operation ................................................................................ 7-44
7-12 MAC Control Frame Format...................................................................................7-46
7-13 Timing Relationship of Transmission Signals at MII................................................7-50
7-14 Timing Relationship of Reception Signals at MII .....................................................7-50
7-15 MDIO Sourced by PHY...........................................................................................7-50
7-16 MDIO Sourced by STA...........................................................................................7-50
S3C2500B RISC MICROCONTROLLER xix
List of Figures (Continued)
Figure Title Page
Number Number
8-1 HDLC Module Block Diagram................................................................................ 8-3
8-2 Baud Rate Generator Block Diagram ..................................................................... 8-7
8-3 DPLL Block Diagram............................................................................................. 8-9
8-4 Clock Usage Method Diagram............................................................................... 8-9
8-5 Data Encoding Methods and Timing Diagrams ...................................................... 8-12
8-6 HDLC Data Setup and Timing Diagrams................................................................ 8-13
8-7 nCTS Already Asserted ......................................................................................... 8-17
8-8 CTS Lost During Transmission .............................................................................. 8-17
8-9 CTS Delayed on.................................................................................................... 8-18
8-10 Transmit Buffer Descriptor..................................................................................... 8-21
8-11 Receive Buffer Descriptor...................................................................................... 8-22
8-12 Data Structure of the Receive Data Buffer ............................................................. 8-23
8-13 HMODE Register ................................................................................................... 8-29
8-14 HDLC Control Register.......................................................................................... 8-34
8-15 HDLC Status Register............................................................................................ 8-40
8-16 HDLC Interrupt Enable Register............................................................................. 8-43
8-17 HDLC Tx FIFO Function Diagram.......................................................................... 8-44
8-18 HDLC Rx FIFO Function Diagram......................................................................... 8-45
8-19 HDLC BRG Time Constant Register...................................................................... 8-46
8-20 HDLC Preamble Constant Register........................................................................ 8-47
8-21 Address Recognition.............................................................................................. 8-48
8-22 HDLC Station Address and HMASK Register......................................................... 8-49
8-23 DMA Tx Buffer Descriptor Pointer.......................................................................... 8-49
8-24 DMA Rx Buffer Descriptor Pointer......................................................................... 8-50
8-25 Maximum Frame Length Register.......................................................................... 8-50
8-26 DMA Receive Buffer Size Register........................................................................ 8-51
8-27 HDLC Synchronization Register............................................................................. 8-51
8-28 Data Sampling Method.......................................................................................... 8-52
9-1 IOM2 Channel Structure in Terminal...................................................................... 9-2
9-2 Monitor Channel Handshake Protocol.................................................................... 9-4
9-3 Abortion of Monitor Channel Transmission ............................................................ 9-5
9-4 Structure of Last Byte of Channel 2 on DU ............................................................ 9-7
9-5 Structure of Last Byte of Channel 2 on DD ............................................................ 9-8
9-6 TSA Block Diagram............................................................................................... 9-9
9-7 IOM2 Control Register........................................................................................... 9-13
9-8 IOM2 Status Register ............................................................................................ 9-15
9-9 IOM2 Interrupt Enable Register ............................................................................. 9-17
9-10 IOM2 TIC Bus Address Register............................................................................ 9-18
9-11 IOM2 IC Channel Transmit Data Register .............................................................. 9-19
9-12 IOM2 IC Channel Receive Data Register............................................................... 9-19
xxxx S3C2500B RISC MICROCONTROLLER
List of Figures (Continued)
Figure Title Page
Number Number
9-13 IOM2 C/I0 Channel Transmit Data Register............................................................ 9-20
9-14 IOM2 C/I0 Channel Receive Data Register.............................................................9-20
9-15 IOM2 C/I1 Channel Transmit Data Register............................................................ 9-21
9-16 IOM2 C/I1 Channel Receive Data Register.............................................................9-21
9-17 IOM2 Monitor Channel Transmit Data Register ......................................................9-22
9-18 IOM2 Monitor Channel Receive Data Register ....................................................... 9-22
9-19 TSA A Control Register..........................................................................................9-23
9-20 TSA B Control Register..........................................................................................9-24
9-21 TSA C Control Register..........................................................................................9-25
9-22 IOM2 Strobe Register .............................................................................................9-26
10-1 SOF Packets..........................................................................................................10-3
10-2 USB 1.1 Frame Model............................................................................................10-4
10-3 USB Frame Format................................................................................................10-5
10-4 USB Core Block Diagram.......................................................................................10-7
10-5 SIE Block Diagram.................................................................................................10-8
10-6 USBFA Register.....................................................................................................10-11
10-7 USBPM Register....................................................................................................10-13
10-8 USBINTR Register .................................................................................................10-16
10-9 USBINTRE Register...............................................................................................10-18
10-10 USBFN Register .....................................................................................................10-19
10-11 USBDISCONN Register ......................................................................................... 10-21
10-12 USBEP0CSR Register............................................................................................10-24
10-13 USBEP1CSR Register............................................................................................10-29
10-14 USBEP2CSR Register............................................................................................10-34
10-15 USBEP3CSR Register............................................................................................10-39
10-16 USBEP4CSR Register............................................................................................10-44
10-17 USBWCEP0 Register.............................................................................................10-46
10-18 USBWCEP1 Register.............................................................................................10-48
10-19 USBWCEP2 Register.............................................................................................10-50
10-20 USBWCEP3 Register.............................................................................................10-52
10-21 USBWCEP4 Register.............................................................................................10-54
10-22 USBEP0/1/2/3/4 FIFO Registers ............................................................................10-56
11-1 DES/3DES Block Diagram .....................................................................................11-2
S3C2500B RISC MICROCONTROLLER xxi
List of Figures (Continued)
Figure Title Page
Number Number
12-1 GDMA Controller Block Diagram........................................................................... 12-2
12-2 GDMA Programmable Priority Registers................................................................ 12-5
12-3 GDMA Control Register......................................................................................... 12-11
12-4 GDMA Source/Destination Address Register ......................................................... 12-12
12-5 GDMA Transfer Count Register............................................................................. 12-13
12-6 GDMA Run Enable Register.................................................................................. 12-14
12-7 GDMA Interrupt Pending Register.......................................................................... 12-15
12-8 External GDMA Requests (Single Mode)............................................................... 12-18
12-9 External GDMA Requests (Block Mode)................................................................ 12-18
12-10 External GDMA Requests Detailed Timing ............................................................ 12-19
12-11 Single and One Data Burst Mode Timing............................................................... 12-20
12-12 Single and Four Data Burst Mode Timing .............................................................. 12-21
12-13 Block and One Data Burst Mode Timing................................................................ 12-22
12-14 Block and Four Data Burst Timing......................................................................... 12-23
13-1 Console UART Block Diagram............................................................................... 13-2
13-2 Console UART Control Register ............................................................................ 13-6
13-3 Console UART Control Register ............................................................................ 13-7
13-4 Console UART Status Register .............................................................................. 13-10
13-5 Console UART Interrupt Enable Register ............................................................... 13-12
13-6 Console UART Transmit Data Register.................................................................. 13-13
13-7 Console UART Receive Data Register................................................................... 13-14
13-8 Console UART Baud Rate Divisor Register ........................................................... 13-15
13-9 Console UART Baud Rate Generator (BRG).......................................................... 13-16
13-10 Console UART Control Character 1 Register......................................................... 13-17
13-11 Console UART Control Character 2 Register......................................................... 13-17
13-12 Interrupt-Based Serial I/O Transmit and Receive Timing Diagram......................... 13-18
13-13 Serial I/O Frame Timing Diagram (Normal Console UART)................................... 13-19
13-14 Infra-Red Transmit Mode Frame Timing Diagram.................................................. 13-19
13-15 Infra-Red Receive Mode Frame Timing Diagram................................................... 13-20
14-1 High-Speed UART Block Diagram......................................................................... 14-2
14-2 High-Speed UART Control Register....................................................................... 14-7
14-3 High-Speed UART Status Register........................................................................ 14-12
14-4 High-Speed UART Interrupt Enable Register......................................................... 14-15
14-5 High-Speed UART Transmit Buffer Register .......................................................... 14-16
14-6 High-Speed UART Receive Buffer Register........................................................... 14-17
14-7 High-Speed UART Baud Rate Divisor Register...................................................... 14-18
14-8 High-Speed UART Baud Rate Generator (BRG).................................................... 14-19
14-9 High-Speed UART Control Character 1 Register.................................................... 14-20
14-10 High-Speed UART Control Character 2 Register.................................................... 14-21
xxiixxii S3C2500B RISC MICROCONTROLLER
List of Figures (Concluded)
Figure Title Page
Number Number
14-11 AutoBaud Boundary Regsiter Range ...................................................................... 14-22
14-12 High-Speed UART AutoBaud Boundary Register.................................................... 14-22
14-13 Example of AutoBaud Table Register Setting.........................................................14-23
14-14 High-Speed UART AutoBaud Boundary Register.................................................... 14-23
14-15 When Signal is Asserted During Transmit Operation..............................................14-25
14-16 When CTS Signal is Deasserted During Transmit Operation..................................14-25
14-17 Normal Received Rx Data......................................................................................14-26
14-18 DCD Lost During Rx Data Receive.........................................................................14-26
14-19 Interrupt-Based Serial I/O Transmit and Receive Timing Diagram ..........................14-27
14-20 DMA-Based Serial I/O Timing Diagram (Tx Only)...................................................14-28
14-21 DMA-Based Serial I/O Timing Diagram (Rx Only) ..................................................14-28
14-22 Serial I/O Frame Timing Diagram (Normal High-Speed UART)..............................14-29
14-23 Infra-Red Transmit Mode Frame Timing Diagram...................................................14-29
14-24 Infra-Red Receive Mode Frame Timing Diagram ...................................................14-30
15-1 I/O Port Mode Registers 1/2 ...................................................................................15-4
15-2 I/O Function Control Register 1 ..............................................................................15-6
15-3 I/O Function Control Register 2 ..............................................................................15-7
15-4 I/O Port Control Register for GDMA........................................................................15-8
15-5 I/O Port Control Register for External Interrupt.......................................................15-10
15-6 I/O Port External Interrupt Clear Register...............................................................15-11
16-1 Internal Interrupt Mode Register .............................................................................16-4
16-2 External Interrupt Mode Register............................................................................16-5
16-3 Internal Interrupt Mask Register.............................................................................. 16-6
16-4 External Interrupt Mask Register ............................................................................16-7
16-5 Interrupt Priority Register........................................................................................16-8
17-1 Timer Output Signal Timing....................................................................................17-2
17-2 32-Bit Timer Block Diagram ...................................................................................17-3
17-3 Timer Mode Register..............................................................................................17-5
17-4 Timer Data Registers..............................................................................................17-6
17-5 Timer Counter Registers.........................................................................................17-7
17-6 Timer Interrupt Clear Register................................................................................17-8
17-7 Watchdog Timer Register....................................................................................... 17-9
19-1 272-BGA-2727-AN Package Dimensions................................................................ 19-2
S3C2500B RISC MICROCONTROLLER xxiii
List of Tables
Table Title Page
Number Number
1-1 S3C2500B Signal Descriptions...............................................................................1-13
1-2 S3C2500B Pad Type and Feature..........................................................................1-31
1-3 S3C2500B System Configuration ...........................................................................1-32
1-4 S3C2500B Memory Controller................................................................................1-32
1-5 S3C2500B SDRAM Controller................................................................................1-32
1-6 S3C2500B IIC Controller........................................................................................1-33
1-7 S3C2500B Ethernet Controller 0.............................................................................1-33
1-8 S3C2500B Ethernet Controller 1.............................................................................1-34
1-9 S3C2500B HDLC Controller 0 ................................................................................1-35
1-10 S3C2500B HDLC Controller 1 ................................................................................1-36
1-11 S3C2500B HDLC Controller 2 ................................................................................1-37
1-12 S3C2500B IOM2 Controller....................................................................................1-38
1-13 S3C2500B USB Controller .....................................................................................1-39
1-14 S3C2500B DES Controller .....................................................................................1-40
1-15 S3C2500B GDMA Controller..................................................................................1-41
1-16 S3C2500B Console UART Controller .....................................................................1-42
1-17 S3C2500B High-speed UART Controller 0..............................................................1-42
1-18 S3C2500B High speed UART Controller 1.............................................................. 1-43
1-19 S3C2500B I/O Port Controller ................................................................................1-43
1-20 S3C2500B Interrupt Controller................................................................................1-44
1-21 S3C2500B Timer Controller....................................................................................1-45
2-1 PSR Mode. Bit Values............................................................................................2-10
2-2 Exception Entry/Exit...............................................................................................2-12
2-3 Exception Vectors .................................................................................................. 2-14
2-4 ARM9TDMI Implementation Option........................................................................2-19
2-5 CP15 Register Map................................................................................................2-21
2-6 ID Code Register....................................................................................................2-21
2-7 Cache Type Register Format.................................................................................. 2-22
2-8 CP15 Register 1.....................................................................................................2-23
2-9 Clocking Modes ......................................................................................................2-23
2-10 Cacheable Register Format....................................................................................2-24
2-11 Write Buffer Control Register .................................................................................2-25
2-12 Protection Space Register Format..........................................................................2-26
2-13 Permission Encoding ..............................................................................................2-26
2-14 CP15 Data Protection Region Registers.................................................................2-27
2-15 CP15 Instruction Protection Region Registers ........................................................2-27
2-16 CP15 Protection Region Register Format...............................................................2-28
2-17 Area Size Encoding................................................................................................2-28
2-18 Cache Operations Writing to Register 7..................................................................2-29
2-19 CP15 Register 7 Index/Segment Data Format........................................................2-30
2-20 CP15 Register 7 Prefetch Address Format.............................................................2-30
2-21 Lockdown Register Format.....................................................................................2-31
2-22 CP15 Register 15...................................................................................................2-32
List of Tables (Continued)
Table Title Page
Number Number
3-1 The ARM Instruction Set........................................................................................ 3-2
3-2 Condition Code Summary...................................................................................... 3-4
3-3 ARM Data Processing Instructions ......................................................................... 3-11
3-4 Incremental Cycle Times....................................................................................... 3-17
3-5 Assembler Syntax Descriptions ............................................................................. 3-27
3-6 Addressing Mode Names ....................................................................................... 3-45
3-7 THUMB Instruction Set Opcodes........................................................................... 3-65
3-8 Summary of Format 1 Instructions ......................................................................... 3-67
3-9 Summary of Format 2 Instructions ......................................................................... 3-68
3-10 Summary of Format 3 Instructions ......................................................................... 3-70
3-11 Summary of Format 4 Instructions ......................................................................... 3-71
3-12 Summary of Format 5 Instructions ......................................................................... 3-74
3-13 Summary of PC-Relative Load Instruction............................................................. 3-76
3-14 Summary of Format 7 Instructions ......................................................................... 3-77
3-15 Summary of format 8 instructions.......................................................................... 3-79
3-16 Summary of Format 9 Instructions ......................................................................... 3-81
3-17 Half-word Data Transfer Instructions...................................................................... 3-83
3-18 SP-Relative Load/Store Instructions ...................................................................... 3-84
3-19 Load Address ........................................................................................................ 3-85
3-20 The ADD SP Instruction......................................................................................... 3-87
3-21 PUSH and POP Instructions.................................................................................. 3-88
3-22 The Multiple Load/Store Instructions ...................................................................... 3-90
3-23 The Conditional Branch Instructions ...................................................................... 3-91
3-24 The SWI Instruction ............................................................................................... 3-92
3-25 Summary of Branch Instruction.............................................................................. 3-93
3-26 The BL Instruction ................................................................................................. 3-94
4-1 The Base Address of Remapped Memory.............................................................. 4-3
4-2 AHB Bus Priorities for Arbitration ........................................................................... 4-4
4-3 Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins.... 4-9
4-4 P, M, S values of the S3C2500B PLL.................................................................... 4-13
4-5 System Configuration Registers............................................................................. 4-15
xxvixxvi S3C2500B RISC MICROCONTROLLER
List of Tables (Continued)
Table Title Page
Number Number
5-1 Base Address of Each Bank ...................................................................................5-3
5-2 Bus Interface Signals..............................................................................................5-5
5-3 External 32-bit Memory Store Operation with Big-Endian .......................................5-7
5-4 External 32-bit Memory Load Operation with Big-Endian........................................5-7
5-5 External 16-bit Store Operation with Big-Endian.....................................................5-8
5-6 External 16-bit Load Operation with Big-Endian......................................................5-8
5-7 External 8-bit Store Operation with Big-Endian.......................................................5-9
5-8 External 8-bit Load Operation with Big-Endian........................................................5-9
5-9 External 32-bit Memory Store Operation with Little-Endian.....................................5-10
5-10 External 32-bit Memory Load Operation with Little-Endian......................................5-10
5-11 External 16-bit Store Operation with Little-Endian...................................................5-11
5-12 External 16-bit Load Operation with Little-Endian...................................................5-11
5-13 External 8-bit Store Operation with Little-Endian ....................................................5-12
5-14 External 8-bit Load Operation with Little-Endian.....................................................5-12
5-15 Ext. I/O Bank Controller Special Registers .............................................................5-21
5-16 Bank n Control (BnCON) Register..........................................................................5-23
5-17 Muxed Bus Control Register...................................................................................5-25
5-18 WAIT Control Register ........................................................................................... 5-27
5-19 Supported SDRAM Configuration of 32-bit External Bus.........................................5-40
5-20 Supported SDRAM Configuration of 16-bit External Bus.........................................5-41
5-21 SDRAM Address Mapping of 32-bit External Bus ...................................................5-42
5-22 SDRAM address mapping of 16-bit external bus.....................................................5-43
5-23 SDRAM commands................................................................................................5-44
5-24 SDRAM Special Registers......................................................................................5-47
5-25 SDRAM Configuration Register..............................................................................5-47
5-26 SDRAM Command Register...................................................................................5-50
5-27 SDRAM Refresh Timer Register .............................................................................5-52
5-28 SDRAM Write Buffer Time-out Register.................................................................5-53
6-1 Control Status Register...........................................................................................6-9
6-2 IICCON Register Description..................................................................................6-9
6-3 IICBUF Register.....................................................................................................6-11
6-4 IICBUF Register Description................................................................................... 6-11
6-5 IICPS Register .......................................................................................................6-11
6-6 IICPS Register Description.....................................................................................6-11
6-7 IICCNT Register.....................................................................................................6-12
6-8 IICCNT Register Description...................................................................................6-12
6-9 IICPND Register .....................................................................................................6-12
6-10 IICPND Register Description .................................................................................. 6-12
S3C2500B RISC MICROCONTROLLER xxvii
List of Tables (Continued)
Table Title Page
Number Number
7-1 MAC Function Block Descriptions.......................................................................... 7-3
7-2 ETHERNET 0 Special Registers............................................................................ 7-13
7-3 ETHERNET 1 Special Registers............................................................................ 7-14
7-4 BDMATXCON Register.......................................................................................... 7-15
7-5 BDMA Transmit Control Register Description ........................................................ 7-15
7-6 BDMA RXCON Register........................................................................................ 7-16
7-7 BDMA Receive Control Register Description ......................................................... 7-16
7-8 BDMATXDPTR Register ........................................................................................ 7-17
7-9 BDMA Transmit Buffer descriptor Start Address Register Description.................... 7-17
7-10 BDMARXDPTR Register ....................................................................................... 7-17
7-11 BDMA Receive Buffer Descriptor Start Address Register Description.................... 7-17
7-12 BTXBDCNT Register............................................................................................. 7-18
7-13 BDMA Transmit Buffer descriptor Counter............................................................. 7-18
7-14 BRXBDCNT Register............................................................................................. 7-18
7-15 BDMA Receive Buffer descriptor Counter .............................................................. 7-18
7-16 BMTXINTEN Register............................................................................................ 7-19
7-17 BDMA/MAC Transmit Interrupt Enable Register Description.................................. 7-19
7-18 BMTXSTAT Register............................................................................................. 7-20
7-19 BDMA/MAC Transmit Interrupt Status Register Description................................... 7-20
7-20 BMRXINTEN Register ........................................................................................... 7-21
7-21 BDMA/MAC Receive Interrupt Enable Register Description................................... 7-21
7-22 BMRXSTAT Register ............................................................................................. 7-22
7-23 BDMA/MAC Receive Interrupt Status Register Description.................................... 7-22
7-24 BDMARXLEN Register.......................................................................................... 7-23
7-25 BDMA Receive Frame Size Register Description................................................... 7-23
7-26 CFTXSTAT Register.............................................................................................. 7-24
7-27 Transmit Control Frame Register Description ........................................................ 7-24
7-28 MACCON Register ................................................................................................ 7-25
7-29 MAC Control Register Description ......................................................................... 7-25
7-30 CAMCON Register ................................................................................................ 7-26
7-31 CAM Control Register Description ......................................................................... 7-26
7-32 MACTXCON Register............................................................................................ 7-27
7-33 MAC Transmit Control Register Description........................................................... 7-27
7-34 MACTXSTAT Register........................................................................................... 7-28
7-35 MAC Transmit Status Register Description............................................................ 7-28
7-36 MACRXCON Register............................................................................................ 7-29
7-37 MAC Receive Control Register Description............................................................ 7-29
7-38 MACRXSTAT Register .......................................................................................... 7-30
7-39 MAC Receive Status Register Description............................................................. 7-30
7-40 STADATA Register................................................................................................ 7-31
xxviiixxviii S3C2500B RISC MICROCONTROLLER
List of Tables (Continued)
Table Title Page
Number Number
7-41 Station Management Register Description..............................................................7-31
7-42 STACON Register..................................................................................................7-32
7-43 STACON Register Description................................................................................7-32
7-44 CAMEN Register....................................................................................................7-33
7-45 CAM Enable Register Description...........................................................................7-33
7-46 MISSCNT Register.................................................................................................7-34
7-47 Missed Error Count Register Description ................................................................7-34
7-48 PZCNT Register.....................................................................................................7-35
7-49 Received Pause Count Register Description...........................................................7-35
7-50 RMPZCNT Register................................................................................................7-35
7-51 Remote Pause Count Register Description.............................................................7-35
7-52 CAM Register.........................................................................................................7-36
7-55 Content Address Memory (CAM) Register Description............................................ 7-36
7-53 MAC Frame Format Description.............................................................................7-37
7-54 STA Frame Structure Description...........................................................................7-45
8-1 HDLC Data Frame Format .....................................................................................8-4
8-2 Baud Rate Example of HDLC.................................................................................8-8
8-3 HDLC Data Setup and Hold Timing........................................................................8-13
8-4 HDLC Channel A Special Registers .......................................................................8-24
8-5 HDLC Channel B Special Registers .......................................................................8-25
8-6 HDLC Channel C Special Registers.......................................................................8-26
8-7 HMODEA, HMODEB, and HMODEC Register........................................................ 8-27
8-8 HMODE Register Description.................................................................................8-27
8-9 HCONA , HCONB, and HCONC Register...............................................................8-30
8-10 HCON Register Description....................................................................................8-30
8-11 HSTATA, HSTATB, and HSTATC Register............................................................8-36
8-12 HSTAT Register Description................................................................................... 8-37
8-13 HINTENA, HINTENB, and HINTENC Register........................................................ 8-42
8-14 HINTEN Register Description.................................................................................8-42
8-15 HBRGTCA and HBRGTCB Register....................................................................... 8-46
8-16 HPRMBA and HPRMBB Register...........................................................................8-47
8-17 Preamble Reference Pattern..................................................................................8-47
8-18 HSADR and HMASK Register ................................................................................8-48
8-19 DMA Tx Buffer Descriptor Pointer Registers ...........................................................8-49
8-20 DMA Rx Buffer Descriptor Pointer Registers ..........................................................8-50
8-21 HDMATXCNT and HDMARXCNT Registers...........................................................8-50
8-22 DMA Rx Buffer Size Register.................................................................................8-51
8-23 Synchronization Register ........................................................................................8-51
8-24 Transparent Control Register.................................................................................. 8-52
8-25 HTXBDCNTA, HTXBDCNTB, and HTXBDCNTC Register......................................8-53
8-26 HRXBDCNTA, HRXBDCNTB, and HRXBDCNTC Register.....................................8-53
8-27 HTXBDMAXCNTA, HTXBDMAXCNTB, and HTXBDMAXCNTC Register ...............8-54
8-28 HRXBDMAXCNTA, HRXBDMAXCNTB, and HRXBDMAXCNTC Register ..............8-54
S3C2500B RISC MICROCONTROLLER xxix
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