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S3C2500B
User Guide
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SAMSUNG S3C2500B User Guide

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USER'S MANUAL
21-S3C2500B-032003
S3C2500B
32-Bit RISC
Microprocessor
Revision 1
S3C2500B
MICROPROCESSOR
USER'S MANUAL
Revision 1
Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.
This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.
"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.
Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur.
Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.
S3C2500B RISC Microprocessor User's Manual, Revision 1.0
Publication Number: 21.0-S3-C2500B-052003
2003 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.
Samsung Electronics' Microprocessor business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives.
Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung-Eup Yongin-City, Kyunggi-Do, Korea C.P.O. Box #37, Suwon 449-900
TEL: (82)-(31)-209-2831 FAX: (82)-(31)-209-3262 Home-Page URL: http://www.samsungsemi.com
Printed in the Republic of Korea
Table of Contents
Chapter 1 Product Overview
1.1 Overview...........................................................................................................................................1-1
1.2 Features ............................................................................................................................................ 1-2
1.3 Block Diagram...................................................................................................................................1-5
1.4 Package Diagram ..............................................................................................................................1-6
1.5 Pin Assignment ..................................................................................................................................1-7
1.6 Signal Description..............................................................................................................................1-13
1.7 Pad Type...........................................................................................................................................1-31
1.8 Special Registers...............................................................................................................................1-32
Chapter 2 Programmer's Model
2.1 Overview...........................................................................................................................................2-1
2.2 Switching State..................................................................................................................................2-1
2.2.1 Entering THUMB State...........................................................................................................2-1
2.2.2 Entering ARM State................................................................................................................2-1
2.3 Memory Formats................................................................................................................................2-2
2.3.1 Big-Endian Format..................................................................................................................2-2
2.3.2 Little-Endian Format...............................................................................................................2-2
2.4 Instruction Length .............................................................................................................................. 2-3
2.5 Data Types ........................................................................................................................................2-3
2.6 Operating Modes ............................................................................................................................... 2-3
2.7 Registers ...........................................................................................................................................2-4
2.7.3 The Relationship Between ARM and THUMB State Registers.................................................2-7
2.7.4 Accessing Hi-Registers in THUMB State.................................................................................2-8
2.8 The Program Status Registers...........................................................................................................2-8
2.8.1 The Condition Code Flags ......................................................................................................2-9
2.8.2 The Control Bits...................................................................................................................... 2-9
2.9 Exceptions.........................................................................................................................................2-11
2.9.1 Action on Entering an Exception.............................................................................................2-11
2.9.2 Action on Leaving an Exception..............................................................................................2-11
2.9.3 Exception Entry/Exit Summary...............................................................................................2-12
2.9.4 FIQ.........................................................................................................................................2-12
2.9.5 IRQ.........................................................................................................................................2-13
2.9.6 Abort ......................................................................................................................................2-13
2.9.7 Software Interrupt...................................................................................................................2-14
2.9.8 Undefined Instruction ..............................................................................................................2-14
2.10 Exception Vectors............................................................................................................................2-14
2.10.1 Exception Priorities ...............................................................................................................2-15
2.10.2 Not All Exceptions Can Occur at Once: ................................................................................2-15
2.11 Interrupt Latencies ...........................................................................................................................2-16
2.12 Reset...............................................................................................................................................2-16
2.13 Introduction for ARM940T................................................................................................................2-17
2.14 ARM940T Block Diagram.................................................................................................................2-18
2.15 About The ARM940T Programmer's Model......................................................................................2-19
2.15.1 Data Abort Model.................................................................................................................. 2-20
2.15.2 Instruction Set Extension Spaces.......................................................................................... 2-20
2.16 ARM940T CP15 Registers...............................................................................................................2-21
2.16.1 CP15 Register Map Summary ..............................................................................................2-21
S3C2500B RISC MICROCONTROLLER iii
Table of Contents (Continued)
Chapter 3 Instruction Set
3.1 Instruction Set Summay.................................................................................................................... 3-1
3.1.1 Format Summary................................................................................................................... 3-1
3.1.2 Instruction Summary .............................................................................................................. 3-2
3.2 The Condition Field ........................................................................................................................... 3-4
3.3 Branch and Exchange (BX)............................................................................................................... 3-5
3.3.1 Instruction Cycle Times.......................................................................................................... 3-5
3.3.2 Assembler Syntax .................................................................................................................. 3-5
3.3.3 Using R15 as an Operand...................................................................................................... 3-5
3.4 Branch and Branch with Link (B, BL)................................................................................................. 3-7
3.4.1 The Link Bit ........................................................................................................................... 3-7
3.4.2 Instruction Cycle Times.......................................................................................................... 3-7
3.4.3 Assembler Syntax .................................................................................................................. 3-8
3.5 Data Processing ................................................................................................................................ 3-9
3.5.1 CPSR Flags ........................................................................................................................... 3-11
3.5.2 Shifts..................................................................................................................................... 3-12
3.5.3 Immediate Operand Rotates.................................................................................................. 3-16
3.5.4 Writing to R15........................................................................................................................ 3-16
3.5.5 Using R15 as an Operand...................................................................................................... 3-16
3.5.6 Teq, Tst, Cmp and CMN Opcodes......................................................................................... 3-16
3.5.7 Instruction Cycle Times.......................................................................................................... 3-17
3.6.8 Assembler Syntax .................................................................................................................. 3-17
3.6 PSR Transfer (MRS, MSR)............................................................................................................... 3-19
3.6.1 Operand Restrictions ............................................................................................................. 3-19
3.6.2 Reserved Bits........................................................................................................................ 3-21
3.6.3 Instruction Cycle Times.......................................................................................................... 3-21
3.6.4 Assembler Syntax .................................................................................................................. 3-22
3.7 Multiply and Multiply-Accumulate (MUL, MLA).................................................................................. 3-23
3.7.1 CPSR Flags ........................................................................................................................... 3-24
3.7.2 Instruction Cycle Times.......................................................................................................... 3-24
3.7.3 Assembler Syntax .................................................................................................................. 3-24
3.8 Multiply Long and Multiply-Accumulate Long (MULL, MLAL)............................................................. 3-25
3.8.1 Operand Restrictions ............................................................................................................. 3-25
3.8.2 CPSR Flags ........................................................................................................................... 3-26
3.8.3 Instruction Cycle Times.......................................................................................................... 3-26
3.8.4 Assembler Syntax .................................................................................................................. 3-27
3.9 Single Data Transfer (LDR, STR)...................................................................................................... 3-28
3.9.1 Offsets and Auto-Indexing ..................................................................................................... 3-29
3.9.2 Shifted Register Offset........................................................................................................... 3-29
3.9.3 Bytes and Words ................................................................................................................... 3-29
3.9.4 Use of R15............................................................................................................................. 3-31
3.9.5 Restriction on the Use of Base Register................................................................................. 3-31
3.9.6 Data Aborts............................................................................................................................ 3-31
3.9.7 Instruction Cycle Times.......................................................................................................... 3-31
3.9.8 Assembler Syntax .................................................................................................................. 3-32
iviv S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.10 Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH).................................................3-34
3.10.1 Offsets and Auto-Indexing .................................................................................................... 3-35
3.10.2 Half-Word Load and Stores ..................................................................................................3-36
3.10.3 Signed Byte and Half-Word Loads........................................................................................3-36
3.10.4 Endianness and Byte/Half-Word Selection............................................................................ 3-36
3.10.5 Use of R15 ...........................................................................................................................3-37
3.10.6 Data Aborts...........................................................................................................................3-37
3.10.7 Instruction Cycle Times ........................................................................................................3-37
3.10.8 Assembler Syntax................................................................................................................. 3-38
3.11 Block Data Transfer (LDM, STM).....................................................................................................3-40
3.11.1 The Register List...................................................................................................................3-40
3.11.2 Addressing Modes ................................................................................................................3-41
3.11.3 Address Alignment................................................................................................................3-41
3.11.4 Use of the S Bit ....................................................................................................................3-43
3.11.5 Use of R15 as the Base........................................................................................................3-43
3.11.6 Inclusion of the Base in the Register List...............................................................................3-44
3.11.7 Data Aborts...........................................................................................................................3-44
3.11.8 Instruction Cycle Times ........................................................................................................3-44
3.11.9 Assembler Syntax................................................................................................................. 3-45
3.12 Single Data Swap (SWP).................................................................................................................3-47
3.12.1 Bytes and Words ..................................................................................................................3-47
3.12.2 Use of R15 ...........................................................................................................................3-47
3.12.3 Data Aborts...........................................................................................................................3-48
3.12.4 Instruction Cycle Times ........................................................................................................3-48
3.12.5 Assembler Syntax................................................................................................................. 3-48
3.13 Software Interrupt (SWI)..................................................................................................................3-49
3.13.1 Return from the Supervisor................................................................................................... 3-49
3.13.2 Comment Field.....................................................................................................................3-49
3.13.3 Instruction Cycle Times ........................................................................................................3-49
3.13.4 Assembler Syntax................................................................................................................. 3-50
3.14 Coprocessor Data Operations (CDP)................................................................................................3-51
3.14.1 Coprocessor Instructions.......................................................................................................3-51
3.14.2 The Coprocessor Fields........................................................................................................3-51
3.14.3 Instruction Cycle Times ........................................................................................................3-52
3.14.4 Assembler Syntax................................................................................................................. 3-52
3.15 Coprocessor Data Transfers (LDC, STC) ......................................................................................... 3-53
3.15.1 The Coprocessor Fields........................................................................................................3-53
3.15.2 Addressing Modes ................................................................................................................3-54
3.15.3 Address Alignment................................................................................................................3-54
3.15.4 Use of R15 ...........................................................................................................................3-54
3.15.5 Data Aborts...........................................................................................................................3-54
3.15.6 Instruction Cycle Times ........................................................................................................3-54
3.15.7 Assembler Syntax................................................................................................................. 3-55
S3C2500B RISC MICROCONTROLLER v
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.16 Coprocessor Register Transfers (MRC, MCR)................................................................................. 3-56
3.16.1 The Coprocessor Fields....................................................................................................... 3-56
3.16.2 Transfers to R15.................................................................................................................. 3-57
3.16.3 Transfers from R15.............................................................................................................. 3-57
3.16.4 Instruction Cycle Times........................................................................................................ 3-57
3.16.5 Assembler Syntax................................................................................................................ 3-57
3.17 Undefined Instruction ...................................................................................................................... 3-58
3.17.1 Instruction Cycle Times........................................................................................................ 3-58
3.17.2 Assembler Syntax................................................................................................................ 3-58
3.18 Instruction Set Examples................................................................................................................. 3-59
3.18.1 Using The Conditional Instructions....................................................................................... 3-59
3.18.2 Pseudo-Random Binary Sequence Generator...................................................................... 3-61
3.18.3 Multiplication by Constant Using The Barrel Shifter.............................................................. 3-61
3.18.4 Loading a Word From an Unknown Alignment..................................................................... 3-63
3.19 Thumb Instruction Set Format......................................................................................................... 3-64
3.19.1 Format Summary ................................................................................................................. 3-64
3.19.2 Opcode Summary ................................................................................................................ 3-65
3.20 Format 1: Move Shifted Register..................................................................................................... 3-67
3.20.1 Operation............................................................................................................................. 3-67
3.20.2 Instruction Cycle Times........................................................................................................ 3-67
3.21 Format 2: Add/Subtract................................................................................................................... 3-68
3.21.1 Operation............................................................................................................................. 3-68
3.21.2 Instruction Cycle Times........................................................................................................ 3-69
3.22 Format 3: Move/Compare/Add/Subtract Immediate......................................................................... 3-70
3.22.1 Operations........................................................................................................................... 3-70
3.22.2 Instruction Cycle Times........................................................................................................ 3-70
3.23 Format 4: ALU Operations .............................................................................................................. 3-71
3.23.1 Operation............................................................................................................................. 3-71
3.23.2 Instruction Cycle Times........................................................................................................ 3-72
3.24 Format 5: Hi-Register Operations/Branch Exchange ....................................................................... 3-73
3.24.1 Operation............................................................................................................................. 3-73
3.24.2 Instruction Cycle Times........................................................................................................ 3-74
3.24.3 The Bx Instruction ................................................................................................................ 3-74
3.24.4 Using R15 as an Operand.................................................................................................... 3-75
3.25 Format 6: PC-Relative Load............................................................................................................ 3-76
3.25.1 Operation............................................................................................................................. 3-76
3.25.2 Instruction Cycle Times........................................................................................................ 3-76
3.26 Format 7: Load/Store With Register Offset...................................................................................... 3-77
3.26.1 Operation............................................................................................................................. 3-77
3.26.2 Instruction Cycle Times........................................................................................................ 3-78
3.27 Format 8: Load/Store Sign-Extended Byte/Half-Word ..................................................................... 3-79
3.27.1 Operation............................................................................................................................. 3-79
3.27.2 Instruction Cycle Times........................................................................................................ 3-80
vivi S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 3 Instruction Set (Continued)
3.28 Format 9: Load/Store with Immediate Offset....................................................................................3-81
3.28.1 Operation..............................................................................................................................3-81
3.28.2 Instruction Cycle Times ........................................................................................................3-82
3.29 Format 10: Load/Store Half-Word....................................................................................................3-83
3.29.1 Operation..............................................................................................................................3-83
3.29.2 Instruction Cycle Times ........................................................................................................3-83
3.30 Format 11: SP-Relative Load/Store .................................................................................................3-84
3.30.1 Operation..............................................................................................................................3-84
3.30.2 Instruction Cycle Times ........................................................................................................3-84
3.31 Format 12: Load Addres...................................................................................................................3-85
3.31.1 Operation..............................................................................................................................3-85
3.31.2 Instruction Cycle Times ........................................................................................................3-86
3.32 Format 13: Add Offset to Stack Pointer............................................................................................ 3-87
3.32.1 Operation..............................................................................................................................3-87
3.32.2 Instruction Cycle Times ........................................................................................................3-87
3.33 Format 14: Push/Pop Registers........................................................................................................3-88
3.33.1 Operation..............................................................................................................................3-88
3.33.2 Instruction Cycle Times ........................................................................................................3-89
3.34 Format 15: Multiple Load/Store........................................................................................................3-90
3.34.1 Operation..............................................................................................................................3-90
3.34.2 Instruction Cycle Times ........................................................................................................3-90
3.35 Format 16: Conditional Branch.........................................................................................................3-91
3.35.1 Operation..............................................................................................................................3-91
3.35.2 Instruction Cycle Times ........................................................................................................3-92
3.36 Format 17: Software Interrupt .......................................................................................................... 3-93
3.36.1 Operation..............................................................................................................................3-93
3.36.2 Instruction Cycle Times ........................................................................................................3-93
3.37 Format 18: Unconditional Branch.....................................................................................................3-94
3.37.1 Operation..............................................................................................................................3-94
3.38 Format 19: Long Branch With Link ...................................................................................................3-95
3.38.1 Operation..............................................................................................................................3-95
3.38.2 Instruction Cycle Times ........................................................................................................3-96
3.39 Instruction Set Examples ................................................................................................................. 3-97
3.39.1 Multiplication by a Constant Using Shifts and Adds ...............................................................3-97
3.39.2 General Purpose Signed Divide............................................................................................3-98
3.39.3 Division by a Constant..........................................................................................................3-100
S3C2500B RISC MICROCONTROLLER vii
Table of Contents (Continued)
Chapter 4 System Configuration
4.1 Overview .......................................................................................................................................... 4-1
4.2 Features............................................................................................................................................ 4-1
4.3 Address Map..................................................................................................................................... 4-2
4.4 Remap of Memory Space ................................................................................................................. 4-3
4.5 External Address Translation ............................................................................................................ 4-3
4.6 Arbitration Scheme ........................................................................................................................... 4-4
4.6.1 Problem Solvings with Programmable Round-Robin.............................................................. 4-7
4.7 Clock Configuration........................................................................................................................... 4-9
4.8 External Bus Master .......................................................................................................................... 4-14
4.9 System Configuration Special Registers............................................................................................ 4-15
4.9.1 System Configuration Register............................................................................................... 4-16
4.9.2 Product Code and Revision Number Register........................................................................ 4-18
4.9.3 Clock Control Register........................................................................................................... 4-19
4.9.4 Peripheral Clock Disable Register .......................................................................................... 4-20
4.9.5 Clock Status Register ............................................................................................................ 4-21
4.9.6 AHB Bus Master Priority Register .......................................................................................... 4-21
4.9.7 Core PLL Control Register..................................................................................................... 4-22
4.9.8 System Bus PLL Control Register.......................................................................................... 4-23
4.9.9 USB PLL Control Register ..................................................................................................... 4-24
4.9.10 PHY PLL Control Register.................................................................................................... 4-24
Chapter 5 Memory Controller
5.1 Overview .......................................................................................................................................... 5-1
5.2 Features............................................................................................................................................ 5-2
5.3 Memory Map ..................................................................................................................................... 5-3
5.4 Bus Interface Signals........................................................................................................................ 5-5
5.5 Endian Modes................................................................................................................................... 5-7
5.6 Ext I/O Bank Controller..................................................................................................................... 5-13
5.6.1 Features ................................................................................................................................ 5-13
5.6.2 External Device Connection................................................................................................... 5-14
5.6.3 Ext. I/O Bank Controller Special Register............................................................................... 5-21
5.6.4 Timing Diagram..................................................................................................................... 5-29
5.7 SDRAM Controller ............................................................................................................................ 5-38
5.7.1 Features ................................................................................................................................ 5-38
5.7.2 SDRAM Size and Configuration............................................................................................. 5-39
5.7.3 Address Mapping................................................................................................................... 5-42
5.7.4 SDRAM Commands............................................................................................................... 5-44
5.7.5 External Data Bus Width........................................................................................................ 5-45
5.7.6 Merging Write Buffer ............................................................................................................. 5-45
5.7.7 Self Refresh........................................................................................................................... 5-45
5.7.8 Basic Operation..................................................................................................................... 5-46
5.7.9 SDRAM Special Registers ..................................................................................................... 5-47
5.7.10 SDRAM Controller Timing.................................................................................................... 5-54
viiiviii S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 6 I2C Controller
6.1 Overview...........................................................................................................................................6-1
6.2 Features ............................................................................................................................................ 6-1
6.3 Functional Description .......................................................................................................................6-2
6.4 I2C Concepts .....................................................................................................................................6-3
6.4.1 Basic Operation......................................................................................................................6-3
6.4.2 General Characteristics .......................................................................................................... 6-4
6.4.3 Bit Transfers...........................................................................................................................6-4
6.4.4 Data Validity...........................................................................................................................6-5
6.4.5 Start And Stop Conditions.......................................................................................................6-5
6.4.6 Data Trsansfer Operations ......................................................................................................6-6
6.5 I2C Special Registers.........................................................................................................................6-9
6.5.1 Control Status Register ...........................................................................................................6-9
6.5.2 Shift Buffer Register...............................................................................................................6-11
6.5.3 Prescaler Register..................................................................................................................6-11
6.5.4 Prescaler Counter Register.....................................................................................................6-12
6.5.5 Interrupt Pending Register......................................................................................................6-12
Chapter 7 Ethernet Controller
7.1 Overview...........................................................................................................................................7-1
7.2 Features ............................................................................................................................................ 7-2
7.3 MAC Function Blocks.........................................................................................................................7-3
7.3.1 Media Independent Interface (MII)..........................................................................................7-3
7.3.2 Physical Layer Entity (PHY) ....................................................................................................7-4
7.3.3 Buffered Dma Interface (BDI).................................................................................................7-4
7.3.4 The MAC Transmitter Block.................................................................................................... 7-4
7.3.5 The MAC Receiver Block........................................................................................................7-6
7.3.6 Flow Control Block..................................................................................................................7-7
7.3.7 Buffered DMA (BDMA) Overview ...........................................................................................7-7
7.4 Ethernet Controller Special Registers.................................................................................................7-13
7.4.1 BDMA Relative Special Register ............................................................................................7-15
7.4.2 MAC Relative Special Register ...............................................................................................7-24
7.5 Ethernet Operations...........................................................................................................................7-37
7.5.1 MAC Frame Format................................................................................................................ 7-37
7.5.2 The MII Station Manager ........................................................................................................7-45
7.5.3 Full-Duplex Pause Operations................................................................................................7-46
7.5.4 Error Signalling .......................................................................................................................7-48
7.5.5 Timing Parameters for MII Transactions.................................................................................7-50
S3C2500B RISC MICROCONTROLLER ix
Table of Contents (Continued)
Chapter 8 HDLC Controller
8.1 Overview .......................................................................................................................................... 8-1
8.2 Features............................................................................................................................................ 8-2
8.3 Function Descriptions........................................................................................................................ 8-3
8.3.1 HDLC Frame Format............................................................................................................. 8-4
8.4 Protocol Features.............................................................................................................................. 8-6
8.4.1 Invalid Frame ........................................................................................................................ 8-6
8.4.2 Zero Insertion and Zero Deletion............................................................................................ 8-6
8.4.3 Abort...................................................................................................................................... 8-6
8.4.4 Idle and Time Fill................................................................................................................... 8-6
8.4.5 FIFO Structure....................................................................................................................... 8-7
8.4.6 Two-Channel DMA Engine ..................................................................................................... 8-7
8.4.7 Baud Rate Generator............................................................................................................. 8-7
8.4.8 Digital Phase-Locked Loop (DPLL) ........................................................................................ 8-9
8.4.9 Clock Usage Method.............................................................................................................. 8-9
8.5 HDLC Operational Description .......................................................................................................... 8-11
8.5.1 HDLC Initialization................................................................................................................. 8-11
8.5.2 HDLC Data Encoding/Decoding............................................................................................. 8-12
8.5.3 HDLC Data Setup and Hold Timing with Clock....................................................................... 8-13
8.5.4 HDLC Transmitter Operation ................................................................................................. 8-14
8.5.5 HDLC Receiver Operation ..................................................................................................... 8-16
8.5.6 Hardware Flow Control .......................................................................................................... 8-17
8.5.7 Memory Data Structure .......................................................................................................... 8-19
8.5.8 Data Buffer Descriptor ........................................................................................................... 8-20
8.6 Buffer Descriptor............................................................................................................................... 8-21
8.6.1 Transmit Buffer Descriptor..................................................................................................... 8-21
8.6.2 Receive Buffer Descriptor...................................................................................................... 8-22
8.7 HDLC Special Registers.................................................................................................................... 8-24
8.7.1 HDLC Global Mode Register .................................................................................................. 8-27
8.7.2 HDLC Control Register .......................................................................................................... 8-30
8.7.3 HDLC Status Register ........................................................................................................... 8-36
8.7.4 Summary............................................................................................................................... 8-36
8.7.5 HDLC Interrupt Enable Register ............................................................................................. 8-42
8.7.6 HDLC Tx Fifo......................................................................................................................... 8-44
8.7.7 HDLC Rx Fifo........................................................................................................................ 8-45
8.7.8 HDLC Brg Time Constant Registers ....................................................................................... 8-46
8.7.9 HDLC Preamble Constant Register ........................................................................................ 8-47
8.7.10 HDLC Station Address Registers and Hmask Register......................................................... 8-48
8.7.11 Dma Tx Buffer Descriptor Pointer Register .......................................................................... 8-49
8.7.12 Dma Rx Buffer Descriptor Pointer Register.......................................................................... 8-50
8.7.13 Maximum Frame Length Register........................................................................................ 8-50
8.7.14 Receive Buffer Size Register............................................................................................... 8-51
8.7.15 Synchronization Register ..................................................................................................... 8-51
8.7.16 Transparent Control Register............................................................................................... 8-52
8.7.17 Tx Buffer Descriptor Count Register..................................................................................... 8-53
8.7.18 Rx Buffer Descriptor Count Register.................................................................................... 8-53
8.7.19 Tx Buffer Descriptor Maximum Count Register.................................................................... 8-54
8.7.20 Rx Buffer Descriptor Maximum Count Register .................................................................... 8-54
xx S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 9 IOM2 & TSA Controller
9.1 Overview...........................................................................................................................................9-1
9.2 Features ............................................................................................................................................ 9-1
9.3 IOM2 Bus...........................................................................................................................................9-2
9.3.1 B Channels.............................................................................................................................9-3
9.3.2 D Channel .............................................................................................................................. 9-3
9.3.3 Monitor Channels....................................................................................................................9-3
9.3.4 Command and Indicate Channels...........................................................................................9-3
9.3.5 Intercommunication Channels.................................................................................................9-3
9.3.6 TIC Bus..................................................................................................................................9-3
9.3.7 Channel Operation..................................................................................................................9-4
9.4 TSA (Time Slot Assigner) ..................................................................................................................9-9
9.4.1 Overview................................................................................................................................9-9
9.4.2 TSA Block Diagram................................................................................................................9-9
9.4.3 HDLC External Pin Multiplexed Signals..................................................................................9-10
9.4.4 Operation ...............................................................................................................................9-10
9.5 IOM2 Special Registers ..................................................................................................................... 9-11
9.5.1 IOM2CON Register.................................................................................................................9-12
9.5.2 IOM2 Status Register .............................................................................................................9-14
9.5.3 IOM2 Interrupt Enable Register ..............................................................................................9-16
9.5.4 IOM2 TIC Bus Address Register.............................................................................................9-18
9.5.5 IOM2 IC Channel Transmit Data Register...............................................................................9-19
9.5.6 IOM2 C/I0 Channel Transmit Data Register............................................................................9-20
9.5.7 IOM2 C/I1 Channel Transmit Data Register............................................................................9-21
9.5.8 IOM2 C/I1 Channel Receive Data Register.............................................................................9-21
9.5.9 IOM2 Monitor Channel Transmit Data Register....................................................................... 9-22
9.5.10 IOM2 Monitor Channel Receive Data Register...................................................................... 9-22
9.5.11 TSA A Control Register.........................................................................................................9-23
9.5.12 TSA B Control Register.........................................................................................................9-24
9.5.13 TSA C Control Register ........................................................................................................ 9-25
9.5.14 IOM2STRB (Strobe Register) ...............................................................................................9-26
S3C2500B RISC MICROCONTROLLER xi
Table of Contents (Continued)
Chapter 10USB Controller
10.1 Overview ........................................................................................................................................ 10-1
10.2 Features.......................................................................................................................................... 10-2
10.3 Function Descriptions ...................................................................................................................... 10-3
10.3.1 USB Bus Topology and Physical Connection ....................................................................... 10-3
10.3.2 Frame Generation................................................................................................................ 10-3
10.3.3 Packet Formats.................................................................................................................... 10-4
10.3.4 Bit Stuffing and NRZI Coding............................................................................................... 10-5
10.3.5 Bulk Transactions ................................................................................................................ 10-5
10.3.6 Control Transactions............................................................................................................ 10-6
10.3.7 Isochronous Transactions .................................................................................................... 10-6
10.3.8 Interrupt Transactions.......................................................................................................... 10-6
10.4 USB Block Descriptions .................................................................................................................. 10-7
10.4.1 USB Block Overview ........................................................................................................... 10-7
10.4.2 SIE (Serial Interface Engine) Block...................................................................................... 10-7
10.5 USB Special Registers.................................................................................................................... 10-9
10.5.1 USB Function Address Register........................................................................................... 10-10
10.5.2 USB Power Management Register....................................................................................... 10-12
10.5.3 USB Interrupt Register......................................................................................................... 10-14
10.5.4 USB Interrupt Enable Register............................................................................................. 10-17
10.5.5 USB Frame Number Register .............................................................................................. 10-19
10.5.6 USB Disconnect Timer Register........................................................................................... 10-20
10.5.7 USB Endpoint 0 Common Status Register........................................................................... 10-22
10.5.8 USB Endpoint 1 Common Status Register........................................................................... 10-25
10.5.9 USB Endpoint 2 Common Status Register........................................................................... 10-30
10.5.10 USB Endpoint 3 Common Status Register ......................................................................... 10-35
10.5.11 USB Endpoint 4 Common Status Register ......................................................................... 10-40
10.5.12 USB Write Count for Endpoint 0 Register........................................................................... 10-45
10.5.13 USB Write Count for Endpoint 1 Register........................................................................... 10-47
10.5.14 USB Write Count for Endpoint 2 Register........................................................................... 10-49
10.5.15 USB Write Count for Endpoint 3 Register........................................................................... 10-51
10.5.16 USB Write Count for Endpoint 4 Register........................................................................... 10-53
10.5.17 USB Endpoint 0/1/2/3/4 FIFO Register............................................................................... 10-55
xiixii S3C2500B RISC MICROCONTROLLER
Table of Contents (Continued)
Chapter 11DES/3DES
11.1 Overview .........................................................................................................................................11-1
11.2 Feature............................................................................................................................................11-1
11.3 DES/3DES Special Registers ...........................................................................................................11-3
11.3.1 DES/3DES Control Register .................................................................................................11-4
11.3.2 DES/3DES Status Register...................................................................................................11-5
11.3.3 DES/3DES Interrupt Enable Register....................................................................................11-6
11.3.4 DES/3DES Run Enable Register...........................................................................................11-6
11.3.5 DES/3DES Key1 Left/Right Side Register............................................................................. 11-6
11.3.6 DES/3DES Key 2 Left/Right Side Register............................................................................ 11-7
11.3.7 DES/3DES Key 3 Left Side Register.....................................................................................11-7
11.3.8 DES/3DES IV Left/Right Side Register .................................................................................11-7
11.3.9 DES/3DES Input/Output Data FIFO Register........................................................................11-8
11.4 DES/3DES Operation.......................................................................................................................11-9
11.5 Performance Calculation Guide ....................................................................................................... 11-10
Chapter 12GDMA Controller
12.1 Overview .........................................................................................................................................12-1
12.2 Feature............................................................................................................................................12-1
12.3 GDMA Special Registers..................................................................................................................12-3
12.3.1 GDMA Programmable Priority Registers ...............................................................................12-4
12.3.2 GDMA Control Registers.......................................................................................................12-9
12.3.3 GDMA Source/Destination Address Registers .......................................................................12-12
12.3.4 GDMA Transfer Count Registers...........................................................................................12-13
12.3.5 GDMA Run Enable Registers................................................................................................12-14
12.3.6 GDMA Interrupt Pending Register......................................................................................... 12-15
12.4 GDMA Mode Operation....................................................................................................................12-16
12.4.1 Software Mode .....................................................................................................................12-16
12.4.2 External GDMA Request Mode.............................................................................................12-16
12.4.3 HUART Mode.......................................................................................................................12-16
12.4.4 DES Mode............................................................................................................................12-17
12.5 GDMA Function Description .............................................................................................................12-17
12.5.1 GDMA Transfers................................................................................................................... 12-17
12.5.2 Starting/Ending GDMA Transfers ..........................................................................................12-17
12.5.3 Data Transfer Modes............................................................................................................12-18
12.6 GDMA Transfer Timing Data............................................................................................................12-19
12.6.1 Single and One Data Burst Mode.......................................................................................... 12-20
12.6.2 Single and Four Data Burst Mode.........................................................................................12-21
12.6.3 Block and One Data Burst Mode...........................................................................................12-22
12.6.4 Block and Four Data Burst....................................................................................................12-23
S3C2500B RISC MICROCONTROLLER xiii
Table of Contents (Continued)
Chapter 13 Serial I/O (Console UART)
13.1 Overview ........................................................................................................................................ 13-1
13.2 Features.......................................................................................................................................... 13-1
13.3 Console UART Special Registers.................................................................................................... 13-3
13.3.1 Console UART Control Registers......................................................................................... 13-4
13.3.2 Console UART Status Registers .......................................................................................... 13-8
13.3.3 Console UART Interrupt Enable Register............................................................................. 13-11
13.3.4 UART Transmit Data Register.............................................................................................. 13-13
13.3.5 UART Receive Data Register............................................................................................... 13-14
13.3.6 UART Baud Rate Divisor Register ....................................................................................... 13-15
13.3.7 Console UART Baud Rate Examples................................................................................... 13-16
13.3.8 UART Control Character Register 1 and 2............................................................................ 13-17
Chapter 14Serial I/O (High-Speed UART)
14.1 Overview ........................................................................................................................................ 14-1
14.2 Features.......................................................................................................................................... 14-1
14.3 High-Speed UART Special Registers .............................................................................................. 14-3
14.3.1 High-Speed UART Control Registers ................................................................................... 14-4
14.3.2 High-Speed UART Status Registers ..................................................................................... 14-9
14.3.3 High-Speed UART Interrupt Enable Register ....................................................................... 14-14
14.3.4 High-Speed UART Transmit Buffer Register........................................................................ 14-16
14.3.5 High-Speed UART Receive Buffer Register......................................................................... 14-17
14.3.6 High-Speed UART Baud Rate Divisor Register.................................................................... 14-18
14.3.7 High-Speed UART Baud Rate Examples ............................................................................. 14-19
14.3.8 High-Speed UART Control Character 1 Register.................................................................. 14-20
14.3.9 High-Speed UART Control Character 2 Register.................................................................. 14-21
14.3.10 High-Speed UART Autoband Boundary Register................................................................ 14-22
14.3.11 High-Speed UART Autobaud Table Regsiter ...................................................................... 14-23
14.4 High-Speed UART Operation.......................................................................................................... 14-24
14.4.1 FIFO Operation.................................................................................................................... 14-24
14.4.2 Hardware Flow Control......................................................................................................... 14-24
14.4.3 Software Flow Control.......................................................................................................... 14-26
14.4.4 Auto Baud Rate Detection.................................................................................................... 14-26
Chapter 15I/O Ports
15.1 Overview ........................................................................................................................................ 15-1
15.2 Features.......................................................................................................................................... 15-1
15.3 I/O Port Special Register................................................................................................................. 15-2
15.3.1 I/O Port Mode Select Register.............................................................................................. 15-3
15.3.2 I/O Port Function Control Register ....................................................................................... 15-5
15.3.3 I/O Port Control Register for GDMA..................................................................................... 15-8
15.3.4 I/O Port Control Register for External Interrupt..................................................................... 15-9
15.3.5 I/O Port External Interrupt Clear Register............................................................................. 15-11
15.3.6 I/O Port Data Register.......................................................................................................... 15-12
15.3.7 I/O Port Drive Control Register ............................................................................................ 15-12
xivxiv S3C2500B RISC MICROCONTROLLER
Table of Contents (Concluded)
Chapter 16Interrupt Controller
16.1 Overview .........................................................................................................................................16-1
16.2 Features ..........................................................................................................................................16-1
16.3 Interrupt Sources .............................................................................................................................16-2
16.4 Interrupt Controller Special Registers...............................................................................................16-3
16.4.1 Interrupt Mode Registers.......................................................................................................16-3
16.4.2 Interrupt Mask Registers.......................................................................................................16-5
16.4.3 Interrupt Priority Registers ....................................................................................................16-8
16.4.4 Interrupt Offset Register .......................................................................................................16-9
16.4.5 Interrupt by Priority Register .................................................................................................16-12
16.4.6 Interrupt Test Register..........................................................................................................16-12
Chapter 1732-bit Timers
17.1 Overview .........................................................................................................................................17-1
17.2 Feature............................................................................................................................................17-1
17.3 Interval Mode Operation ..................................................................................................................17-2
17.4 Toggle Mode Operation ...................................................................................................................17-2
17.5 Timer Operation Guidelines.............................................................................................................17-3
17.6 Timer Special Register.....................................................................................................................17-4
17.6.1 Timer Mode Register............................................................................................................17-4
17.6.2 Timer Data Registers............................................................................................................17-6
17.6.3 Timer Count Registers..........................................................................................................17-7
17.6.4 Timer Interrupt Clear Registers.............................................................................................17-8
17.6.5 Watchdog Timer Register.....................................................................................................17-9
Chapter 18Electrical Data
18.1 Overview .........................................................................................................................................18-1
18.2 Absolute Maximum Ratings .............................................................................................................18-1
18.3 Recommended Operating Conditions............................................................................................... 18-1
18.4 DC Electrical Specifications.............................................................................................................18-2
18.5 Max Power Consumption.................................................................................................................18-4
18.6 AC Electrical Characteristics............................................................................................................18-5
Chapter 19Mechanical Data
19.1 Overview .........................................................................................................................................19-1
S3C2500B RISC MICROCONTROLLER xv
List of Figures
Figure Title Page Number Number
1-1 S3C2500B Block Diagram......................................................................................1-5
1-2 S3C2500B Pin Assignment Diagram ......................................................................1-6
2-1 Big-Endian Addresses of Bytes within Words..........................................................2-2
2-2 Little-Endian Addresses of Bytes Words.................................................................2-2
2-3 Register Organization in ARM State.......................................................................2-5
2-4 Register Organization in THUMB State ..................................................................2-6
2-5 Mapping of THUMB State Registers onto ARM State Registers ..............................2-7
2-6 Program Status Register Format............................................................................2-8
2-7 ARM940T Block Diagram.......................................................................................2-18
3-1 ARM Instruction Set Format ...................................................................................3-1
3-2 Branch and Exchange Instructions..........................................................................3-5
3-3 Branch Instructions .................................................................................................3-7
3-4 Data Processing Instructions .................................................................................. 3-9
3-5 ARM Shift Operations.............................................................................................3-12
3-6 Logical Shift Left .................................................................................................... 3-12
3-7 Logical Shift Right..................................................................................................3-13
3-8 Arithmetic Shift Right .............................................................................................3-13
3-9 Rotate Right...........................................................................................................3-14
3-10 Rotate Right Extended ........................................................................................... 3-14
3-11 PSR Transfer ......................................................................................................... 3-20
3-12 Multiply Instructions ................................................................................................3-23
3-13 Multiply Long Instructions.......................................................................................3-25
3-14 Single Data Transfer Instructions............................................................................ 3-28
3-15 Little-Endian Offset Addressing ..............................................................................3-30
3-16 Half-word and Signed Data Transfer with Register Offset.......................................3-34
3-17 Half-word and Signed Data Transfer with Immediate Offset and Auto-Indexing......3-35
3-18 Block Data Transfer Instructions.............................................................................3-40
3-19 Post-Increment Addressing.....................................................................................3-41
3-20 Pre-Increment Addressing......................................................................................3-42
3-21 Post-Decrement Addressing...................................................................................3-42
3-22 Pre-Decrement Addressing.....................................................................................3-43
3-23 Swap Instruction.....................................................................................................3-47
3-24 Software Interrupt Instruction.................................................................................. 3-49
3-25 Coprocessor Data Operation Instruction .................................................................3-51
3-26 Coprocessor Data Transfer Instructions..................................................................3-53
3-27 Coprocessor Register Transfer Instructions ............................................................ 3-56
3-28 Undefined Instruction..............................................................................................3-58
3-29 THUMB Instruction Set Formats.............................................................................3-64
S3C2500B RISC MICROCONTROLLER xvii
List of Figures (Continued)
Figure Title Page Number Number
3-30 Format 1................................................................................................................ 3-67
3-31 Format 2................................................................................................................ 3-68
3-32 Format 3................................................................................................................ 3-70
3-33 Format 4................................................................................................................ 3-71
3-34 Format 5................................................................................................................ 3-73
3-35 Format 6................................................................................................................ 3-76
3-36 Format 7................................................................................................................ 3-77
3-37 Format 8................................................................................................................ 3-79
3-38 Format 9................................................................................................................ 3-81
3-39 Format 10.............................................................................................................. 3-83
3-40 Format 11.............................................................................................................. 3-84
3-41 Format 12.............................................................................................................. 3-85
3-42 Format 13.............................................................................................................. 3-87
3-43 Format 14.............................................................................................................. 3-88
3-44 Format 15.............................................................................................................. 3-90
3-45 Format 16.............................................................................................................. 3-91
3-46 Format 17.............................................................................................................. 3-93
3-47 Format 18.............................................................................................................. 3-94
3-48 Format 19.............................................................................................................. 3-95
4-1 S3C2500B Address map after resest..................................................................... 4-2
4-2 External Address Bus Diagram.............................................................................. 4-4
4-3 Priority Groups of S3C2500B................................................................................. 4-5
4-4 AHB Programmable Priority Registers................................................................... 4-6
4-5 Shows the Clock Generation Logic of the S3C2500B............................................. 4-14
4-6 Divided System Clock Timing Diagram.................................................................. 4-19
5-1 Memory Bank Address map................................................................................... 5-4
5-2 Memory Controller Bus Signals.............................................................................. 5-6
5-3 8-bit ROM, SRAM and Flash Basic Connection ..................................................... 5-14
5-4 8-bit ROM, SRAM and Flash Basic Connection (8-bit Memory x 2)........................ 5-15
5-5 16-bit SRAM Basic Connection .............................................................................. 5-16
5-6 16-bit ROM and Flash Basic Connection ............................................................... 5-17
5-7 16-bit ROM Basic Connection 2 ............................................................................. 5-18
5-8 16-bit SRAM Basic Connection 2........................................................................... 5-19
5-9 ROM & SRAM with Muxed Address & Data Bus Connection.................................. 5-20
5-10 BnCON.................................................................................................................. 5-22
5-11 Bank n Control (BnCON) Register Configuration.................................................... 5-24
5-12 Muxed Bus Control (MUXBCON) Register Configuration....................................... 5-26
5-13 Wait Control (WAITCON) Register Configuration .................................................. 5-28
xviiixviii S3C2500B RISC MICROCONTROLLER
List of Figures (Continued)
Figure Title Page Number Number
5-14 Read Timing Diagram 1 .........................................................................................5-29
5-15 Write Timing Diagram 1 .........................................................................................5-30
5-16 Read Timing Diagram 2 .........................................................................................5-31
5-17 Write Timing Diagram 2 .........................................................................................5-32
5-18 Read after Write at the Same Bank (COHDIS = 1).................................................5-33
5-19 Read Timing Diagram (Muxed Bus)........................................................................5-34
5-20 Write Timing Diagram (Muxed Bus) .......................................................................5-35
5-21 Write Timing Diagram (nEWAIT)............................................................................5-36
5-22 Write Timing Diagram (nREADY)...........................................................................5-37
5-23 SDRAM Configuration Register 0 ...........................................................................5-49
5-24 SDRAM Command Register...................................................................................5-51
5-25 SDRAM Refresh Timer Register .............................................................................5-52
5-26 SDRAM Write Buffer Time-out Register.................................................................5-53
5-27 Single Read Operation (CAS Latency=2).................................... 5-54
5-28 Single Read Operation (CAS Latency=3).................................... 5-55
5-29 Single Write Operation ................................................... 5-56
5-30 Burst Read Operation (CAS Latency = 2) ................................... 5-57
5-31 Burst Read Operation (CAS Latency = 3) ................................... 5-58
5-32 Burst Write Operation............................................................................................. 5-59
6-1 I2C Block Diagram.................................................................................................. 6-1
6-2 Master Transmitter and Slave Receiver..................................................................6-3
6-3 Master Receiver and Slave Transmitter..................................................................6-4
6-4 Start and Stop Conditions .......................................................................................6-5
6-5 Data Transfer Format.............................................................................................6-7
6-6 I2C Control Status Register.....................................................................................6-10
7-1 Ethernet Diagram...................................................................................................7-1
7-2 Data Structure of Tx Buffer Descriptor.................................................................... 7-10
7-3 Data Structure of Rx Buffer Descriptor ................................................................... 7-11
7-4 Data Structure of the Receive Frame .....................................................................7-12
7-5 Fields of an IEEE802.3/Ethernet Frame ................................................................. 7-38
7-6 CSMA/CD Transmit Operation ...............................................................................7-40
7-7 Timing for Transmission without Collision ...............................................................7-41
7-8 Timing for Transmission with Collision in Preamble................................................7-42
7-9 Receiving Frame without Error...............................................................................7-43
7-10 Receiving Frame with Error....................................................................................7-43
7-11 CSMA/CD Receive Operation ................................................................................ 7-44
7-12 MAC Control Frame Format...................................................................................7-46
7-13 Timing Relationship of Transmission Signals at MII................................................7-50
7-14 Timing Relationship of Reception Signals at MII .....................................................7-50
7-15 MDIO Sourced by PHY...........................................................................................7-50
7-16 MDIO Sourced by STA...........................................................................................7-50
S3C2500B RISC MICROCONTROLLER xix
List of Figures (Continued)
Figure Title Page Number Number
8-1 HDLC Module Block Diagram................................................................................ 8-3
8-2 Baud Rate Generator Block Diagram ..................................................................... 8-7
8-3 DPLL Block Diagram............................................................................................. 8-9
8-4 Clock Usage Method Diagram............................................................................... 8-9
8-5 Data Encoding Methods and Timing Diagrams ...................................................... 8-12
8-6 HDLC Data Setup and Timing Diagrams................................................................ 8-13
8-7 nCTS Already Asserted ......................................................................................... 8-17
8-8 CTS Lost During Transmission .............................................................................. 8-17
8-9 CTS Delayed on.................................................................................................... 8-18
8-10 Transmit Buffer Descriptor..................................................................................... 8-21
8-11 Receive Buffer Descriptor...................................................................................... 8-22
8-12 Data Structure of the Receive Data Buffer ............................................................. 8-23
8-13 HMODE Register ................................................................................................... 8-29
8-14 HDLC Control Register.......................................................................................... 8-34
8-15 HDLC Status Register............................................................................................ 8-40
8-16 HDLC Interrupt Enable Register............................................................................. 8-43
8-17 HDLC Tx FIFO Function Diagram.......................................................................... 8-44
8-18 HDLC Rx FIFO Function Diagram......................................................................... 8-45
8-19 HDLC BRG Time Constant Register...................................................................... 8-46
8-20 HDLC Preamble Constant Register........................................................................ 8-47
8-21 Address Recognition.............................................................................................. 8-48
8-22 HDLC Station Address and HMASK Register......................................................... 8-49
8-23 DMA Tx Buffer Descriptor Pointer.......................................................................... 8-49
8-24 DMA Rx Buffer Descriptor Pointer......................................................................... 8-50
8-25 Maximum Frame Length Register.......................................................................... 8-50
8-26 DMA Receive Buffer Size Register........................................................................ 8-51
8-27 HDLC Synchronization Register............................................................................. 8-51
8-28 Data Sampling Method.......................................................................................... 8-52
9-1 IOM2 Channel Structure in Terminal...................................................................... 9-2
9-2 Monitor Channel Handshake Protocol.................................................................... 9-4
9-3 Abortion of Monitor Channel Transmission ............................................................ 9-5
9-4 Structure of Last Byte of Channel 2 on DU ............................................................ 9-7
9-5 Structure of Last Byte of Channel 2 on DD ............................................................ 9-8
9-6 TSA Block Diagram............................................................................................... 9-9
9-7 IOM2 Control Register........................................................................................... 9-13
9-8 IOM2 Status Register ............................................................................................ 9-15
9-9 IOM2 Interrupt Enable Register ............................................................................. 9-17
9-10 IOM2 TIC Bus Address Register............................................................................ 9-18
9-11 IOM2 IC Channel Transmit Data Register .............................................................. 9-19
9-12 IOM2 IC Channel Receive Data Register............................................................... 9-19
xxxx S3C2500B RISC MICROCONTROLLER
List of Figures (Continued)
Figure Title Page Number Number
9-13 IOM2 C/I0 Channel Transmit Data Register............................................................ 9-20
9-14 IOM2 C/I0 Channel Receive Data Register.............................................................9-20
9-15 IOM2 C/I1 Channel Transmit Data Register............................................................ 9-21
9-16 IOM2 C/I1 Channel Receive Data Register.............................................................9-21
9-17 IOM2 Monitor Channel Transmit Data Register ......................................................9-22
9-18 IOM2 Monitor Channel Receive Data Register ....................................................... 9-22
9-19 TSA A Control Register..........................................................................................9-23
9-20 TSA B Control Register..........................................................................................9-24
9-21 TSA C Control Register..........................................................................................9-25
9-22 IOM2 Strobe Register .............................................................................................9-26
10-1 SOF Packets..........................................................................................................10-3
10-2 USB 1.1 Frame Model............................................................................................10-4
10-3 USB Frame Format................................................................................................10-5
10-4 USB Core Block Diagram.......................................................................................10-7
10-5 SIE Block Diagram.................................................................................................10-8
10-6 USBFA Register.....................................................................................................10-11
10-7 USBPM Register....................................................................................................10-13
10-8 USBINTR Register .................................................................................................10-16
10-9 USBINTRE Register...............................................................................................10-18
10-10 USBFN Register .....................................................................................................10-19
10-11 USBDISCONN Register ......................................................................................... 10-21
10-12 USBEP0CSR Register............................................................................................10-24
10-13 USBEP1CSR Register............................................................................................10-29
10-14 USBEP2CSR Register............................................................................................10-34
10-15 USBEP3CSR Register............................................................................................10-39
10-16 USBEP4CSR Register............................................................................................10-44
10-17 USBWCEP0 Register.............................................................................................10-46
10-18 USBWCEP1 Register.............................................................................................10-48
10-19 USBWCEP2 Register.............................................................................................10-50
10-20 USBWCEP3 Register.............................................................................................10-52
10-21 USBWCEP4 Register.............................................................................................10-54
10-22 USBEP0/1/2/3/4 FIFO Registers ............................................................................10-56
11-1 DES/3DES Block Diagram .....................................................................................11-2
S3C2500B RISC MICROCONTROLLER xxi
List of Figures (Continued)
Figure Title Page Number Number
12-1 GDMA Controller Block Diagram........................................................................... 12-2
12-2 GDMA Programmable Priority Registers................................................................ 12-5
12-3 GDMA Control Register......................................................................................... 12-11
12-4 GDMA Source/Destination Address Register ......................................................... 12-12
12-5 GDMA Transfer Count Register............................................................................. 12-13
12-6 GDMA Run Enable Register.................................................................................. 12-14
12-7 GDMA Interrupt Pending Register.......................................................................... 12-15
12-8 External GDMA Requests (Single Mode)............................................................... 12-18
12-9 External GDMA Requests (Block Mode)................................................................ 12-18
12-10 External GDMA Requests Detailed Timing ............................................................ 12-19
12-11 Single and One Data Burst Mode Timing............................................................... 12-20
12-12 Single and Four Data Burst Mode Timing .............................................................. 12-21
12-13 Block and One Data Burst Mode Timing................................................................ 12-22
12-14 Block and Four Data Burst Timing......................................................................... 12-23
13-1 Console UART Block Diagram............................................................................... 13-2
13-2 Console UART Control Register ............................................................................ 13-6
13-3 Console UART Control Register ............................................................................ 13-7
13-4 Console UART Status Register .............................................................................. 13-10
13-5 Console UART Interrupt Enable Register ............................................................... 13-12
13-6 Console UART Transmit Data Register.................................................................. 13-13
13-7 Console UART Receive Data Register................................................................... 13-14
13-8 Console UART Baud Rate Divisor Register ........................................................... 13-15
13-9 Console UART Baud Rate Generator (BRG).......................................................... 13-16
13-10 Console UART Control Character 1 Register......................................................... 13-17
13-11 Console UART Control Character 2 Register......................................................... 13-17
13-12 Interrupt-Based Serial I/O Transmit and Receive Timing Diagram......................... 13-18
13-13 Serial I/O Frame Timing Diagram (Normal Console UART)................................... 13-19
13-14 Infra-Red Transmit Mode Frame Timing Diagram.................................................. 13-19
13-15 Infra-Red Receive Mode Frame Timing Diagram................................................... 13-20
14-1 High-Speed UART Block Diagram......................................................................... 14-2
14-2 High-Speed UART Control Register....................................................................... 14-7
14-3 High-Speed UART Status Register........................................................................ 14-12
14-4 High-Speed UART Interrupt Enable Register......................................................... 14-15
14-5 High-Speed UART Transmit Buffer Register .......................................................... 14-16
14-6 High-Speed UART Receive Buffer Register........................................................... 14-17
14-7 High-Speed UART Baud Rate Divisor Register...................................................... 14-18
14-8 High-Speed UART Baud Rate Generator (BRG).................................................... 14-19
14-9 High-Speed UART Control Character 1 Register.................................................... 14-20
14-10 High-Speed UART Control Character 2 Register.................................................... 14-21
xxiixxii S3C2500B RISC MICROCONTROLLER
List of Figures (Concluded)
Figure Title Page Number Number
14-11 AutoBaud Boundary Regsiter Range ...................................................................... 14-22
14-12 High-Speed UART AutoBaud Boundary Register.................................................... 14-22
14-13 Example of AutoBaud Table Register Setting.........................................................14-23
14-14 High-Speed UART AutoBaud Boundary Register.................................................... 14-23
14-15 When Signal is Asserted During Transmit Operation..............................................14-25
14-16 When CTS Signal is Deasserted During Transmit Operation..................................14-25
14-17 Normal Received Rx Data......................................................................................14-26
14-18 DCD Lost During Rx Data Receive.........................................................................14-26
14-19 Interrupt-Based Serial I/O Transmit and Receive Timing Diagram ..........................14-27
14-20 DMA-Based Serial I/O Timing Diagram (Tx Only)...................................................14-28
14-21 DMA-Based Serial I/O Timing Diagram (Rx Only) ..................................................14-28
14-22 Serial I/O Frame Timing Diagram (Normal High-Speed UART)..............................14-29
14-23 Infra-Red Transmit Mode Frame Timing Diagram...................................................14-29
14-24 Infra-Red Receive Mode Frame Timing Diagram ...................................................14-30
15-1 I/O Port Mode Registers 1/2 ...................................................................................15-4
15-2 I/O Function Control Register 1 ..............................................................................15-6
15-3 I/O Function Control Register 2 ..............................................................................15-7
15-4 I/O Port Control Register for GDMA........................................................................15-8
15-5 I/O Port Control Register for External Interrupt.......................................................15-10
15-6 I/O Port External Interrupt Clear Register...............................................................15-11
16-1 Internal Interrupt Mode Register .............................................................................16-4
16-2 External Interrupt Mode Register............................................................................16-5
16-3 Internal Interrupt Mask Register.............................................................................. 16-6
16-4 External Interrupt Mask Register ............................................................................16-7
16-5 Interrupt Priority Register........................................................................................16-8
17-1 Timer Output Signal Timing....................................................................................17-2
17-2 32-Bit Timer Block Diagram ...................................................................................17-3
17-3 Timer Mode Register..............................................................................................17-5
17-4 Timer Data Registers..............................................................................................17-6
17-5 Timer Counter Registers.........................................................................................17-7
17-6 Timer Interrupt Clear Register................................................................................17-8
17-7 Watchdog Timer Register....................................................................................... 17-9
19-1 272-BGA-2727-AN Package Dimensions................................................................ 19-2
S3C2500B RISC MICROCONTROLLER xxiii
List of Tables
Table Title Page Number Number
1-1 S3C2500B Signal Descriptions...............................................................................1-13
1-2 S3C2500B Pad Type and Feature..........................................................................1-31
1-3 S3C2500B System Configuration ...........................................................................1-32
1-4 S3C2500B Memory Controller................................................................................1-32
1-5 S3C2500B SDRAM Controller................................................................................1-32
1-6 S3C2500B IIC Controller........................................................................................1-33
1-7 S3C2500B Ethernet Controller 0.............................................................................1-33
1-8 S3C2500B Ethernet Controller 1.............................................................................1-34
1-9 S3C2500B HDLC Controller 0 ................................................................................1-35
1-10 S3C2500B HDLC Controller 1 ................................................................................1-36
1-11 S3C2500B HDLC Controller 2 ................................................................................1-37
1-12 S3C2500B IOM2 Controller....................................................................................1-38
1-13 S3C2500B USB Controller .....................................................................................1-39
1-14 S3C2500B DES Controller .....................................................................................1-40
1-15 S3C2500B GDMA Controller..................................................................................1-41
1-16 S3C2500B Console UART Controller .....................................................................1-42
1-17 S3C2500B High-speed UART Controller 0..............................................................1-42
1-18 S3C2500B High speed UART Controller 1.............................................................. 1-43
1-19 S3C2500B I/O Port Controller ................................................................................1-43
1-20 S3C2500B Interrupt Controller................................................................................1-44
1-21 S3C2500B Timer Controller....................................................................................1-45
2-1 PSR Mode. Bit Values............................................................................................2-10
2-2 Exception Entry/Exit...............................................................................................2-12
2-3 Exception Vectors .................................................................................................. 2-14
2-4 ARM9TDMI Implementation Option........................................................................2-19
2-5 CP15 Register Map................................................................................................2-21
2-6 ID Code Register....................................................................................................2-21
2-7 Cache Type Register Format.................................................................................. 2-22
2-8 CP15 Register 1.....................................................................................................2-23
2-9 Clocking Modes ......................................................................................................2-23
2-10 Cacheable Register Format....................................................................................2-24
2-11 Write Buffer Control Register .................................................................................2-25
2-12 Protection Space Register Format..........................................................................2-26
2-13 Permission Encoding ..............................................................................................2-26
2-14 CP15 Data Protection Region Registers.................................................................2-27
2-15 CP15 Instruction Protection Region Registers ........................................................2-27
2-16 CP15 Protection Region Register Format...............................................................2-28
2-17 Area Size Encoding................................................................................................2-28
2-18 Cache Operations Writing to Register 7..................................................................2-29
2-19 CP15 Register 7 Index/Segment Data Format........................................................2-30
2-20 CP15 Register 7 Prefetch Address Format.............................................................2-30
2-21 Lockdown Register Format.....................................................................................2-31
2-22 CP15 Register 15...................................................................................................2-32
List of Tables (Continued)
Table Title Page Number Number
3-1 The ARM Instruction Set........................................................................................ 3-2
3-2 Condition Code Summary...................................................................................... 3-4
3-3 ARM Data Processing Instructions ......................................................................... 3-11
3-4 Incremental Cycle Times....................................................................................... 3-17
3-5 Assembler Syntax Descriptions ............................................................................. 3-27
3-6 Addressing Mode Names ....................................................................................... 3-45
3-7 THUMB Instruction Set Opcodes........................................................................... 3-65
3-8 Summary of Format 1 Instructions ......................................................................... 3-67
3-9 Summary of Format 2 Instructions ......................................................................... 3-68
3-10 Summary of Format 3 Instructions ......................................................................... 3-70
3-11 Summary of Format 4 Instructions ......................................................................... 3-71
3-12 Summary of Format 5 Instructions ......................................................................... 3-74
3-13 Summary of PC-Relative Load Instruction............................................................. 3-76
3-14 Summary of Format 7 Instructions ......................................................................... 3-77
3-15 Summary of format 8 instructions.......................................................................... 3-79
3-16 Summary of Format 9 Instructions ......................................................................... 3-81
3-17 Half-word Data Transfer Instructions...................................................................... 3-83
3-18 SP-Relative Load/Store Instructions ...................................................................... 3-84
3-19 Load Address ........................................................................................................ 3-85
3-20 The ADD SP Instruction......................................................................................... 3-87
3-21 PUSH and POP Instructions.................................................................................. 3-88
3-22 The Multiple Load/Store Instructions ...................................................................... 3-90
3-23 The Conditional Branch Instructions ...................................................................... 3-91
3-24 The SWI Instruction ............................................................................................... 3-92
3-25 Summary of Branch Instruction.............................................................................. 3-93
3-26 The BL Instruction ................................................................................................. 3-94
4-1 The Base Address of Remapped Memory.............................................................. 4-3
4-2 AHB Bus Priorities for Arbitration ........................................................................... 4-4
4-3 Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins.... 4-9
4-4 P, M, S values of the S3C2500B PLL.................................................................... 4-13
4-5 System Configuration Registers............................................................................. 4-15
xxvixxvi S3C2500B RISC MICROCONTROLLER
List of Tables (Continued)
Table Title Page Number Number
5-1 Base Address of Each Bank ...................................................................................5-3
5-2 Bus Interface Signals..............................................................................................5-5
5-3 External 32-bit Memory Store Operation with Big-Endian .......................................5-7
5-4 External 32-bit Memory Load Operation with Big-Endian........................................5-7
5-5 External 16-bit Store Operation with Big-Endian.....................................................5-8
5-6 External 16-bit Load Operation with Big-Endian......................................................5-8
5-7 External 8-bit Store Operation with Big-Endian.......................................................5-9
5-8 External 8-bit Load Operation with Big-Endian........................................................5-9
5-9 External 32-bit Memory Store Operation with Little-Endian.....................................5-10
5-10 External 32-bit Memory Load Operation with Little-Endian......................................5-10
5-11 External 16-bit Store Operation with Little-Endian...................................................5-11
5-12 External 16-bit Load Operation with Little-Endian...................................................5-11
5-13 External 8-bit Store Operation with Little-Endian ....................................................5-12
5-14 External 8-bit Load Operation with Little-Endian.....................................................5-12
5-15 Ext. I/O Bank Controller Special Registers .............................................................5-21
5-16 Bank n Control (BnCON) Register..........................................................................5-23
5-17 Muxed Bus Control Register...................................................................................5-25
5-18 WAIT Control Register ........................................................................................... 5-27
5-19 Supported SDRAM Configuration of 32-bit External Bus.........................................5-40
5-20 Supported SDRAM Configuration of 16-bit External Bus.........................................5-41
5-21 SDRAM Address Mapping of 32-bit External Bus ...................................................5-42
5-22 SDRAM address mapping of 16-bit external bus.....................................................5-43
5-23 SDRAM commands................................................................................................5-44
5-24 SDRAM Special Registers......................................................................................5-47
5-25 SDRAM Configuration Register..............................................................................5-47
5-26 SDRAM Command Register...................................................................................5-50
5-27 SDRAM Refresh Timer Register .............................................................................5-52
5-28 SDRAM Write Buffer Time-out Register.................................................................5-53
6-1 Control Status Register...........................................................................................6-9
6-2 IICCON Register Description..................................................................................6-9
6-3 IICBUF Register.....................................................................................................6-11
6-4 IICBUF Register Description................................................................................... 6-11
6-5 IICPS Register .......................................................................................................6-11
6-6 IICPS Register Description.....................................................................................6-11
6-7 IICCNT Register.....................................................................................................6-12
6-8 IICCNT Register Description...................................................................................6-12
6-9 IICPND Register .....................................................................................................6-12
6-10 IICPND Register Description .................................................................................. 6-12
S3C2500B RISC MICROCONTROLLER xxvii
List of Tables (Continued)
Table Title Page Number Number
7-1 MAC Function Block Descriptions.......................................................................... 7-3
7-2 ETHERNET 0 Special Registers............................................................................ 7-13
7-3 ETHERNET 1 Special Registers............................................................................ 7-14
7-4 BDMATXCON Register.......................................................................................... 7-15
7-5 BDMA Transmit Control Register Description ........................................................ 7-15
7-6 BDMA RXCON Register........................................................................................ 7-16
7-7 BDMA Receive Control Register Description ......................................................... 7-16
7-8 BDMATXDPTR Register ........................................................................................ 7-17
7-9 BDMA Transmit Buffer descriptor Start Address Register Description.................... 7-17
7-10 BDMARXDPTR Register ....................................................................................... 7-17
7-11 BDMA Receive Buffer Descriptor Start Address Register Description.................... 7-17
7-12 BTXBDCNT Register............................................................................................. 7-18
7-13 BDMA Transmit Buffer descriptor Counter............................................................. 7-18
7-14 BRXBDCNT Register............................................................................................. 7-18
7-15 BDMA Receive Buffer descriptor Counter .............................................................. 7-18
7-16 BMTXINTEN Register............................................................................................ 7-19
7-17 BDMA/MAC Transmit Interrupt Enable Register Description.................................. 7-19
7-18 BMTXSTAT Register............................................................................................. 7-20
7-19 BDMA/MAC Transmit Interrupt Status Register Description................................... 7-20
7-20 BMRXINTEN Register ........................................................................................... 7-21
7-21 BDMA/MAC Receive Interrupt Enable Register Description................................... 7-21
7-22 BMRXSTAT Register ............................................................................................. 7-22
7-23 BDMA/MAC Receive Interrupt Status Register Description.................................... 7-22
7-24 BDMARXLEN Register.......................................................................................... 7-23
7-25 BDMA Receive Frame Size Register Description................................................... 7-23
7-26 CFTXSTAT Register.............................................................................................. 7-24
7-27 Transmit Control Frame Register Description ........................................................ 7-24
7-28 MACCON Register ................................................................................................ 7-25
7-29 MAC Control Register Description ......................................................................... 7-25
7-30 CAMCON Register ................................................................................................ 7-26
7-31 CAM Control Register Description ......................................................................... 7-26
7-32 MACTXCON Register............................................................................................ 7-27
7-33 MAC Transmit Control Register Description........................................................... 7-27
7-34 MACTXSTAT Register........................................................................................... 7-28
7-35 MAC Transmit Status Register Description............................................................ 7-28
7-36 MACRXCON Register............................................................................................ 7-29
7-37 MAC Receive Control Register Description............................................................ 7-29
7-38 MACRXSTAT Register .......................................................................................... 7-30
7-39 MAC Receive Status Register Description............................................................. 7-30
7-40 STADATA Register................................................................................................ 7-31
xxviiixxviii S3C2500B RISC MICROCONTROLLER
List of Tables (Continued)
Table Title Page Number Number
7-41 Station Management Register Description..............................................................7-31
7-42 STACON Register..................................................................................................7-32
7-43 STACON Register Description................................................................................7-32
7-44 CAMEN Register....................................................................................................7-33
7-45 CAM Enable Register Description...........................................................................7-33
7-46 MISSCNT Register.................................................................................................7-34
7-47 Missed Error Count Register Description ................................................................7-34
7-48 PZCNT Register.....................................................................................................7-35
7-49 Received Pause Count Register Description...........................................................7-35
7-50 RMPZCNT Register................................................................................................7-35
7-51 Remote Pause Count Register Description.............................................................7-35
7-52 CAM Register.........................................................................................................7-36
7-55 Content Address Memory (CAM) Register Description............................................ 7-36
7-53 MAC Frame Format Description.............................................................................7-37
7-54 STA Frame Structure Description...........................................................................7-45
8-1 HDLC Data Frame Format .....................................................................................8-4
8-2 Baud Rate Example of HDLC.................................................................................8-8
8-3 HDLC Data Setup and Hold Timing........................................................................8-13
8-4 HDLC Channel A Special Registers .......................................................................8-24
8-5 HDLC Channel B Special Registers .......................................................................8-25
8-6 HDLC Channel C Special Registers.......................................................................8-26
8-7 HMODEA, HMODEB, and HMODEC Register........................................................ 8-27
8-8 HMODE Register Description.................................................................................8-27
8-9 HCONA , HCONB, and HCONC Register...............................................................8-30
8-10 HCON Register Description....................................................................................8-30
8-11 HSTATA, HSTATB, and HSTATC Register............................................................8-36
8-12 HSTAT Register Description................................................................................... 8-37
8-13 HINTENA, HINTENB, and HINTENC Register........................................................ 8-42
8-14 HINTEN Register Description.................................................................................8-42
8-15 HBRGTCA and HBRGTCB Register....................................................................... 8-46
8-16 HPRMBA and HPRMBB Register...........................................................................8-47
8-17 Preamble Reference Pattern..................................................................................8-47
8-18 HSADR and HMASK Register ................................................................................8-48
8-19 DMA Tx Buffer Descriptor Pointer Registers ...........................................................8-49
8-20 DMA Rx Buffer Descriptor Pointer Registers ..........................................................8-50
8-21 HDMATXCNT and HDMARXCNT Registers...........................................................8-50
8-22 DMA Rx Buffer Size Register.................................................................................8-51
8-23 Synchronization Register ........................................................................................8-51
8-24 Transparent Control Register.................................................................................. 8-52
8-25 HTXBDCNTA, HTXBDCNTB, and HTXBDCNTC Register......................................8-53
8-26 HRXBDCNTA, HRXBDCNTB, and HRXBDCNTC Register.....................................8-53
8-27 HTXBDMAXCNTA, HTXBDMAXCNTB, and HTXBDMAXCNTC Register ...............8-54
8-28 HRXBDMAXCNTA, HRXBDMAXCNTB, and HRXBDMAXCNTC Register ..............8-54
S3C2500B RISC MICROCONTROLLER xxix
List of Tables (Continued)
Table Title Page Number Number
9-1 HDLC External Pin Multiplexed Signals................................................................. 9-10
9-2 IOM2 Special Registers......................................................................................... 9-11
9-3 IOM2CON Register (Control Register)................................................................... 9-12
9-4 IOM2STAT Register (Status Register)................................................................... 9-14
9-5 IOM2INTEN Register (Interrupt Enable Register)................................................... 9-16
9-6 IOM2TBA Register (TIC Bus Address Register)..................................................... 9-18
9-7 IOM2ICTD (IOM2 IC Channel Transmit Data Register).......................................... 9-19
9-8 IOM2ICRD (IOM2 IC Channel Receive Data Register) .......................................... 9-19
9-9 IOM2CITD0 (IOM2 C/I0 Channel Transmit Data Register)..................................... 9-20
9-10 IOM2CIRD0 (IOM2 C/I0 Channel Receive Data Register) ..................................... 9-20
9-11 IOM2CITD1 (IOM2 C/I1 Channel Transmit Data Register)..................................... 9-21
9-12 IOM2CIRD1 (IOM2 C/I1 Channel Receive Data Register) ..................................... 9-21
9-13 IOM2MTD (IOM2 Monitor Channel Transmit Data Register).................................. 9-22
9-14 IOM2MRD (IOM2 Monitor Channel Receive Data Register)................................... 9-22
9-15 TSAACON (TSA A Control Register)..................................................................... 9-23
9-16 TSABCON (TSA B Control Register)..................................................................... 9-24
9-17 TSACCON (TSA C Control Register) ..................................................................... 9-25
9-18 IOM2STRB (Strobe Register) ................................................................................ 9-26
10-1 USB Registers....................................................................................................... 10-9
10-2 USBFA Register.................................................................................................... 10-10
10-3 USBFA Register Description.................................................................................. 10-10
10-4 USBPM Register ................................................................................................... 10-12
10-5 USBPM Register Description................................................................................. 10-12
10-6 USBINTR Register ................................................................................................ 10-14
10-7 USBINTR Register Description.............................................................................. 10-15
10-8 USBINTRE Register.............................................................................................. 10-17
10-9 USBINTRE Register Description............................................................................ 10-17
10-10 USBFN Register.................................................................................................... 10-19
10-11 USBFN Register Descriptions................................................................................ 10-19
10-12 CNTVLE Table...................................................................................................... 10-20
10-13 USBDISCONN Register......................................................................................... 10-20
10-14 USBDISCONN Register Description...................................................................... 10-20
10-15 USBEP0CSR Register........................................................................................... 10-22
10-16 USBEP0CSR Register Description ........................................................................ 10-22
10-17 USBEP1CSR Register........................................................................................... 10-25
10-18 USBEP1CSR Register Description ........................................................................ 10-25
10-19 USBEP2CSR Register........................................................................................... 10-30
10-20 USBEP2CSR Register Description ........................................................................ 10-30
xxxxxx S3C2500B RISC MICROCONTROLLER
List of Tables (Continued)
Table Title Page Number Number
10-21 USBEP3CSR Register............................................................................................10-35
10-22 USBEP3CSR Register Description.........................................................................10-35
10-23 USBEP4CSR Register............................................................................................10-40
10-24 USBEP4CSR Register Description.........................................................................10-40
10-25 USBWCEP0 Register.............................................................................................10-45
10-26 USBWCEP0 Register Description ..........................................................................10-45
10-27 USBWCEP1 Register.............................................................................................10-47
10-28 USBWCEP1 Register Description ..........................................................................10-47
10-29 USBWCEP2 Register.............................................................................................10-49
10-30 USBWCEP2 Register Description ..........................................................................10-49
10-31 USBWCEP3 Register.............................................................................................10-51
10-32 USBWCEP3 Register Description ..........................................................................10-51
10-33 USBWCEP4 Register.............................................................................................10-53
10-34 USBWCEP4 Register Description ..........................................................................10-53
10-35 USBEP0, 1, 2, 3, 4, 5 Descriptions.........................................................................10-55
11-1 DES/3DES Special Registers Overview ................................................................. 11-3
11-2 DES/3DES Control Register Description................................................................. 11-4
11-3 DES/3DES Status Register Description..................................................................11-5
11-4 DES/3DES Interrupt Enable Register Description...................................................11-6
11-5 DES/3DES Run Enable Register Description ..........................................................11-6
11-6 DES/3DES Key1 Left Side Register Description.....................................................11-6
11-7 DES/3DES Key 1 Right Side Register Description..................................................11-6
11-8 DES/3DES Key 2 Left Side Register Description....................................................11-7
11-9 DES/3DES Key 2 Right Side Register Description..................................................11-7
11-10 DES/3DES Key 3 Left Side Register Description....................................................11-7
11-11 DES/3DES Key 3 Right Side Register Description..................................................11-7
11-12 DES/3DES IV Left Side Register Description.......................................................... 11-7
11-13 DES/3DES IV Right Side Register Description .......................................................11-7
11-14 DES/3DES Input Data FIFO Description................................................................. 11-8
11-15 DES/3DES Output Data FIFO Description..............................................................11-8
12-1 GDMA Special Registers Overview........................................................................12-3
12-2 GDMA Programmable Priority Registers ................................................................12-4
12-3 DCON0/1/2/3/4/5 Registers....................................................................................12-9
12-4 GDMA Control Register Description .......................................................................12-9
12-5 DSAR0/1/2/3/4/5 and DDAR0/1/2/3/4/5 Registers................................................... 12-12
12-6 DTCR0/1/2/3/4/5 Registers .....................................................................................12-13
12-7 DRER0/1/2/3/4/5 Registers.....................................................................................12-14
12-8 DIPR0/1/2/3 Registers............................................................................................12-15
S3C2500B RISC MICROCONTROLLER xxxi
List of Tables (Continued)
Table Title Page Number Number
13-1 Console UART Special Registers Overview........................................................... 13-3
13-2 CUCON Registers ................................................................................................. 13-4
13-3 Console UART Control Register Description.......................................................... 13-4
13-4 CUSTAT Registers................................................................................................ 13-8
13-5 Console UART Status Register Description ........................................................... 13-8
13-6 CUINT Registers ................................................................................................... 13-11
13-7 Console UART Interrupt Enable Register Description ............................................ 13-11
13-8 CUTXBUF Registers.............................................................................................. 13-13
13-9 Console UART Transmit Register Description........................................................ 13-13
13-10 CURXBUF Registers ............................................................................................. 13-14
13-11 Console UART Receive Register Description ........................................................ 13-14
13-12 CUBRD Registers .................................................................................................. 13-15
13-13 Typical Baud Rates Examples of Console UART................................................... 13-16
13-14 CUCHAR 1, 2 Registers ........................................................................................ 13-17
14-1 High-Speed UART 0 Special Registers Overview.................................................. 14-3
14-2 High-Speed UART 1 Special Registers Overview.................................................. 14-3
14-3 High-Speed UART Control Registers.................................................................... 14-4
14-4 High-Speed UART Control Register Description .................................................... 14-4
14-5 High-Speed UART Status Registers ...................................................................... 14-9
14-6 High-Speed UART Status Register Description...................................................... 14-9
14-7 HUCON Interrupt Enable Registers........................................................................ 14-14
14-8 High-Speed UART Interrupt Enable Register Description....................................... 14-14
14-9 HUTXBUF Registers.............................................................................................. 14-16
14-10 High-Speed UART Transmit Register Description.................................................. 14-16
14-11 HURXBUF Registers ............................................................................................. 14-17
14-12 High-Speed UART Receive Register Description ................................................... 14-17
14-13 HUBRD0 and HUBRD0 Registers.......................................................................... 14-18
14-14 Typical Baud Rates Examples of High-Speed UART............................................. 14-19
14-15 HUCHAR1 Registers ............................................................................................. 14-20
14-16 HUCHAR2 Registers ............................................................................................. 14-21
14-17 HUABB Registers.................................................................................................. 14-22
14-18 HUABT Registers .................................................................................................. 14-23
xxxiixxxii S3C2500B RISC MICROCONTROLLER
List of Tables (Concluded)
Table Title Page Number Number
15-1 I/O Port Special Registers ......................................................................................15-2
15-2 IOPMODE1/2 Registers..........................................................................................15-3
15-3 IOPCON1/2 Register..............................................................................................15-5
15-4 IOPGDMA Register................................................................................................15-8
15-5 IOPEXTINT Register..............................................................................................15-9
15-6 IOPEXTINTPND Register .......................................................................................15-11
15-7 IOPDATA1/2 Register ............................................................................................ 15-12
15-8 IOPDRV1/2 Register .............................................................................................. 15-12
16-1 S3C2500B Internal Interrupt Sources .....................................................................16-2
16-2 S3C2500B External Interrupt Sources....................................................................16-3
16-3 INTMOD, EXTMOD Register..................................................................................16-3
16-4 INTMASK, EXTMASK Register .............................................................................. 16-5
16-5 Interrupt Priority Register........................................................................................16-8
16-6 INTOFFSET_FIQ, INTOFFSET_IRQ Register .......................................................16-9
16-7 Index Value of Interrupt Sources ............................................................................ 16-10
16-8 IPRIORHI, IPRIORLO Register ..............................................................................16-12
16-9 INTTSTHI, INTTSTLO Register ..............................................................................16-12
17-1 TMOD Register ......................................................................................................17-4
17-2 TDATA0 - TDATA5 Registers.................................................................................17-6
17-3 TCNT0 - TCNT5 Registers .....................................................................................17-7
17-4 Timer Interrupt Clear Registers...............................................................................17-8
17-5 WDT Register ........................................................................................................17-9
17-6 Watchdog Timer Timeout Value.............................................................................17-10
18-1 Absolute Maximum Ratings....................................................................................18-1
18-2 Recommended Operating Conditions.....................................................................18-1
18-3 D.C Electric Characteristics....................................................................................18-2
18-4 Operating Frequency ..............................................................................................18-4
18-5 Clock AC timing specification.................................................................................18-4
18-6 AC Electrical Characteristics for S3C2500B ...........................................................18-5
S3C2500B RISC MICROCONTROLLER xxxiii
S3C2500B PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
1.1 OVERVIEW
Samsung's S3C2500B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems, for example, SOHO router, internet gateway, WLAN AP, etc. A variety of communication features is embedded into S3C2500B required in many communication areas, including two Ethernet MACs, three HDLCs and three TSAs supporting IOM2, two high speed UARTs, a console UART, and USB. A security feature is also supported by DES/3DES accelerator. This highly integrated microcontroller enables customers to save system costs and increase performance over other 32-bit microcontroller.
The S3C2500B is built based on an outstanding CPU core: The ARM940T cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-on-a-chip processor solutions. It provides a complete high performance CPU subsystem, including ARM9TDMI RISC integer CPU, 4KB instruction/data caches, write buffer, and protection unit, with an AMBA bus interface. The ARM9TDMI core within the ARM940T executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. It is binary compatible with ARM7TDMI, ARM10TDMI, and Strong ARM processors, and is supported by a wide range of tools, operating systems, and application software.
The following integrated on-chip functions are described in detail in this user's manual :
• ARM940T cached processor
• Ethernet Controller
• HDLC Controller
• GDMA Controller
• UART Controller
• I2C Controller
• USB Controller
• IOM2 Controller
• Programmable I/O ports
• Interrupt Controller
1-1
PRODUCT OVERVIEW S3C2500B
1.2 FEATURES
ARM940T Core processor
• Fully 16/32-bit RISC architecture.
• Harvard cache architecture with separate 4KB
Instruction and Data cache
• Protection unit to partition memory and set individual protection attributes for each partition
• AMBA Bus architecture
• Up to 166MHz operating frequency
Memory Controller
• 24-Bit External Address Pins
• 2 Banks for SDRAM with 16/32-bit external bus.
• 8 Banks for Flash/ROM/SRAM/External I/O with
8/16/32-bit external bus.
• One External Bus Master with Bus Request/Acknowledge Pins
Ethernet Controllers
• Buffered DMA (BDMA) engine using burst mode
• BDMA Tx/Rx buffers (256-byte/256-byte)
• MAC Tx/Rx FIFOs (80-byte/16-byte) to support
re-transmit after collision without DMA request
• Data alignment logic
• Support for old and new media (compatible with
existing 10M-bit/s networks)
On-chip CAM (21 addresses)
• Full-duplex mode for doubled bandwidth
• Pause operation hardware support for full-
duplex flow control
• Long packet mode for specialized environments
• Short packet mode for fast testing
• PAD generation for ease of processing and
reduced processing time
HDLC Controllers and Three TSAs
• Four address station registers and one mask register for address search mode
• Selectable CRC/No-CRC mode
• Automatic CRC generator pre-set
• Digital PLL block for clock recovery
• Baud rate generator
• NRZ/NRZI/FM/Manchester data formats for
Tx/Rx
• Loop-back and auto-echo mode
• Tx and Rx FIFOs with 8-word (8 × 32-bit) depth
• Data alignment logic
• Hardware flow control
• • Embedded DMA Controller with Buffer
Descriptor for Tx/Rx channel
• 10/100 Mbps operation to increase price/performance options and to support phased conversions
• Full IEEE 802.3 compatibility for existing applications
• Media Independent interface (MII) or 7-wire interface
• Station management (STA) signaling for external physical layer configuration and link negotiation
1-2
Universal Serial Bus (USB)
• USB specification 1.1 compliant
• Full speed 12 Mbps operation with internal
transceiver only
• A total of 5 endpoints: 1 control endpoint and 4 data endpoints that can support control, interrupt, bulk transaction.
• Two data endpoints have 32-byte FIFO, two data endpoints have 64-byte FIFO.
• General DMA support
S3C2500B PRODUCT OVERVIEW
1.2 FEATURES (Continue)
IOM2 Controller
• IOM2 terminal mode support
• Inter-device communication via IC channel
• TIC bus access control
• Monitor channel collision control
• Optional signals such as BCL and STRB
• Bus Deactivation/Activation via C/I0
• Bus Reversal
Universal Asynchronous Receiver Transmitter (UART)
• Programmable baud rates
• 32-byte Transmit FIFO and 32-byte Receive
FIFO
• UART source clock selectable (Internal clock : PCLK2, External clock: EXT_UCLK)
• Auto baud rate detection
• Infra-red (IR) transmit/receive
• Insertion of one or two Stop bits per frame
• Selectable 5-bit, 6-bit, 7-bit, or 8-bit data
transfers
General DMA Channels
• Six GDMA channels
• Memory to memory data transfer
• Memory to peripheral data transfer (high-speed
UART, DES, and USB controller)
• Support for four external GDMA requests from GDMA request pins (xGDMA_Req0 - xGDMA_Req3).
Six Programmable Timers
• Interval or toggle mode operation
Hardware Watchdog Timer
• Useful for periodic reset or interrupts
Programmable Interrupt Controller
• 39 programmable interrupt sources
• 33 internal sources and 6 external sources
• programmable priority control
Programmable I/O port Controller
• 64 programmable I/O ports
• Parity checking
DES/3DES Accelerator
• DES or Triple DES mode
• ECB or CBC mode
• Encryption or decryption support
• General DMA support
• Individually configurable to input, output, or I/O
mode for dedicated signals
• 6 external interrupt request
• 4 external GDMA request
• 4 external GDMA acknowledge
• 6 timer outputs
• 14 UART signals
• 22 HDLC signals
1-3
PRODUCT OVERVIEW S3C2500B
1.2 FEATURES (Continue)
I2C Controller
• Master mode operation only
• Baud rate generator for serial clock
Four PLLs for System, Core, USB and PHY Clock Each
PLL0 for ARM940T
• The Input frequency is 10MHz.
• Provide up to 166MHz output to ARM940T
PLL1 for system clock
• The Input frequency is 10MHz.
• • Provide up to 133MHz output to system
PLL2 for USB
• The input frequency is 10MHz
• Provide 48MHz output to USB
PLL3 for PHY
• The input frequency is 10MHz
• Provide 20MHz or 25MHz output to external
PHY chip
Operating Voltage Range
• Internal Power: 1.8V ± 5%
• I/O Power: 3.3V ± 5%
Operating temperature range
• -40 °C – 85 °C
Package Type
• 272 BGA
1-4
S3C2500B PRODUCT OVERVIEW
1.3 BLOCK DIAGRAM
2-bank
SDRAM
8-bank
Flash/ROM/
SRAM/Ext
I/O
TSA/
IOM-2
10/100
Ethernet
MAC
10/100
Ethernet
MAC
HDLC
A
HDLC
B
HDLC
C
Controller
Memory
DMA
DMA
DMA
DMA
DMA
133 MHz AHB BUS
A H B
I/F
APB
Bridge
Sys. Bus
Arbiter
Six
GDMA
4KB
D-Cache
ARM940T (166 MHz)
4KB
D-Cache
Interrupt
Controller
DES/
3DES
WDT
Six
Timers
133 MHz APB BUS
High Speed UART
High Speed UART
Console
UART
I2C
GPIOs
USB 1.1
Function
External
Bus Master
REQ/ACK
Clock Gen.
&
Reset Drv. with 4
PLLs
10 MHz
OSC.
20 MHz or
Figure 1-1. S3C2500B Block Diagram
1-5
25 MHz
PRODUCT OVERVIEW S3C2500B
1.4 PACKAGE DIAGRAM
TOP View
A1 ball pad corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ABCDEFGHJKLMNPRTUVWY
1-6
Figure 1-2. S3C2500B Pin Assignment Diagram
S3C2500B PRODUCT OVERVIEW
1.5 PIN ASSIGNMENT
Pin # Pin Name Direction Pin # Pin Name Direction
A1 GND B11 ADDR17 O A2 PHY_FREQ I B12 ADDR15 O A3 HnRTS2/GPIO59 I/O B13 ADDR11 O A4 HTXD2/GPIO56 I/O B14 ADDR8 O A5 HnCTS1/GPIO52 I/O B15 ADDR5 O A6 HRXD1/GPIO49 I/O B16 ADDR1 O A7 HTXC0/FSC/GPIO47 I/O B17 XDATA27 I/O A8 HnCTS0/GPIO44 I/O B18 XDATA26 I/O
A9 HTXD0/DU I/O B19 XDATA23 I/O A10 ADDR20 O B20 XDATA21 I/O A11 ADDR19 O C1 TXD0_0/TXD_10M O A12 ADDR16 O C2 MDC_0 O A13 ADDR12 O C3 PHY_CLKO O A14 ADDR9 O C4 HnDCD2/GPIO61 I/O A15 ADDR6 O C5 HRXD2/GPIO57 I/O A16 ADDR2 O C6 HRXC1/GPIO54 I/O A17 XDATA31 I/O C7 HnDTR1/GPIO50 I/O A18 XDATA30 I/O C8 HRXC0/DCL/GPIO46 I/O A19 XDATA25 I/O C9 HnDTR0/BCL/GPIO42 I/O A20 XDATA24 I/O C10 ADDR22 O
B1 PHY_CLKSEL I C11 ADDR18 O
B2 HTXC2/GPIO63 I/O C12 ADDR14 O
B3 HRXC2/GPIO62 I/O C13 ADDR10/AP O
B4 HnDTR2/GPIO58 I/O C14 ADDR7 O
B5 HTXC1/GPIO55 I/O C15 ADDR3 O
B6 HnRTS1/GPIO51 I/O C16 ADDR0 O
B7 HTXD1/GPIO48 I/O C17 XDATA28 I/O
B8 HnDCD0/GPIO45 I/O C18 XDATA22 I/O
B9 HRXD0/DD I/O C19 XDATA20 I/O B10 ADDR21 O C20 XDATA17 I/O
1-7
PRODUCT OVERVIEW S3C2500B
1.5 PIN ASSIGNMENT (Continue)
Pin # Pin Name Direction Pin # Pin Name Direction
D1 TXD0_1/LOOP10M O E19 XDATA13 I/O D2 MDIO_0 I/O E20 XDATA10 I/O D3 COL_0 I F1 RXD0_0/RXD_10M I D4 GND F2 RX_CLK_0 I D5 HnCTS2/GPIO60 I/O F3 TX_ERR_0/PCOMP_10M O D6 VDD1.8 F4 VDD1.8 D7 HnDCD1/GPIO53 I/O F17 VDD3.3 D8 GND F18 XDATA12 I/O
D9 HnRTS0/STRB/GPIO43 I/O F19 XDATA9 I/O D10 ADDR23/ALE O F20 XDATA7 I/O D11 VDD1.8 G1 RXD0_2 I D12 ADDR13 O G2 RXD0_1 I
D!3 GND G3 VDD3.3 D14 ADDR4 O G4 CRS_0 I D15 VDD1.8 G17 XDATA11 I/O D16 XDATA29 I/O G18 XDATA8 I/O D17 GND G19 XDATA6 I/O D18 XDATA19 I/O G20 XDATA5 I/O D19 XDATA16 I/O H1 RX_ERR_0 I D20 XDATA14 I/O H2 RX_DV_0/LINK_10M I
E1 TX_EN_0 O H3 RXD0_3 I E2 TXD0_3 O H4 GND E3 TXD0_2 O H17 GND
E4 TX_CLK_0 I H18 XDATA4 I/O E17 XDATA18 I/O H19 XDATA3 I/O E18 XDATA15 I/O H20 XDATA2 I/O
1-8
S3C2500B PRODUCT OVERVIEW
1.5 PIN ASSIGNMENT (Continued)
Pin # Pin Name Direction Pin # Pin Name Direction
J1 VDD1.8_A L1 VDD1.8_A J2 USB_CLKSEL I L2 VDD1.8 J3 USB_D- B L3 CPU_FILTER O J4 USB_D+ B L4 GND
J9 GND L9 GND J10 GND L10 GND J11 GND L11 GND J12 GND L12 GND J17 XDATA1 I/O L17 VDD3.3 J18 XDATA0 I/O L18 nWBE1/nBE1/DQM1 O J19 nSDCAS O L19 nWBE0/nBE0/DQM0 O J20 nSDRAS O L20 nWBE2/nBE2/DQM2 O
K1 GND M1 VDD1.8_A K2 VDD1.8 M2 VDD1.8 K3 BUS_FILTER O M3 PHY_FILTER O K4 VDD1.8 M4 GND
K9 GND M9 GND K10 GND M10 GND K11 GND M11 GND K12 GND M12 GND K17 nSDCS1 O M17 nRCS5 O K18 nSDCS0 O M18 nRCS6 O K19 nSDWE/nWE16 O M19 nRCS7 O K20 nWBE3/nBE3/DQM3 O M20 nOE O
1-9
PRODUCT OVERVIEW S3C2500B
1.5 PIN ASSIGNMENT (Continued)
Pin # Pin Name Direction Pin # Pin Name Direction
N1 VDD1.8_A T3 TX_ERR_1/PCOMP_10M O N2 VDD1.8 T4 RXD1_0/RXD_10M I N3 USB_FILTER O T17 BUS_FREQ2 I
N4 GND T18 CPU_FREQ2 I N17 GND T19 XBMREQ I N18 nRCS2 O T20 XBMACK O N19 nRCS3 O U1 TX_EN_1 O N20 nRCS4 O U2 CRS_1 I
P1 GND U3 RXD1_1 I
P2 MDC_1 O U4 GND
P3 COL_1 I U5 USB_XCLK I
P4 TXD1_1/LOOP_10M O U6 VDD3.3 P17 B0SIZE1 I U7 HURXD1/GPIO35 I/O P18 CKE O U8 GND P19 nRCS0 O U9 GPIO0 I/O P20 nRCS1 O U10 VDD3.3
R1 MDIO_1 I/O U11 xINT2/GPIO10 I/O
R2 TX_CLK_1 I U12 xGDMA_Req0/GPIO14 I/O
R3 TXD1_2 O U13 GND
R4 VDD1.8 U14 TIMER2/GPIO24 I/O R17 VDD3.3 U15 VDD3.3 R18 B0SIZE0 I U16 TMODE I R19 nEWAIT I U17 GND R20 BIG I U18 BUS_FREQ1 I
T1 TXD1_0/TXD_10M O U19 BUS_FREQ0 I T2 TXD1_3 O U20 CPU_FREQ1 I
1-10
S3C2500B PRODUCT OVERVIEW
1.5 PIN ASSIGNMENT (Continued)
Pin # Pin Name Direction Pin # Pin Name Direction
V1 RX_CLK_1 I W1 RXD1_3 I V2 RXD1_2 I W2 RX_ERR_1 I V3 RX_DV_1/LINK10M I W3 CUTXD O V4 HUTXD0/ GPIO29 I/O W4 HURXD0/GPIO28 I/O V5 UCLK I W5 HUnRTS0/GPIO32 I/O V6 HUnDCD0/GPIO34 I/O W6 XCLK I V7 HUnDTR1/GPIO37 I/O W7 HUnDSR1/GPIO38 I/O V8 HUnCTS1/GPIO40 I/O W8 HUnDCD1/GPIO41 I/O
V9 GPIO1 I/O W9 GPIO2 I/O V10 GPIO5 I/O W10 GPIO4 I/O V11 xINT1/GPIO9 I/O W11 xINT0/GPIO8 I/O V12 xINT5/GPIO13 I/O W12 xINT4/GPIO12 I/O V13 xGDMA_Req3/GPIO17 I/O W13 xGDMA_Req2/GPIO16 I/O V14 xGDMA_Ack3/GPIO21 I/O W14 xGDMA_Ack1/GPIO19 I/O V15 TIMER3/GPIO25 I/O W15 TIMER0/GPIO22 I/O V16 TIMER5/GPIO27 I/O W16 TIMER4/GPIO26 I/O V17 nRESET I W17 SCL I/O V18 TDI I W18 TCK I V19 CLKMOD1 I W19 TDO O V20 CPU_FREQ0 I W20 CLKMOD0 I
1-11
PRODUCT OVERVIEW S3C2500B
1.5 PIN ASSIGNMENT (Continued)
Pin # Pin Name Direction Pin # Pin Name Direction
Y1 CURXD I Y11 GPIO7 I/O Y2 CLKSEL I Y12 xINT3/GPIO11 I/O Y3 HUnDTR0/GPIO30 I/O Y13 xGDMA_Req1/GPIO15 I/O Y4 HUnDSR0/GPIO31 I/O Y14 xGDMA_Ack0/GPIO18 I/O Y5 HUnCTS0/GPIO33 I/O Y15 xGDMA_Ack2/GPIO20 I/O Y6 HUTXD1/GPIO36 I/O Y16 TIMER1/GPIO23 I/O Y7 HUnRTS1/GPIO39 I/O Y17 GND Y8 HCLKO O Y18 SDA I/O Y9 GPIO3 I/O Y19 TMS I
Y10 GPIO6 I/O Y20 nTRST I
1-12
S3C2500B PRODUCT OVERVIEW
1.6 SIGNAL DESCRIPTION
Table 1-1. S3C2500B Signal Descriptions
Group Pin Name Pin Type Pad Type Description
System
Config
(20)
XCLK 1 I Phic S3C2500B PLL Clock Source. If CLKSEL is
Low, PLL output clock is used as the system clock. If CLKSEL is high, XCLK is used as the system clock.
HCLKO 1 O phbst24 System clock output. The internal system
clock is monitored via HCLKO. If SDRAM is used, this clock should be used SDRAM clock.
CLKSEL 1 I Phic Clock Select for CPU PLL and system PLL.
If CLKSEL is low, CPU PLL clock is used as ARM940T source clock and system PLL clock is used system clock source, depending on CLKMOD[1:0]. If CLKSEL is high, XCLK is used both clock sources. See Figure 4-5.
BUS_FILTER 1 I poar50_abb PLL filter pin for System PLL.
If the PLL is used, 320pF capacitor should be connected between the pin and ground.
PHY_FREQ 1 I Phic PHY clock frequency select for PHY PLL.
0 = 20MHz, 1 = 25MHz
PHY_CLKSEL 1 I Phic Clock Select for PHY PLL
If this pin is set to low, the PHY PLL generates clock depending on PHY_FREQ state. The PHY PLL goes into power down mode with PHY_CLKSEL set to high. See Figure 4-5.
PHY_FILTER 1 O poar50_abb PLL filter pin for PHY PLL.
If the PLL is used, 320pF capacitor should be connected between the pin and ground.
PHY_CLKO 1 O phob8 PHY clock Out
PHY PLL clock output can be monitored by PHY_CLKO. This clock is used as the external phy source clock. However, some switches may cause a link failure when S3C2500’s PHY source clock, PHY_CLKO, is used.
CPU_FILTER 1 O poar50_abb PLL filter pin for System PLL.
If the PLL is used, 320pF capacitor should be connected between the pin and ground.
1-13
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
System
Config
(20)
CLKMOD [1:0] 2 I Phic The CLKMOD pin determines internal clock
scheme of S3C2500B. When CLKMOD is “00”, the nfast clock mode is defined. In this mode, the same clock is used as CPU clock and system clock. When CLKMOD is "11", the async clock mode is defined. In this mode, the CPU clock and system clock can operate independently as long as the CPU clock is
faster than system clock. CPU_FREQ [2:0] 3 I phic CPU Clock Frequency Selection. BUS_FREQ [2:0] 3 I phic System Bus Clock Frequency Selection.
nRESET 1 I phis Not Reset. NRESET is the global reset input
for the S3C2500B and nRESET must be held
to "low" for at least 64 clock cycles for digital
filtering.
TMODE 1 I phicd Test Mode. The TMODE pin setting is
interpreted as follows:
0 = normal operating mode
1 = chip test mode.
BIG 1 I phicd BIG endian mode select pin
When this pin state is “0”, the S3C2500B
operates in litte endian mode. When this pin
state is “1”, the S3C2500B operates in big
endian mode.
1-14
S3C2500B PRODUCT OVERVIEW
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Memory
Interface
(80)
ADDR[23:0]
ADDR[10]/AP
24 O Phot20 Address bus.
The 24-bit address bus covers the full 16 M word address range of each ROM/SRAM /FLASH and external I/O bank. In the SDRAM interface, ADDR[14:13] is always used as bank address of SDRAM devices. If SDRAM devices with 2 internal bank is used, ADDR[13] should be connected to the BA of SDRAM. If SDRAM devices with 4 internal bank is used, ADDR[14:13] should be connected to the BA[1:0] of SDRAM. ADDR[10]/AP is the auto precharge control pin. The auto precharge command is issued at the same time as burst read or burst write by asserting high on ADDR[10]/AP.
XDATA[31:0] 32 I/O phbsut20 External bi-directional 32bit data bus.
The S3C2500B supports 8 bit, 16bit, 32bit bus with ROM/SRAM/Flash/Ext IO bank, but supports 16 bit or 32 bit bus with SDRAM bank.
nSDCS[1:0] 2 O phot20 Not chip select strobe for SDRAM.
Two SDRAM banks are supported.
nSDRAS 1 O phot20 Not row address strobe for SDRAM.
NSDRAS signal is used for both SDRAM banks.
nSDCAS 1 O phot20 Not column address strobe for SDRAM.
NSDCAS signal is used for both SDRAM banks.
CKE 1 O phob12 Clock Enable for SDRAM
CKE is clock enable signal for SDRAM.
nSDWE/nWE16 1 O phot20 Not Write Enable for SDRAM or 16 bit
ROM/SRAM. This signal is always used as write enable of SDRAM and is used as write enable of only 16-bit ROM/SRAM/Flash. (That is, It is not enabled for 8 bit Memory)
1-15
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Memory
Interface
(80)
nEWAIT 1 I phicu Not External wait signal.
This signal is activated when an external I/O device or ROM/SRAM/Flash banks need more access cycles than those defined in the corresponding control register.
nRCS[7:0] 8 O phot20 Not ROM/SRAM/Flash/ External I/O Chip
select. The S3C2500B supports upt to 8 banks of ROM/SRAM/Flash/ External I/O. By controlling the nRCS signals, you can map CPU address into the physical memory banks.
B0SIZE[1:0] 2 I phic Bank 0 Data Bus Access Size.
Bank0 is used for the boot program. You use these pins to set the size of the bank 0 data bus as follows: “01” = Byte, “10” = Half word, “11” = Word, and “00” = reserved.
nOE 1 O phot20 Not output enable.
Whenever a memory read access occurs, the nOE output controls the output enable port of the specific memory device.
nWBE[3:0]/
nBE[3:0]/
DQM[3:0]
4 O phot20 Not write byte enable or DQM for SDRAM
Whenever a memory write access occurs, the nWBE output controls the write enable port of the specific memory device. DQM is data input/output mask signal for SDRAM.
1-16
S3C2500B PRODUCT OVERVIEW
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Memory
Interface
(80)
XBMREQ 1 I phicd External Master bus request.
An external bus master uses this pin to request the external bus. When it activates the XBMREQ, the S3C2500B drives the state of external bus pins to high impedance. This lets the external bus master take control of the external bus. When it has control, the external bus master assumes responsibity for SDRAM refresh operation. The XBMREQ is deactivated when the external bus master releases the external bus. When this occurs, the S3C2500B can get the control of the bus and the XBMACK goes “low”.
XBMACK 1 O phob8 External bus Acknowledge.
TAP
Control
(5)
TCK 1 I phic JTAG Test Clock.
The JTAG test clock shifts state information and test data into, and out of, the S3C2500B during JTAG test operations.
TMS 1 I phicu JTAG Test Mode Select.
This pin controls JTAG test operations in the S3C2500B. This pin is internally connected pull-up.
TDI 1 I phicu JTAG Test Data In.
The TDI level is used to serially shift test data and instructions into the S3C2500B during JTAG test operations. This pin is internally connected pull-up.
TDO 1 O phot12 JTAG Test Data Out.
The TDO level is used to serially shift test data and instructions out of the S3C2500B during JTAG test operations.
nTRST 1 I phicu JTAG Not Reset.
Asynchronous reset of the JTAG logic. This pin is internally connected pull-up.
1-17
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Ethernet
Controller0
(18)
MDC_0 1 O phob12 Management Data Clock.
The signal level at the MDC pin is used as a timing reference for data transfers that are controlled by the MDIO signal.
MDIO_0 1 I/O phbcut12 Management Data I/O.
When a read command is being executed, data that is clocked out of the PHY is presented on this pin. When a write command is being executed, data that is clocked out of the controller is presented on this pin for the Physical Layer Entity, PHY.
COL_0 1 I phis Collision Detected/Collision Detected for 10M.
COL is asserted asynchronously with minimum delay from the start of a collision on the medium in MII mode. COL_10M is asserted when a 10-Mbit/s PHY detects a collision.
TX_CLK_0 1 I phis Transmit Clock/Transmit Clock for 10M.
The controller drives TXD[3:0] and TX_EN from the rising edge of TX_CLK. In MII mode, the PHY samples TXD[3:0] and TX_EN on the rising edge of TX_CLK. For data transfers, TXCLK_10M is provided by the 10M-bit/s PHY.
TXD0[3:0]/ TXD_10M/
LOOP_10M
4 O phob12 Transmit Data/Transmit Data for 10M.
Transmit data is aligned on nibble boundaries. TXD[0] corresponds to the first bit to be transmitted on the physical medium, which is the LSB of the first byte and the fifth bit of that byte during the next clock. TXD_10M is shared with TXD[0] and is a data line for transmitting to the 10M-bit/s PHY. LOOP_10M is shared with TXD[1] and is driven by the loop-back bit in the control register.
1-18
S3C2500B PRODUCT OVERVIEW
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Ethernet
Controller0
(18)
TX_EN_0 1 O phob4 Transmit Enable/Transmit Enable for 10M.
TX_EN provides precise framing for the data carried on TXD[3:0]. This pin is active during the clock periods in which TXD[3:0] contains valid data to be transmitted from the preamble stage through CRC. When the controller is ready to transfer data, it asserts TXEN_10M.
TX_ERR_0/
PCOMP_10M
1 O phob4 Transmit Error/Packet Compression Enable
for 10M. TX_ERR is driven synchronously to TX_CLK and sampled continuously by the Physical Layer Entity, PHY. If asserted for one or more TX_CLK periods, TX_ERR causes the PHY to emit one or more symbols which are not part of the valid data, or delimiter set located somewhere in the frame that is being transmitted. PCOMP_10M is asserted immediately after the packet’s DA field is received. PCOMP_10M is used with the Management Bus of the DP83950 Repeater Interface Controller (from National Semiconductor). The MAC can be programmed to assert PCOMP if there is a CAM match, or if there is not a match. The RIC (Repeater Interface Controller) uses this signal to compress (shorten) the packet received for management purposes and to reduce memory usage. (See the DP83950 Data Sheet, published by National Semiconductor, for details on the RIC Management Bus.) This pin is controlled by a special register, with which you can define the polarity and assertion method (CAM match active or not match active) of the PCOMP signal.
1-19
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Ethernet
Controller0
(18)
CRS_0 1 I phis Carrier Sense/Carrier Sense for 10M.
CRS is asserted asynchronously with minimum delay from the detection of a non­idle medium in MII mode. CRS_10M is asserted when a 10-Mbit/s PHY has data to transfer. A 10-Mbit/s transmission also uses this signal.
RX_CLK_0 1 I phis Receive Clock/Receive Clock for 10M.
RX_CLK is a continuous clock signal. Its frequency is 25 MHz for 100-Mbit/s operation, and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV, and RX_ERR are driven by the PHY off the falling edge of RX_CLK, and sampled on the rising edge of RX_CLK. To receive data, the RXCLK_10 M clock comes from the 10Mbit/s PHY.
RXD0[3:0]/
RXD_10M
4 I phis Receive Data/Receive Data for 10M.
RXD is aligned on nibble boundaries. RXD[0] corresponds to the first bit received on the physical medium, which is the LSB of the byte in one clock period and the fifth bit of that byte in the next clock. RXD_10M is shared with RXD[0] and it is a line for receiving data from the 10-Mbit/s PHY.
RX_DV_0/ LINK_10M
1 I phis Receive Data Valid.
PHY asserts RX_DV synchronously, holding it active during the clock periods in which RXD[3:0] contains valid data received. PHY asserts RX_DV no later than the clock period when it places the first nibble of the start frame delimiter (SFD) on RXD[3:0]. If PHY asserts RX_DV prior to the first nibble of the SFD, then RXD[3:0] carries valid preamble symbols. LINK_10M is shared with RX_DV and used to convey the link status of the 10­Mbit/s endec. The value is stored in a status register.
1-20
S3C2500B PRODUCT OVERVIEW
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Ethernet
Controller0
(18)
RX_ERR_0 1 I phisd Receive Error.
PHY asserts RX_ERR synchronously whenever it detects a physical medium error (e.g., a coding violation). PHY asserts RX_ERR only when it asserts RX_DV.
Ethernet
Controller1
(18)
MDC_1 1 O phob12 Management Data Clock.
The signal level at the MDC pin is used as a timing reference for data transfers that are controlled by the MDIO signal.
MDIO_1 1 I/O phbcut12 Management Data I/O.
When a read command is being executed, data that is clocked out of the PHY is presented on this pin. When a write command is being executed, data that is clocked out of the controller is presented on this pin for the Physical Layer Entity, PHY.
COL_1 1 I phis Collision Detected/Collision Detected for 10M.
COL is asserted asynchronously with minimum delay from the start of a collision on the medium in MII mode. COL_10M is asserted when a 10-Mbit/s PHY detects a collision.
TX_CLK_1 1 I phis Transmit Clock/Transmit Clock for 10M.
The controller drives TXD[3:0] and TX_EN from the rising edge of TX_CLK. In MII mode, the PHY samples TXD[3:0] and TX_EN on the rising edge of TX_CLK. For data transfers, TXCLK_10M is provided by the 10M-bit/s PHY.
1-21
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Ethernet
Controller1
(18)
TXD1[3:0]/ TXD_10M/
LOOP_10M
4 O phob12 Transmit Data/Transmit Data for 10M.
Transmit data is aligned on nibble boundaries. TXD[0] corresponds to the first bit to be transmitted on the physical medium, which is the LSB of the first byte and the fifth bit of that byte during the next clock. TXD_10M is shared with TXD[0] and is a data line for transmitting to the 10-Mbit/s PHY. LOOP_10M is shared with TXD[1] and is driven by the loop-back bit in the control register.
TX_EN_1 1 O phob4 Transmit Enable/Transmit Enable for 10M.
TX_EN provides precise framing for the data carried on TXD[3:0]. This pin is active during the clock periods in which TXD[3:0] contains valid data to be transmitted from the preamble stage through CRC. When the controller is ready to transfer data, it asserts TXEN_10M.
1-22
S3C2500B PRODUCT OVERVIEW
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Ethernet
Controller1
(18)
TX_ERR_1/
PCOMP_10M
1 O phob4 Transmit Error/Packet Compression Enable
for 10M. TX_ERR is driven synchronously to TX_CLK and sampled continuously by the Physical Layer Entity, PHY. If asserted for one or more TX_CLK periods, TX_ERR causes the PHY to emit one or more symbols which are not part of the valid data, or delimiter set located somewhere in the frame that is being transmitted. PCOMP_10M is asserted immediately after the packet‘s DA field is received. PCOMP_10M is used with the Management Bus of the DP83950 Repeater Interface Controller (from National Semiconductor). The MAC can be programmed to assert PCOMP if there is a CAM match, or if there is not a match. The RIC (Repeater Interface Controller) uses this signal to compress (shorten) the packet received for management purposes and to reduce memory usage. (See the DP83950 Data Sheet, published by National Semiconductor, for details on the RIC Management Bus.) This pin is controlled by a special register, with which you can define the polarity and assertion method (CAM match active or not match active) of the PCOMP signal.
CRS_1 1 I phis Carrier Sense/Carrier Sense for 10M.
CRS is asserted asynchronously with minimum delay from the detection of a non­idle medium in MII mode. CRS_10M is asserted when a 10M-bit/s PHY has data to transfer. A 10M-bit/s transmission also uses this signal.
1-23
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
Ethernet
Controller1
(18)
RX_CLK_1 1 I phis Receive Clock/Receive Clock for 10M.
RX_CLK is a continuous clock signal. Its frequency is 25 MHz for 100-Mbit/s operation, and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV, and RX_ERR are driven by the PHY off the falling edge of RX_CLK, and sampled on the rising edge of RX_CLK. To receive data, the RXCLK_10 M clock comes from the 10M-bit/s PHY.
RXD1[3:0]/
RXD_10M
4 I phis Receive Data/Receive Data for 10M.
RXD is aligned on nibble boundaries. RXD[0] corresponds to the first bit received on the physical medium, which is the LSB of the byte in one clock period and the fifth bit of that byte in the next clock. RXD_10M is shared with RXD[0] and it is a line for receiving data from the 10M-bit/s PHY.
RX_DV_1
LINK_10M
1 I phis Receive Data Valid.
PHY asserts RX_DV synchronously, holding it active during the clock periods in which RXD[3:0] contains valid data received. PHY asserts RX_DV no later than the clock period when it places the first nibble of the start frame delimiter (SFD) on RXD[3:0]. If PHY asserts RX_DV prior to the first nibble of the SFD, then RXD[3:0] carries valid preamble symbols. LINK_10M is shared with RX_DV and used to convey the link status of the 10­Mbit/s endec. The value is stored in a status register.
RX_ERR_1 1 I phisd Receive Error.
PHY asserts RX_ERR synchronously whenever it detects a physical medium error (e.g., a coding violation). PHY asserts RX_ERR only when it asserts RX_DV.
1-24
S3C2500B PRODUCT OVERVIEW
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
HDLC0
(8)
HTXD0/DU 1 I/O phbsud4 IOM2 Data Upstream. Open Drain Output and
schmit trigger input. HDLC Ch-0 Transmit Data. The serial data output from the transmitter is encoded in NRZ/NRZI/ FM/Manchester data format.
HRXD0/DD 1 I/O phbsud4 IOM2 Data Down Stream. Open Drain Output
and schmit trigger input. HDLC Ch-0 Receive Data. The serial data input should be coded in NRZ/NRZI/FM/Manchester data form at. The data should not exceed the rate of the S3C2500B internal master clock.
HnDTR0/BCL/
GPIO42
1 I/O phbst8 IOM2 bit clock, 768 KHz.
HDLC Ch-0 Data Terminal Ready. NDTR0 output indicates that the data terminal device is ready for transmis sion and reception. General I/O Port.
HnRTS0/STRB/
GPIO43
1 I/O phbst8 IOM2 Data Strobe. 8 KHz programable signal
for selecting an 8-bit timeslot or 16 bit timeslot. HDLC Ch-0 Request To Send. The nRTS0 output is controlled by the Tx Request to send control bit. When the TxRTS bit is set to ‘1’ , the nRTS output is driven log. When the TxRTS bit is clear to ‘0’ , the nRTS output remains still low until 1) when the sending frame is reached to end, and 2) when there is no more data in the TxFIFO for sending a new frame. General I/O Port.
1-25
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
HDLC0
(8)
HnCTS0/
GPIO44
1 I/O phbst8 HDLC Ch-0 Clear To Send.
The S3C2500B stores each transition of nCTS to ensure that its occurrence will be acknowledged by the system. General I/O Port.
HnDCD0/
GPIO45
1 I/O phbst8 HDLC Ch-0 Data Carrier Detected.
A high level on this pin resets and inhibits the receiver operation. Data from a previous frame that may remain in the RxFIFO is retained. The pin state of transition is stored by the register. General I/O Port.
HRXC0/DCL/
GPIO46
1 I/O phbst8 IOM2 Data Clock.
HDLC Ch-0 Receiver Clock. When this clock input is used as the receiver clock, the receiver samples the data on the positive or negedge of HRXC0 clock. This can be determined by S/W selection. This clock can be the source clock of the receiver, the baud rate generator, or the DPLL. General I/O Port.
HTXC0/FSC/
GPIO47
1 I/O phbst8 IOM2 Frame Syncronization Clock.
HDLC Ch-0 Transmitter Clock. When this clock input is used as the transmitter clock, the transmitter shifts data on the positive or negative transition of the HTXC0 clock input. This can be determined by S/W selection. If you don’t use HTXC0 as the transmitter clock, you can use it as an output pin for monitoring internal clock such as the transmitter clock, receiver clock, and baud rate generator output clocks. General I/O Port.
1-26
S3C2500B PRODUCT OVERVIEW
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
HDLC1
(8)
HTXD1/GPIO48 1 I/O phbst16 HDLC Ch-1 Transmit Data.
See the HTXD0 description General I/O Port.
HRXD1/GPIO49 1 I/O phbst8 HDLC Ch-1 Receive Data.
See the HRXD0 description General I/O Port.
HnDTR1/GPIO50 1 I/O phbst16 HDLC Ch-1 Data Terminal Ready.
See the HnDTR0 description General I/O Port.
HnRTS1/GPIO51 1 I/O phbst16 HDLC Ch-1 Request To Send.
See the HnRTS0 description General I/O Port.
HnCTS1/GPIO52 1 I/O phbst8 HDLC Ch-1 Clear To Send.
See the HnCTS0 description General I/O Port.
HnDCD1/GPIO53 1 I/O phbst8 HDLC Ch-1 Data Carrier Detected.
See the HnDCD0 description General I/O Port.
HRXC1/GPIO54 1 I/O phbst8 HDLC Ch-1 Receiver Clock.
See the HRXC0 description General I/O Port.
HTXC1/GPIO55 1 I/O phbst8 HDLC Ch-1 Transmitter Clock.
See the HTXC0 description General I/O Port.
HDLC2
(8)
HTXD2/GPIO56 1 I/O phbst8 HDLC Ch-2 Transmit Data.
See the HTXD0 description General I/O Port.
HRXD2/GPIO57 1 I/O phbst8 HDLC Ch-2 Receive Data.
See the HRXD0 description General I/O Port.
HnDTR2/GPIO58 1 I/O phbst8 HDLC Ch-2 Data Terminal Ready.
See the HnDTR0 description General I/O Port.
HnRTS2/GPIO59 1 I/O phbst8 HDLC Ch-2 Request To Send.
See the HnRTS0 description General I/O Port.
HnCTS2/GPIO60 1 I/O phbst8 HDLC Ch-2 Clear To Send.
See the HnCTS0 description General I/O Port.
1-27
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
HDLC2
(8)
HnDCD2/
GPIO61
1 I/O phbst8 HDLC Ch-2 Data Carrier Detected.
See the HnDCD0 description General I/O Port
HRXC2/ GPIO62
1 I/O phbst8 HDLC Ch-2 Receiver Clock.
See the HRXC0 description General I/O Port
HTXC2/
GPIO63
1 I/O phbst8 HDLC Ch-2 Transmitter Clock.
See the HTXC0 description General I/O Port
USB USB_D+ 1 B pbusbfs Internal USB transceiver differential I/O
(5) USB_D- 1 B pbusbfs Internal USB transceiver differential I/O
USB_XCLK 1 I phic USB clock source input.
USB_CLKSEL 1 I phic USB Clock Select.
When USB_CLKSEL is ‘0’ , USB PLL output is used as the USB clock. When USB_CLKSEL is ‘1’ , the USB_XCLK is usedas the USB clock. See Figure 4-5.
USB_FILTER 1 O poar50_abb Filter for USB PLL
If the PLL is used, 320pF capacitor should be connected between the pin and ground.
CUART CURXD 1 I phis Console UART Receive Data.
(2) CUTXD 1 O phob8 Console UART Transmit Data.
HUART0 UCLK 1 I Phis HUART External Clock for HUART0/HUART1
(7) HURXD0/
GPIO28
1 I/O phbst8 HUART0 Receive Data.
HURXD0 is the HUART0 input signal for receiving serial data. General I/O Port
HUTXD0/
GPIO29
1 I/O phbst8 HUART0 Transmit Data.
HUTXD0 is the HUART0 output signal for transmitting serial data. General I/O Port
HUnDTR0/
GPIO30
1 I/O phbst8 Not HUART0 Data Terminal Ready..
This output signals the host (or peripheral) that HUART0 is ready to transmit or receive serial data. General I/O Port
1-28
S3C2500B PRODUCT OVERVIEW
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
HUART0
(7)
HUnDSR0/
GPIO31
1 I/O phbst8 Not HUART0 Data Set Ready.
This input signals in the HUART0 that the peripheral (or host) is ready to transmit or receive serial data General I/O Port
HUnRTS0/
GPIO32
1 I/O phbst8 Not request to send.
This pin output state goes Low or High according to the transmit data is in Tx buffer or Tx FIFO when hardware flow control bit value set to one in HUART0 control register. If Tx buffer or Tx FIFO has data to send, this pin state goes low. If hardware flow control bit is zero, this pin output can be controlled directly by HUART0 control register. General I/O Port
HUnCTS0/
GPIO33
1 I/O phbst8 Not Clear to send
This input pin function controlled by hardware flow control bit value in HUART0 control register. If hardware flow control bit set to one, HUART0 can transmit the transmitting data only when this pin state is active. General I/O Port
HUnDCD0/
GPIO34
1 I/O phbst8 Not Data Carrier Detect.
This input pin function is determined by hardware flow control bit value in HUART control register. If hardware flow control bit set to one, HUART0 can receive the receiving data only when this pin state is active. General I/O Port
HUART1
(7)
HURXD1/
GPIO35
1 I/O phbst8 HUART1 Receive Data.
See HURXD0 description General I/O Port
HUTXD1/
GPIO36
1 I/O phbst8 HUART1 Transmit Data.
See HUTXD0 description General I/O Port
1-29
PRODUCT OVERVIEW S3C2500B
Table 1-1. S3C2500B Signal Descriptions (Continue)
Group Pin Name Pin Type Pad Type Description
HUART1
(7)
HUnDTR1/
GPIO37
1 I/O phbst8 Not HUART1 Data Terminal Ready..
See HUnDTR0description General I/O Port
HUnDSR1/
GPIO38
1 I/O phbst8 Not HUART1 Data Set Ready.
See HUnDSR0 description General I/O Port
HUnRTS1/
GPIO39
1 I/O phbst8 Not Request to send
See HUnRTS0 description General I/O Port
HUnCTS1/
GPIO40
1 I/O phbst8 Not Clear to send
See HUnCTS0 description General I/O Port
HUnDCD1/
GPIO41
1 I/O phbst8 Not Data carrier detected
See HUnDCD0 description General I/O Port
GPIO
GPIO[7:0] 8 I/O phbst8 General I/O Ports
Included
xINT
xGDMA_
Req
xGDMA_
Ack
Timer
XINT[5:0]/
GPIO[13:8]
XGDMA_Req[3:0]/
GPIO[17:14]
XGDMA_Ack[3:0]/
GPIO[21:18]
6 I/O phbst8 External interrupt requests/General I/O
Ports
4 I/O phbst8 External DMA requests for GDMA/General
I/O Ports
4 I/O phbst8 External DMA acknowledge from
GDMA/General I/O Ports TIMER0/GPIO[22] 1 I/O phbst8 TIMER0 Out/General I/O Port TIMER1/GPIO[23] 1 I/O phbst8 TIMER1 Out/General I/O Port TIMER2/GPIO[24] 1 I/O phbst8 TIMER2 Out/General I/O Port TIMER3/GPIO[25] 1 I/O phbst8 TIMER3 Out/General I/O Port TIMER4/GPIO[26] 1 I/O phbst8 TIMER4 Out/General I/O Port TIMER5/GPIO[27] 1 I/O phbst8 TIMER5 Out/General I/O Port
I2C (2)
SCL 1 I/O phbcd8 I2C serial clock SDA 1 I/O phbcd8 I2C serial data
NOTE: Total Number of Signal Pins = 217
1-30
S3C2500B PRODUCT OVERVIEW
1.7 PAD TYPE
Table 1-2. S3C2500B Pad Type and Feature
PAD Type Type Current
Cell Type Feature Slew Rate
Drive
Phic I – LVCMOS Level 3.3V – Phicd I – LVCMOS Level 3.3V – Phicu I – LVCMOS Level 3.3V
Pull-up resistor
Phis I – LVCMOS Schmitt Trigger 3.3V – Phisd I – LVCMOS Schmitt Trigger 3.3V
Pull-down resister
Poar50_abb O – Analog output with seperate
bulk bias
phob4 O 4mA Normal Buffer
Phob12 O 12mA Normal Buffer
Phot12 O 12mA Tri-State Buffer – phot20 O 20mA Tri-State Buffer –
Phbcut12 I/O 12mA LVCMOS Level
Tri-State Buffer
phbsud4 I/O 4sm LVCMOS Schmit trigger level
Tri-State Buffer
phbst8 I/O 8mA LVCMOS Schmit trigger level
3.3V
Pull-up resistor
3.3
Pull-up resister
3.3V
Tri-State Buffer
phbst16 I/O 16mA LVCMOS Schmit trigger leve
3.3V
Tri-State Buffer
Phbst24 I/O 24mA LVCMOS Schmit trigger level
3.3V
Tri-State Buffer
Phbsut20 I/O 20mA LVCMOS Schmit trigger level
Tri-State Buffer
phbcd8 I/O 8mA LVCMOS Level
3.3V
Pull-up resistor
3.3V –
Open drain buffer
Pbusbfs I/O 6mA USB Buffer –
Control
–
–
–
–
NOTE: For the detail information about the pad type, “Input/Output Cells of the STD130/MDL130
0.18µm 3.3V Standard Cell Library Data Book” which is produced by Samsung Electronics Co., Ltd, ASIC Team.
1-31
PRODUCT OVERVIEW S3C2500B
1.8 SPECIAL REGISTERS
Table 1-3. S3C2500B System Configuration
Registers Address R/W Description Reset Value
SYSCFG 0xF0000000 R/W System configuration register – PDCODE 0xF0000004 R Product code and revision number register 0x25000000 CLKCON 0xF0000008 R/W System clock control register 0x00000000 PCLKDIS 0xF000000C R/W Peripheral clock disable register 0x00000000 CLKST 0xF0000010 R Clock Status register HPRIF 0xF0000014 R/W AHB bus master fixed priority register 0x00543210 HPRIR 0xF0000018 R/W AHB bus master round-robin priority register 0x00000000 CPLL 0xF000001C R/W Core PLL Configuration Register 0x0001039E SPLL 0xF0000020 R/W System BUS PLL Configuration Register 0x00010370 UPLL 0xF0000024 R/W USB PLL Configuration Register 0x00010328 PPLL 0xF0000028 R/W PHY PLL Configuration Register 0x000103111
Table 1-4. S3C2500B Memory Controller
Registers Address R/W Description Reset Value
B0CON 0xF0010000 R/W Bank 0 control register 0xC514E488 B1CON 0xF0010004 R/W Bank 1 control register 0xC514E488 B2CON 0xF0010008 R/W Bank 2 control register 0xC514E488 B3CON 0xF001000C R/W Bank 3 control register 0xC514E488 B4CON 0xF0010010 R/W Bank 4 control register 0xC514E488 B5CON 0xF0010014 R/W Bank 5 control register 0xC514E488 B6CON 0xF0010018 R/W Bank 6 control register 0xC514E488 B7CON 0xF001001C R/W Bank 7 control register 0xC514E488 MUXBCON 0xF0010020 R/W Muxed bus control register 0x006DB6DB WAITCON 0xF0010024 R/W Wait control register 0x00000000
Table 1-5. S3C2500B SDRAM Controller
Registers Address R/W Description Reset Value
CFGREG 0xF0020000 R/W SDRAM Configuration register 0x00099F0C CMDREG 0xF0020004 R/W SDRAM Command register 0x00000000 REFREG 0xF0020008 R/W Refresh timer register 0x00000020 WBTOREG 0xF002000C R/W Write buffer time-out register 0x00000000
1-32
S3C2500B PRODUCT OVERVIEW
Table 1-6. S3C2500B IIC Controller
Registers Address R/W Description Reset Value
IICCON 0xF00F0000 R/W Control status register 0x00000000 IICBUF 0xF00F0004 R/W Shift buffer register Undefined IICPS 0xF00F0008 R/W Prescaler register 0x00000000 IICCNT 0xF00F000C R/W Prescaler counter register 0x00000000 IICPND 0xF00F0010 R/W Interrupt pending register 0x00000000
Table 1-7. S3C2500B Ethernet Controller 0
Registers Address R/W Description Reset Value
BDMATXCONA 0xF00A0000 R/W Buffered DMA transmit control register 0x00000000 BDMARXCONA 0xF00A0004 R/W Buffered DMA receive control register 0x00000000 BDMATXDPTRA 0xF00A0008 R/W Transmit buffer descriptor start address 0x00000000 BDMARXDPTRA 0xF00A000C R/W Receive buffer descriptor start address 0x00000000 BTXBDCNTA 0xF00A0010 R/W BDMA Tx buffer descriptor counter 0x00000000 BRXBDCNTA 0xF00A0014 R/W BDMA Rx buffer descriptor counter 0x00000000 BMTXINTENA 0xF00A0018 R/W BDMA/MAC Tx Interrupt enable register 0x00000000 BMRXINTENA 0xF00A001C R/W BDMA/MAC Rx Interrupt enable register 0x00000000 BMTXSTATA 0xF00A0020 R/W BDMA/MAC Tx Status register 0x00000000 BMRXSTATA 0xF00A0024 R/W BDMA/MAC Rx Status register 0x00000000 BDMARXLENA 0xF00A0028 R/W Receive Frame Size 0x00000000 CFTXSTATA 0xF00A0030 R Transmit control frame status 0x00000000 MACCONA 0xF00B0000 R/W MAC control 0x00000000 CAMCONA 0xF00B0004 R/W CAM control 0x00000000 MACTXCONA 0xF00B0008 R/W Transmit control 0x00000000 MACTXSTATA 0xF00B000C R/W Transmit status 0x00000000 MACRXCONA 0xF00B0010 R/W Receive control 0x00000000 MACRXSTATA 0xF00B0014 R/W Receive status 0x00000000 STADATAA 0xF00B0018 R/W Station management data 0x00000000 STACONA 0xF00B001C R/W Station management control and address 0x00006000 CAMENA 0xF00B0028 R/W CAM enable 0x00000000 MISSCNTA 0xF00B003C R(Clr)/W Missed error count 0x00000000 PZCNTA 0xF00B0040 R Pause count 0x00000000 RMPZCNTA 0xF00B0044 R Remote pause count 0x00000000 CAMA 0xF00B0080-
W CAM content (32 words) Undefined
0xF00B00FC
1-33
PRODUCT OVERVIEW S3C2500B
Table 1-8. S3C2500B Ethernet Controller 1
Registers Address R/W Description Reset Value
BDMATXCONB 0xF00C0000 R/W Buffered DMA transmit control register 0x00000000 BDMARXCONB 0xF00C0004 R/W Buffered DMA receive control register 0x00000000 BDMATXDPTRB 0xF00C0008 R/W Transmit buffer descriptor start address 0x00000000 BDMARXDPTRB 0xF00C000C R/W Receive buffer descriptor start address 0x00000000 BTXBDCNTB 0xF00C0010 R/W BDMA Tx buffer descriptor counter 0x00000000 BRXBDCNTB 0xF00C0014 R/W BDMA Rx buffer descriptor counter 0x00000000 BMTXINTENB 0xF00C0018 R/W BDMA/MAC Tx Interrupt enable register 0x00000000 BMRXINTENB 0xF00C001C R/W BDMA/MAC Rx Interrupt enable register 0x00000000 BMTXSTATB 0xF00C0020 R/W BDMA/MAC Tx Status register 0x00000000 BMRXSTATB 0xF00C0024 R/W BDMA/MAC Rx Status register 0x00000000 BDMARXLENB 0xF00C0028 R/W Receive Frame Size 0x00000000 CFTXSTATB 0xF00C0030 R Transmit control frame status 0x00000000 MACCONB 0xF00D0000 R/W MAC control 0x00000000 CAMCONB 0xF00D0004 R/W CAM control 0x00000000 MACTXCONB 0xF00D0008 R/W Transmit control 0x00000000 MACTXSTATB 0xF00D000C R/W Transmit status 0x00000000 MACRXCONB 0xF00D0010 R/W Receive control 0x00000000 MACRXSTATB 0xF00D0014 R/W Receive status 0x00000000 STADATAB 0xF00D0018 R/W Station management data 0x00000000 STACONB 0xF00D001C R/W Station management control and address 0x00006000 CAMENB 0xF00D0028 R/W CAM enable 0x00000000 MISSCNTB 0xF00D003C R(Clr)/W Missed error count 0x00000000 PZCNTB 0xF00D0040 R Pause count 0x00000000 RMPZCNTB 0xF00D0044 R Remote pause count 0x00000000 CAMB 0xF00D0080-
W CAM content (32 words) Undefined
0xF00D00FC
1-34
S3C2500B PRODUCT OVERVIEW
Table 1-9. S3C2500B HDLC Controller 0
Registers Address R/W Description Reset Value
HMODE HCON HSTAT HINTEN HTxFIFOC
0×F0100000 0×F0100004 0×F0100008 0×F010000C 0×F0100010
R/W HDLC mode register R/W HDLC control register R/W HDLC status register R/W HDLC interrupt enable register
0×00000000 0×00000000 0×00000000 0×00000000
W HTxFIFO frame continue register –
(Frame Continue) HTxFIFOT
0×F0100014
W HTxFIFO frame terminate register – (Frame Terminate)
HRxFIFO HBRGTC HPRMB HSAR0 HSAR1 HSAR2 HSAR3 HMASK HDMATxPTR HDMARxPTR HMFLR HRBSR
0×F0100018 0×F010001C 0×F0100020 0×F0100024 0×F0100028 0×F010002C 0×F0100030 0×F0100034 0×F0100038 0×F010003C 0×F0100040 0×F0100044
R HRxFIFO entry register R/W HDLC BRG time constant register R/W HDLC preamble register R/W HDLC station address 0 R/W HDLC station address 1 R/W HDLC station address 2 R/W HDLC station address 3 R/W HDLC mask register R/W DMA Tx buffer descriptor pointer R/W DMA Rx buffer descriptor pointer R/W Maximum frame length register R/W Receive buffer size register
0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×FFFFFFFF 0×FFFFFFFF 0×XXXX0000
0×XXXX0000 HSYNC 0xF0100048 R/W HDLC Sync Register 0xXXXXXX7E HTXBDCNT HRXBDCNT HTXMAXBDCNT HRXMAXBDCNT TCON
0×F01000C0 0×F01000C4 0×F01000C8 0×F01000CC 0×F010004C
R Tx buffer descriptor count register
R Rx buffer descriptor count register R/W Tx buffer descriptor maximum count register R/W Rx buffer descriptor maximum count register R/W Transparent Control register
0×XXXXX000 0×XXXXX000 0×XXXXXFFF 0×XXXXXFFF 0×XXXX0000
1-35
PRODUCT OVERVIEW S3C2500B
Table 1-10. S3C2500B HDLC Controller 1
Registers Address R/W Description Reset Value
HMODE HCON HSTAT HINTEN HTxFIFOC
0×F0110000 0×F0110004 0×F011F0008 0×F011F000C 0×F0110010
R/W HDLC mode register R/W HDLC control register R/W HDLC status register R/W HDLC interrupt enable register
0×00000000 0×00000000 0×00000000 0×00000000
W HTxFIFO frame continue register –
(Frame Continue) HTxFIFOT
0×F0110014
W HTxFIFO frame terminate register –
(Frame Terminate) HRxFIFO HBRGTC HPRMB HSAR0 HSAR1 HSAR2 HSAR3 HMASK HDMATxPTR HDMARxPTR HMFLR HRBSR
0×F0110018 0×F011001C 0×F0110020 0×F0110024 0×F0110028 0×F011002C 0×F0110030 0×F0110034 0×F0110038 0×F011003C 0×F0110040 0×F0110044
R HRxFIFO entry register R/W HDLC BRG time constant register R/W HDLC preamble register R/W HDLC station address 0 R/W HDLC station address 1 R/W HDLC station address 2 R/W HDLC station address 3 R/W HDLC mask register R/W DMA Tx buffer descriptor pointer R/W DMA Rx buffer descriptor pointer R/W Maximum frame length register R/W Receive buffer size register
0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×FFFFFFFF 0×FFFFFFFF 0×XXXX0000
0×XXXX0000 HSYNC 0xF0110048 R/W HDLC Sync Register 0xXXXXXX7E HTXBDCNT HRXBDCNT HTXMAXBDCNT HRXMAXBDCNT TCON
0×F01100C0 0×F01100C4 0×F01100C8 0×F01100CC 0×F011004C
R Tx buffer descriptor count register
R Rx buffer descriptor count register R/W Tx buffer descriptor maximum count register R/W Rx buffer descriptor maximum count register R/W Transparent Control register
0×XXXXX000 0×XXXXX000 0×XXXXXFFF 0×XXXXXFFF 0×XXXX0000
1-36
S3C2500B PRODUCT OVERVIEW
Table 1-11. S3C2500B HDLC Controller 2
Registers Address R/W Description Reset Value
HMODE HCON HSTAT HINTEN HTxFIFOC
0×F0120000 0×F0120004 0×F0120008 0×F012000C 0×F0120010
R/W HDLC mode register R/W HDLC control register R/W HDLC status register R/W HDLC interrupt enable register
0×00000000 0×00000000 0×00000000 0×00000000
W HTxFIFO frame continue register –
(Frame Continue) HTxFIFOT
0×F0120014
W HTxFIFO frame terminate register –
(Frame Terminate) HRxFIFO HBRGTC HPRMB HSAR0 HSAR1 HSAR2 HSAR3 HMASK HDMATxPTR HDMARxPTR HMFLR HRBSR
0×F0120018 0×F012001C 0×F0120020 0×F0120024 0×F0120028 0×F012002c 0×F0120030 0×F0120034 0×F0120038 0×F012003C 0×F0120040 0×F0120044
R HRxFIFO entry register R/W HDLC BRG time constant register R/W HDLC preamble register R/W HDLC station address 0 R/W HDLC station address 1 R/W HDLC station address 2 R/W HDLC station address 3 R/W HDLC mask register R/W DMA Tx buffer descriptor pointer R/W DMA Rx buffer descriptor pointer R/W Maximum frame length register R/W Receive buffer size register
0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×00000000 0×FFFFFFFF 0×FFFFFFFF 0×XXXX0000
0×XXXX0000 HSYNC 0xF0120048 R/W HDLC Sync Register 0xXXXXXX7E HTXBDCNT HRXBDCNT HTXBDMAXCNT HRXBDMAXCNT TCON
0×F01200C0 0×F01200C4 0×F01200C8 0×F01200CC 0×F012004C
R Tx buffer descriptor count register
R Rx buffer descriptor count register R/W Tx buffer descriptor maximum count register R/W Rx buffer descriptor maximum count register R/W Transparent control register
0×XXXXX000 0×XXXXX000 0×XXXXXFFF 0×XXXXXFFF 0×XXXX0000
1-37
PRODUCT OVERVIEW S3C2500B
Table 1-12. S3C2500B IOM2 Controller
Register Address R/W Description Reset Value
IOM2CON 0xF0130000 R/W Control Register 0x00000000 IOM2STAT 0xF0130004 R/W Status Register 0x00000080 IOM2INTEN 0xF0130008 R/W Interrupt Enable Register 0x00000000 IOM2TBA 0xF013000C R/W TIC Bus Address 0x00000007 IOM2ICTD 0xF0130010 R/W IC Channel Tx Buffer 0x000000FF IOM2ICRD 0xF0130014 R/W IC Channel Rx Buffer 0x00000000 IOM2CITD0 0xF0130018 R/W C/I0 Channel Tx Buffer 0x0000000F IOM2CIRD0 0xF013001C R/W C/I0 Channel Rx Buffer 0x00000000 IOM2CITD1 0xF0130020 R/W C/I1 Channel Tx Buffer 0x0000003F IOM2CIRD1 0xF0130024 R/W C/I1 Channel Rx Buffer 0x00000000 IOM2MTD 0xF0130028 R/W Monitor Channel Tx Buffer 0x000000FF IOM2MRD 0xF013002C R/W Monitor Channel Rx Buffer 0x000000FF TSAACON 0xF0130030 R/W TSA A Control Register 0x00000000 TSABCON 0xF0130034 R/W TSA B Control Register 0x00000000 TSACCON 0xF0130038 R/W TSA C Control Register 0x00000000 IOM2STRB 0xF013003C R/W IOM2 Strobe Set Register 0x00000000
1-38
S3C2500B PRODUCT OVERVIEW
Table 1-13. S3C2500B USB Controller
Register Address R/W Description Reset Value
USBFA 0xF00E0000 R/W USB function address register 0x00000000 USBPM 0xF00E0004 R/W USB power management register 0x00000000 USBINTR 0xF00E0008 R/W USB interrupt register 0x00000000 USBINTRE 0xF00E000C R/W USB interrupt enable register 0x00000000 USBFN 0xF00E0010 R USB frame number register 0x00000000 USBDISCONN 0xF00E0014 R/W USB disconnect timer register 0x00000001 USBEP0CSR 0xF00E0018 R/W USB endpoint 0 common status register 0x00000001 USBEP1CSR 0xF00E001C R/W USB endpoint 1 common status register 0x00000401 USBEP2CSR 0xF00E0020 R/W USB endpoint 2 common status register 0x00000401 USBEP3CSR 0xF00E0024 R/W USB endpoint 3 common status register 0x00000401 USBEP4CSR 0xF00E0028 R/W USB endpoint 4 common status register 0x00000401
0xF00E002C Reserved USBWCEP0 0xF00E0030 R/W USB write count register for endpoint 0 0x00000000 USBWCEP1 0xF00E0034 R/W USB write count register for endpoint 1 0x00000000 USBWCEP2 0xF00E0038 R/W USB write count register for endpoint 2 0x00000000 USBWCEP3 0xF00E003C R/W USB write count register for endpoint 3 0x00000000 USBWCEP4 0xF00E0040 R/W USB write count register for endpoint 4 0x00000000
0xF00E0044-
Reserved
0xF00E007C USBEP0 0xF00E0080 R/W USB endpoint 0 FIFO Undefined USBEP1 0xF00E0084 R[W] USB endpoint 1 FIFO Undefined USBEP2 0xF00E0088 R[W] USB endpoint 2 FIFO Undefined USBEP3 0xF00E008C R[W] USB endpoint 3 FIFO Undefined USBEP4 0xF00E0090 R[W] USB endpoint 4 FIFO Undefined
1-39
PRODUCT OVERVIEW S3C2500B
Table 1-14. S3C2500B DES Controller
Registers Address R/W Description Reset Value
DESCON 0xF0090000 R/W DES/3DES control register
0×00000000 DESSTA 0xF0090004 R DES/3DES status register 0x00000231 DESINT 0xF0090008 R/W DES/3DES interrupt enable register 0x00000000 DESRUN 0xF009000C W DES/3DES run enable register 0x00000000 DESKEY1L 0xF0090010 R/W Key 1 left half 0x00000000 DESKEY1R 0xF0090014 R/W Key 1 right half 0x00000000 DESKEY2L 0xF0090018 R/W Key 2 left half 0x00000000 DESKEY2R 0xF009001C R/W Key 2 right half 0x00000000 DESKEY3L 0xF0090020 R/W Key 3 left half 0x00000000 DESKEY3R 0xF0090024 R/W Key 3 right half 0x00000000 DESIVL 0xF0090028 R/W IV left half 0x00000000 DESIVR 0xF009002C R/W IV right half 0x00000000 DESINFIFO 0xF0090030 W DES/3DES input FIFO 0xXXXXXXXX DESOUTFIFO 0xF0090034 R DES/3DES output FIFO 0xXXXXXXXX
1-40
S3C2500B PRODUCT OVERVIEW
Table 1-15. S3C2500B GDMA Controller
Registers Address R/W Description Reset Value
DPRIC 0xF0051000 R/W GDMA priority configuration register 0x00000000 DPRIF 0xF0052000 R/W GDMA programmable priority register for fixed 0x00543210 DPRIR 0xF0053000 R/W GDMA programmable priority register for round-
0x00000000
robin DCON0 0xF0050000 R/W GDMA channel 0 control register 0x00000000 DSAR0 0xF0050004 R/W GDMA channel 0 source address register 0x00000000 DDAR0 0xF0050008 R/W GDMA channel 0 destination address register 0x00000000 DTCR0 0xF005000C R/W GDMA channel 0 transfer count register 0x00000000 DRER0 0xF0050010 W GDMA channel 0 run enable register 0x00000000 DIPR0 0xF0050014 R/WC GDMA channel 0 interrupt pending register 0x00000000 DCON1 0xF0050020 R/W GDMA channel 1 control register 0x00000000 DSAR1 0xF0050024 R/W GDMA channel 1 source address register 0x00000000 DDAR1 0xF0050028 R/W GDMA channel 1 destination address register 0x00000000 DTCR1 0xF005002C R/W GDMA channel 1 transfer count register 0x00000000 DRER1 0xF0050030 W GDMA channel 1 run enable register 0x00000000 DIPR1 0xF0050034 R/WC GDMA channel 1 interrupt pending register 0x00000000 DCON2 0xF0050040 R/W GDMA channel 2 control register 0x00000000 DSAR2 0xF0050044 R/W GDMA channel 2 source address register 0x00000000 DDAR2 0xF0050048 R/W GDMA channel 2 destination address register 0x00000000 DTCR2 0xF005004C R/W GDMA channel 2 transfer count register 0x00000000 DRER2 0xF0050050 W GDMA channel 2 run enable register 0x00000000 DIPR2 0xF0050054 R/WC GDMA channel 2 interrupt pending register 0x00000000 DCON3 0xF0050060 R/W GDMA channel 3 control register 0x00000000 DSAR3 0xF0050064 R/W GDMA channel 3 source address register 0x00000000 DDAR3 0xF0050068 R/W GDMA channel 3 destination address register 0x00000000 DTCR3 0xF005006C R/W GDMA channel 3 transfer count register 0x00000000 DRER3 0xF0050070 W GDMA channel 3 run enable register 0x00000000 DIPR3 0xF0050074 R/WC GDMA channel 3 interrupt pending register 0x00000000 DCON4 0xF0050080 R/W GDMA channel 4 control register 0x00000000 DSAR4 0xF0050084 R/W GDMA channel 4 source address register 0x00000000 DDAR4 0xF0050088 R/W GDMA channel 4 destination address register 0x00000000 DTCR4 0xF005008C R/W GDMA channel 4 transfer count register 0x00000000
1-41
PRODUCT OVERVIEW S3C2500B
Table 1-15. S3C2500B GDMA Controller (Continued)
Registers Address R/W Description Reset Value
DRER4 0xF0050090 W GDMA channel 4 run enable register 0x00000000 DIPR4 0xF0050094 R/WC GDMA channel 4 interrupt pending register 0x00000000 DCON5 0xF00500A0 R/W GDMA channel 5 control register 0x00000000 DSAR5 0xF00500A4 R/W GDMA channel 5 source address register 0x00000000 DDAR5 0xF00500A8 R/W GDMA channel 5 destination address register 0x00000000 DTCR5 0xF00500AC R/W GDMA channel 5 transfer count register 0x00000000 DRER5 0xF00500B0 W GDMA channel 5 run enable register 0x00000000 DIPR5 0xF00500B4 R/WC GDMA channel 5 interrupt pending register 0x00000000
Table 1-16. S3C2500B Console UART Controller
Register Address R/W Description Reset Value
CUCON 0xF0060000 R/W Console UART control register 0x00000000 CUSTAT 0xF0060004 R/W Console UART status register 0x00060800 CUINT 0xF0060008 R/W Console UART interrupt enable register 0x00000000 CUTXBUF 0xF006000C W Console UART transmit data register – CURXBUF 0xF0060010 R Console UART receive data register – CUBRD 0xF0060014 R/W Console UART baud rate divisor register 0x0000 CUCHAR1 0xF0060018 R/W Console UART control character register 1 0x00000000 CUCHAR2 0xF006001C R/W Console UART control character register 2 0x00000000
Table 1-17. S3C2500B High-speed UART Controller 0
Register Address R/W Description Reset Value
HUCON 0xF0070000 R/W High-Speed UART control register 0x00000000 HUSTAT 0xF0070004 R/W High-Speed UART status register – HUINT 0xF0070008 R/W High-Speed UART interrupt enable register 0x00000000 HUTXBUF 0xF007000C W High-Speed UART transmit data register – HURXBUF 0xF0070010 R High-Speed UART receive data register – HUBRD 0xF0070014 R/W High-Speed UART baud rate divisor register 0x00000000 HUCHAR1 0xF0070018 R/W High-Speed UART control character register 1 0x00000000 HUCHAR2 0xF007001C R/W High-Speed UART control character register 2 0x00000000 HUABB 0xF0070100 R/W High-Speed UART autobaud boundary register 0x1F0F0703 HUABT 0xF0070104 R/W High-Speed UART autobaud table register 0x170B0502
1-42
S3C2500B PRODUCT OVERVIEW
Table 1-18. S3C2500B High speed UART Controller 1
Register Address R/W Description Reset Value
HUCON 0xF0080000 R/W High-Speed UART control register 0x00000000 HUSTAT 0xF0080004 R/W High-Speed UART status register – HUINT 0xF0080008 R/W High-Speed UART interrupt enable register 0x00000000 HUTXBUF 0xF008000C W High-Speed UART transmit data register – HURXBUF 0xF0080010 R High-Speed UART receive data register – HUBRD 0xF0080014 R/W High-Speed UART baud rate divisor register 0x00000000 HUCHAR1 0xF0080018 R/W High-Speed UART control character register 1 0x00000000 HUCHAR2 0xF008001C R/W High-Speed UART control character register 2 0x00000000 HUABB 0xF0080100 R/W High-Speed UART autobaud boundary register 0x1F0F0703 HUABT 0xF0080104 R/W High-Speed UART autobaud table register 0x170B0502
Table 1-19. S3C2500B I/O Port Controller
Register Address R/W Description Reset Value
IOPMODE1 0xF0030000 R/W I/O port mode select lower register for port 0 to310xF003FFFF
IOPMODE2 0xF0030004 R/W I/O port mode select upper register for port 32 to630xFFFFFFFF
IOPCON1 0xF0030008 R/W I/O port function control register for port 0 to 31 0x0FFFFF00 IOPCON2 0xF003000C R/W I/O port select function control register for port
0x00000000
32 to 63 IOPGDMA 0xF0030010 R/W I/O port special function register for GDMA 0x00000000 IOPEXTINT 0xF0030014 R/W I/O port special function register for external
0x00000000
interrupt IOPEXTINTPND 0xF0030018 R/W I/O port external Interrupt clear register 0x00000000 IOPDATA1 0xF003001C R/W I/O port data register for port 0 to 31 Undefined IOPDATA2 0xF0030020 R/W I/O port data register for port 32 to 63 Undefined IOPDRV1 0xF0030024 R/W I/O port drive control register for port 0 to 31 0x00000000 IOPDRV2 0xF0030028 R/W I/O port drive control register for port 32 to 63 0x00000000
1-43
PRODUCT OVERVIEW S3C2500B
Table 1-20. S3C2500B Interrupt Controller
Register Address R/W Description Reset Value
INTMOD 0xF0140000 R/W Internal interrupt mode register 0x00000000 EXTMOD 0xF0140004 R/W External interrupt mode register 0x00000000 INTMASK 0xF0140008 R/W Internal Interrupt mask register 0xFFFFFFFF EXTMASK 0xF014000C R/W External Interrupt mask register 0x8000007F INTPRIOR0 0xF0140020 R/W Interrupt priority register 0 0x03020100 INTPRIOR1 0xF0140024 R/W Interrupt priority register 1 0x07060504 INTPRIOR2 0xF0140028 R/W Interrupt priority register 2 0x0B0A0908 INTPRIOR3 0xF014002C R/W Interrupt priority register 3 0x0F0E0D0C INTPRIOR4 0xF0140030 R/W Interrupt priority register 4 0x13121110 INTPRIOR5 0xF0140034 R/W Interrupt priority register 5 0x17161514 INTPRIOR6 0xF0140038 R/W Interrupt priority register 6 0x1B1A1918 INTPRIOR7 0xF014003C R/W Interrupt priority register 7 0x1F1E1D1C INTPRIOR8 0xF0140040 R/W Interrupt priority register 8 0x23222120 INTPRIOR9 0xF0140044 R/W Interrupt priority register 9 0x00262524 INTOFFSET_FIQ 0xF0140018 R FIQ interrupt offset register 0x00000027 INTOFFSET_IRQ 0xF014001C R IRQ interrupt offset register 0x00000027 IPRIORHI 0xF0140010 R High bits, 38-32 bit, Interrupt by priority register 0x00000000 IPRIORLO 0xF0140014 R Low bits, 31-0 bit, Interrupt by priority register 0x00000000 INTTSTHI 0xF0140048 R High bits, 38-7 bit, Interrupt test register 0x00000000 INTTSTLO 0xF014004C R Low bits, 6-0 bit, Interrupt test register 0x00000000
1-44
S3C2500B PRODUCT OVERVIEW
Table 1-21. S3C2500B Timer Controller
Register Address R/W Description Reset Value
TMOD 0xF0040000 R/W Timer mode register 0x00000000 TIC 0xF0040004 R/W Timer Interrupt Clear 0x00000000 WDT 0xF0040008 R/W Watchdog Timer Register 0x00000000 TDATA0 0xF0040010 R/W Timer 0 data register 0x00000000 TCNT0 0xF0040014 R/W Timer 0 count register 0xFFFFFFFF TDATA1 0xF0040018 R/W Timer 1 data register 0x00000000 TCNT1 0xF004001C R/W Timer 1 count register 0xFFFFFFFF TDATA2 0xF0040020 R/W Timer 2 data register 0x00000000 TCNT2 0xF0040024 R/W Timer 2 count register 0xFFFFFFFF TDATA3 0xF0040028 R/W Timer 3 data register 0x00000000 TCNT3 0xF004002C R/W Timer 3 count register 0xFFFFFFFF TDATA4 0xF0040030 R/W Timer 4 data register 0x00000000 TCNT4 0xF0040034 R/W Timer 4 count register 0xFFFFFFFF TDATA5 0xF0040038 R/W Timer 5 data register 0x00000000 TCNT5 0xF004003C R/W Timer 5 count register 0xFFFFFFFF
1-45
PRODUCT OVERVIEW S3C2500B
NOTES
1-46
S3C2500B PROGRAMMER′′S MODEL
2 PROGRAMMER′′S MODEL
2.1 OVERVIEW
S3C2500B was developed using the advanced ARM9TDMI core designed by advanced RISC machines, Ltd. — Processor Operating States
From the programmer′s point of view, the ARM9TDMI can be in one of two states: — ARM state which executes 32-bit, word-aligned ARM instructions.
— THUMB state which operates with 16-bit, half-word-aligned THUMB instructions. In this state, the PC uses
bit 1 to select between alternate half-words.
NOTE
Transition between these two states does not affect the processor mode or the contents of the registers.
2.2 SWITCHING STATE
2.2.1 ENTERING THUMB STATE
Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand register.
Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the processor in THUMB state.
2.2.2 ENTERING ARM STATE
Entry into ARM state happens:
1. On execution of the BX instruction with the state bit clear in the operand register.
2. On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is placed in the exception mode′s link register, and execution commences at the exception′s vector address.
2-1
PROGRAMMER′′S MODEL S3C2500B
2.3 MEMORY FORMATS
ARM9TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM9TDMI can treat words in memory as being stored either in Big-Endian or Little-Endian format.
2.3.1 BIG-ENDIAN FORMAT
In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.
Higher Address
Lower Address
31 8
4 0
Most significant byte is at lowest address. Word is addressed by byte address of most significant byte.
23
24 1516
9 5 1
10 6 2
8 7 0
11 7 3
Word Address
8 4 0
Figure 2-1. Big-Endian Addresses of Bytes within Words
NOTE
The data locations in the external memory are different with Figure 2-1 in the S3C2500B. Please refer to the chapter 4, system manager.
2.3.2 LITTLE-ENDIAN FORMAT
In Little-Endian format, the lowest numbered byte in a word is considered the word′s least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0.
2-2
Higher Address
Lower Address
31 23 8 7 0 11
7 3
24 1516
10 6 2
Least significant byte is at lowest address. Word is addressed by byte address of least significant byte.
9 5 1
8 4 0
Figure 2-2. Little-Endian Addresses of Bytes Words
Word Address
8 4 0
S3C2500B PROGRAMMER′′S MODEL
2.4 INSTRUCTION LENGTH
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
2.5 DATA TYPES
ARM9TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four­byte boundaries and half words to two-byte boundaries.
2.6 OPERATING MODES
ARM9TDMI supports seven modes of operation: User (usr): The normal ARM program execution state FIQ (fiq): Designed to support a data transfer or channel process IRQ (irq): Used for general-purpose interrupt handling Supervisor (svc): Protected mode for the operating system Abort mode (abt): Entered after a data or instruction prefetch abort System (sys): A privileged user mode for the operating system Undefined (und): Entered when an undefined instruction is executed
Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources.
2-3
PROGRAMMER′′S MODEL S3C2500B
2.7 REGISTERS
ARM9TDMI has a total of 37 registers-31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer.
2.7.1 The ARM State Register Set
In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (non­User) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle.
The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information.
Register 14 is used as the subroutine link register. This receives a copy of R15 when a branch
and link (BL) instruction is executed. At all other times it may be treated as a general-purpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise, or when branch and link instructions are executed within interrupt or exception routines.
Register 15
Register 16
holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC.
is the CPSR (Current Program Status Register). This contains condition code flags and the current mode bits.
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.
2-4
S3C2500B PROGRAMMER′′S MODEL
ARM State General Registers and Program Counter
System & User FIQ Supervisor About IRQ Undefined
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC)
CPSR CPSR
R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC)
SPSR_fiq
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC)
ARM State Program Status Register
CPSR
SPSR_svc
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC)
CPSR
SPSR_abt
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC)
CPSR
SPSR_irq
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC)
CPSR
SPSR_und
= banked register
Figure 2-3. Register Organization in ARM State
2-5
PROGRAMMER′′S MODEL S3C2500B
2.7.2 The THUMB State Register Set
The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0–R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked stack pointers, link registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in Figure 2-4.
THUMB State General Registers and Program Counter
System & User FIQ Supervisor About IRQ Undefined
R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC
CPSR CPSR
= banked register
R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq LR_fiq PC
SPSR_fiq
Figure 2-4. Register Organization in THUMB State
R0 R1 R2 R3 R4 R5 R6 R7 SP_svg LR_svc PC
THUMB State Program Status Registers
CPSR
SPSR_svc
R0 R1 R2 R3 R4 R5 R6 R7 SP_abt LR_abt PC
CPSR
SPSR_abt
R0 R1 R2 R3 R4 R5 R6 R7 SP_irq LR_irq PC
CPSR
SPSR_irq
R0 R1 R2 R3 R4 R5 R6 R7 SP_und LR_und PC
CPSR
SPSR_und
2-6
S3C2500B PROGRAMMER′′S MODEL
Lo-registersHi-registers
2.7.3 THE RELATIONSHIP BETWEEN ARM AND THUMB STATE REGISTERS
The THUMB state registers relate to the ARM state registers in the following way: — THUMB state R0–R7 and ARM state R0–R7 are identical — THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical — THUMB state SP maps onto ARM state R13 — THUMB state LR maps onto ARM state R14 The THUMB state program counter maps onto the ARM state program counter (R15)
This relationship is shown in Figure 2-5.
THUMB State ARM State
R0 R1 R2 R3 R4 R5 R6 R7
Stack Pointer (SP)
Link Register (LR)
Program Counter (PC)
CPSR SPSR
R0 R1 R2 R3 R4 R5 R6 R7 R8
R9 R10 R11 R12
Stack Pointer (R13) Link Register (R14)
Program Counter (R15)
CPSR SPSR
Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers
2-7
PROGRAMMER′′S MODEL S3C2500B
2.7.4 ACCESSING HI-REGISTERS IN THUMB STATE
In THUMB state, registers R8–R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage.
A value may be transferred from a register in the range R0–R7 (a Lo register) to a Hi register, and from a Hi register to a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions. For more information, refer to Figure 3-34.
2.8 THE PROGRAM STATUS REGISTERS
The ARM9TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These register′s functions are:
— Hold information about the most recently performed ALU operation — Control the enabling and disabling of interrupts — Set the processor operating mode
The arrangement of bits is shown in Figure 2-6.
Condition Code Flags (Reserved)
31 30 29 28 27 26 25 24 8 7 6 5 4 3 2 1 0
N Z C V . . .. . . I F T M4 M3 M2 M1 M0
Overflow Carry/Borrow/Extend Zero Negative/Less Than
Control Bits
Figure 2-6. Program Status Register Format
Mode bits State bit FIQ disable FRQ disable
2-8
S3C2500B PROGRAMMER′′S MODEL
2.8.1 THE CONDITION CODE FLAGS
The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed.
In ARM state, all instructions may be executed conditionally: see Table 3-2 for details. In THUMB state, only the branch instruction is capable of conditional execution: see Figure 3-46 for details.
2.8.2 THE CONTROL BITS
The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will change when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software.
The T bit This reflects the operating state. When this bit is set, the processor is executing in
THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal.
Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state.
Interrupt disable bits
The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively.
The mode bits
The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor′s operating mode, as shown in Table 2-1. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied.
2-9
PROGRAMMER′′S MODEL S3C2500B
Table 2-1. PSR Mode. Bit Values
M[4:0] Mode Visible THUMB State Registers Visible ARM State Registers
10000 User R7..R0,
LR, SP
R14..R0, PC, CPSR
PC, CPSR
10001 FIQ R7..R0,
LR_fiq, SP_fiq PC, CPSR, SPSR_fiq
10010 IRQ R7..R0,
LR_irq, SP_irq PC, CPSR, SPSR_irq
10011 Supervisor R7..R0,
LR_svc, SP_svc, PC, CPSR, SPSR_svc
10111 Abort R7..R0,
LR_abt, SP_abt, PC, CPSR, SPSR_abt
11011 Undefined R7..R0
LR_und, SP_und, PC, CPSR, SPSR_und
11111 System R7..R0,
LR, SP
R7..R0, R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq R12..R0, R14_irq..R13_irq, PC, CPSR, SPSR_irq R12..R0, R14_svc..R13_svc, PC, CPSR, SPSR_svc R12..R0, R14_abt..R13_abt, PC, CPSR, SPSR_abt R12..R0, R14_und..R13_und, PC, CPSR R14..R0, PC, CPSR
PC, CPSR
Reserved bits
2-10
The remaining bits in the PSRs are reserved. When changing a PSR′s flag or control bits, you must ensure that these unused bits are not altered. Also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.
S3C2500B PROGRAMMER′′S MODEL
2.9 EXCEPTIONS
Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished.
It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order. See Exception Priorities on page 2-15.
2.9.1 ACTION ON ENTERING AN EXCEPTION
When handling an exception, the ARM9TDMI:
1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from THUMB state, then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception. This means that the exception handler need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC, R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state.
2. Copies the CPSR into the appropriate SPSR
3. Forces the CPSR mode bits to a value which depends on the exception
4. Forces the PC to fetch the next instruction from the relevant exception vector
It may also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the
PC is loaded with the exception vector address.
2.9.2 ACTION ON LEAVING AN EXCEPTION
On completion, the exception handler:
1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the type of exception.)
2. Copies the SPSR back to the CPSR
3. Clears the interrupt disable flags, if they were set on entry
NOTE
An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception.
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2.9.3 EXCEPTION ENTRY/EXIT SUMMARY
Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler.
Table 2-2. Exception Entry/Exit
Return Instruction Previous State Notes
ARM R14_x THUMB R14_x
BL MOV PC, R14 PC + 4 PC + 2 1 SWI MOVS PC, R14_svc PC + 4 PC + 2 1 UDEF MOVS PC, R14_und PC + 4 PC + 2 1 FIQ SUBS PC, R14_fiq, #4 PC + 4 PC + 4 2 IRQ SUBS PC, R14_irq, #4 PC + 4 PC + 4 2 PABT SUBS PC, R14_abt, #4 PC + 4 PC + 4 1 DABT SUBS PC, R14_abt, #8 PC + 8 PC + 8 3 RESET NA – – 4
NOTES:
1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort.
2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority.
3. Where PC is the address of the Load or Store instruction which generated the data abort.
4. The value saved in R14_svc upon reset is unpredictable.
2.9.4 FIQ
The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context switching).
FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow.
Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt by executing
SUBS PC,R14_fiq,#4
FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is clear, ARM9TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction.
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2.9.5 IRQ
The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode.
Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the interrupt by executing
SUBS PC,R14_irq,#4
2.9.6 ABORT
An abort indicates that the current memory access cannot be completed. It can be signalled by the external ABORT input. ARM9TDMI checks for the abort exception during memory access cycles.
There are two types of abort:
— Prefetch abort: occurs during an instruction prefetch.
— Data abort: occurs during a data access.
If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. If the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place.
If a data abort occurs, the action taken depends on the instruction type:
— Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must
be aware of this.
— The swap instruction (SWP) is aborted as though it had not been executed. — Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the
instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last register to be transferred) is preserved in an aborted LDM instruction.
The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. The application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort.
After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb):
SUBS PC,R14_abt,#4 ; for a prefetch abort, or SUBS PC,R14_abt,#8 ; for a data abort
This restores both the PC and the CPSR, and retries the aborted instruction.
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2.9.7 SOFTWARE INTERRUPT
The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb):
MOV PC,R14_svc
This restores the PC and CPSR, and returns to the instruction following the SWI.
NOTE
nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM9TDMI CPU core.
2.9.8 UNDEFINED INSTRUCTION
When ARM9TDMI comes across an instruction which it cannot handle, it takes the undefined instruction trap. This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation.
After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or Thumb):
MOVS PC,R14_und
This restores the CPSR and returns to the instruction following the undefined instruction.
2.10 EXCEPTION VECTORS
The following table shows the exception vector addresses.
Table 2-3. Exception Vectors
Address Exception Mode in Entry
0x00000000 Reset Supervisor 0x00000004 Undefined instruction Undefined 0x00000008 Software Interrupt Supervisor
0x0000000C Abort (prefetch) Abort
0x00000010 Abort (data) Abort 0x00000014 Reserved Reserved 0x00000018 IRQ IRQ
0x0000001C FIQ FIQ
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2.10.1 EXCEPTION PRIORITIES
When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled:
Highest priority:
1. Reset
2. Data abort
3. FIQ
4. IRQ
5. Prefetch abort
Lowest priority:
6. Undefined Instruction, Software interrupt.
2.10.2 NOT ALL EXCEPTIONS CAN OCCUR AT ONCE:
Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (non-overlapping) decoding of the current instruction.
If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM9TDMI enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection. The time for this exception entry should be added to worst-case FIQ latency calculations.
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2.11 INTERRUPT LATENCIES
The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM9TDMI will be executing the instruction at 0x1C.
Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser (Tsyncmin) plus Tfiq. This is 4 processor cycles.
2.12 RESET
When the nRESET signal goes LOW, ARM9TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses.
When nRESET goes HIGH again, ARM9TDMI:
1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined.
2. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit.
3. Forces the PC to fetch the next instruction from address 0x00.
4. Execution resumes in ARM state.
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2.13 INTRODUCTION FOR ARM940T
The ARM940T cached processor macrocell is a member of the ARM9 Thumb Family of high-performance 32-bit system-on-a-chip processor solutions. It is targeted at a wide range of embedded control applications where high performance, low system cost, small die size, and low power are key considerations.
The ARM940T processor macrocell provides a complete high performance CPU subsystem, including ARM9TDMI RISC integer CPU, caches, write buffer, and protection unit, with an AMBA ASB bus interface. Providing a complete high-frequency CPU subsystem frees the system-on-a-chip designer to concentrate on design issues unique to their system.
The ARM9TDMI core within the ARM940T macrocell executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. It is binary compatible with ARM7TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating systems, and application software.
The ARM940T processor macrocell is designed to be integrated into larger chips. It supports EmbeddedICE software and hardware debug and efficient production test when embedded in larger devices. The Advanced Microcontroller Bus Architecture (AMBA) provides a high performance 32-bit System Bus (ASB) and a low power peripheral bus (APB). The ASB is re-used to provide a channel for production test vectors with low silicon and pin overhead. The ASB is a multi-master on-chip bus interface designed specifically to address the needs of system­on-a-chip designs.
The EmbeddedICE software and hardware debug features of the ARM940T macrocell are accessed via a standard 5-pin JTAG port, and are supported by ARM's Software Development Toolkit and Multi-ICE interface hardware. The EmbeddedICE features allow software download and debug of the final production system with no cost overhead (there is no monitor code or other use of target resident RAM or ROM).
The ARM940T processor has a Harvard cache architecture with separate 4KB instruction and 4KB data caches, each with a 4-word line length. A protection unit allows 8 regions of memory to be defined, each with individual cache and write buffer configurations and access permissions. The cache system is software configurable to provide highest average performance or to meet the needs of real-time systems.
Software configurable options include:
• Random or round robin replacement algorithm
• Write-through or write-back cache operation (independently selectable for each memory region)
• Cache locking with granularity 1/64 th of cache size.
Overall, the cache and write buffers improve CPU performance and minimize accesses to the AMBA bus and to any off-chip memory, thus reducing overall system power consumption.
The ARM940T includes support for coprocessors, allowing a floating point unit or other application specific hardware acceleration to be added.
To minimize die size and power consumption the ARM940T does not provide virtual to physical address mapping as this is not required in most embedded applications. For systems requiring virtual memory capability, ARM provides an alternative product, the ARM920T cached processor macrocell. The ARM940T also features a TrackingICE mode which allows an approach similar to a conventional ICE mode of operation.
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2.14 ARM940T BLOCK DIAGRAM
CPID[31:0] CPDIN[31:0] CPDOUT[31:0]
ID[31:0]
I Cache
Control
Instruction
Cache
4K
JTAG
Interface[4:0]
IA[31:0]
Coprocessor
Interface
Protection Unit
CP15
ARM9TDMI
Processor Core
(Integral EmbeddedICE)
AMBA Interface
BA[31:0] Bcontrol BD[31:0]
DA[31:0]
DD[31:0]
D Cache
Control
Data
Cache
4K
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Figure 2-7. ARM940T Block Diagram
S3C2500B PROGRAMMER′′S MODEL
2.15 ABOUT THE ARM940T PROGRAMMER'S MODEL
The ARM940T cached processor macrocell includes the ARM9TDMI microprocessor core, instruction and data caches, a write-buffer, and a protection unit for defining the attributes of regions of memory.
The ARM940T incorporates two coprocessors:
• CP14 which allows software access to the debug communications channel
• CP15 which allows configuration of the caches, protection unit, and other system options such as big or little
endian operation.
The ARM940T also features an external coprocessor interface which allows the attachment of a closely coupled coprocessor on the same chip, for example, a floating point unit.
The programmer's model of the ARM940T consists of the programmer's model of the ARM9TDMI with the following additions and modifications:
• Memory accesses for instruction fetches and data loads and stores may be cached or buffered. Cache and write buffer configuration and operation is described in detail in following chapters.
• The registers defined in CP14 are accessible with MCR and MRC instructions. These are described in Debug communications channel on page 8-46.
• The registers defined in CP15 are accessible with MCR and MRC instructions. These are described in ARM940T CP15 registers on page 2-5.
• Registers and operations provided by any coprocessors attached to the external coprocessor interface will be accessible with appropriate coprocessor instructions.
The ARM9TDMI processor core implements ARM Architecture v4T, and so executes the ARM 32-bit instruction set and the compressed Thumb 16-bit instruction set. The programmer's model is fully described in the ARM Architecture Reference Manual.
The ARM v4T architecture specifies a small number of implementation options. The options selected in the ARM9TDMI implementation are listed in Table 2-4. For comparison, the options selected for the ARM9TDMI implementation are also shown.
Table 2-4. ARM9TDMI Implementation Option
Processor Core ARM
Architecture
ARM7TDMI v4T Base updatd Address of Inst + 12 ARM9TDMI v4T Base restored Address of Inst + 12
The ARM9TDMI is code-compatible with the ARM7TDMI, with two exceptions:
• The ARM9TDMI implements the base restored data abort model, which significantly simplifies the software data abort handler.
Data Abort Mode Value Stored by Direct
STR, STRT, STM of PC
• The ARM9TDMI fully implements the instruction set extension spaces added to the ARM (32-bit) instruction set in architecture v4 and v4T.
These differences are explained in more detail below.
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2.15.1 DATA ABORT MODEL
The base restored data abort model differs from the base updated data abort model implemented by ARM7TDMI. The difference in the data abort model affects only a very small section of operating system code, the data abort
handler. It does not affect user code. With the base restored data abort model, when a data abort exception occurs during the execution of a memory access instruction, the base register is always restored by the processor hardware to the value the register contained before the instruction was executed. This removes the need for the data abort handler to unwind any base register update which may have been specified by the aborted instruction.
The base restored data abort model significantly simplifies the software data abort handler.
2.15.2 INSTRUCTION SET EXTENSION SPACES
All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception. That is, ARM instructions with opcode[27:25] = 0b011 and opcode[4] = 1 are undefined on all ARM processors including the ARM9TDMI and ARM7TDMI.
ARM Architecture v4 and v4T also introduced a number of instruction set extension spaces to the ARM instruction set. These are:
• Arithmetic instruction extension space
• Control instruction extension space
• Coprocessor instruction extension space
• Load/store instruction extension space.
Instructions in these spaces are undefined (they cause an undefined instruction exception). The ARM9TDMI fully implements all the instruction set extension spaces defined in ARM Architecture v4T as undefined instructions, allowing emulation of future instruction set additions.
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