SAMSUNG S3C2416 User Guide

USER'S MANUAL

S3C2416

16/32-Bit RISC Microprocessor

October 2008

REV 1.10

Confidential Proprietary of Samsung Electronics Co., Ltd

Important Notice

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S3C2416 16/32-Bit RISC Microprocessor User's Manual, Revision 1.10

Publication Number: 21.10-S3-C2416- 082008

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

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objectives.

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NOTIFICATION OF REVISIONS

ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea

PRODUCT NAME: S3C2416 RISC Microprocessor

DOCUMENT NAME: S3C2416 User's Manual, Revision 1.10

DOCUMENT NUMBER: 21.10-S3-C2416-082008

EFFECTIVE DATE: October, 2008

DIRECTIONS: Revision 1.10

REVISION HISTORY

Revision No Description of Change Refer to Author(s) Date

1.00 Initial release - AP app part. August 27, 2008

1.10 Overview, System controller, DMA controller, I/O ports, LCD controller are updated.

- AP app part. October 06, 2008

REVISION DESCRIPTIONS FOR REVISION 1.10

Chapter

Chapter Name Page

1. Overview 1-2

2. System controller 2-1,6,8,9

8. DMA controller 8-2

8. DMA controller 8-16,17

10. I/O ports 10-37

21. LCD controller 21-23

Subjects (Major changes comparing with last version)

Way number of Cache Memory is corrected. Camera related explanation is removed. DMA request sources are corrected. Referred Register name, bit and pages are corrected. CF related description is removed. Camera related explanation is removed.

Chapter 1 Product Overview

1 Introduction ...............................................................................................................................................1-1

2 Features....................................................................................................................................................1-2

3 Block Diagram...........................................................................................................................................1-5

4 Pin Assignments .......................................................................................................................................1-6

4.1 Signal Descriptions..........................................................................................................................1-24

4.2 S3C2416 Operation Mode Description ...........................................................................................1-31

4.3 S3C2416 Memory MAP and Base Address of Special Registers...................................................1-32

Chapter 2 System Controller

1 Overview..................................................................................................................... ..............................2-1

2 Feature......................................................................................................................................................2-1

3 Block Diagram...........................................................................................................................................2-2

4 Functional Descriptions.............................................................................................................................2-3

4.1 Reset Management and Types.......................................................................................................2-3

4.2 Hardware Reset...............................................................................................................................2-3

4.3 Watchdog Reset..............................................................................................................................2-4

4.4 Software Reset................................................................................................................................2-5

4.5 Wakeup Reset.................................................................................................................................2-5

5 Clock Management...................................................................................................................................2-6

5.1 Clock Generation Overview.............................................................................................................2-6

5.2 Clock Source Selection ...................................................................................................................2-6

5.3 PLL (Phase-Locked-Loop) ..............................................................................................................2-8

5.4 Change PLL Settings In Normal Operation.....................................................................................2-8

5.5 System Clock Control......................................................................................................................2-9

5.6 ARM & BUS Clock Divide Ratio ......................................................................................................2-10

5.7 Examples for configuring clock regiter to produce specific frequency of AMBA clocks..................2-11

5.8 ESYSCLK Control ...........................................................................................................................2-12

6 Power Management..................................................................................................................................2-13

6.1 Power Mode State Diagram............................................................................................................2-13

6.2 Power Saving Modes.......................................................................................................................2-14

6.3 Wake-Up Event

6.4 Output Port State and STOP and SLEEP Mode.............................................................................2-19

6.5 Power Saving Mode Entering/Exiting Condition..............................................................................2-20

7 Register Descriptions................................................................................................................................2-21

7.1 Address Map ...................................................................................................................................2-21

...............................................................................................................................2-19

S3C2416X RISC MICROPROCESSOR i

Table of Contents (Continued)

Chapter 2 System Controller (Continued)

8 Individual Register Descriptions................................................................................................................2-22

8.1 Clock Source Control Registers

(LOCKCON0, LOCKCON1, OSCSET, MPLLCON, and EPLLCON)..............................................2-22

8.2 Clock Control Register (CLKSRC, CLKDIV, HCLKCON, PCLKCON, and SCLKCON).................2-25

8.3 Power Management Registers (PWRMODE and PWRCFG) .........................................................2-31

8.4 Reset Control Registers (SWRST and RSTCON)...........................................................................2-33

8.5 Control of retention PAD(I/O) when normal mode and wake-up from sleep mode.........................2-34

8.6 System Controller Status Registers (WKUPSTAT and RSTSTAT).................................................2-35

8.7 Bus Configuration Register (BUSPRI0, BUSPRI1, and BUSMISC)................................................2-36

8.8 Information Register 0,1,2,3 ............................................................................................................2-37

8.9 USB PHY Control register (PHYCTRL)...........................................................................................2-38

8.10 USB PHY Power Control Register (PHYPWR) .............................................................................2-39

8.11 USB Reset Control Register (URSTCON).....................................................................................2-39

8.12 USB Clock Control Register (UCLKCON).....................................................................................2-40

Chapter 3 Bus Matrix & EBI

1 Overview....................................................................................................................................................3-1

2 Special Function Registers .......................................................................................................................3-2

2.1 Matrix Core 0 Priority Register (Bpriority0)......................................................................................3-2

2.2 Matrix Core 1 Priority Register (Bpriority1)......................................................................................3-2

2.3 EBI Control Register (EBICON).......................................................................................................3-3

Chapter 4 Bus Priorities

1 Overview....................................................................................................................................................4-1

1.1 Bus Priority MAP..............................................................................................................................4-1

ii S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 5 Static Memory Controller (SMC)

1 Overview..................................................................................................................... ..............................5-1

2 Feature......................................................................................................................................................5-2

3 Block Diagram...........................................................................................................................................5-3

3.1 Asynchronous Read........................................................................................................................5-4

3.2 Asynchronous Burst Read...............................................................................................................5-6

3.3 Synchronous Read/Synchronous Burst Read.................................................................................5-7

3.4 Asynchronous Write ........................................................................................................................5-8

3.5 Synchronous Write/ Synchronous Burst Write................................................................................5-10

3.6 Bus Turnaround...............................................................................................................................5-11

4 Special Registers......................................................................................................................................5-14

4.1 Bank Idle Cycle Control Registers 0-5 ............................................................................................5-14

4.2 Bank Read Wait State Control Registers 0-5..................................................................................5-14

4.3 Bank Write Wait State Control Registers 0-5..................................................................................5-15

4.4 Bank Output Enable Assertion Delay Control Registers 0-5...........................................................5-15

4.5 Bank Write Enable Assertion Delay Control Registers 0-5.............................................................5-16

4.6 Bank Control Registers 0-5 .............................................................................................................5-17

4.7 Bank Onenand Type Selection Register.........................................................................................5-19

4.8 SMC Status Register.......................................................................................................................5-19

4.9 SMC Control Register......................................................................................................................5-20

Chapter 6 Mobile DRAM Controller

1 Overview..................................................................................................................... ..............................6-1

2 Block Diagram...........................................................................................................................................6-2

3 Mobile DRAM Initialization Sequence.......................................................................................................6-3

3.1 Mobile DRAM(SDRAM or mobile DDR) Initialization Sequence.....................................................6-3

3.2 DDR2 Initialization Sequence..........................................................................................................6-3

3.3 Mobile DRAM Configuration Register .............................................................................................6-8

3.4 Mobile DRAM Control Register.......................................................................................................6-9

3.5 Mobile DRAM Timming Control Register ........................................................................................6-10

3.6 Mobile DRAM (Extended ) Mode RegiSter Set Register.................................................................6-11

3.7 Mobile DRAM Refresh Control Register .........................................................................................6-14

3.8 Mobile DRAM Write Buffer Time out Register.................................................................................6-14

S3C2416X RISC MICROPROCESSOR iii

Table of Contents (Continued)

Chapter 7 NAND Flash Controller

1 Overview....................................................................................................................................................7-1

2 Features ....................................................................................................................................................7-1

3 Block Diagram...........................................................................................................................................7-2

4 Boot Loader Function................................................................................................................................7-2

5 GPC5/6/7 Pin Configuration Table in IROM Boot Mode...........................................................................7-3

6 NAND Flash Memory Timing ....................................................................................................................7-3

7 NAND Flash Access..................................................................................................................................7-4

8 Data Register Configuration......................................................................................................................7-5

9 Steppingstone (8KB in 64KB SRAM)........................................................................................................7-5

10 1bit / 4bit / 8bit ECC (Error Correction Code) .......................................................................................7-5

10.1 ECC Module Features...................................................................................................................7-5

10.2 1-bit ECC Programming Encoding and Decoding.........................................................................7-7

10.3 4-bit ECC Programming Guide (ENCODING)...............................................................................7-7

10.4 4-bit ECC Programming Guide (DECODING)...............................................................................7-8

10.5 8-bit ECC Programming Guide (ENCODING)...............................................................................7-8

10.6 8-bit ECC Programming Guide (DECODING)...............................................................................7-9

11 Memory Mapping(NAND boot and Other boot).......................................................................................7-10

12 NAND Flash Memory Configuration........................................................................................................7-11

13 NAND Flash Controller Special Registers ..............................................................................................7-12

13.1 NAND Flash Controller Register Map............................................................................................7-12

13.2 Nand Flash Configuration Register ...............................................................................................7-13

13.3 Control Regis

13.4 Command Register........................................................................................................................7-17

13.5 Address Register ...........................................................................................................................7-17

13.6 Data Register.................................................................................................................................7-17

13.7 Main Data area ECC Register.......................................................................................................7-18

13.8 Spare area ECC Register..............................................................................................................7-18

13.9 Progrmmable Block Address Register...........................................................................................7-19

13.10 NFCON Status Register ..............................................................................................................7-21

13.11 ECC0/1 Error Status Register......................................................................................................7-22

13.12 Main Data Area ECC0 Status Register .......................................................................................7-24

13.13 Spare Area ECC Status Register ................................................................................................7-25

13.14 4-bit ECC Error Patten Register ..................................................................................................7-25

13.15 ECC 0/1/2 for 8bit ECC Status Register......................................................................................7-26

13.16 8bit ECC Main Data ECC 0/1/2/3 Status Register.......................................................................7-27

13.17 8bit ECC Error Pattern Register ..................................................................................................7-28

ter.............................................................................................................................7-15

iv S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 8 DMA Controller

1 Overview..................................................................................................................... ..............................8-1

2 DMA Request Sources .............................................................................................................................8-2

3 DMA Operation .........................................................................................................................................8-3

3.1 External DMA Dreq/Dack Protocol..................................................................................................8-4

3.2 Examples of Possible Cases...........................................................................................................8-7

4 DMA Special Registers.............................................................................................................................8-8

4.1 DMA Initial Source Register (DISRC)..............................................................................................8-8

4.2 DMA Initial Source Control Register (DISRCC)..............................................................................8-9

4.3 DMA Initial Destination Register (DIDST) .......................................................................................8-10

4.4 DMA Initial Destination Control Register (DIDSTC)........................................................................8-11

4.5 DMA Control Register (DCON) .......................................................................................................8-12

4.6 DMA Status Register (DSTAT)........................................................................................................8-14

4.7 DMA Current Source Register (DCSRC) ........................................................................................8-15

4.8 Current Destination Register (DCDST)...........................................................................................8-15

4.9 DMA Mask Trigger Register (DMASKTRIG)...................................................................................8-16

4.10 DMA Requeset Selection Register (DMAREQSEL)......................................................................8-17

Chapter 9 Interrupt Controller

1 Overview..................................................................................................................... ..............................9-1

1.1 Interrupt Controller Operation..........................................................................................................9-3

1.2 Interrupt Sources.............................................................................................................................9-4

1.3 Interrupt Priority Generating Block..................................................................................................9-6

1.4 Interrupt Priority...............................................................................................................................9-7

2 Interrupt Controller Special Registers.......................................................................................................9-8

2.1 Source Pending (SRCPND) Register..............................................................................................9-10

2.2 Interrupt Mode (INTMOD) Register.................................................................................................9-12

2.3 Interrupt Mask (INTMSK) Register..................................................................................................9-14

2.4 Interrupt Pending (INTPND) Register..............................................................................................9-16

2.5 Interrupt Offset (INTOFFSET) Register...........................................................................................9-18

2.6 Sub Source Pending (SUBSRCPND) Register...............................................................................9-20

2.7 Interrupt Sub Mask (INTSUBMSK) Register...................................................................................9-22

2.8 Priority Mode Register (priority_MODE)..........................................................................................9-24

2.9 Priority Update Register (priority_UPDATE)...................................................................................9-29

S3C2416X RISC MICROPROCESSOR v

Table of Contents (Continued)

Chapter 10 I/O Ports

1 Overview....................................................................................................................................................10-1

2 Port Control Descriptions ..........................................................................................................................10-9

2.1 Port Configuration Register (GPACON-GPMCON).........................................................................10-9

2.2 Port Data Register (GPADAT-GPMDAT) ........................................................................................10-9

2.3 Port Pull-Up/Down Register (GPBUDP-GPMUDP).........................................................................10-9

2.4 Miscellaneous Control Register.......................................................................................................10-9

2.5 External Interrupt Control Register..................................................................................................10-9

3 I/O Port Control Register...........................................................................................................................10-10

3.1 PORT A Control Registers (GPACON, GPADAT)...........................................................................10-10

3.2 PORT B Control Registers (GPBCON, GPBDAT, GPBUDP, GPBSEL).........................................10-12

3.3 PORT C Control Registers (GPCCON, GPCDAT, GPCUDP) ........................................................10-14

3.4 PORT D Control Registers (GPDCON, GPDDAT, GPDUDP) ........................................................10-16

3.5 PORT E Control Registers (GPECON, GPEDAT, GPEUDP, GPESEL).........................................10-18

3.6 PORT F Control Registers (GPFCON, GPFDAT, GPFUDP)..........................................................10-20

3.7 PORT G Control Registers (GPGCON, GPGDAT, GPGUDP)........................................................10-21

3.8 PORT H Control Registers (GPHCON, GPHDAT, GPHUDP) ........................................................10-23

3.9 PORT J Control Registers (GPJCON, GPJDAT, GPJUDP, GPJSEL)............................................10-25

3.10 PORT K Control Registers (GPKCON, GPKDAT, GPKUDP).......................................................10-27

3.11 PORT L Control Registers (GPLCON, GPLDAT, GPLUDP, GPLSEL).........................................10-29

3.12 PORT M Control Registers (GPMCON, GPMDAT, GPMUDP).....................................................10-31

3.13 Miscellaneous Control Register (MISCCR)...................................................................................10-32

3.14 DCLK Control Regis

3.15 EXTINTn (External Interrupt Control Register n)...........................................................................10-35

3.16 EINTFLTn (External Interrupt Filter Register n).............................................................................10-40

3.17 EINTMASK (External Interrupt Mask Register).............................................................................10-41

3.18 EINTPEND (External Interrupt Pending Register).........................................................................10-42

3.19 GSTATUSn (General Status Registers)........................................................................................10-43

3.20 DSCn (Drive Strength Control)......................................................................................................10-44

3.21 PDDMCON (Power Down SDRAM Control Register)...................................................................10-48

3.22 PDSMCON (Power Down SRAM Control Register)......................................................................10-49

4 GPIO Alive & Sleep Part ..........................................................................................................................10-51

ters (DCLKCON)...........................................................................................10-34

vi S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 11 WatchDog Timer

1 Overview..................................................................................................................... ..............................11-1

1.1 Features...........................................................................................................................................11-1

2 Watchdog Timer Operation.......................................................................................................................11-2

2.1 Block Diagram.................................................................................................................................11-2

2.2 WTDAT & WTCNT ..........................................................................................................................11-2

2.3 Consideration of Debugging Environment ......................................................................................11-3

3 Watchdog Timer Special Registers ..........................................................................................................11-4

3.1 Watchdog Timer Control (WTCON) Register..................................................................................11-4

3.2 Watchdog Timer Data (WTDAT) Register.......................................................................................11-5

3.3 Watchdog Timer Count (WTCNT) Register ....................................................................................11-5

Chapter 12 PWM Timer

1 Overview..................................................................................................................... ..............................12-1

1.1 Feature ............................................................................................................................................12-1

2 PWM Timer Operation..............................................................................................................................12-3

2.1 Prescaler & Divider..........................................................................................................................12-3

2.2 Basic Timer Operation.....................................................................................................................12-4

2.3 Auto Reload & Double Buffering .....................................................................................................12-5

2.4 Timer Initialization Using Manual Update Bit and Inverter Bit.........................................................12-6

2.5 Timer Operation...............................................................................................................................12-7

2.6 Pulse Width Modulation (PWM) ......................................................................................................12-8

2.7 Output Level Control........................................................................................................................12-9

2.8 DEAD Zone Generator....................................................................................................................12-10

2.9 DMA Request Mode........................................................................................................................12-11

3 PWM Timer Control Registers.................................................................................................................12-12

3.1 Timer Configuration Register0 (TCFG0)..........................................................................................12-12

3.2 Timer Configuration Register1 (TCFG1).........................................................................................12-13

3.3 Timer Control (TCON) Register.......................................................................................................12-14

3.4 Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)...........................12-16

3.5 Timer 0 Count Observation Register (TCNTO0).............................................................................12-16

3.6 Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)...........................12-17

3.7 Timer 1 Count Observation Register (TCNTO1).............................................................................12-17

3.8 Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)...........................12-18

3.9 Timer 2 Count Observation Register (TCNTO2)

3.10 Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3).........................12-19

3.11 Timer 3 Count Observation Register (TCNTO3)...........................................................................12-19

3.12 Timer 4 Count Buffer Register (TCNTB4).....................................................................................12-20

3.13 Timer 4 Count Observation Register (TCNTO4)...........................................................................12-20

.............................................................................12-18

S3C2416X RISC MICROPROCESSOR vii

Table of Contents (Continued)

Chapter 13 Real Time Clock (RTC)

1 Overview....................................................................................................................................................13-1

1.1 Features...........................................................................................................................................13-1

1.2 Real Time Clock Operation Description ..........................................................................................13-2

1.3 External Interface.............................................................................................................................13-6

1.4 Register Description ........................................................................................................................13-7

1.5 Individual Register Descriptions ......................................................................................................13-8

Chapter 14 UART

1 Overview....................................................................................................................................................14-1

1.1 Features...........................................................................................................................................14-1

2 Block Diagram...........................................................................................................................................14-2

2.1 UART Operation ..............................................................................................................................14-3

3 UART Special Registers ...........................................................................................................................14-12

3.1 UART Line Control Register............................................................................................................14-12

3.2 UART Control Register....................................................................................................................14-13

3.3 UART FIFO Control Register...........................................................................................................14-15

3.4 UART Modem Control Register.......................................................................................................14-16

3.5 UART Tx/Rx Status Register...........................................................................................................14-17

3.6 UART Error Status Register ............................................................................................................14-18

3.7 UART FIFO Status Register ............................................................................................................14-19

3.8 UART Modem Status Register ........................................................................................................14-20

3.9 UART Transmit BUffer register (Holding Register & FIFO Register) ..............................................14-21

3.10 UART Receive BUffer Register (Holding Register & FIFO Register)............................................14-21

3.11 UART Baud RATE Divisor Register ..............................................................................................14-22

3.12 UART Dividing Slot Register..........................................................................................................14-23

Chapter 15 USB Host Controller

1 Overview....................................................................................................................................................14-1

1.1 USB Host Controller Special Registers ...........................................................................................14-2

viii S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 16 USB 2.0 Function

1 Overview..................................................................................................................... ..............................16-1

1.1 Feature ............................................................................................................................................16-1

2 Block Diagram...........................................................................................................................................16-2

3 To Activate USB Port1 for USB 2.0 Function ...........................................................................................16-3

4 SIE (Serial Interface Engine) ....................................................................................................................16-4

5 UPH (Universal Protocol Handler)............................................................................................................16-4

6 UTMI (USB 2.0 Transceiver Macrocell Interface).....................................................................................16-4

7 USB 2.0 Function Controller Special Registers........................................................................................16-5

8 Registers...................................................................................................................................................16-7

8.1 Index Register (IR) ..........................................................................................................................16-7

8.2 Endpoint Interrupt Register (EIR)....................................................................................................16-8

8.3 Endpoint Interrupt Enable Register (EIER) .....................................................................................16-9

8.4 Function Address Register (FAR) ...................................................................................................16-10

8.5 ENdpoint Direction Register (EDR).................................................................................................16-11

8.6 Test Register (TR)...........................................................................................................................16-12

8.7 System Status Register (SSR)........................................................................................................16-13

8.8 System Control Register (SCR) ......................................................................................................16-15

8.9 EP0 Status Register (EP0SR).........................................................................................................16-16

8.10 EP0 Control Register (EP0CR).....................................................................................................16-17

8.11 Endpoint# Buffer Register (EP#BR).............................................................................................16-18

8.12 Endpoint Status Register (ESR)

8.13 Endpoint Control Register (ECR)..................................................................................................16-21

8.14 Byte read Count Register (BRCR) ................................................................................................16-22

8.15 Byte Write Count Register (BWCR) ..............................................................................................16-23

8.16 MAX Packet Register (MPR).........................................................................................................16-24

8.17 DMA Control Register (DCR)........................................................................................................16-25

8.18 DMA Transfer Counter Register (DTCR)......................................................................................16-26

8.19 DMA FIFO Counter Register (DFCR) ...........................................................................................16-27

8.20 DMA Total Transfer Counter Register 1/2 (DTTCR 1/2)...............................................................16-28

8.21 DMA Interface Control Register (DICR)........................................................................................16-29

8.22 Memory Base Address Register (MBAR)......................................................................................16-30

8.23 Memory Current Address Register (MCAR)..................................................................................16-31

8.24 Burst FIFO Control Register(FCON).............................................................................................16-31

8.25 Burst FIFO Status Register(FSTAT) .............................................................................................16-31

8.26 AHB Master(DMA) Operation Flow Chart.....................................................................................16-32

....................................................................................................16-19

S3C2416X RISC MICROPROCESSOR ix

Table of Contents (Continued)

Chapter 17 IIC-Bus Interface

1 Overview....................................................................................................................................................17-1

1.1 IIC-Bus Interface..............................................................................................................................17-3

1.2 Start And Stop Conditions ...............................................................................................................17-3

1.3 Data Transfer Format ......................................................................................................................17-4

1.4 ACK Signal Transmission................................................................................................................17-5

1.5 Read-Write Operation......................................................................................................................17-6

1.6 Bus Arbitration Procedures..............................................................................................................17-6

1.7 Abort Conditions ..............................................................................................................................17-6

1.8 Configuring IIC-Bus..........................................................................................................................17-6

1.9 Flowcharts of Operations in Each Mode..........................................................................................17-7

2 IIC-Bus Interface Special Registers..........................................................................................................17-11

2.1 Multi-Master IIC-Bus Control (IICCON) Register.............................................................................17-11

2.2 Multi-Master IIC-Bus Control/Status (IICSTAT) Register ................................................................17-12

2.3 Multi-Master IIC-Bus Address (IICADD) Register ...........................................................................17-13

2.4 Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register ..............................................17-13

2.5 Multi-Master IIC-Bus Line Control(IICLC) Register .........................................................................17-14

Chapter 18 2D

1 Introduction................................................................................................................................................18-1

1.1 Features...........................................................................................................................................18-1

2 Color Format Conversion..........................................................................................................................18-2

3 Command FIFO.........................................................................................................................................18-3

4 Rendering Pipeline....................................................................................................................................18-4

4.1 Primitive Drawing.............................................................................................................................18-4

4.2 Rotation............................................................................................................................................18-9

4.3 Clipping............................................................................................................................................18-11

4.4 Stencil Test......................................................................................................................................18-11

4.5 Raster Operation..............................................................................................................................18-11

4.6 Alpha Blending.................................................................................................................................18-13

5 Register Descriptions................................................................................................................................18-14

5.1 General Registers............................................................................................................................18-16

5.2 Command Registers........................................................................................................................18-19

5.3 Parameter Setting Registers............................................................................................................18-21

x S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 19 HS_SPI Controller

1 Overview..................................................................................................................... ..............................19-1

2 Features....................................................................................................................................................19-1

3 Signal Descriptions...................................................................................................................................19-2

4 Operation ..................................................................................................................................................19-2

4.1 Operation Mode...............................................................................................................................19-3

4.2 FIFO Access....................................................................................................................................19-3

4.3 Trailing Bytes in the Rx FIFO ..........................................................................................................19-3

4.4 Packet Number Control...................................................................................................................19-3

4.5 NCS Control ....................................................................................................................................19-3

4.6 HS_SPI Transfer Format.................................................................................................................19-4

5 Special Function Register Descriptions....................................................................................................19-5

5.1 Setting Sequence of Special Function Register..............................................................................19-5

5.2 Special Function Register ...............................................................................................................19-6

Chapter 20 SD/MMC Host Controller

1 Overview..................................................................................................................... ..............................20-1

2 Features....................................................................................................................................................20-1

3 Block Diagram...........................................................................................................................................20-2

4 Sequence..................................................................................................................................................20-3

4.1 SD Card Detection Sequence.........................................................................................................20-3

4.2 SD Clock Supply Sequence............................................................................................................20-4

4.3 SD Clock Stop Sequence................................................................................................................20-5

4.4 SD Clock Frequency Change Sequence ........................................................................................20-5

4.5 SD Bus Power Control Sequence...................................................................................................20-6

4.6 Change Bus Width Sequence.........................................................................................................20-7

4.7 Timeout Setting for DAT Line..........................................................................................................20-8

4.8 SD Transaction Generation.............................................................................................................20-8

4.9 SD Command Issue Sequence.......................................................................................................20-9

4.10 Command Complete Sequence....................................................................................................20-10

4.11 Transaction Control with Data Transfer Using DAT Line..............................................................20-12

4.12 Abort Transaction..........................................................................................................................20-16

5 SDI Special Registers...............................................................................................................................20-17

5.1 Configuration Register Types..........................................................................................................20-17

5.2 SDMA System Address Register ....................................................................................................20-18

5.3 Block Size Register .........................................................................................................................20-19

5.4 Block Count Register.......................................................................................................................20-21

5.5 Argument Register...........................................................................................................................20-22

5.6 Transfer Mode Register...................................................................................................................20-23

5.7 Command Register..........................................................................................................................20-25

5.8 Response Register..........................................................................................................................20-27

5.9 Buffer Data Port Register ................................................................................................................20-29

5.10 Present State Regis

5.11 Host Control Register....................................................................................................................20-36

5.12 Power Control Register .................................................................................................................20-37

ter ..................................................................................................................20-30

S3C2416X RISC MICROPROCESSOR xi

Table of Contents (Continued)

Chapter 20 SD/MMC Host Controller (Continued)

5.13 Block Gap Control Register...........................................................................................................20-38

5.14 Wakeup Control Register...............................................................................................................20-40

5.15 Clock Control Register...................................................................................................................20-41

5.16 Timeout Control Register...............................................................................................................20-43

5.17 Software Reset Register................................................................................................................20-44

5.18 Normal Interrupt Status Register...................................................................................................20-46

5.19 Error Interrupt Status Register.......................................................................................................20-50

5.20 Normal Interrupt Status Enable Register.......................................................................................20-53

5.21 Error Interrupt Status Enable Register ..........................................................................................20-55

5.22 Normal Interrupt Signal Enable Register.......................................................................................20-56

5.23 Error Interrupt Signal Enable Register...........................................................................................20-58

5.24 Autocmd12 Error Status Register..................................................................................................20-59

5.25 Capabilities Register......................................................................................................................20-61

5.26 Maximum Current Capabilities Register........................................................................................20-63

5.27 Control Register 2..........................................................................................................................20-64

5.28 Control Register 3..........................................................................................................................20-67

5.29 Debug Register..............................................................................................................................20-68

5.30 Control Register 4..........................................................................................................................20-68

5.31 Force Event Register for Auto CMD12 Error Status......................................................................20-69

5.32 Force Event Register for Error Interrupt Status.............................................................................20-70

5.33 ADMA Error Status Register..........................................................................................................20-71

5.34 ADMA System Address Register...................................................................................................20-73

5.35 HOST Controller Version Register ................................................................................................20-74

Chapter 21 LCD Controller

1 Overview....................................................................................................................................................21-1

1.1 Features...........................................................................................................................................21-2

2 Functional Description...............................................................................................................................21-3

2.1 Brief of the sub-block.......................................................................................................................21-3

2.2 Data Flow.........................................................................................................................................21-3

2.3 Interface...........................................................................................................................................21-4

2.4 Overview of the Color Data..............................................................................................................21-5

2.5 VD signal Connection ......................................................................................................................21-18

2.6 Palette usage...................................................................................................................................21-20

3 Window Blending.......................................................................................................................................21-22

3.1 Overview..........................................................................................................................................21-22

3.2 Blending Diagram/Details................................................................................................................21-23

4 Vtime Controller Operation........................................................................................................................21-26

4.1 RGB Interface..................................................................................................................................21-26

4.2 I80-System Interface........................................................................................................................21-26

5 Virtual Display ...........................................................................................................................................21-27

6 RGB Interface I/O......................................................................................................................................21-28

7 LCD CPU Interface I/O (I80-system I/F) ...................................................................................................21-29

8 Programmer’s Model.................................................................................................................................21-31

8.1 Overview..........................................................................................................................................21-31

xii S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 22 ADC & Touch Screen Interface

1 Overview..................................................................................................................... ..............................22-1

1.1 Features...........................................................................................................................................22-1

2 ADC & Touch Screen Interface Operation................................................................................................22-2

2.1 Block Diagram.................................................................................................................................22-2

2.2 Function Descriptions......................................................................................................................22-3

3 ADC and Touch Screen Interface Special Registers................................................................................22-5

3.1 ADC Control (ADCCON) Register...................................................................................................22-5

3.2 ADC Touch Screen Control (ADCTSC) Register............................................................................22-6

3.3 ADC Start Delay (ADCDLY) Register..............................................................................................22-7

3.4 ADC Conversion Data (ADCDAT0) Register..................................................................................22-8

3.5 ADC Conversion Data (ADCDAT1) Register..................................................................................22-9

3.6 ADC Touch Screen up-Down Int Check Register (ADCUPDN)......................................................22-9

3.7 ADC Channel Mux Register (ADCMUX).........................................................................................22-10

Chapter 23 IIS Multi Audio Interface

1 Overview..................................................................................................................... ..............................23-1

2 Feature......................................................................................................................................................23-1

3 Signals ......................................................................................................................................................23-1

4 Block Diagram...........................................................................................................................................23-2

5 Functional Descriptions.............................................................................................................................23-2

5.1 Master/Slave Mode..........................................................................................................................23-3

5.2 DMA Transfer ..................................................................................................................................23-4

6 Audio Serial Data Format..........................................................................................................................23-5

6.1 IIS-Bus Format ................................................................................................................................23-5

6.2 MSB (Left) Justified .........................................................................................................................23-5

6.3 LSB (Right) Justified........................................................................................................................23-5

6.4 Sampling Frequency and Master Clock ..........................................................................................23-7

6.5 IIS Clock Mapping Table .................................................................................................................23-7

7 Programming Guide..................................................................................................................................23-8

7.1 Initialization......................................................................................................................................23-8

7.2 Play Mode (TX mode) with DMA.....................................................................................................23-8

7.3 Recording Mode (RX mode) with DMA...........................................................................................23-8

7.4 Example Code.................................................................................................................................23-9

8 IIS-BUS Interface Special Registers.........................................................................................................23-15

8.1 IIS Control Register (IISCON) .........................................................................................................23-16

8.2 IIS Mode Register (IISMOD) ...........................................................................................................23-18

8.3 IIS FIFO Control Register (IISFIC)..................................................................................................23-20

8.4 IIS Pres

8.5 IIS Transmit Register (IISTXD)........................................................................................................23-21

8.6 IIS Receive Register (IISRXD) .......................................................................................................23-21

caler Control Register (IISPSR)..........................................................................................23-20

S3C2416X RISC MICROPROCESSOR xiii

Table of Contents (Continued)

Chapter 24 AC97 Controller

1 Overview....................................................................................................................................................24-1

1.1 Feature.............................................................................................................................................24-1

1.2 Signals .............................................................................................................................................24-1

2 AC97 Controller Operation........................................................................................................................24-2

2.1 Block Diagram..................................................................................................................................24-2

2.2 Internal Data Path............................................................................................................................24-3

3 Operation Flow Chart................................................................................................................................24-4

4 AC-link Digital Interface Protocol ..............................................................................................................24-5

4.1 AC-link Output Frame (SDATA_OUT).............................................................................................24-6

4.2 AC-link Input Frame (SDATA_IN)....................................................................................................24-7

5 AC97 Power-Down....................................................................................................................................24-9

6 Codec Reset..............................................................................................................................................24-10

7 AC97 Controller State Diagram.................................................................................................................24-11

8 AC97 Controller Special Registers............................................................................................................24-12

8.1 AC97 Special Funcion Register Summary......................................................................................24-12

8.2 AC97 Global Control Register (AC_GLBCTRL)..............................................................................24-13

8.3 AC97 Global Status Register (AC_GLBSTAT)................................................................................24-14

8.4 AC97 Codec Command Register (AC_CODEC_CMD) ..................................................................24-14

8.5 AC97 Codec Status Register (AC_CODEC_STAT)........................................................................24-15

8.6 AC97 PCM Out/In Channel Fifo Address Register (AC_PCMADDR).............................................24-15

8.7 AC97 MIC In Channel FIFO Address Register (AC_MICADDR) ....................................................24-16

8.8 AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA)

8.9 AC97 MIC In Channel FIFO Data Register (AC_MICDATA)...........................................................24-16

.................................................24-16

xiv S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 25 PCM Audio Interface

1 Overview..................................................................................................................... ..............................25-1

1.1 Feature ............................................................................................................................................25-1

1.2 Signals.............................................................................................................................................25-1

2 PCM Audio Interface.................................................................................................................................25-2

3 PCM Timing ..............................................................................................................................................25-3

3.1 PCM Input Clock Diagram...............................................................................................................25-4

3.2 PCM Registers ................................................................................................................................25-5

3.3 PCM Register Summary..................................................................................................................25-5

3.4 PCM Control Register......................................................................................................................25-6

3.5 PCM CLK Control Register .............................................................................................................25-8

3.6 The PCM Tx FIFO Register.............................................................................................................25-9

3.7 PCM Rx FIFO Register....................................................................................................................25-10

3.8 PCM Interrupt Control Register.......................................................................................................25-11

3.9 PCM Interrupt Status Register ........................................................................................................25-14

3.10 PCM FIFO Status Register............................................................................................................25-16

3.11 PCM Interrupt Clear Register........................................................................................................25-17

Chapter 26 Electrical Data

1 Absolute Maximum Ratings......................................................................................................................26-1

2 Recommended Operating Conditions.......................................................................................................26-2

3 D.C. Electrical Characteristics ..................................................................................................................26-4

4 A.C. Electrical Characteristics ..................................................................................................................26-6

Chapter 27 Mechanical Data

1 Package Dimensions........................................................................................................... .....................27-1

S3C2416X RISC MICROPROCESSOR xv

List of Figures

Figure Title Page Number Number

1-1 S3C2416 Block Diagram..............................................................................................1-5

1-2 S3C2416 Pin Assignments (400-FBGA) Top view......................................................1-6

1-3 Memory Map ................................................................................................................1-32

2-1 System Controller Block Diagram................................................................................2-2

2-2 Power-On Reset Sequence.........................................................................................2-4

2-3 Clock Generator Block Diagram ..................................................................................2-6

2-4 Main Oscillator Circuit Examples.................................................................................2-7

2-5 PLL(Phase-Locked Loop) Block Diagram....................................................................2-8

2-6 The Case that Changes Slow Clock by Setting PMS Value........................................2-8

2-7 The Clock Distribution Block Diagram .........................................................................2-9

2-8 MPLL Based Clock Domain.........................................................................................2-9

2-9 EPLL Based Clock Domain..........................................................................................2-12

2-10 Power Mode State Diagram.........................................................................................2-13

2-11 Entering STOP Mode and Exiting STOP Mode (wake-up)..........................................2-17

2-12 Entering SLEEP Mode and Exiting SLEEP Mode (wake-up) ......................................2-18

2-13 Usage of PWROFF_SLP .............................................................................................2-34

3-1 The Configuration of MATRIX and Memory Sub-System of S3C2416........................3-1

5-1 SMC Block Diagram.....................................................................................................5-3

5-2 SMC Core Block Diagram............................................................................................5-3

5-3 External Memory Two Output Enable Delay State Read.............................................5-4

5-4 Read Timing Diagram (DRnCS = 1, DRnOWE = 0)....................................................5-4

5-5 Read Timing Diagram (DRnCS = 1, DRnOWE = 1)....................................................5-5

5-6

5-7 External Synchronous Fixed Length Four Transfer Burst Read..................................5-7

5-8 External Memory Two Write Enable Delay State Write...............................................5-8

5-9 Write Timing Diagram (DRnCS = 1, DRnOWE = 0) ....................................................5-9

5-10 Write Timing Diagram (DRnCS = 1, DRnOWE = 1) ....................................................5-9

5-11 Synchronous Two Wait State Write.............................................................................5-10

5-12 Read, then two Writes (WSTRD=WSTWR=0), Two Turnaround Cycles (IDCY=2)....5-11

5-13 Memory Interface with 8-bit SRAM (2MB) ...................................................................5-13

5-14 Memory Interface with 16-bit SRAM (4MB) .................................................................5-13

6-1 Mobile DRAM Controller Block Diagram......................................................................6-2

6-2 Memory Interface with 16-bit SDRAM (4Mx16, 4banks) .............................................6-4

6-3 Memory Interface with 32-bit SDRAM (4Mx16 * 2ea, 4banks)....................................6-4

6-4 Memory Interface with 16-bit Mobile DDR and DDR2.................................................6-5

6-5 DRAM Timing Diagram................................................................................................6-6

6-6 CL (CAS Latency) Timing Diagram..............................................................................6-6

6-7 t

External Burst ROM with WSTRD=2 and WSTBRD=1 Fixed Length Burst Read......5-6

Timing Diagram..................................................................................................6-7

ARFC

xvi S3C2416X RISC MICROPROCESSOR

List of Figures

Figure Title Page Number Number

7-1 NAND Flash Controller Block Diagram........................................................................7-2

7-2 NAND Flash Controller Boot Loader Block Diagram...................................................7-2

7-3 CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) Block Diagram................7-3

7-4 nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram.................................7-4

7-5 NAND Flash Memory Mapping Block Diagram...........................................................7-10

7-6 A 8-bit NAND Flash Memory Interface Block Diagram................................................7-11

7-7 Softlock and Lock-tight ................................................................................................7-20

8-1 Basic DMA Timing Diagram.........................................................................................8-4

8-2 Demand/Handshake Mode Comparison.....................................................................8-5

8-3 Burst 4 Transfer size....................................................................................................8-6

8-4 Single service, Demand Mode, Single Transfer Size..................................................8-7

8-5 Single service, Handshake Mode, Single Transfer Size .............................................8-7

8-6 Whole service, Handshake Mode, Single Transfer Size.............................................8-7

9-1 Interrupt Process Diagram...........................................................................................9-1

9-2 Interrupt Group Multiplexing Diagram..........................................................................9-2

9-3 Priority Generating Block.............................................................................................9-6

11-1 Watchdog Timer Block Diagram..................................................................................11-2

12-1 16-bit PWM Timer Block Diagram...............................................................................12-2

12-2 Timer Operations.........................................................................................................12-4

12-3 Example of Double Buffering Function........................................................................12-5

12-4 Example of a Timer Operation.....................................................................................12-7

12-5

12-6 Inverter On/Off.............................................................................................................12-9

12-7 The Wave Form When a Dead Zone Feature is Enabled...........................................12-10

12-8 Timer4 DMA Mode Operation......................................................................................12-11

Example of PWM.........................................................................................................12-8

S3C2416X RISC MICROPROCESSOR xvii

List of Figures

Figure Title Page Number Number

13-1 Real Time Clock Block Diagram..................................................................................13-2

13-2 RTC Tick Interrupt Clock Scheme ...............................................................................13-5

13-3 Main Oscillator Circuit Example...................................................................................13-6

14-1 UART Block Diagram (with FIFO)................................................................................14-2

14-2 UART AFC Interface....................................................................................................14-4

14-3 Example showing UART Receiving 5 Characters with 2 Errors..................................14-7

14-4 IrDA Function Block Diagram.......................................................................................14-8

14-5 Serial I/O Frame Timing Diagram (Normal UART)......................................................14-9

14-6 Infrared Transmit Mode Frame Timing Diagram..........................................................14-9

14-7 Infrared Receive Mode Frame Timing Diagram...........................................................14-9

14-8 nCTS and Delta CTS Timing Diagram.........................................................................14-20

15-1 USB Host Controller Block Diagram............................................................................15-1

16-1 USB2.0 Block Diagram ................................................................................................16-2

16-2 USB2.0 Function Block Diagram .................................................................................16-3

16-3 OUT Transfer Operation Flow......................................................................................16-32

16-4 IN Transfer Operation Flow..........................................................................................16-33

17-1 IIC-Bus Block Diagram.................................................................................................17-2

17-2 Start and Stop Condition..............................................................................................17-3

17-3 IIC-Bus Interface Data Format.....................................................................................17-4

17-4 Data Transfer on the IIC-Bus.......................................................................................17-5

17-5 Acknowledge on the IIC-Bus........................................................................................17-5

17-6 Operations for Master/Trans

17-7 Operations for Master/Receiver Mode.........................................................................17-8

17-8 Operations for Slave/Transmitter Mode.......................................................................17-9

17-9 Operations for Slave/Receiver Mode...........................................................................17-10

18-1 Color Format................................................................................................................18-2

18-2 YUV 2-Planar Format...................................................................................................18-3

18-3 2D Rendering Pipeline.................................................................................................18-4

18-4 Data Format.................................................................................................................18-4

18-5 Transparent Mode........................................................................................................18-6

18-6 Color Expansion...........................................................................................................18-8

18-7 Font Drawing with Transparent Mode..........................................................................18-8

18-8 Rotation Example.........................................................................................................18-10

mitter Mode.....................................................................17-7

xviii S3C2416X RISC MICROPROCESSOR

List of Figures

Figure Title Page Number Number

19-1 HS_SPI Transfer Format.............................................................................................19-4

20-1 HSMMC Block Diagram...............................................................................................20-2

20-2 SD Card Detect Sequence ..........................................................................................20-3

20-3 SD Clock Supply Sequence ........................................................................................20-4

20-4 SD Clock Stop Sequence............................................................................................20-5

20-5 SD Clock Change Sequence.......................................................................................20-5

20-6 SD Bus Power Control Sequence ...............................................................................20-6

20-7 Change Bus Width Sequence .....................................................................................20-7

20-8 Timeout Setting Sequence ..........................................................................................20-8

20-9 Timeout Setting Sequence ..........................................................................................20-9

20-10 Command Complete Sequence..................................................................................20-11

20-11 Transaction Control with Data Transfer Using DAT Line Sequence (Not using DMA) 20-13

20-12 Transaction Control with Data Transfer Using DAT Line Sequence (Using DMA).....20-15

20-13 Card Detect State........................................................................................................20-34

20-14 Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer...20-35

20-15 Timing of Command Inhibit (DAT) for the case of response with busy.......................20-35

20-16 Timing of Command Inhibit (CMD) for the case of no response command................20-35

21-1 LCD Controller Block diagram.....................................................................................21-1

21-2 Block diagram of the Data Flow...................................................................................21-4

21-3 16BPP(1+5:5:5, BSWP/HWSWP=0) Display Types...................................................21-12

21-4 16BPP(5:6:5, BSWP/HWSWP=0) Display Types .......................................................21-13

21-5 Blending Operations....................................................................................................21-22

21-6 Color Key Block Diagram.............................................................................................21-24

21-7 Color Key Operations ..................................................................................................21-24

21-8 Color Key Function Configurations..............................................................................21-25

21-9 Example of Scrolling in Virtual Display........................................................................21-27

21-10 LCD RGB Interface Timing..........................................................................................21-28

21-11 Write Cycle Timing.......................................................................................................21-29

S3C2416X RISC MICROPROCESSOR xix

List of Figures

Figure Title Page Number Number

22-1 ADC and Touch Screen Interface Block Diagram .......................................................22-2

22-2 Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode.........................22-4

23-1 IIS-Bus Block Diagram.................................................................................................23-2

23-2 IIS Clock Control Block Diagram..................................................................................23-3

23-3 IIS Audio Serial Data Formats .....................................................................................23-6

23-4 TX FIFO Structure for BLC = 00 or BLC = 01..............................................................23-10

23-5 TX FIF0 Structure for BLC = 10 (24-bits/channel).......................................................23-11

23-6 RX FIFO Structure for BLC = 00 or BLC = 01 .............................................................23-13

23-7 RX FIF0 Structure for BLC = 10 (24-bits/channel).......................................................23-14

24-1 AC97 Block Diagram....................................................................................................24-2

24-2 Internal Data Path........................................................................................................24-3

24-3 AC97 Operation Flow Chart.........................................................................................24-4

24-4 Bi-directional AC-link Frame with Slot Assignments....................................................24-5

24-5 AC-link Output Frame ..................................................................................................24-6

24-6 AC-link Input Frame.....................................................................................................24-8

24-7 AC97 Power-down Timing...........................................................................................24-9

24-9 AC97 State Diagram....................................................................................................24-11

25-1 PCM timing, TX_MSB_POS / RX_MSB_POS = 0.......................................................25-3

25-2 PCM timing, TX_MSB_POS / RX_MSB_POS = 1.......................................................25-3

25-3 Input Clock Diagram for PCM......................................................................................25-4

xx S3C2416X RISC MICROPROCESSOR

List of Figures

Figure Title Page Number Number

26-1 XTIpll Clock Timing......................................................................................................26-7

26-2 EXTCLK Clock Input Timing........................................................................................26-7

26-3 EXTCLK/HCLK in case that EXTCLK is used without the PLL...................................26-7

26-4 HCLK/CLKOUT/SCLK in case that EXTCLK is used..................................................26-8

26-5 Manual Reset Input Timing..........................................................................................26-8

26-6 Power-On Oscillation Setting Timing...........................................................................26-9

26-7 Sleep Mode Return Oscillation Setting Timing............................................................26-10

26-8 SMC Synchronous Read Timing.................................................................................26-11

26-9 SMC Asynchronous Read Timing ...............................................................................26-11

26-10 SMC Asynchronous Write Timing................................................................................26-12

26-11 SMC Synchronous Write Timing.................................................................................26-12

26-12 SMC Wait Timing.........................................................................................................26-13

26-13 Nand Flash Timing.......................................................................................................26-14

26-14 SDRAM READ / WRITE Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit)..................26-15

26-15 DDR2 Timing...............................................................................................................26-16

26-16 SDRAM MRS Timing...................................................................................................26-17

26-17 SDRAM Auto Refresh Timing (Trp = 2, Trc = 4).........................................................26-18

26-18 External DMA Timing (Handshake, Single transfer)....................................................26-19

26-19 TFT LCD Controller Timing..........................................................................................26-19

26-20 IIS Interface Timing (I2S Master Mode Only)..............................................................26-20

26-21 IIS Interface Timing (I 2S Slave Mode Only)................................................................26-20

26-22 IIC Interface Timing.....................................................................................................26-20

26-23

26-24 High Speed SPI Interface Timing (CPHA = 0, CPOL = 0)...........................................26-21

26-25 USB Timing (Data signal rise/fall time)........................................................................26-22

26-26 PCM Interf ace Timing..................................................................................................26-22

27-1 400-FBGA-1313 Package Dimension 1 (Top View)....................................................27-1

27-2 400-FBGA-1313 Package Dimension 2 (Bottom View)...............................................27-2

High Speed SDMMC Interface Timing ........................................................................26-21

S3C2416X RISC MICROPROCESSOR xxi

List of Tables

Table Title Page Number Number

1-1 400-Pin FBGA Pin Assignments − Pin Number Order (1/4)........................................1-7

1-1 400-Pin FBGA Pin Assignments − Pin Number Order (2/4)........................................1-8

1-1 400-Pin FBGA Pin Assignments − Pin Number Order (3/4)........................................1-9

1-1 400-Pin FBGA Pin Assignments – Pin Number Order (4/4)........................................1-10

1-2 S3C2416 400-Pin FBGA Pin Assignments..................................................................1-11

1-3 I/O Cell Types and Descriptions ..................................................................................1-23

1-4 S3C2416 Signal Descriptions......................................................................................1-24

1-5 S3C2416 Operation Mode Description........................................................................1-31

1-6 Base Address of Special Registers..............................................................................1-33

1-7 S3C2416 Special Registers.........................................................................................1-34

2-1 Registers & GPIO Status in RESET (R: reset, S: sustain previous value)..................2-5

2-2 Clock source selection for the main PLL and clock generation logic ..........................2-6

2-3 Clock Source Selection for the EPLL...........................................................................2-7

2-4 PLL & Clock Generator Condition................................................................................2-7

2-5 Clock Division Ratio of MPLL Region..........................................................................2-10

2-6 ESYSCLK Control........................................................................................................2-12

2-7 The Status of PLL and ARMCLK After Wake-up.........................................................2-19

2-8 Power Saving Mode Entering/Exiting Condition..........................................................2-20

2-9 System Controller Address Map..................................................................................2-21

8-1 DMA request sources for each channel.......................................................................8-2

10-1 S3C2416 Port Configuration (Sheet 1)

13-1 RTC Register summary ...............................................................................................13-7

14-1 Example of nRTS signal change by FIFO Spare size

(In case of Reception Case in UART A) ......................................................................14-4

14-2 Interrupts in Connection with FIFO..............................................................................14-6

14-3 Clock, EPLL Speed Guide ...........................................................................................14-11

14-4 Recommended Value Table of DIVSLOTn Register ...................................................14-23

15-1 OHCI Registers for USB Host Controller.....................................................................15-2

........................................................................10-2

xxii S3C2416X RISC MICROPROCESSOR

List of Tables

Table Title Page Number Number

16-1 Non-Indexed Registers................................................................................................16-5

16-2 Indexed Registers........................................................................................................16-6

19-1 External Signals Description........................................................................................19-2

20-1 Determination of Transfer Type...................................................................................20-24

20-2 Relation Between Parameters and the Name of Response Type...............................20-26

20-3 Response Bit Definition for Each Response Type. .....................................................20-27

20-4 The relation between Command CRC Error and Command Timeout Error ...............20-52

20-5 The Relation Between Command CRC Error and Command Timeout Error..............20-60

20-6 Maximum Current Value Definition..............................................................................20-63

21-1 25BPP(A:8:8:8) Palette Data Format ..........................................................................21-20

21-2 19BPP (A:6:6:6) Palette Data Format .........................................................................21-21

21-3 16BPP(A:5:5:5) Palette Data Format ..........................................................................21-21

21-4 Alpha Value Selection Table for Blending...................................................................21-23

21-5 Relation between VCLK and CLKVAL (Freq. of Video Clock Source=60MHz)..........21-26

21-6 LCD Signal Muxing Table (RGB and i-80 I/F) .............................................................21-30

23-1 CODEC clock (CODECLK = 256fs, 384fs, 512fs, 768fs)............................................23-7

23-2 IIS Clock Mapping Table..............................................................................................23-7

24-1 Input Slot 1 Bit Definitions............................................................................................24-7

S3C2416X RISC MICROPROCESSOR xxiii

List of Tables

Table Title Page Number Number

26-1 Absolute Maximum Rating...........................................................................................26-1

26-2 Recommended Operating Conditions (400MHz).........................................................26-2

26-3 Recommended Operating Conditions (533MHz).........................................................26-3

26-4 Normal I/O PAD DC Electrical Characteristics ............................................................26-4

26-5 Special Memory DDR I/O PAD DC Electrical Characteristics.....................................26-5

26-6 USB DC Electrical Characteristics...............................................................................26-6

26-7 RTC OSC DC Electrical Characteristics......................................................................26-6

26-8 Clock Timing Constants...............................................................................................26-23

26-9 SMC Timing Constants................................................................................................26-24

26-10 NFCON Bus Timing Constants....................................................................................26-24

26-11 Memory Interface Timing Constants (SDRAM)...........................................................26-25

26-12 DMA Controller Module Signal Timing Constants.......................................................26-26

26-13 TFT LCD Controller Module Signal Timing Constants................................................26-26

26-14 IIS Controller Module Signal Timing Constants(I2S Master Mode Only) ....................26-26

26-15 IIS Controller Module Signal Timing Constants(I2S Slave Mode Only).......................26-27

26-16 IIC BUS Controller Module Signal Timing....................................................................26-27

26-17 High Speed SPI Interface Transmit/Receive Timing Constants.................................26-28

26-18 USB Electrical Specifications.......................................................................................26-28

26-19 USB Full Speed Output Buffer Electrical Characteristics.............................................26-29

26-20 USB High Speed Output Buffer Electrical Characteristics...........................................26-29

26-21 High Speed SDMMC Interface Transmit/Receive Timing Constants..........................26-29

26-22 PCM Interf ace Timing..................................................................................................26-30

xxiv S3C2416X RISC MICROPROCESSOR

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

1 INTRODUCTION

This user’s manual describes SAMSUNG's S3C2416X 16/32-bit RISC microprocessor. SAMSUNG’s S3C2416X is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2416X includes the following components.

The S3C2416X is developed with ARM926EJ core, 65nm CMOS standard cells and a memory complier. Its lowpower, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2416X offers outstanding features with its CPU core, a 16/32-bit ARM926EJ RISC processor designed by Advanced RISC Machines, Ltd. The ARM926EJ implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals, the S3C2416X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:

• Around 400MHz @ 1.3V, 266MHz @ TBDV Core, 1.8V/2.5V/3.0V/3.3V ROM/SRAM, 1.8V/2.5V mSDR/mDDR/DDR2 SDRAM, 1.8V/2.5V/3.3V external I/O microprocessor with 16KB I/D-Cache/MMU

• External memory controller (mSDR/mDDR/DDR2 SDRAM Control and Chip Select logic)

• LCD controller (up to 256K color) with LCD-dedicated DMA

• 6-ch DMA controllers with external request pins

• 4-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

• 1-ch High Speed SPls

• 1 IIC bus interfaces (multi-master support)

• 1 IIS Audio CODEC interfaces (24-bit, port 0 supports 5.1ch)

• AC97/PCM CODEC Interface(muxed with I2S)

• 2 High-Speed MMC and SDMMC combo (SD Host 2.0 and MMC protocol 4.2 compatible)

• 2-ch USB Host controller (ver 1.1 Compliant)/1-ch USB Device controller (ver 2.0 Compliant)

• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

• 10-ch 12-bit ADC and Touch screen interface

• RTC with calendar function

• 138 General Purpose I/O ports / 16-ch external interrupt source

• Power control: Normal, Idle, Stop, Deep Stop and Sleep mode

• On-chip clock generator with PLL

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PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

2 FEATURES

2.1.1 Architecture

• Integrated system for hand-held devices and general embedded applications.

• 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ CPU core.

• Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.

• Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance.

• ARM926EJ CPU core supports the ARM debug architecture.

• Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB).

2.1.2 System Manager

• Little/Big Endian support.

• Two independent memory bus - one for the

ROM/SRAM bus (ROM Bank0~Bank5) and one for the DRAM bus (mSDR/mDDR/DDR2 SDRAM Bank0~Bank1)

• Address space: 64M bytes for Rom bank0 ~ bank5, 128M bytes for SDRAM bank0 ~ bank1.

• Supports programmable 8/16-bit data bus width for ROM/SRAM bank and programmable 16/32bit data bus width for SDRAM bank

• Fixed bank start address from Rom bank 0 to bank 5 and SDRAM bank 0 to bank1.

• Eight memory banks:

– Six memory banks for ROM, SRAM, and

others (NAND etc.).

– Two memory banks for Synchronous DRAM.

• Complete Programmable access cycles for all memory banks.

• Supports external wait signals to expand the bus cycle.

• Supports self-refresh mode in SDRAM for power-down.

• Supports various types of ROM for booting (NOR Flash, EEPROM, OneNAND, IROM and others).

2.1.3 NAND Flash

• Supports booting from NAND flash memory by selecting OM as IROM boot mode. (Only 8bit Nand and 8ECC is supported when it boots)

• 64KB for internal SRAM Buffer(8KB internal buffer for booting)

• Supports storage memory for NAND flash memory after booting.

• Supports Advanced NAND flash

2.1.4 Cache Memory

• 4-way set-associative cache with I-Cache (16KB) and D-Cache (16KB).

• 8words length per line with one valid bit and two dirty bits per line.

• Pseudo random or round robin replacement algorithm.

• Write-through or write-back cache operation to update the main memory.

• The write buffer can hold 16 words of data and four addresses.

2.1.5 Clock & Power Manager

• On-chip MPLL and EPLL: EPLL generates the clock to operate USB Host, IIS, UART, etc. MPLL generates the clock to operate MCU at maximum 400MHz @ 1.3 V.

• Clock can be fed selectively to each function block by software.

• Power mode: Normal, Idle, Stop, Deep Stop and Sleep mode Normal mode: Normal operating mode Idle mode: The clock for only CPU is stopped. Stop mode: All clocks are stopped. Deep Stop mode: CPU power is gated and all clocks are stopped. Sleep mode: The Core power including all peripherals is shut down.

• Woken up by EINT[15:0] or RTC alarm & tick interrupt from Sleep mode and (Deep)STOP mode.

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