SAMSUNG S3C2416 User Guide

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USER'S MANUAL

S3C2416

16/32-Bit RISC Microprocessor

October 2008

REV 1.10

Confidential Proprietary of Samsung Electronics Co., Ltd

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

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"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.

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S3C2416 16/32-Bit RISC Microprocessor User's Manual, Revision 1.10

Publication Number: 21.10-S3-C2416- 082008

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001

certification (BSI Certificate No. FM24653). All semiconductor products are

designed and manufactured in accordance with the highest quality standards and

objectives.

Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 446-711

TEL: (82)-(31)-209-4593 FAX: (82)-(31)-209-5324

Home Page: http://www.samsungsemi.com Printed in the Republic of Korea

E-Mail: mobilesol.cs@samsung.com

NOTIFICATION OF REVISIONS

ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea

PRODUCT NAME: S3C2416 RISC Microprocessor

DOCUMENT NAME: S3C2416 User's Manual, Revision 1.10

DOCUMENT NUMBER: 21.10-S3-C2416-082008

EFFECTIVE DATE: October, 2008

DIRECTIONS: Revision 1.10

REVISION HISTORY

Revision No Description of Change Refer to Author(s) Date

1.00 Initial release - AP app part. August 27, 2008

1.10 Overview, System controller, DMA controller, I/O ports, LCD controller are updated.

- AP app part. October 06, 2008

REVISION DESCRIPTIONS FOR REVISION 1.10

Chapter

Chapter Name Page

1. Overview 1-2

2. System controller 2-1,6,8,9

8. DMA controller 8-2

8. DMA controller 8-16,17

10. I/O ports 10-37

21. LCD controller 21-23

Subjects (Major changes comparing with last version)

Way number of Cache Memory is corrected. Camera related explanation is removed. DMA request sources are corrected. Referred Register name, bit and pages are corrected. CF related description is removed. Camera related explanation is removed.

Chapter 1 Product Overview

1 Introduction ...............................................................................................................................................1-1

2 Features....................................................................................................................................................1-2

3 Block Diagram...........................................................................................................................................1-5

4 Pin Assignments .......................................................................................................................................1-6

4.1 Signal Descriptions..........................................................................................................................1-24

4.2 S3C2416 Operation Mode Description ...........................................................................................1-31

4.3 S3C2416 Memory MAP and Base Address of Special Registers...................................................1-32

Chapter 2 System Controller

1 Overview..................................................................................................................... ..............................2-1

2 Feature......................................................................................................................................................2-1

3 Block Diagram...........................................................................................................................................2-2

4 Functional Descriptions.............................................................................................................................2-3

4.1 Reset Management and Types.......................................................................................................2-3

4.2 Hardware Reset...............................................................................................................................2-3

4.3 Watchdog Reset..............................................................................................................................2-4

4.4 Software Reset................................................................................................................................2-5

4.5 Wakeup Reset.................................................................................................................................2-5

5 Clock Management...................................................................................................................................2-6

5.1 Clock Generation Overview.............................................................................................................2-6

5.2 Clock Source Selection ...................................................................................................................2-6

5.3 PLL (Phase-Locked-Loop) ..............................................................................................................2-8

5.4 Change PLL Settings In Normal Operation.....................................................................................2-8

5.5 System Clock Control......................................................................................................................2-9

5.6 ARM & BUS Clock Divide Ratio ......................................................................................................2-10

5.7 Examples for configuring clock regiter to produce specific frequency of AMBA clocks..................2-11

5.8 ESYSCLK Control ...........................................................................................................................2-12

6 Power Management..................................................................................................................................2-13

6.1 Power Mode State Diagram............................................................................................................2-13

6.2 Power Saving Modes.......................................................................................................................2-14

6.3 Wake-Up Event

6.4 Output Port State and STOP and SLEEP Mode.............................................................................2-19

6.5 Power Saving Mode Entering/Exiting Condition..............................................................................2-20

7 Register Descriptions................................................................................................................................2-21

7.1 Address Map ...................................................................................................................................2-21

...............................................................................................................................2-19

S3C2416X RISC MICROPROCESSOR i

Table of Contents (Continued)

Chapter 2 System Controller (Continued)

8 Individual Register Descriptions................................................................................................................2-22

8.1 Clock Source Control Registers

(LOCKCON0, LOCKCON1, OSCSET, MPLLCON, and EPLLCON)..............................................2-22

8.2 Clock Control Register (CLKSRC, CLKDIV, HCLKCON, PCLKCON, and SCLKCON).................2-25

8.3 Power Management Registers (PWRMODE and PWRCFG) .........................................................2-31

8.4 Reset Control Registers (SWRST and RSTCON)...........................................................................2-33

8.5 Control of retention PAD(I/O) when normal mode and wake-up from sleep mode.........................2-34

8.6 System Controller Status Registers (WKUPSTAT and RSTSTAT).................................................2-35

8.7 Bus Configuration Register (BUSPRI0, BUSPRI1, and BUSMISC)................................................2-36

8.8 Information Register 0,1,2,3 ............................................................................................................2-37

8.9 USB PHY Control register (PHYCTRL)...........................................................................................2-38

8.10 USB PHY Power Control Register (PHYPWR) .............................................................................2-39

8.11 USB Reset Control Register (URSTCON).....................................................................................2-39

8.12 USB Clock Control Register (UCLKCON).....................................................................................2-40

Chapter 3 Bus Matrix & EBI

1 Overview....................................................................................................................................................3-1

2 Special Function Registers .......................................................................................................................3-2

2.1 Matrix Core 0 Priority Register (Bpriority0)......................................................................................3-2

2.2 Matrix Core 1 Priority Register (Bpriority1)......................................................................................3-2

2.3 EBI Control Register (EBICON).......................................................................................................3-3

Chapter 4 Bus Priorities

1 Overview....................................................................................................................................................4-1

1.1 Bus Priority MAP..............................................................................................................................4-1

ii S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 5 Static Memory Controller (SMC)

1 Overview..................................................................................................................... ..............................5-1

2 Feature......................................................................................................................................................5-2

3 Block Diagram...........................................................................................................................................5-3

3.1 Asynchronous Read........................................................................................................................5-4

3.2 Asynchronous Burst Read...............................................................................................................5-6

3.3 Synchronous Read/Synchronous Burst Read.................................................................................5-7

3.4 Asynchronous Write ........................................................................................................................5-8

3.5 Synchronous Write/ Synchronous Burst Write................................................................................5-10

3.6 Bus Turnaround...............................................................................................................................5-11

4 Special Registers......................................................................................................................................5-14

4.1 Bank Idle Cycle Control Registers 0-5 ............................................................................................5-14

4.2 Bank Read Wait State Control Registers 0-5..................................................................................5-14

4.3 Bank Write Wait State Control Registers 0-5..................................................................................5-15

4.4 Bank Output Enable Assertion Delay Control Registers 0-5...........................................................5-15

4.5 Bank Write Enable Assertion Delay Control Registers 0-5.............................................................5-16

4.6 Bank Control Registers 0-5 .............................................................................................................5-17

4.7 Bank Onenand Type Selection Register.........................................................................................5-19

4.8 SMC Status Register.......................................................................................................................5-19

4.9 SMC Control Register......................................................................................................................5-20

Chapter 6 Mobile DRAM Controller

1 Overview..................................................................................................................... ..............................6-1

2 Block Diagram...........................................................................................................................................6-2

3 Mobile DRAM Initialization Sequence.......................................................................................................6-3

3.1 Mobile DRAM(SDRAM or mobile DDR) Initialization Sequence.....................................................6-3

3.2 DDR2 Initialization Sequence..........................................................................................................6-3

3.3 Mobile DRAM Configuration Register .............................................................................................6-8

3.4 Mobile DRAM Control Register.......................................................................................................6-9

3.5 Mobile DRAM Timming Control Register ........................................................................................6-10

3.6 Mobile DRAM (Extended ) Mode RegiSter Set Register.................................................................6-11

3.7 Mobile DRAM Refresh Control Register .........................................................................................6-14

3.8 Mobile DRAM Write Buffer Time out Register.................................................................................6-14

S3C2416X RISC MICROPROCESSOR iii

Table of Contents (Continued)

Chapter 7 NAND Flash Controller

1 Overview....................................................................................................................................................7-1

2 Features ....................................................................................................................................................7-1

3 Block Diagram...........................................................................................................................................7-2

4 Boot Loader Function................................................................................................................................7-2

5 GPC5/6/7 Pin Configuration Table in IROM Boot Mode...........................................................................7-3

6 NAND Flash Memory Timing ....................................................................................................................7-3

7 NAND Flash Access..................................................................................................................................7-4

8 Data Register Configuration......................................................................................................................7-5

9 Steppingstone (8KB in 64KB SRAM)........................................................................................................7-5

10 1bit / 4bit / 8bit ECC (Error Correction Code) .......................................................................................7-5

10.1 ECC Module Features...................................................................................................................7-5

10.2 1-bit ECC Programming Encoding and Decoding.........................................................................7-7

10.3 4-bit ECC Programming Guide (ENCODING)...............................................................................7-7

10.4 4-bit ECC Programming Guide (DECODING)...............................................................................7-8

10.5 8-bit ECC Programming Guide (ENCODING)...............................................................................7-8

10.6 8-bit ECC Programming Guide (DECODING)...............................................................................7-9

11 Memory Mapping(NAND boot and Other boot).......................................................................................7-10

12 NAND Flash Memory Configuration........................................................................................................7-11

13 NAND Flash Controller Special Registers ..............................................................................................7-12

13.1 NAND Flash Controller Register Map............................................................................................7-12

13.2 Nand Flash Configuration Register ...............................................................................................7-13

13.3 Control Regis

13.4 Command Register........................................................................................................................7-17

13.5 Address Register ...........................................................................................................................7-17

13.6 Data Register.................................................................................................................................7-17

13.7 Main Data area ECC Register.......................................................................................................7-18

13.8 Spare area ECC Register..............................................................................................................7-18

13.9 Progrmmable Block Address Register...........................................................................................7-19

13.10 NFCON Status Register ..............................................................................................................7-21

13.11 ECC0/1 Error Status Register......................................................................................................7-22

13.12 Main Data Area ECC0 Status Register .......................................................................................7-24

13.13 Spare Area ECC Status Register ................................................................................................7-25

13.14 4-bit ECC Error Patten Register ..................................................................................................7-25

13.15 ECC 0/1/2 for 8bit ECC Status Register......................................................................................7-26

13.16 8bit ECC Main Data ECC 0/1/2/3 Status Register.......................................................................7-27

13.17 8bit ECC Error Pattern Register ..................................................................................................7-28

ter.............................................................................................................................7-15

iv S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 8 DMA Controller

1 Overview..................................................................................................................... ..............................8-1

2 DMA Request Sources .............................................................................................................................8-2

3 DMA Operation .........................................................................................................................................8-3

3.1 External DMA Dreq/Dack Protocol..................................................................................................8-4

3.2 Examples of Possible Cases...........................................................................................................8-7

4 DMA Special Registers.............................................................................................................................8-8

4.1 DMA Initial Source Register (DISRC)..............................................................................................8-8

4.2 DMA Initial Source Control Register (DISRCC)..............................................................................8-9

4.3 DMA Initial Destination Register (DIDST) .......................................................................................8-10

4.4 DMA Initial Destination Control Register (DIDSTC)........................................................................8-11

4.5 DMA Control Register (DCON) .......................................................................................................8-12

4.6 DMA Status Register (DSTAT)........................................................................................................8-14

4.7 DMA Current Source Register (DCSRC) ........................................................................................8-15

4.8 Current Destination Register (DCDST)...........................................................................................8-15

4.9 DMA Mask Trigger Register (DMASKTRIG)...................................................................................8-16

4.10 DMA Requeset Selection Register (DMAREQSEL)......................................................................8-17

Chapter 9 Interrupt Controller

1 Overview..................................................................................................................... ..............................9-1

1.1 Interrupt Controller Operation..........................................................................................................9-3

1.2 Interrupt Sources.............................................................................................................................9-4

1.3 Interrupt Priority Generating Block..................................................................................................9-6

1.4 Interrupt Priority...............................................................................................................................9-7

2 Interrupt Controller Special Registers.......................................................................................................9-8

2.1 Source Pending (SRCPND) Register..............................................................................................9-10

2.2 Interrupt Mode (INTMOD) Register.................................................................................................9-12

2.3 Interrupt Mask (INTMSK) Register..................................................................................................9-14

2.4 Interrupt Pending (INTPND) Register..............................................................................................9-16

2.5 Interrupt Offset (INTOFFSET) Register...........................................................................................9-18

2.6 Sub Source Pending (SUBSRCPND) Register...............................................................................9-20

2.7 Interrupt Sub Mask (INTSUBMSK) Register...................................................................................9-22

2.8 Priority Mode Register (priority_MODE)..........................................................................................9-24

2.9 Priority Update Register (priority_UPDATE)...................................................................................9-29

S3C2416X RISC MICROPROCESSOR v

Table of Contents (Continued)

Chapter 10 I/O Ports

1 Overview....................................................................................................................................................10-1

2 Port Control Descriptions ..........................................................................................................................10-9

2.1 Port Configuration Register (GPACON-GPMCON).........................................................................10-9

2.2 Port Data Register (GPADAT-GPMDAT) ........................................................................................10-9

2.3 Port Pull-Up/Down Register (GPBUDP-GPMUDP).........................................................................10-9

2.4 Miscellaneous Control Register.......................................................................................................10-9

2.5 External Interrupt Control Register..................................................................................................10-9

3 I/O Port Control Register...........................................................................................................................10-10

3.1 PORT A Control Registers (GPACON, GPADAT)...........................................................................10-10

3.2 PORT B Control Registers (GPBCON, GPBDAT, GPBUDP, GPBSEL).........................................10-12

3.3 PORT C Control Registers (GPCCON, GPCDAT, GPCUDP) ........................................................10-14

3.4 PORT D Control Registers (GPDCON, GPDDAT, GPDUDP) ........................................................10-16

3.5 PORT E Control Registers (GPECON, GPEDAT, GPEUDP, GPESEL).........................................10-18

3.6 PORT F Control Registers (GPFCON, GPFDAT, GPFUDP)..........................................................10-20

3.7 PORT G Control Registers (GPGCON, GPGDAT, GPGUDP)........................................................10-21

3.8 PORT H Control Registers (GPHCON, GPHDAT, GPHUDP) ........................................................10-23

3.9 PORT J Control Registers (GPJCON, GPJDAT, GPJUDP, GPJSEL)............................................10-25

3.10 PORT K Control Registers (GPKCON, GPKDAT, GPKUDP).......................................................10-27

3.11 PORT L Control Registers (GPLCON, GPLDAT, GPLUDP, GPLSEL).........................................10-29

3.12 PORT M Control Registers (GPMCON, GPMDAT, GPMUDP).....................................................10-31

3.13 Miscellaneous Control Register (MISCCR)...................................................................................10-32

3.14 DCLK Control Regis

3.15 EXTINTn (External Interrupt Control Register n)...........................................................................10-35

3.16 EINTFLTn (External Interrupt Filter Register n).............................................................................10-40

3.17 EINTMASK (External Interrupt Mask Register).............................................................................10-41

3.18 EINTPEND (External Interrupt Pending Register).........................................................................10-42

3.19 GSTATUSn (General Status Registers)........................................................................................10-43

3.20 DSCn (Drive Strength Control)......................................................................................................10-44

3.21 PDDMCON (Power Down SDRAM Control Register)...................................................................10-48

3.22 PDSMCON (Power Down SRAM Control Register)......................................................................10-49

4 GPIO Alive & Sleep Part ..........................................................................................................................10-51

ters (DCLKCON)...........................................................................................10-34

vi S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 11 WatchDog Timer

1 Overview..................................................................................................................... ..............................11-1

1.1 Features...........................................................................................................................................11-1

2 Watchdog Timer Operation.......................................................................................................................11-2

2.1 Block Diagram.................................................................................................................................11-2

2.2 WTDAT & WTCNT ..........................................................................................................................11-2

2.3 Consideration of Debugging Environment ......................................................................................11-3

3 Watchdog Timer Special Registers ..........................................................................................................11-4

3.1 Watchdog Timer Control (WTCON) Register..................................................................................11-4

3.2 Watchdog Timer Data (WTDAT) Register.......................................................................................11-5

3.3 Watchdog Timer Count (WTCNT) Register ....................................................................................11-5

Chapter 12 PWM Timer

1 Overview..................................................................................................................... ..............................12-1

1.1 Feature ............................................................................................................................................12-1

2 PWM Timer Operation..............................................................................................................................12-3

2.1 Prescaler & Divider..........................................................................................................................12-3

2.2 Basic Timer Operation.....................................................................................................................12-4

2.3 Auto Reload & Double Buffering .....................................................................................................12-5

2.4 Timer Initialization Using Manual Update Bit and Inverter Bit.........................................................12-6

2.5 Timer Operation...............................................................................................................................12-7

2.6 Pulse Width Modulation (PWM) ......................................................................................................12-8

2.7 Output Level Control........................................................................................................................12-9

2.8 DEAD Zone Generator....................................................................................................................12-10

2.9 DMA Request Mode........................................................................................................................12-11

3 PWM Timer Control Registers.................................................................................................................12-12

3.1 Timer Configuration Register0 (TCFG0)..........................................................................................12-12

3.2 Timer Configuration Register1 (TCFG1).........................................................................................12-13

3.3 Timer Control (TCON) Register.......................................................................................................12-14

3.4 Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)...........................12-16

3.5 Timer 0 Count Observation Register (TCNTO0).............................................................................12-16

3.6 Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)...........................12-17

3.7 Timer 1 Count Observation Register (TCNTO1).............................................................................12-17

3.8 Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)...........................12-18

3.9 Timer 2 Count Observation Register (TCNTO2)

3.10 Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3).........................12-19

3.11 Timer 3 Count Observation Register (TCNTO3)...........................................................................12-19

3.12 Timer 4 Count Buffer Register (TCNTB4).....................................................................................12-20

3.13 Timer 4 Count Observation Register (TCNTO4)...........................................................................12-20

.............................................................................12-18

S3C2416X RISC MICROPROCESSOR vii

Table of Contents (Continued)

Chapter 13 Real Time Clock (RTC)

1 Overview....................................................................................................................................................13-1

1.1 Features...........................................................................................................................................13-1

1.2 Real Time Clock Operation Description ..........................................................................................13-2

1.3 External Interface.............................................................................................................................13-6

1.4 Register Description ........................................................................................................................13-7

1.5 Individual Register Descriptions ......................................................................................................13-8

Chapter 14 UART

1 Overview....................................................................................................................................................14-1

1.1 Features...........................................................................................................................................14-1

2 Block Diagram...........................................................................................................................................14-2

2.1 UART Operation ..............................................................................................................................14-3

3 UART Special Registers ...........................................................................................................................14-12

3.1 UART Line Control Register............................................................................................................14-12

3.2 UART Control Register....................................................................................................................14-13

3.3 UART FIFO Control Register...........................................................................................................14-15

3.4 UART Modem Control Register.......................................................................................................14-16

3.5 UART Tx/Rx Status Register...........................................................................................................14-17

3.6 UART Error Status Register ............................................................................................................14-18

3.7 UART FIFO Status Register ............................................................................................................14-19

3.8 UART Modem Status Register ........................................................................................................14-20

3.9 UART Transmit BUffer register (Holding Register & FIFO Register) ..............................................14-21

3.10 UART Receive BUffer Register (Holding Register & FIFO Register)............................................14-21

3.11 UART Baud RATE Divisor Register ..............................................................................................14-22

3.12 UART Dividing Slot Register..........................................................................................................14-23

Chapter 15 USB Host Controller

1 Overview....................................................................................................................................................14-1

1.1 USB Host Controller Special Registers ...........................................................................................14-2

viii S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 16 USB 2.0 Function

1 Overview..................................................................................................................... ..............................16-1

1.1 Feature ............................................................................................................................................16-1

2 Block Diagram...........................................................................................................................................16-2

3 To Activate USB Port1 for USB 2.0 Function ...........................................................................................16-3

4 SIE (Serial Interface Engine) ....................................................................................................................16-4

5 UPH (Universal Protocol Handler)............................................................................................................16-4

6 UTMI (USB 2.0 Transceiver Macrocell Interface).....................................................................................16-4

7 USB 2.0 Function Controller Special Registers........................................................................................16-5

8 Registers...................................................................................................................................................16-7

8.1 Index Register (IR) ..........................................................................................................................16-7

8.2 Endpoint Interrupt Register (EIR)....................................................................................................16-8

8.3 Endpoint Interrupt Enable Register (EIER) .....................................................................................16-9

8.4 Function Address Register (FAR) ...................................................................................................16-10

8.5 ENdpoint Direction Register (EDR).................................................................................................16-11

8.6 Test Register (TR)...........................................................................................................................16-12

8.7 System Status Register (SSR)........................................................................................................16-13

8.8 System Control Register (SCR) ......................................................................................................16-15

8.9 EP0 Status Register (EP0SR).........................................................................................................16-16

8.10 EP0 Control Register (EP0CR).....................................................................................................16-17

8.11 Endpoint# Buffer Register (EP#BR).............................................................................................16-18

8.12 Endpoint Status Register (ESR)

8.13 Endpoint Control Register (ECR)..................................................................................................16-21

8.14 Byte read Count Register (BRCR) ................................................................................................16-22

8.15 Byte Write Count Register (BWCR) ..............................................................................................16-23

8.16 MAX Packet Register (MPR).........................................................................................................16-24

8.17 DMA Control Register (DCR)........................................................................................................16-25

8.18 DMA Transfer Counter Register (DTCR)......................................................................................16-26

8.19 DMA FIFO Counter Register (DFCR) ...........................................................................................16-27

8.20 DMA Total Transfer Counter Register 1/2 (DTTCR 1/2)...............................................................16-28

8.21 DMA Interface Control Register (DICR)........................................................................................16-29

8.22 Memory Base Address Register (MBAR)......................................................................................16-30

8.23 Memory Current Address Register (MCAR)..................................................................................16-31

8.24 Burst FIFO Control Register(FCON).............................................................................................16-31

8.25 Burst FIFO Status Register(FSTAT) .............................................................................................16-31

8.26 AHB Master(DMA) Operation Flow Chart.....................................................................................16-32

....................................................................................................16-19

S3C2416X RISC MICROPROCESSOR ix

Table of Contents (Continued)

Chapter 17 IIC-Bus Interface

1 Overview....................................................................................................................................................17-1

1.1 IIC-Bus Interface..............................................................................................................................17-3

1.2 Start And Stop Conditions ...............................................................................................................17-3

1.3 Data Transfer Format ......................................................................................................................17-4

1.4 ACK Signal Transmission................................................................................................................17-5

1.5 Read-Write Operation......................................................................................................................17-6

1.6 Bus Arbitration Procedures..............................................................................................................17-6

1.7 Abort Conditions ..............................................................................................................................17-6

1.8 Configuring IIC-Bus..........................................................................................................................17-6

1.9 Flowcharts of Operations in Each Mode..........................................................................................17-7

2 IIC-Bus Interface Special Registers..........................................................................................................17-11

2.1 Multi-Master IIC-Bus Control (IICCON) Register.............................................................................17-11

2.2 Multi-Master IIC-Bus Control/Status (IICSTAT) Register ................................................................17-12

2.3 Multi-Master IIC-Bus Address (IICADD) Register ...........................................................................17-13

2.4 Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register ..............................................17-13

2.5 Multi-Master IIC-Bus Line Control(IICLC) Register .........................................................................17-14

Chapter 18 2D

1 Introduction................................................................................................................................................18-1

1.1 Features...........................................................................................................................................18-1

2 Color Format Conversion..........................................................................................................................18-2

3 Command FIFO.........................................................................................................................................18-3

4 Rendering Pipeline....................................................................................................................................18-4

4.1 Primitive Drawing.............................................................................................................................18-4

4.2 Rotation............................................................................................................................................18-9

4.3 Clipping............................................................................................................................................18-11

4.4 Stencil Test......................................................................................................................................18-11

4.5 Raster Operation..............................................................................................................................18-11

4.6 Alpha Blending.................................................................................................................................18-13

5 Register Descriptions................................................................................................................................18-14

5.1 General Registers............................................................................................................................18-16

5.2 Command Registers........................................................................................................................18-19

5.3 Parameter Setting Registers............................................................................................................18-21

x S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 19 HS_SPI Controller

1 Overview..................................................................................................................... ..............................19-1

2 Features....................................................................................................................................................19-1

3 Signal Descriptions...................................................................................................................................19-2

4 Operation ..................................................................................................................................................19-2

4.1 Operation Mode...............................................................................................................................19-3

4.2 FIFO Access....................................................................................................................................19-3

4.3 Trailing Bytes in the Rx FIFO ..........................................................................................................19-3

4.4 Packet Number Control...................................................................................................................19-3

4.5 NCS Control ....................................................................................................................................19-3

4.6 HS_SPI Transfer Format.................................................................................................................19-4

5 Special Function Register Descriptions....................................................................................................19-5

5.1 Setting Sequence of Special Function Register..............................................................................19-5

5.2 Special Function Register ...............................................................................................................19-6

Chapter 20 SD/MMC Host Controller

1 Overview..................................................................................................................... ..............................20-1

2 Features....................................................................................................................................................20-1

3 Block Diagram...........................................................................................................................................20-2

4 Sequence..................................................................................................................................................20-3

4.1 SD Card Detection Sequence.........................................................................................................20-3

4.2 SD Clock Supply Sequence............................................................................................................20-4

4.3 SD Clock Stop Sequence................................................................................................................20-5

4.4 SD Clock Frequency Change Sequence ........................................................................................20-5

4.5 SD Bus Power Control Sequence...................................................................................................20-6

4.6 Change Bus Width Sequence.........................................................................................................20-7

4.7 Timeout Setting for DAT Line..........................................................................................................20-8

4.8 SD Transaction Generation.............................................................................................................20-8

4.9 SD Command Issue Sequence.......................................................................................................20-9

4.10 Command Complete Sequence....................................................................................................20-10

4.11 Transaction Control with Data Transfer Using DAT Line..............................................................20-12

4.12 Abort Transaction..........................................................................................................................20-16

5 SDI Special Registers...............................................................................................................................20-17

5.1 Configuration Register Types..........................................................................................................20-17

5.2 SDMA System Address Register ....................................................................................................20-18

5.3 Block Size Register .........................................................................................................................20-19

5.4 Block Count Register.......................................................................................................................20-21

5.5 Argument Register...........................................................................................................................20-22

5.6 Transfer Mode Register...................................................................................................................20-23

5.7 Command Register..........................................................................................................................20-25

5.8 Response Register..........................................................................................................................20-27

5.9 Buffer Data Port Register ................................................................................................................20-29

5.10 Present State Regis

5.11 Host Control Register....................................................................................................................20-36

5.12 Power Control Register .................................................................................................................20-37

ter ..................................................................................................................20-30

S3C2416X RISC MICROPROCESSOR xi

Table of Contents (Continued)

Chapter 20 SD/MMC Host Controller (Continued)

5.13 Block Gap Control Register...........................................................................................................20-38

5.14 Wakeup Control Register...............................................................................................................20-40

5.15 Clock Control Register...................................................................................................................20-41

5.16 Timeout Control Register...............................................................................................................20-43

5.17 Software Reset Register................................................................................................................20-44

5.18 Normal Interrupt Status Register...................................................................................................20-46

5.19 Error Interrupt Status Register.......................................................................................................20-50

5.20 Normal Interrupt Status Enable Register.......................................................................................20-53

5.21 Error Interrupt Status Enable Register ..........................................................................................20-55

5.22 Normal Interrupt Signal Enable Register.......................................................................................20-56

5.23 Error Interrupt Signal Enable Register...........................................................................................20-58

5.24 Autocmd12 Error Status Register..................................................................................................20-59

5.25 Capabilities Register......................................................................................................................20-61

5.26 Maximum Current Capabilities Register........................................................................................20-63

5.27 Control Register 2..........................................................................................................................20-64

5.28 Control Register 3..........................................................................................................................20-67

5.29 Debug Register..............................................................................................................................20-68

5.30 Control Register 4..........................................................................................................................20-68

5.31 Force Event Register for Auto CMD12 Error Status......................................................................20-69

5.32 Force Event Register for Error Interrupt Status.............................................................................20-70

5.33 ADMA Error Status Register..........................................................................................................20-71

5.34 ADMA System Address Register...................................................................................................20-73

5.35 HOST Controller Version Register ................................................................................................20-74

Chapter 21 LCD Controller

1 Overview....................................................................................................................................................21-1

1.1 Features...........................................................................................................................................21-2

2 Functional Description...............................................................................................................................21-3

2.1 Brief of the sub-block.......................................................................................................................21-3

2.2 Data Flow.........................................................................................................................................21-3

2.3 Interface...........................................................................................................................................21-4

2.4 Overview of the Color Data..............................................................................................................21-5

2.5 VD signal Connection ......................................................................................................................21-18

2.6 Palette usage...................................................................................................................................21-20

3 Window Blending.......................................................................................................................................21-22

3.1 Overview..........................................................................................................................................21-22

3.2 Blending Diagram/Details................................................................................................................21-23

4 Vtime Controller Operation........................................................................................................................21-26

4.1 RGB Interface..................................................................................................................................21-26

4.2 I80-System Interface........................................................................................................................21-26

5 Virtual Display ...........................................................................................................................................21-27

6 RGB Interface I/O......................................................................................................................................21-28

7 LCD CPU Interface I/O (I80-system I/F) ...................................................................................................21-29

8 Programmer’s Model.................................................................................................................................21-31

8.1 Overview..........................................................................................................................................21-31

xii S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 22 ADC & Touch Screen Interface

1 Overview..................................................................................................................... ..............................22-1

1.1 Features...........................................................................................................................................22-1

2 ADC & Touch Screen Interface Operation................................................................................................22-2

2.1 Block Diagram.................................................................................................................................22-2

2.2 Function Descriptions......................................................................................................................22-3

3 ADC and Touch Screen Interface Special Registers................................................................................22-5

3.1 ADC Control (ADCCON) Register...................................................................................................22-5

3.2 ADC Touch Screen Control (ADCTSC) Register............................................................................22-6

3.3 ADC Start Delay (ADCDLY) Register..............................................................................................22-7

3.4 ADC Conversion Data (ADCDAT0) Register..................................................................................22-8

3.5 ADC Conversion Data (ADCDAT1) Register..................................................................................22-9

3.6 ADC Touch Screen up-Down Int Check Register (ADCUPDN)......................................................22-9

3.7 ADC Channel Mux Register (ADCMUX).........................................................................................22-10

Chapter 23 IIS Multi Audio Interface

1 Overview..................................................................................................................... ..............................23-1

2 Feature......................................................................................................................................................23-1

3 Signals ......................................................................................................................................................23-1

4 Block Diagram...........................................................................................................................................23-2

5 Functional Descriptions.............................................................................................................................23-2

5.1 Master/Slave Mode..........................................................................................................................23-3

5.2 DMA Transfer ..................................................................................................................................23-4

6 Audio Serial Data Format..........................................................................................................................23-5

6.1 IIS-Bus Format ................................................................................................................................23-5

6.2 MSB (Left) Justified .........................................................................................................................23-5

6.3 LSB (Right) Justified........................................................................................................................23-5

6.4 Sampling Frequency and Master Clock ..........................................................................................23-7

6.5 IIS Clock Mapping Table .................................................................................................................23-7

7 Programming Guide..................................................................................................................................23-8

7.1 Initialization......................................................................................................................................23-8

7.2 Play Mode (TX mode) with DMA.....................................................................................................23-8

7.3 Recording Mode (RX mode) with DMA...........................................................................................23-8

7.4 Example Code.................................................................................................................................23-9

8 IIS-BUS Interface Special Registers.........................................................................................................23-15

8.1 IIS Control Register (IISCON) .........................................................................................................23-16

8.2 IIS Mode Register (IISMOD) ...........................................................................................................23-18

8.3 IIS FIFO Control Register (IISFIC)..................................................................................................23-20

8.4 IIS Pres

8.5 IIS Transmit Register (IISTXD)........................................................................................................23-21

8.6 IIS Receive Register (IISRXD) .......................................................................................................23-21

caler Control Register (IISPSR)..........................................................................................23-20

S3C2416X RISC MICROPROCESSOR xiii

Table of Contents (Continued)

Chapter 24 AC97 Controller

1 Overview....................................................................................................................................................24-1

1.1 Feature.............................................................................................................................................24-1

1.2 Signals .............................................................................................................................................24-1

2 AC97 Controller Operation........................................................................................................................24-2

2.1 Block Diagram..................................................................................................................................24-2

2.2 Internal Data Path............................................................................................................................24-3

3 Operation Flow Chart................................................................................................................................24-4

4 AC-link Digital Interface Protocol ..............................................................................................................24-5

4.1 AC-link Output Frame (SDATA_OUT).............................................................................................24-6

4.2 AC-link Input Frame (SDATA_IN)....................................................................................................24-7

5 AC97 Power-Down....................................................................................................................................24-9

6 Codec Reset..............................................................................................................................................24-10

7 AC97 Controller State Diagram.................................................................................................................24-11

8 AC97 Controller Special Registers............................................................................................................24-12

8.1 AC97 Special Funcion Register Summary......................................................................................24-12

8.2 AC97 Global Control Register (AC_GLBCTRL)..............................................................................24-13

8.3 AC97 Global Status Register (AC_GLBSTAT)................................................................................24-14

8.4 AC97 Codec Command Register (AC_CODEC_CMD) ..................................................................24-14

8.5 AC97 Codec Status Register (AC_CODEC_STAT)........................................................................24-15

8.6 AC97 PCM Out/In Channel Fifo Address Register (AC_PCMADDR).............................................24-15

8.7 AC97 MIC In Channel FIFO Address Register (AC_MICADDR) ....................................................24-16

8.8 AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA)

8.9 AC97 MIC In Channel FIFO Data Register (AC_MICDATA)...........................................................24-16

.................................................24-16

xiv S3C2416X RISC MICROPROCESSOR

Table of Contents (Continued)

Chapter 25 PCM Audio Interface

1 Overview..................................................................................................................... ..............................25-1

1.1 Feature ............................................................................................................................................25-1

1.2 Signals.............................................................................................................................................25-1

2 PCM Audio Interface.................................................................................................................................25-2

3 PCM Timing ..............................................................................................................................................25-3

3.1 PCM Input Clock Diagram...............................................................................................................25-4

3.2 PCM Registers ................................................................................................................................25-5

3.3 PCM Register Summary..................................................................................................................25-5

3.4 PCM Control Register......................................................................................................................25-6

3.5 PCM CLK Control Register .............................................................................................................25-8

3.6 The PCM Tx FIFO Register.............................................................................................................25-9

3.7 PCM Rx FIFO Register....................................................................................................................25-10

3.8 PCM Interrupt Control Register.......................................................................................................25-11

3.9 PCM Interrupt Status Register ........................................................................................................25-14

3.10 PCM FIFO Status Register............................................................................................................25-16

3.11 PCM Interrupt Clear Register........................................................................................................25-17

Chapter 26 Electrical Data

1 Absolute Maximum Ratings......................................................................................................................26-1

2 Recommended Operating Conditions.......................................................................................................26-2

3 D.C. Electrical Characteristics ..................................................................................................................26-4

4 A.C. Electrical Characteristics ..................................................................................................................26-6

Chapter 27 Mechanical Data

1 Package Dimensions........................................................................................................... .....................27-1

S3C2416X RISC MICROPROCESSOR xv

List of Figures

Figure Title Page Number Number

1-1 S3C2416 Block Diagram..............................................................................................1-5

1-2 S3C2416 Pin Assignments (400-FBGA) Top view......................................................1-6

1-3 Memory Map ................................................................................................................1-32

2-1 System Controller Block Diagram................................................................................2-2

2-2 Power-On Reset Sequence.........................................................................................2-4

2-3 Clock Generator Block Diagram ..................................................................................2-6

2-4 Main Oscillator Circuit Examples.................................................................................2-7

2-5 PLL(Phase-Locked Loop) Block Diagram....................................................................2-8

2-6 The Case that Changes Slow Clock by Setting PMS Value........................................2-8

2-7 The Clock Distribution Block Diagram .........................................................................2-9

2-8 MPLL Based Clock Domain.........................................................................................2-9

2-9 EPLL Based Clock Domain..........................................................................................2-12

2-10 Power Mode State Diagram.........................................................................................2-13

2-11 Entering STOP Mode and Exiting STOP Mode (wake-up)..........................................2-17

2-12 Entering SLEEP Mode and Exiting SLEEP Mode (wake-up) ......................................2-18

2-13 Usage of PWROFF_SLP .............................................................................................2-34

3-1 The Configuration of MATRIX and Memory Sub-System of S3C2416........................3-1

5-1 SMC Block Diagram.....................................................................................................5-3

5-2 SMC Core Block Diagram............................................................................................5-3

5-3 External Memory Two Output Enable Delay State Read.............................................5-4

5-4 Read Timing Diagram (DRnCS = 1, DRnOWE = 0)....................................................5-4

5-5 Read Timing Diagram (DRnCS = 1, DRnOWE = 1)....................................................5-5

5-6

5-7 External Synchronous Fixed Length Four Transfer Burst Read..................................5-7

5-8 External Memory Two Write Enable Delay State Write...............................................5-8

5-9 Write Timing Diagram (DRnCS = 1, DRnOWE = 0) ....................................................5-9

5-10 Write Timing Diagram (DRnCS = 1, DRnOWE = 1) ....................................................5-9

5-11 Synchronous Two Wait State Write.............................................................................5-10

5-12 Read, then two Writes (WSTRD=WSTWR=0), Two Turnaround Cycles (IDCY=2)....5-11

5-13 Memory Interface with 8-bit SRAM (2MB) ...................................................................5-13

5-14 Memory Interface with 16-bit SRAM (4MB) .................................................................5-13

6-1 Mobile DRAM Controller Block Diagram......................................................................6-2

6-2 Memory Interface with 16-bit SDRAM (4Mx16, 4banks) .............................................6-4

6-3 Memory Interface with 32-bit SDRAM (4Mx16 * 2ea, 4banks)....................................6-4

6-4 Memory Interface with 16-bit Mobile DDR and DDR2.................................................6-5

6-5 DRAM Timing Diagram................................................................................................6-6

6-6 CL (CAS Latency) Timing Diagram..............................................................................6-6

6-7 t

External Burst ROM with WSTRD=2 and WSTBRD=1 Fixed Length Burst Read......5-6

Timing Diagram..................................................................................................6-7

ARFC

xvi S3C2416X RISC MICROPROCESSOR

List of Figures

Figure Title Page Number Number

7-1 NAND Flash Controller Block Diagram........................................................................7-2

7-2 NAND Flash Controller Boot Loader Block Diagram...................................................7-2

7-3 CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) Block Diagram................7-3

7-4 nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram.................................7-4

7-5 NAND Flash Memory Mapping Block Diagram...........................................................7-10

7-6 A 8-bit NAND Flash Memory Interface Block Diagram................................................7-11

7-7 Softlock and Lock-tight ................................................................................................7-20

8-1 Basic DMA Timing Diagram.........................................................................................8-4

8-2 Demand/Handshake Mode Comparison.....................................................................8-5

8-3 Burst 4 Transfer size....................................................................................................8-6

8-4 Single service, Demand Mode, Single Transfer Size..................................................8-7

8-5 Single service, Handshake Mode, Single Transfer Size .............................................8-7

8-6 Whole service, Handshake Mode, Single Transfer Size.............................................8-7

9-1 Interrupt Process Diagram...........................................................................................9-1

9-2 Interrupt Group Multiplexing Diagram..........................................................................9-2

9-3 Priority Generating Block.............................................................................................9-6

11-1 Watchdog Timer Block Diagram..................................................................................11-2

12-1 16-bit PWM Timer Block Diagram...............................................................................12-2

12-2 Timer Operations.........................................................................................................12-4

12-3 Example of Double Buffering Function........................................................................12-5

12-4 Example of a Timer Operation.....................................................................................12-7

12-5

12-6 Inverter On/Off.............................................................................................................12-9

12-7 The Wave Form When a Dead Zone Feature is Enabled...........................................12-10

12-8 Timer4 DMA Mode Operation......................................................................................12-11

Example of PWM.........................................................................................................12-8

S3C2416X RISC MICROPROCESSOR xvii

List of Figures

Figure Title Page Number Number

13-1 Real Time Clock Block Diagram..................................................................................13-2

13-2 RTC Tick Interrupt Clock Scheme ...............................................................................13-5

13-3 Main Oscillator Circuit Example...................................................................................13-6

14-1 UART Block Diagram (with FIFO)................................................................................14-2

14-2 UART AFC Interface....................................................................................................14-4

14-3 Example showing UART Receiving 5 Characters with 2 Errors..................................14-7

14-4 IrDA Function Block Diagram.......................................................................................14-8

14-5 Serial I/O Frame Timing Diagram (Normal UART)......................................................14-9

14-6 Infrared Transmit Mode Frame Timing Diagram..........................................................14-9

14-7 Infrared Receive Mode Frame Timing Diagram...........................................................14-9

14-8 nCTS and Delta CTS Timing Diagram.........................................................................14-20

15-1 USB Host Controller Block Diagram............................................................................15-1

16-1 USB2.0 Block Diagram ................................................................................................16-2

16-2 USB2.0 Function Block Diagram .................................................................................16-3

16-3 OUT Transfer Operation Flow......................................................................................16-32

16-4 IN Transfer Operation Flow..........................................................................................16-33

17-1 IIC-Bus Block Diagram.................................................................................................17-2

17-2 Start and Stop Condition..............................................................................................17-3

17-3 IIC-Bus Interface Data Format.....................................................................................17-4

17-4 Data Transfer on the IIC-Bus.......................................................................................17-5

17-5 Acknowledge on the IIC-Bus........................................................................................17-5

17-6 Operations for Master/Trans

17-7 Operations for Master/Receiver Mode.........................................................................17-8

17-8 Operations for Slave/Transmitter Mode.......................................................................17-9

17-9 Operations for Slave/Receiver Mode...........................................................................17-10

18-1 Color Format................................................................................................................18-2

18-2 YUV 2-Planar Format...................................................................................................18-3

18-3 2D Rendering Pipeline.................................................................................................18-4

18-4 Data Format.................................................................................................................18-4

18-5 Transparent Mode........................................................................................................18-6

18-6 Color Expansion...........................................................................................................18-8

18-7 Font Drawing with Transparent Mode..........................................................................18-8

18-8 Rotation Example.........................................................................................................18-10

mitter Mode.....................................................................17-7

xviii S3C2416X RISC MICROPROCESSOR

List of Figures

Figure Title Page Number Number

19-1 HS_SPI Transfer Format.............................................................................................19-4

20-1 HSMMC Block Diagram...............................................................................................20-2

20-2 SD Card Detect Sequence ..........................................................................................20-3

20-3 SD Clock Supply Sequence ........................................................................................20-4

20-4 SD Clock Stop Sequence............................................................................................20-5

20-5 SD Clock Change Sequence.......................................................................................20-5

20-6 SD Bus Power Control Sequence ...............................................................................20-6

20-7 Change Bus Width Sequence .....................................................................................20-7

20-8 Timeout Setting Sequence ..........................................................................................20-8

20-9 Timeout Setting Sequence ..........................................................................................20-9

20-10 Command Complete Sequence..................................................................................20-11

20-11 Transaction Control with Data Transfer Using DAT Line Sequence (Not using DMA) 20-13

20-12 Transaction Control with Data Transfer Using DAT Line Sequence (Using DMA).....20-15

20-13 Card Detect State........................................................................................................20-34

20-14 Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer...20-35

20-15 Timing of Command Inhibit (DAT) for the case of response with busy.......................20-35

20-16 Timing of Command Inhibit (CMD) for the case of no response command................20-35

21-1 LCD Controller Block diagram.....................................................................................21-1

21-2 Block diagram of the Data Flow...................................................................................21-4

21-3 16BPP(1+5:5:5, BSWP/HWSWP=0) Display Types...................................................21-12

21-4 16BPP(5:6:5, BSWP/HWSWP=0) Display Types .......................................................21-13

21-5 Blending Operations....................................................................................................21-22

21-6 Color Key Block Diagram.............................................................................................21-24

21-7 Color Key Operations ..................................................................................................21-24

21-8 Color Key Function Configurations..............................................................................21-25

21-9 Example of Scrolling in Virtual Display........................................................................21-27

21-10 LCD RGB Interface Timing..........................................................................................21-28

21-11 Write Cycle Timing.......................................................................................................21-29

S3C2416X RISC MICROPROCESSOR xix

List of Figures

Figure Title Page Number Number

22-1 ADC and Touch Screen Interface Block Diagram .......................................................22-2

22-2 Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode.........................22-4

23-1 IIS-Bus Block Diagram.................................................................................................23-2

23-2 IIS Clock Control Block Diagram..................................................................................23-3

23-3 IIS Audio Serial Data Formats .....................................................................................23-6

23-4 TX FIFO Structure for BLC = 00 or BLC = 01..............................................................23-10

23-5 TX FIF0 Structure for BLC = 10 (24-bits/channel).......................................................23-11

23-6 RX FIFO Structure for BLC = 00 or BLC = 01 .............................................................23-13

23-7 RX FIF0 Structure for BLC = 10 (24-bits/channel).......................................................23-14

24-1 AC97 Block Diagram....................................................................................................24-2

24-2 Internal Data Path........................................................................................................24-3

24-3 AC97 Operation Flow Chart.........................................................................................24-4

24-4 Bi-directional AC-link Frame with Slot Assignments....................................................24-5

24-5 AC-link Output Frame ..................................................................................................24-6

24-6 AC-link Input Frame.....................................................................................................24-8

24-7 AC97 Power-down Timing...........................................................................................24-9

24-9 AC97 State Diagram....................................................................................................24-11

25-1 PCM timing, TX_MSB_POS / RX_MSB_POS = 0.......................................................25-3

25-2 PCM timing, TX_MSB_POS / RX_MSB_POS = 1.......................................................25-3

25-3 Input Clock Diagram for PCM......................................................................................25-4

xx S3C2416X RISC MICROPROCESSOR

List of Figures

Figure Title Page Number Number

26-1 XTIpll Clock Timing......................................................................................................26-7

26-2 EXTCLK Clock Input Timing........................................................................................26-7

26-3 EXTCLK/HCLK in case that EXTCLK is used without the PLL...................................26-7

26-4 HCLK/CLKOUT/SCLK in case that EXTCLK is used..................................................26-8

26-5 Manual Reset Input Timing..........................................................................................26-8

26-6 Power-On Oscillation Setting Timing...........................................................................26-9

26-7 Sleep Mode Return Oscillation Setting Timing............................................................26-10

26-8 SMC Synchronous Read Timing.................................................................................26-11

26-9 SMC Asynchronous Read Timing ...............................................................................26-11

26-10 SMC Asynchronous Write Timing................................................................................26-12

26-11 SMC Synchronous Write Timing.................................................................................26-12

26-12 SMC Wait Timing.........................................................................................................26-13

26-13 Nand Flash Timing.......................................................................................................26-14

26-14 SDRAM READ / WRITE Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit)..................26-15

26-15 DDR2 Timing...............................................................................................................26-16

26-16 SDRAM MRS Timing...................................................................................................26-17

26-17 SDRAM Auto Refresh Timing (Trp = 2, Trc = 4).........................................................26-18

26-18 External DMA Timing (Handshake, Single transfer)....................................................26-19

26-19 TFT LCD Controller Timing..........................................................................................26-19

26-20 IIS Interface Timing (I2S Master Mode Only)..............................................................26-20

26-21 IIS Interface Timing (I 2S Slave Mode Only)................................................................26-20

26-22 IIC Interface Timing.....................................................................................................26-20

26-23

26-24 High Speed SPI Interface Timing (CPHA = 0, CPOL = 0)...........................................26-21

26-25 USB Timing (Data signal rise/fall time)........................................................................26-22

26-26 PCM Interf ace Timing..................................................................................................26-22

27-1 400-FBGA-1313 Package Dimension 1 (Top View)....................................................27-1

27-2 400-FBGA-1313 Package Dimension 2 (Bottom View)...............................................27-2

High Speed SDMMC Interface Timing ........................................................................26-21

S3C2416X RISC MICROPROCESSOR xxi

List of Tables

Table Title Page Number Number

1-1 400-Pin FBGA Pin Assignments − Pin Number Order (1/4)........................................1-7

1-1 400-Pin FBGA Pin Assignments − Pin Number Order (2/4)........................................1-8

1-1 400-Pin FBGA Pin Assignments − Pin Number Order (3/4)........................................1-9

1-1 400-Pin FBGA Pin Assignments – Pin Number Order (4/4)........................................1-10

1-2 S3C2416 400-Pin FBGA Pin Assignments..................................................................1-11

1-3 I/O Cell Types and Descriptions ..................................................................................1-23

1-4 S3C2416 Signal Descriptions......................................................................................1-24

1-5 S3C2416 Operation Mode Description........................................................................1-31

1-6 Base Address of Special Registers..............................................................................1-33

1-7 S3C2416 Special Registers.........................................................................................1-34

2-1 Registers & GPIO Status in RESET (R: reset, S: sustain previous value)..................2-5

2-2 Clock source selection for the main PLL and clock generation logic ..........................2-6

2-3 Clock Source Selection for the EPLL...........................................................................2-7

2-4 PLL & Clock Generator Condition................................................................................2-7

2-5 Clock Division Ratio of MPLL Region..........................................................................2-10

2-6 ESYSCLK Control........................................................................................................2-12

2-7 The Status of PLL and ARMCLK After Wake-up.........................................................2-19

2-8 Power Saving Mode Entering/Exiting Condition..........................................................2-20

2-9 System Controller Address Map..................................................................................2-21

8-1 DMA request sources for each channel.......................................................................8-2

10-1 S3C2416 Port Configuration (Sheet 1)

13-1 RTC Register summary ...............................................................................................13-7

14-1 Example of nRTS signal change by FIFO Spare size

(In case of Reception Case in UART A) ......................................................................14-4

14-2 Interrupts in Connection with FIFO..............................................................................14-6

14-3 Clock, EPLL Speed Guide ...........................................................................................14-11

14-4 Recommended Value Table of DIVSLOTn Register ...................................................14-23

15-1 OHCI Registers for USB Host Controller.....................................................................15-2

........................................................................10-2

xxii S3C2416X RISC MICROPROCESSOR

List of Tables

Table Title Page Number Number

16-1 Non-Indexed Registers................................................................................................16-5

16-2 Indexed Registers........................................................................................................16-6

19-1 External Signals Description........................................................................................19-2

20-1 Determination of Transfer Type...................................................................................20-24

20-2 Relation Between Parameters and the Name of Response Type...............................20-26

20-3 Response Bit Definition for Each Response Type. .....................................................20-27

20-4 The relation between Command CRC Error and Command Timeout Error ...............20-52

20-5 The Relation Between Command CRC Error and Command Timeout Error..............20-60

20-6 Maximum Current Value Definition..............................................................................20-63

21-1 25BPP(A:8:8:8) Palette Data Format ..........................................................................21-20

21-2 19BPP (A:6:6:6) Palette Data Format .........................................................................21-21

21-3 16BPP(A:5:5:5) Palette Data Format ..........................................................................21-21

21-4 Alpha Value Selection Table for Blending...................................................................21-23

21-5 Relation between VCLK and CLKVAL (Freq. of Video Clock Source=60MHz)..........21-26

21-6 LCD Signal Muxing Table (RGB and i-80 I/F) .............................................................21-30

23-1 CODEC clock (CODECLK = 256fs, 384fs, 512fs, 768fs)............................................23-7

23-2 IIS Clock Mapping Table..............................................................................................23-7

24-1 Input Slot 1 Bit Definitions............................................................................................24-7

S3C2416X RISC MICROPROCESSOR xxiii

List of Tables

Table Title Page Number Number

26-1 Absolute Maximum Rating...........................................................................................26-1

26-2 Recommended Operating Conditions (400MHz).........................................................26-2

26-3 Recommended Operating Conditions (533MHz).........................................................26-3

26-4 Normal I/O PAD DC Electrical Characteristics ............................................................26-4

26-5 Special Memory DDR I/O PAD DC Electrical Characteristics.....................................26-5

26-6 USB DC Electrical Characteristics...............................................................................26-6

26-7 RTC OSC DC Electrical Characteristics......................................................................26-6

26-8 Clock Timing Constants...............................................................................................26-23

26-9 SMC Timing Constants................................................................................................26-24

26-10 NFCON Bus Timing Constants....................................................................................26-24

26-11 Memory Interface Timing Constants (SDRAM)...........................................................26-25

26-12 DMA Controller Module Signal Timing Constants.......................................................26-26

26-13 TFT LCD Controller Module Signal Timing Constants................................................26-26

26-14 IIS Controller Module Signal Timing Constants(I2S Master Mode Only) ....................26-26

26-15 IIS Controller Module Signal Timing Constants(I2S Slave Mode Only).......................26-27

26-16 IIC BUS Controller Module Signal Timing....................................................................26-27

26-17 High Speed SPI Interface Transmit/Receive Timing Constants.................................26-28

26-18 USB Electrical Specifications.......................................................................................26-28

26-19 USB Full Speed Output Buffer Electrical Characteristics.............................................26-29

26-20 USB High Speed Output Buffer Electrical Characteristics...........................................26-29

26-21 High Speed SDMMC Interface Transmit/Receive Timing Constants..........................26-29

26-22 PCM Interf ace Timing..................................................................................................26-30

xxiv S3C2416X RISC MICROPROCESSOR

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

1 INTRODUCTION

This user’s manual describes SAMSUNG's S3C2416X 16/32-bit RISC microprocessor. SAMSUNG’s S3C2416X is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2416X includes the following components.

The S3C2416X is developed with ARM926EJ core, 65nm CMOS standard cells and a memory complier. Its lowpower, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2416X offers outstanding features with its CPU core, a 16/32-bit ARM926EJ RISC processor designed by Advanced RISC Machines, Ltd. The ARM926EJ implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals, the S3C2416X minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:

• Around 400MHz @ 1.3V, 266MHz @ TBDV Core, 1.8V/2.5V/3.0V/3.3V ROM/SRAM, 1.8V/2.5V mSDR/mDDR/DDR2 SDRAM, 1.8V/2.5V/3.3V external I/O microprocessor with 16KB I/D-Cache/MMU

• External memory controller (mSDR/mDDR/DDR2 SDRAM Control and Chip Select logic)

• LCD controller (up to 256K color) with LCD-dedicated DMA

• 6-ch DMA controllers with external request pins

• 4-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

• 1-ch High Speed SPls

• 1 IIC bus interfaces (multi-master support)

• 1 IIS Audio CODEC interfaces (24-bit, port 0 supports 5.1ch)

• AC97/PCM CODEC Interface(muxed with I2S)

• 2 High-Speed MMC and SDMMC combo (SD Host 2.0 and MMC protocol 4.2 compatible)

• 2-ch USB Host controller (ver 1.1 Compliant)/1-ch USB Device controller (ver 2.0 Compliant)

• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

• 10-ch 12-bit ADC and Touch screen interface

• RTC with calendar function

• 138 General Purpose I/O ports / 16-ch external interrupt source

• Power control: Normal, Idle, Stop, Deep Stop and Sleep mode

• On-chip clock generator with PLL

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PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

2 FEATURES

2.1.1 Architecture

• Integrated system for hand-held devices and general embedded applications.

• 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ CPU core.

• Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.

• Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance.

• ARM926EJ CPU core supports the ARM debug architecture.

• Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB).

2.1.2 System Manager

• Little/Big Endian support.

• Two independent memory bus - one for the

ROM/SRAM bus (ROM Bank0~Bank5) and one for the DRAM bus (mSDR/mDDR/DDR2 SDRAM Bank0~Bank1)

• Address space: 64M bytes for Rom bank0 ~ bank5, 128M bytes for SDRAM bank0 ~ bank1.

• Supports programmable 8/16-bit data bus width for ROM/SRAM bank and programmable 16/32bit data bus width for SDRAM bank

• Fixed bank start address from Rom bank 0 to bank 5 and SDRAM bank 0 to bank1.

• Eight memory banks:

– Six memory banks for ROM, SRAM, and

others (NAND etc.).

– Two memory banks for Synchronous DRAM.

• Complete Programmable access cycles for all memory banks.

• Supports external wait signals to expand the bus cycle.

• Supports self-refresh mode in SDRAM for power-down.

• Supports various types of ROM for booting (NOR Flash, EEPROM, OneNAND, IROM and others).

2.1.3 NAND Flash

• Supports booting from NAND flash memory by selecting OM as IROM boot mode. (Only 8bit Nand and 8ECC is supported when it boots)

• 64KB for internal SRAM Buffer(8KB internal buffer for booting)

• Supports storage memory for NAND flash memory after booting.

• Supports Advanced NAND flash

2.1.4 Cache Memory

• 4-way set-associative cache with I-Cache (16KB) and D-Cache (16KB).

• 8words length per line with one valid bit and two dirty bits per line.

• Pseudo random or round robin replacement algorithm.

• Write-through or write-back cache operation to update the main memory.

• The write buffer can hold 16 words of data and four addresses.

2.1.5 Clock & Power Manager

• On-chip MPLL and EPLL: EPLL generates the clock to operate USB Host, IIS, UART, etc. MPLL generates the clock to operate MCU at maximum 400MHz @ 1.3 V.

• Clock can be fed selectively to each function block by software.

• Power mode: Normal, Idle, Stop, Deep Stop and Sleep mode Normal mode: Normal operating mode Idle mode: The clock for only CPU is stopped. Stop mode: All clocks are stopped. Deep Stop mode: CPU power is gated and all clocks are stopped. Sleep mode: The Core power including all peripherals is shut down.

• Woken up by EINT[15:0] or RTC alarm & tick interrupt from Sleep mode and (Deep)STOP mode.

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S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

2 FEATURES (Continued)

2.1.6 Interrupt Controller

• 71 Interrupt sources (One Watch dog timer, 5 timers, 12 UARTs, 16 external interrupts, 6 DMA, 2 RTC, 2 ADC, 1 IIC, 1 SPI, 2 SDI, 2 USB, 4 LCD, 1 Battery Fault, 1 NAND, 1 AC97 and 1 I2S, 1 PCM, 1 2D)

• Level/Edge mode on external interrupt source

• Programmable polarity of edge and level

• Supports Fast Interrupt request (FIQ) for very

urgent interrupt request

2.1.7 Timer with Pulse Width Modulation (PWM)

• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation

• Programmable duty cycle, frequency, and polarity

• Dead-zone generation

• Supports external clock sources

2.1.8 RTC (Real Time Clock)

• Full clock feature: msec, second, minute, hour, date, day, month, and year

• 32.768 KHz operation

• Alarm interrupt

• Time tick interrupt

2.1.9 General Purpose Input/Output Ports

• 16 external interrupt ports

• 138 Multiplexed input/output ports

• Supports memory to memory, IO to memory,

memory to IO, and IO to IO transfers

• Burst transfer mode to enhance the transfer rate

2.1.11 LCD Controller

• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color

• Supports 16, 24 bpp non-palette true-color displays for color

• Supports maximum 16M color at 24 bpp mode

• Supports multiple screen size

– Typical actual screen size: 640x480, 320x240, 160x160, and others. – Maximum frame buffer size is 4Mbytes. – Maximum virtual screen size in 64K color mode: 2048x2048, and others

• Support 2 overlay windows for LCD

2.1.12 UART

• 4-channel UART with DMA-based or interrupt- based operation

• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive (Tx/Rx)

• Supports external clocks for the UART operation (EXTUARTCLK)

• Programmable baud rate upto 3Mbps

• Supports IrDA 1.0

• Loopback mode for testing

• Each channel has internal 64-byte Tx FIFO and

64-byte Rx FIFO.

2.1.10 DMA Controller

• 6-ch DMA controller

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PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

2 FEATURES (Continued)

2.1.13 A/D Converter & Touch Screen Interface

• 10-ch multiplexed ADC

• Max. 500KSPS and 12-bit Resolution

• Internal FET for direct Touch screen interface

2.1.14 Watchdog Timer

• 16-bit Watchdog Timer

• Interrupt request or system reset at time-out

2.1.15 IIC-Bus Interface

• 1-ch Multi-Master IIC-Bus

• Serial, 8-bit oriented and bi-directional data

transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode.

2.1.16 2D

• Line/Point Drawing

• BitBLT, Color Expansion.

• Maximum 2040*2040 image size

• Window clipping

• 90°/180°/270°/X-flip/Y-flip Rotation

• Totally 256 3-operand Raster Operation (ROP)

• Alpha Blending

• 16/24/32-bpp color format support

• YUV input support (4:2:2, 2-planar)

2.1.17 IIS Multi Audio Interface

• 1 ports audio interface with DMA-based operation.

• Up to 5.1ch, three 32bit 16depth Tx FIFOs, One 32bit 16depth Rx FIFO

• Serial, 8-/16-/24- bit per channel data transfers

• Supports IIS format and MSB-justified data

format

2.1.18 AC97 Audio Interface

• 1port AC97 for audio interface with DMA-based operation

• 16-bit Stereo Audio

2.1.19 PCM Audio Interface

• Mono, 16bit PCM, 1 ports audio interface.

• Master mode only, this block always sources the

main shift clock

• Input (16bit 32depth) and output(16bit 32depth)

FIFOs to buffer data

2.1.20 USB Host

• 2-port USB Host

• Complies with OHCI Rev. 1.0

• Compatible with USB Specification version 1.1

2.1.21 USB Device

• 1-port USB Device

• 9 Endpoints for USB Device

• Compatible with USB Specification version 2.0

2.1.22 SD/MMC Host Interface

• SD Standard Host Spec(ver2.0) compatible

• Dedicated DMA access support

• Compatible with SD Memory Card Protocol

version 2.1

• Compatible with SDIO Card Protocol version 1.0

• Compatible with HS-MMC Protocol version 4.2

• 512 Bytes FIFO for Tx/Rx

• CE-ATA mode support

2.1.23 SPI Interface

• Compatible with 1-ch Serial Peripheral Interface Protocol version 2.11 (1ch. High speed SPI interface)

• 2x8 bits Shift register for Tx/Rx DMA-based or interrupt-based operation

•

2.1.24 Operating Voltage Range

• Core: 1.3V for 400MHz TBD for 266MHz ROM/SRAM: 1.8V/ 2.5V/ 3.0V/ 3.3V

SDRAM: 1.8V/ 2.5V

• I/O: 1.8V/2.5V/3.3V(refer to electrical data)

2.1.25 Operating Frequency

• FCLK Up to 400(266)MHz

• HCLK Up to 133MHz

• PCLK Up to 67MHz

2.1.26 Package

• 330 FBGA 14x14

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S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

3 BLOCK DIAGRAM

Figure 1-1. S3C2416X Block Diagram

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PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

4 PIN ASSIGNMENTS

Figure 1-2. S3C2416X Pin Assignments (330-FBGA, 0.65mm pitch) Top view

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S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 400-Pin FBGA Pin Assignments − Pin Number Order (1/3)

Pin Pin Name Ball Pin Pin Name Ball Pin Pin Name Ball

RSMCLK/GPA23 B1

RSMVAD/GPA24 E4

RSMBWAIT/GPM

3 4

nRCS[3]/GPA14 F4

nRCS[4]/GPA15 C1

nRCS[5]/GPA16 G6 7 8 9

10 11 12 13 14 15

16 17

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

0 C2

nWAIT D3 FCLE/GPA17 G4 FALE/GPA18 D2

nFWE/GPA19 H6

nFRE/GPA20 D1 nFCE/GPA22 H4

FRnB/GPM1 E3

VDDi L8 VSSi N10

VDD_SRAM C5 VSS_SRAM E2

RDATA[15] H7 RDATA[14] E1 RDATA[13] J4 RDATA[12] F2 RDATA[11] J6 RDATA[10] F1

RDATA[9] K4 RDATA[8] G3 RDATA[7] K8 RDATA[6] G2 RDATA[5] K7 RDATA[4] G1 RDATA[3] L7 RDATA[2] H3 RDATA[1] K6 RDATA[0] H2

VDDi P10 VSSi J7

36 VDDi J8 73 VSSiarm L3 110

38 39

40 41

VDDiarm W8 VSSiarm P3

LEND/GPC0 J1

VDDiarm W9

VSSiarm P4 43 RGB_VCLK/GPC1 44 RGB_HSYNC/GPC2 45 RGB_VDEN/GPC4 46 RGB_VSYNC/GPC3 47 48 49 50 51 52

RGB_VD[2]/GPC10 M2

RGB_VD[3]/GPC11 N8

RGB_VD[4]/GPC12 M1

RGB_VD[5]/GPC13 N6

RGB_VD[6]/GPC14 N1

RGB_VD[7]/GPC15 P6 58 59 60 61 62

RGB_VD[10]/GPD2 R4 63

RGB_VD[11]/GPD3 P1 64

RGB_VD[12]/GPD4 T3 65

RGB_VD[13]/GPD5 P2 66

RGB_VD[14]/GPD6 W2 67

RGB_VD[15]/GPD7 R1 68

RGB_VD[16]/GPD8 Y2 69

RGB_VD[17]/GPD9 R2 70

RGB_VD[18]/GPD10 W3

RGB_VD[19]/GPD11 T1

GPC5 M6 GPC6 L1

GPC7 N4 RGB_VD[0]/GPC8 M3 RGB_VD[1]/GPC9 N7

RGB_VD[8]/GPD0 N2 RGB_VD[9]/GPD1 P7

VDDiarm R3 VSSiarm K3

VDDiarm J2

L4 K1

75 76

77 78

79 80 81 82 83 84 85 86 87

nXDACK/I2SSDO_1/GPB9 W4 88 89

nXDREQ/I2SSDO_2/GPB1

90 91

92 93 94 95 96 97 98 99

100 101 102 103 104 105 106 107 108 109

VSS_LCD T2

RGB_VD[20]/GPD12 V3

RGB_VD[21]/GPD13 U2 RGB_VD[22]/GPD14 U3 RGB_VD[23]/GPD15 V1

TOUT[0]/GPB0 T4 TOUT[1]/GPB1 V2 TOUT[2]/GPB2 U4 TOUT[3]/GPB3 W1

TCLK/GPB4 Y3

nXBACK/GPB5 U6

nXBREQ/RTCK/GPB6 V4

VDDiarm K2 VSSiarm U7

0 U5

UARTCLK/GPH12 Y4

nCTS[0]/GPH8 R7 nRTS[0]/GPH9 W5

TXD[0]/GPH0 P8

RXD[0]/GPH1 V6 nCTS[1]/GPH10 R8 nRTS[1]/GPH11 Y5

TXD[1]/GPH2 V7

RXD[1]/GPH3 W6

VDD_OP2 Y6 VSS_OP2 W7

VDDiarm V5

VSSiarm U8 CLKOUT[0]/GPH13 V8 CLKOUT[1]/GPH14 Y7

VDDiarm N3

VSSiarm U9

IICSCL/GPE14 V9 IICSDA/GPE15 Y8

I2SLRCK/GPE0/AC_nRES

ET/PCM_FSYNC

1-7

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

37 VSSi H11 74 VDD_LCD U1 111

I2SSCLK/GPE1/AC_SYNC/

PCM_SCLK

1-8

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 400-Pin FBGA Pin Assignments − Pin Number Order (2/3)

Pin Pin Name Ball Pin Pin Name Ball Pin Pin Name Ball

I2SCDCLK/GPE2/AC_BI

112 113 114

115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131

T_CLK/PCM_CDCLK P9

I2SSDI/GPE3/AC_SDI/P

CM_SDI Y10

I2SSDO/GPE4/AC_SDO

/PCM_SDO N9 SPIMISO/GPE11 W10 SPIMOSI/GPE12 R10

SPICLK/GPE13 V10

TXD[2]/GPH4 R11

RXD[2]/GPH5 Y11 TXD[3]/GPH6/nRTS2 U10 RXD[3]/GPH7/nCTS2 W11

SS/GPL13

V11 164

SD1_CLK/GPL9 U11

SD1_CMD/GPL8 Y12

VDD_SD W12 VSS_SD Y13

VDDi J13

VSSi L6 SD1_DAT[0]/GPL0 V12 SD1_DAT[1]/GPL1 W13 SD1_DAT[2]/GPL2 U12

132 SD1_DAT[3]/GPL3 Y14 174 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152

SD0_CLK/GPE5 V13

SD0_CMD/GPE6 W14 SD0_DAT[0]/GPE7 U13 SD0_DAT[1]/GPE8 Y15 SD0_DAT[2]/GPE9 R12

SD0_DAT[3]/GPE10 W15

VSS_MPLL V15

VDD_MPLL Y16

VSS_UPLL W16

UPLLCAP V16

VDD_UPLL Y17

VSSA_ADC P11

AIN[9] R13 AIN[8] W17 AIN[7] V14 AIN[6] V17 AIN[5] P12 AIN[4] Y18 AIN[3] N11 AIN[2] W18

154 155 156

157 158 159 160 161 162 163

165 166 167 168 169 170 171 172 173

175 176 177 178 179 180 181 182 183 184 185 186

AIN[0] Y19

Vref U15

VDDA_ADC R14

VDD_RTC W19

Xtirtc W20

Xtortc T17 OM[4] V18 OM[3] U16 OM[2] V19 OM[1] U17 OM[0] R17

VDDi M7 VSSi N13

EXTCLK P15

XTIpll V20

XTOpll U18 EINT[0]/GPF0 N15 EINT[1]/GPF1 T18 EINT[2]/GPF2 P17 EINT[3]/GPF3 R18 EINT[4]/GPF4 N17 EINT[5]/GPF5 U19 EINT[6]/GPF6 M17 EINT[7]/GPF7 U20

PWR_EN M15

nBATT_FLT P18

nRESET M14

VDD_OP1 T19

VSS_OP1 T20

VDDalive R19

VSSalive R20

TDO M13 TMS P19

196 197 198

EINT[11]/GPG3 N20

VDD_OP3 M18

VSS_OP3 M19 199 EINT[12]/GPG4 K14 200 EINT[13]/GPG5 M20 201 EINT[14]/GPG6 K13 202 EINT[15]/GPG7 L18 203 VDD_USBOSC L19 204 VSS33C L20 205 XO_UDEV K18 206 XI_UDEV K19 207 VSSIP_UDEV K20 208 VDDI_UDEV J19 209 VSS33T H18 210 DM_UDEV J20 211 REXT H20 212 DP_UDEV H19 213 VSS33T J17 214 VDD33 G18 215 VDD33 G19 216 SDATA[31]/GPK15 J18 217 SDATA[30]/GPK14 G20 218 SDATA[29]/GPK13 J15 219 SDATA[28]/GPK12 F20 220 SDATA[27]/GPK11 J14 221 SDATA[26]/GPK10 F19 222 VDDi G11 223 VSSi H13 224 SDATA[25]/GPK9 H17 225 SDATA[24]/GPK8 F18 226 SDATA[23]/GPK7 H15 227 SDATA[22]/GPK6 E20 228 SDATA[21]/GPK5 G17

187 TDI L17 229 SDATA[20]/GPK4 E19 188 TCK P20 230 SDATA[19]/GPK3 G15 189 nTRST L15 231 SDATA[18]/GPK2 E18 190 DP L14 232 SDATA[17]/GPK1 F17 191 DN L13 233 SDATA[16]/GPK0 D20 192 nRSTOUT N18 234 VDD_SDRAM C16 193 EINT[8]/GPG0 K17 235 VSS_SDRAM C15 194 EINT[9]/GPG1 N19 236 SDATA[15] E17

1-9

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

153

AIN[1] U14

195 EINT[10]/GPG2 K15 237 SDATA[14] C18

1-10

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 400-Pin FBGA Pin Assignments − Pin Number Order (3/3)

Pin Pin Name Ball Pin Pin Name Ball Pin Pin Name Ball

238 SDATA[13] C19 281 SADDR[9] A10 324 nRCS[0] D5 239 SDATA[12] B19 282 SADDR[10] F11 325 nRCS[1]/GPA12 B2 240 SDATA[11] C20 283 SADDR[11] B10 326 nRCS[2]/GPA13 D4 241 SDATA[10] A19 284 SADDR[12] C10 327 VDD_SDRAM H14 242 SDATA[9] B20 285 SADDR[13] A9 328 VDD_SDRAM N12 243 SDATA[8] B18 286 SADDR[14] D10 329 VDD_SDRAM P13 244 SDATA[7] D17 287 SADDR[15] B9 330 VDD_SRAM H1 245 SDATA[6] A18 288 FSOURCE A8 246 SDATA[5] D16 289 VGATE B8 247 SDATA[4] C17 290 VDDi G13 248 SDATA[3] G14 291 VSSi J3

249 SDATA[2] B17 292

RADDR[25]/RDATA

_OEN/GPA10 F10 250 SDATA[1] D15 293 RADDR[24]/GPA9 C8 251 SDATA[0] A17 294 RADDR[23]/GPA8 G10 252 VDD_SDRAM D19 295 RADDR[22]/GPA7 A7 253 VSS_SDRAM D18 296 RADDR[21]/GPA6 H10 254 DQS[1] F14 297 RADDR[20]/GPA5 B7 255 DQS[0] C14 298 RADDR[19]/GPA4 C9 256 DQM[3]/GPA26 D14 299 RADDR[18]/GPA3 C7 257 DQM[2]/GPA25 B16 300 RADDR[17]/GPA2 D9 258 DQM[1] C13 301 RADDR[16]/GPA1 A6 259 DQM[0] A16 302 RADDR[15] F9 260 nSCS[0] F13 303 RADDR[14] B6 261 nSCS[1] B15 304 RADDR[13] G9 262 nSWE D13 305 RADDR[12] C6 263 SCLK A15 306 RADDR[11] H9 264 VDDi N14 307 RADDR[10] A5 265 VSSi M8 308 VDD_SRAM F3 266 nSCLK F12 309 VSS_SRAM B5 267 SCKE B14 310 RADDR[9] D8 268 nSRAS G12 311 RADDR[8] A4 269 nSCAS A14 312 RADDR[7] F8 270 SADDR[0] C12 313 RADDR[6] B4 271 SADDR[1] B13 314 RADDR[5] G8 272 SADDR[2] D12 315 RADDR[4] C4 273 SADDR[3] A13 316 RADDR[3] H8 274 SADDR[4] H12 317 RADDR[2] A3 275 SADDR[5] B12 318 RADDR[1] D7 276 VDD_SDRAM A12 319 RADDR[0]/GPA0 B3 277 VSS_SDRAM B11 320 nRBE1 F7 278 SADDR[6] C11 321 nRBE0 C3 279 SADDR[7] A11 322 nROE D6

1-11

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

280 SADDR[8] D11 323 nRWE A2

Table 1-2. S3C2416X 330-Pin FBGA Pin Assignments

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

1 RSMCLK/GPA23 RSMCLK -/- O(L) pvhbsudtbrt 2 RSMVAD/GPA24 RSMVAD -/- O(H) pvhbsudtbrt 3 RSMBWAIT/GPM0 RSMBWAIT -/- I pvhbsudtbrt 4 nRCS3/GPA14 nRCS3 - O(H) pvhbsudtbrt 5 nRCS4/GPA15 nRCS4 - O(H) pvhbsudtbrt 6 nRCS5/GPA16 nRCS5 -/- O(H) pvhbsudtbrt

7 nWAIT nWAIT - I

pvhbsudtbrtpvisud

crt_hvt 8 FCLE/GPA17 FCLE - O(L) pvhbsudtbrt 9 FALE/GPA18 FALE - O(L) pvhbsudtbrt

10 nFWE/GPA19 nFWE - O(H) pvhbsudtbrt 11 nFRE/GPA20 nFRE - O(H) pvhbsudtbrt 12 nFCE/GPA22 nFCE - O(H) pvhbsudtbrt 13 FRnB/GPM1 FRnB - I pvhbsudtbrt 14 VDDi VDDi - P vddivh_alv 15 VSSi VSSi - P vssipvh_alv 16 VDD_SRAM VDD_SRAM - P vddtvh_alv 17 VSS_SRAM VSS_SRAM - P vsstvh_alv 18 RDATA15 RDATA15 - Hi-z pvhbsudtbrt 19 RDATA14 RDATA14 - Hi-z pvhbsudtbrt 20 RDATA13 RDATA13 - Hi-z pvhbsudtbrt 21 RDATA12 RDATA12 - Hi-z pvhbsudtbrt 22 RDATA11 RDATA11 - Hi-z pvhbsudtbrt 23 RDATA10 RDATA10 - Hi-z pvhbsudtbrt 24 RDATA9 RDATA9 - Hi-z pvhbsudtbrt 25 RDATA8 RDATA8 - Hi-z pvhbsudtbrt 26 RDATA7 RDATA7 - Hi-z pvhbsudtbrt 27 RDATA6 RDATA6 - Hi-z pvhbsudtbrt 28 RDATA5 RDATA5 - Hi-z pvhbsudtbrt 29 RDATA4 RDATA4 - Hi-z pvhbsudtbrt 30 RDATA3 RDATA3 - Hi-z pvhbsudtbrt 31 RDATA2 RDATA2 - Hi-z pvhbsudtbrt 32 RDATA1 RDATA1 - Hi-z pvhbsudtbrt

1-12

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

33 RDATA0 RDATA0 - Hi-z pvhbsudtbrt 34 VDDi VDDi - P vddivh_alv 35 VSSi VSSi - P vssipvh_alv 36 VDDi VDDi - P vddivh_alv 37 VSSi VSSi - P vssipvh_alv 38 VDDiarm VDDiarm - P vddicvlh_alv 39 VSSiarm VSSiarm - P vssicvlh_alv 40 RGB_LEND/GPC0 GPC0 -/- I pvhbsudtart 41 VDDiarm VDDiarm - P vddicvlh_alv 42 VSSiarm VSSiarm - P vssicvlh_alv 43 RGB_VCLK/GPC1 GPC1 -/- I pvhbsudtart 44 RGB_VLINE/GPC2 GPC2 -/- I pvhbsudtart 45 RGB_VDEN/GPC4 GPC4 -/- I pvhbsudtart 46 RGB_VSYNC/GPC3 GPC3 -/- I pvhbsudtart 47 GPC5 GPC5 -/- I pvhbsudtart 48 GPC6 GPC6 -/- I pvhbsudtart 49 GPC7 GPC7 -/- I pvhbsudtart 50 RGB_VD0/GPC8 GPC8 -/- I pvhbsudtart 51 RGB_VD1/GPC9 GPC9 -/- I pvhbsudtart 52 RGB_VD2/GPC10 GPC10 -/- I pvhbsudtart 53 RGB_VD3/GPC11 GPC11 -/- I pvhbsudtart 54 RGB_VD4/GPC12 GPC12 -/- I pvhbsudtart 55 RGB_VD5/GPC13 GPC13 -/- I pvhbsudtart 56 RGB_VD6/GPC14 GPC14 -/- I pvhbsudtart 57 RGB_VD7/GPC15 GPC15 -/- I pvhbsudtart 58 RGB_VD8/GPD0 GPD0 -/- I pvhbsudtart 59 RGB_VD9/GPD1 GPD1 -/- I pvhbsudtart 60 VDDiarm VDDiarm - P vddicvlh_alv 61 VSSiarm VSSiarm - P vssicvlh_alv 62 RGB_VD10/GPD2 GPD2 -/- I pvhbsudtart 63 RGB_VD11/GPD3 GPD3 -/- I pvhbsudtart 64 RGB_VD12/GPD4 GPD4 -/- I pvhbsudtart 65 RGB_VD13/GPD5 GPD5 -/- I pvhbsudtart 66 RGB_VD14/GPD6 GPD6 -/- I pvhbsudtart 67 RGB_VD15/GPD7 GPD7 -/- I pvhbsudtart 68 RGB_VD16/GPD8 GPD8 -/- I pvhbsudtart

1-13

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

69 RGB_VD17/GPD9 GPD9 -/- I pvhbsudtart 70 RGB_VD18/GPD10 GPD10 -/- I pvhbsudtart 71 RGB_VD19/GPD11 GPD11 -/- I pvhbsudtart 72 VDDiarm VDDiarm - P vddicvlh_alv 73 VSSiarm VSSiarm - P vssicvlh_alv 74 VDD_LCD VDD_LCD - P vddtvh_alv 75 VSS_LCD VSS_LCD - P vsstvh_alv 76 RGB_VD20/GPD12 GPD12 -/- I pvhbsudtart 77 RGB_VD21/GPD13 GPD13 -/- I pvhbsudtart 78 RGB_VD22/GPD14 GPD14 -/- I pvhbsudtart 79 RGB_VD23/GPD15 GPD15 -/- I pvhbsudtart 80 TOUT0/GPB0 GPB0 -/- I pvhbsudtart 81 TOUT1/GPB1 GPB1 -/- I pvhbsudtart 82 TOUT2/GPB2 GPB2 -/- I pvhbsudtart 83 TOUT3/GPB3 GPB3 -/- I pvhbsudtart 84 TCLK/GPB4 GPB4 -/- I pvhbsudtart 85 nXBACK/GPB5 GPB5 -/- I pvhbsudtart 86 nXBREQ/GPB6/RTCK RTCK -/- I pvhbsudtart 87 nXDACK/GPB9/I2SSDO_1 GPB9 -/- I pvhbsudtart 88 89 VSSiarm VSSiarm - P vssicvlh_alv 90 nXDREQ/GPB10/I2SSDO_2 GPB10 -/- I pvhbsudtart 91 EXTUARTCLK/GPH12 GPH12 -/- I pvhbsudtart 92 nCTS0/GPH8 GPH8 -/- I pvhbsudtart 93 nRTS0/GPH9 GPH9 -/- I pvhbsudtart 94 TXD0/GPH0 GPH0 -/- I pvhbsudtart 95 RXD0/GPH1 GPH1 -/- I pvhbsudtart 96 nCTS1/GPH10 GPH10 -/- I pvhbsudtart 97 nRTS1/GPH11 GPH11 -/- I pvhbsudtart 98 TXD1/GPH2 GPH2 -/- I pvhbsudtart

99 RXD1/GPH3 GPH3 -/- I pvhbsudtart 100 VDD_OP2 VDD_OP2 - P vddtvh_alv 101 VSS_OP2 VSS_OP2 - P vsstvh_alv 102 VDDiarm VDDiarm - P vddicvlh_alv 103 VSSiarm VSSiarm - P vssicvlh_alv 104 CLKOUT0/GPH13 GPH13 -/- I pvhbsudtart

1-14

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

105 CLKOUT1/GPH14 GPH14 -/- I pvhbsudtart 106 VDDiarm VDDiarm - P vddicvlh_alv 107 VSSiarm VSSiarm - P vssicvlh_alv 108 IICSCL/GPE14 GPE14 -/- I pvhbsudtart 109 IICSDA/GPE15 GPE15 -/- I pvhbsudtart

110

111

112

113

114

I2SLRCK/GPE0/

AC_nRESET/PCM_FSYNC

I2SSCLK/GPE1/AC_SYNC/PC

M_SCLK

I2SCDCLK/GPE2/

AC_BIT_CLK0/PCM_CDCLK

I2SSDI/GPE3/AC_SDI0/PCM_S

I2SSDO_0/GPE4/AC_SDO0/P

CM_SDO

GPE0

GPE1

GPE2

GPE3

GPE4

-/-/- I

pvhbsudtart

115 SPIMISO/GPE11 GPE11 -/- I pvhbsudtart 116 SPIMOSI/GPE12 GPE12 -/- I pvhbsudtart 117 SPICLK/GPE13 GPE13 -/- I pvhbsudtart 118 TXD2/GPH4 GPH4 -/- I pvhbsudtart 119 RXD2/GPH5 GPH5 -/- I pvhbsudtart 120 TXD3/GPH6/nRTS2 GPH6 -/-/- I pvhbsudtart 121 RXD3/GPH7/nCTS2 GPH7 -/-/- I pvhbsudtart 122 SS/GPL13 GPL13 -/- I pvhbsudtart 123 SD1_CLK/GPL9 GPL9 -/- I pvhbsudtart 124 SD1_CMD/GPL8 GPL8 -/- I pvhbsudtart 125 VDD_SD VDD_SD - P vddtvh_alv 126 VSS_SD VSS_SD - P vsstvh_alv 127 VDDi VDDi - P vddivh_alv 128 VSSi VSSi - P vssipvh_alv 129 SD1_DAT[0]/GPL0 GPL0 -/- I pvhbsudtart 130 SD1_DAT[1]/GPL1 GPL1 -/- I pvhbsudtart 131 SD1_DAT[2]/GPL2 GPL2 -/- I pvhbsudtart 132 SD1_DAT[3]/GPL3 GPL3 -/- I pvhbsudtart 133 SD0_CLK/GPE5 GPE5 -/-/- I pvhbsudtart 134 SD0_CMD/GPE6 GPE6 -/-/- I pvhbsudtart 135 SD0_DAT[0]/GPE7 GPE7 -/-/- I pvhbsudtart 136 SD1_DAT[1]/GPE8 GPE8 -/-/- I pvhbsudtart 137 SD1_DAT[2]/GPE9 GPE9 -/-/- I pvhbsudtart

1-15

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

138 SD1_DAT[3]/GPE10 GPE10 -/- I pvhbsudtart 139 VSSA_MPLL VSSA_MPLL - P vsstvlh_alv 140 VDDA_MPLL VDDA_MPLL - P vddtvlh_alv 141 VSSA_EPLL VSSA_EPLL - P vsstvlh_alv 142 UPLLCAP UPLLCAP - AI pvhbr 143 VDDA_EPLL VDDA_EPLL - P vddtvlh_alv 144 VSSA_ADC VSSA_ADC - P 145 AIN9(XP) AIN9 AI vsstvh_alv 146 AIN8(XM) AIN8 - AI pvhbr 147 AIN7(YP) AIN7 - AI pvhbr 148 AIN6(YM) AIN6 - AI pvhbr 149 AIN5 AIN5 - AI pvhbr 150 AIN4 AIN4 - AI pvhbr 151 AIN3 AIN3 - AI pvhbr 152 AIN2 AIN2 - AI pvhbr 153 AIN1 AIN1 - AI pvhbr 154 AIN0 AIN0 - AI pvhbr 155 Vref Vref - AI pvhbr 156 VDDA_ADC VDDA_ADC - P vddtvh_alv 157 VDD_RTC VDD_RTC - P vddrtcvh_alv 158 Xtirtc Xtirtc - AI pvhsosca 159 Xtortc Xtortc - AO pvhsosca 160 OM[4] OM[4] - I pvhbsudtart_alv 161 OM[3] OM[3] - I pvhbsudtart_alv 162 OM[2] OM[2] - I pvhbsudtart_alv 163 OM[1] OM[1] - I pvhbsudtart_alv 164 OM[0] OM[0] - I pvhbsudtart_alv 165 VDDi VDDi - P vddicvlh_alv 166 VSSi VSSi - P vssicvlh_alv 167 EXTCLK EXTCLK - I pvhbsudtart 168 XTIpll XTIpll - AI pvhsoscbrt 169 XTOpll XTOpll - AO pvhsoscbrt 170 EINT0/GPF0 GPF0 -/- I pvhbsudtart_alv 171 EINT1/GPF1 GPF1 -/- I pvhbsudtart_alv 172 EINT2/GPF2 GPF2 -/- I pvhbsudtart_alv 173 EINT3/GPF3 GPF3 -/- I pvhbsudtart_alv

1-16

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

174 EINT4/GPF4 GPF4 -/- I pvhbsudtart_alv 175 EINT5/GPF5 GPF5 -/- I pvhbsudtart_alv 176 EINT6/GPF6 GPF6 -/- I pvhbsudtart_alv 177 EINT7/GPF7 GPF7 -/- I pvhbsudtart_alv 178 PWR_EN PWR_EN O(L) O(H) pvhbsudtart_alv 179 BATT_FLT BATT_FLT - I pvhbsudtart 180 nRESET nRESET - I pvhbsudtart 181 VDD_OP1 VDD_OP1 - P vddtvh_alv 182 VSS_OP1 VSS_OP1 - P vsstvh_alv 183 VDDalive VDDalive - P vddivh_alv 184 VSSalive VSSalive - P vssivh_alv 185 TDO TDO - O pvhbsudtart 186 TMS TMS - I pvhbsudtart 187 TDI TDI - I pvhbsudtart 188 TCK TCK - I pvhbsudtart 189 nTRST nTRST - I pvhbsudtart 190 DP DP - AI usb6002x1_t 191 DN DN - AI usb6002x1_t 192 nRSTOUT nRSTOUT O(H) O(L) pvhbsudtart 193 EINT8/GPG0 GPG0 -/- I pvhbsudtart_alv 194 EINT9/GPG1 GPG1 -/- I pvhbsudtart_alv 195 EINT10/GPG2 GPG2 -/- I pvhbsudtart_alv 196 EINT11/GPG3 GPG3 -/- I pvhbsudtart_alv 197 VDD_OP3 VDD_OP3 - P vddtvh_alv 198 VSS_OP3 VSS_OP3 - P vsstvh_alv 199 EINT12/GPG4 GPG4 -/-/- I pvhbsudtart_alv 200 EINT13/GPG5 GPG5 -/- I pvhbsudtart_alv 201 EINT14/GPG6 GPG6 -/- I pvhbsudtart_alv 202 EINT15/GPG7 GPG7 -/- I pvhbsudtart_alv 203 VDD_USBOSC VDD_USBOSC - P vddtvh_alv 204 VSS33C VSSA33C - P vsstvh_alv 205 XO_UDEV XO_UDEV - I pvhsoscbrt 206 XI_UDEV XI_UDEV - I pvhsoscbrt 207 VSSI_UDEV VSSIP_UDEV - P vssipvh_usb_alv 208 VDDI_UDEV VDDI_UDEV - P vddivh_usb_alv 209 VSS33T VSSA33T - P vsstvh_alv

1-17

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

210 DM_UDEV DM_UDEV Hi-z pvhtbr 211 REXT REXT - pvhbr 212 DP_UDEV DP_UDEV - Hi-z pvhtbr 213 VSS33T2 VSSA33T2 - P vsstvh_alv 214 VDD33 VDDA33T1 - P vddtvh_alv 215 VDD33 VDDA33T1 - P vddtvh_alv 216 SDATA31/GPK15 SDATA31 - Hi-z pvmbsudtbrt 217 SDATA30/GPK14 SDATA30 - Hi-z pvmbsudtbrt 218 SDATA29/GPK13 SDATA29 - Hi-z pvmbsudtbrt 219 SDATA28/GPK12 SDATA28 - Hi-z pvmbsudtbrt 220 SDATA27/GPK11 SDATA27 - Hi-z pvmbsudtbrt 221 SDATA26/GPK10 SDATA26 - Hi-z pvmbsudtbrt 222 VDDi VDDi - P vddivh_alv 223 VSSi VSSi - P vssipvh_alv 224 SDATA25/GPK9 SDATA25 - Hi-z pvmbsudtbrt 225 SDATA24/GPK8 SDATA24 - Hi-z pvmbsudtbrt 226 SDATA23/GPK7 SDATA23 - Hi-z pvmbsudtbrt 227 SDATA22/GPK6 SDATA22 - Hi-z pvmbsudtbrt 228 SDATA21/GPK5 SDATA21 - Hi-z pvmbsudtbrt 229 SDATA20/GPK4 SDATA20 - Hi-z pvmbsudtbrt 230 SDATA19/GPK3 SDATA19 - Hi-z pvmbsudtbrt 231 SDATA18/GPK2 SDATA18 - Hi-z pvmbsudtbrt 232 SDATA17/GPK1 SDATA17 - Hi-z pvmbsudtbrt 233 SDATA16/GPK0 SDATA16 - Hi-z pvmbsudtbrt 234 VDD_SDRAM VDD_SDRAM - Hi-z vddtvm_alv 235 VSS_SDRAM VSS_SDRAM - Hi-z vsstvm_alv 236 SDATA15 SDATA15 - Hi-z pvmbsudtbrt 237 SDATA14 SDATA14 - Hi-z pvmbsudtbrt 238 SDATA13 SDATA13 - Hi-z pvmbsudtbrt 239 SDATA12 SDATA12 - Hi-z pvmbsudtbrt 240 SDATA11 SDATA11 - Hi-z pvmbsudtbrt 241 SDATA10 SDATA10 - Hi-z pvmbsudtbrt 242 SDATA9 SDATA9 - Hi-z pvmbsudtbrt 243 SDATA8 SDATA8 - Hi-z pvmbsudtbrt 244 SDATA7 SDATA7 - Hi-z pvmbsudtbrt 245 SDATA6 SDATA6 - Hi-z pvmbsudtbrt

1-18

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

246 SDATA5 SDATA5 - Hi-z pvmbsudtbrt 247 SDATA4 SDATA4 - Hi-z pvmbsudtbrt 248 SDATA3 SDATA3 - Hi-z pvmbsudtbrt 249 SDATA2 SDATA2 - Hi-z pvmbsudtbrt 250 SDATA1 SDATA1 - Hi-z pvmbsudtbrt 251 SDATA0 SDATA0 - Hi-z pvmbsudtbrt 252 VDD_SDRAM VDD_SDRAM - Hi-z vddtvm_alv 253 VSS_SDRAM VSS_SDRAM - Hi-z vsstvm_alv 254 DQS1 DQS1 O(L) Hi-z pvmbsudtbrt 255 DQS0 DQS0 O(L) Hi-z pvmbsudtbrt 256 DQM3/GPA26 DQM3 O(H)- O(L) pvmbsudtbrt 257 DQM2/GPA25 DQM2 O(H) O(L) pvmbsudtbrt 258 DQM1 DQM1 O(H) O(L) pvmbsudtbrt 259 DQM0 DQM0 O(H) O(L) pvmbsudtbrt 260 nSCS[0] nSCS[0] O(H) O(H) pvmbsudtbrt 261 nSCS[1] nSCS[1] O(H) O(H) pvmbsudtbrt 262 nSWE nSWE O(H) O(H) pvmbsudtbrt 263 SCLK SCLK O(L) O(SCLK) pvmbsudtbrt 264 VDDi VDDi - P vddivh_alv 265 VSSi VSSi - P vssipvh_alv 266 nSCLK nSCLK O(H) O(nSCLK) pvmbsudtbrt 267 SCKE SCKE O(L) O(L) pvmbsudtbrt 268 nSRAS nSRAS O(H) O(H) pvmbsudtbrt 269 nSCAS nSCAS O(H) O(H) pvmbsudtbrt 270 SADDR0 SADDR0 - O(L) pvmbsudtbrt 271 SADDR1 SADDR1 - O(L) pvmbsudtbrt 272 SADDR2 SADDR2 - O(L) pvmbsudtbrt 273 SADDR3 SADDR3 - O(L) pvmbsudtbrt 274 SADDR4 SADDR4 - O(L) pvmbsudtbrt 275 SADDR5 SADDR5 - O(L) pvmbsudtbrt 276 VDD_SDRAM VDD_SDRAM - P vddtvm_alv 277 VSS_SDRAM VSS_SDRAM - P vsstvm_alv 278 SADDR6 SADDR6 - O(L) pvmbsudtbrt 279 SADDR7 SADDR7 - O(L) pvmbsudtbrt 280 SADDR8 SADDR8 - O(L) pvmbsudtbrt 281 SADDR9 SADDR9 - O(L) pvmbsudtbrt

1-19

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

282 SADDR10 SADDR10 - O(L) pvmbsudtbrt 283 SADDR11 SADDR11 - O(L) pvmbsudtbrt 284 SADDR12 SADDR12 - O(L) pvmbsudtbrt 285 SADDR13 SADDR13 - O(L) pvmbsudtbrt 286 SADDR14 SADDR14 - O(L) pvmbsudtbrt 287 SADDR15 SADDR15 - O(L) pvmbsudtbrt 288 FSOURCE FSOURCE - P pvhtbr_efuse00 289 VGATE VGATE - P pvhtbr_efuse00 290 VDDi VDDi - P vddivh_alv 291 VSSi VSSi - P vssipvh_alv

292

RADDR25/RDATA_OEN/GPA1

RADDR25

-/- O(L)

pvhbsudtbrt

293 RADDR24/GPA9 RADDR24 -/- O(L) pvhbsudtbrt 294 RADDR23/GPA8 RADDR23 -/- O(L) pvhbsudtbrt 295 RADDR22/GPA7 RADDR22 -/- O(L) pvhbsudtbrt 296 RADDR21/GPA6 RADDR21 -/- O(L) pvhbsudtbrt 297 RADDR20/GPA5 RADDR20 -/- O(L) pvhbsudtbrt 298 RADDR19/GPA4 RADDR19 -/- O(L) pvhbsudtbrt 299 RADDR18/GPA3 RADDR18 -/- O(L) pvhbsudtbrt 300 RADDR17/GPA2 RADDR17 -/- O(L) pvhbsudtbrt 301 RADDR16/GPA1 RADDR16 -/- O(L) pvhbsudtbrt 302 RADDR15 RADDR15 -/- O(L) pvhbsudtbrt 303 RADDR14 RADDR14 - O(L) pvhbsudtbrt 304 RADDR13 RADDR13 - O(L) pvhbsudtbrt 305 RADDR12 RADDR12 - O(L) pvhbsudtbrt 306 RADDR11 RADDR11 - O(L) pvhbsudtbrt 307 RADDR10 RADDR10 - O(L) pvhbsudtbrt 308 VDD_SRAM VDD_SRAM - P vddtvh_alv 309 VSS_SRAM VSS_SRAM - P vsstvh_alv 310 RADDR9 RADDR9 - O(L) pvhbsudtbrt 311 RADDR8 RADDR8 - O(L) pvhbsudtbrt 312 RADDR7 RADDR7 - O(L) pvhbsudtbrt 313 RADDR6 RADDR6 - O(L) pvhbsudtbrt 314 RADDR5 RADDR5 - O(L) pvhbsudtbrt 315 RADDR4 RADDR4 - O(L) pvhbsudtbrt 316 RADDR3 RADDR3 - O(L) pvhbsudtbrt

1-20

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Number

Name

Default

Function

I/O

State

I/O State

@nRESET

I/O

Type

@Sleep

317 RADDR2 RADDR2 - O(L) pvhbsudtbrt 318 RADDR1 RADDR1 - O(L) pvhbsudtbrt 319 RADDR0/GPA0 RADDR0 -/- O(L) pvhbsudtbrt 320 nRBE1 nRBE1 - O(H) pvhbsudtbrt 321 nRBE0 nRBE0 - O(H) pvhbsudtbrt 322 nROE nROE - O(H) pvhbsudtbrt 323 nRWE nRWE - O(H) pvhbsudtbrt 324 nRCS0 nRCS0 - O(H) pvhbsudtbrt 325 nRCS1/GPA12 nRCS1 - O(H) pvhbsudtbrt 326 nRCS2/GPA13 nRCS2 - O(H) pvhbsudtbrt 327 VDD_SDRAM VDD_SDRAM - P Vddtvm_alv 328 VDD_SDRAM VDD_SDRAM - P Vddtvm_alv 329 VDD_SDRAM VDD_SDRAM - P vddtvm_alv 330 VDD_SRAM VDD_SRAM - P vddtvh_alv

NOTES:

1. The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master.

2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode.

3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register.

4. AI/AO means analog input/analog output.

5. P, I, and O mean power, input and output respectively.

6. The I/O state @nRESET shows the pin status in the @nRESET duration below.

@nRESET > 10 cycle4 OSC in

nRESET

EXTCLK

1-21

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Table 1-3. I/O Cell Types and Descriptions

Cell Name Ftn.

Interface

Voltage

CMOS

/Schmitt

Retention

Pull-up

/Control

Pull-down

/Control

Driver Strength

Pvhbdc Bi 1.8/2.5/3.3V analog - - - -

Pvhbr Bi 1.8/2.5/3.3V analog - - - -

pvhbsudtart Bi 1.8/2.5/3.3V Schmit Y Y Y 2.6/5.2/7.8/10.5mA

pvhbsudtart_alv Bi 1.8/2.5/3.3V Schmit N Y Y 2.6/5.2/7.8/10.5mA

pvhbsudtbrt Bi 1.8/2.5/3.3V Schmit Y Y Y 3.3/6.6/9.9/13.2mA

pvhckdsrt I 1.8/2.5/3.3V Schmit - N N -

pvhsosca OSC 1.8/2.5/3.3V Schmit - N N X1(2.5/3.3),X2(1.8)

pvhsoscbrt OSC 1.8/2.5/3.3V schmit Y N N X1/X2/X3/X4

Pvhtbr Bi 1.8/2.5/3.3V analog - - - -

pvhtbr00_efuse Bi 1.8/2.5/3.3V analog - - - -

pvmbsudtbrt Bi 1.8/2.5V schmit Y Y Y 4.9/9.8/14.8/19.7mA

usb6002x1_t Bi 1.8/2.5/3.3V

vddicvlh_alv PWR 1.3V

vddivh_alv PWR 1.3V

vddivh_usb_alv PWR 1.2V

vddrtcvh_alv PWR 1.8/2.5/3.3V

vddtvh_alv PWR 1.8/2.5/3.3V

vddtvlh_alv PWR 1.3V

vddtvm_alv PWR 1.8V

vssicvlh_alv GND 0V

vssipvh_alv GND 0V

vssipvh_usb_al

GND 0V

vsstvh_alv GND 0V

vsstvlh_alv vsstvm_alv

GND 0V GND 0V

1-22

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

4.1 SIGNAL DESCRIPTIONS

Table 1-4. S3C2416X Signal Descriptions

Signal In/Out Description

Reset, Clock & Power

XTIpll AI Crystal input signals for internal osc circuit.

When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK source. If it isn't used, it has to be Low (0V)

XTOpll AO Crystal output signals for internal osc circuit.

When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK

source. If it isn't used, it has to be float NC AI Not connected. EPLLCAP AI Loop filter capacitor for Extra PLL XTIrtc AI 32.768 kHz crystal input for RTC. If it isn’t used, it has to be High

(VDD_RTC=3.3V). XTOrtc AO 32.768 kHz crystal output for RTC. If it isn’t used, it has to be float. CLKOUT[1:0] O Clock output signal. The CLKSEL of MISCCR(GPIO register) register

configures the clock output mode among the MPLL_CLK, EPLL CLK,

ARMCLK, HCLK, PCLK. nRESET ST nRESET suspends any operation in progress and places S3C2416X into

a known reset state. For a reset, nRESET must be held to L level for at

least 4 OSCin after the processor power has been stabilized. nRSTOUT O For external device reset control (nRSTOUT = nRESET & nWDTRST &

SW_RESET) *SW_RESET = nRSTCON of GPIO MISCCR PWREN O core power on-off control signal nBATT_FLT I Probe for battery state (Does not wake up at Sleep mode in case of low

battery state). If it isn’t used, it has to be High (3.3V). OM[4:0] I OM[4:0] set operating modes of S3C2416X

Refer to “S3C2416X Operation Mode Description Table” EXTCLK I External clock source.

When OM[0] = 1, EXTCLK is used for MPLL and EPLL CLK source.

If it isn't used, it has to be Low (0V).

Memory Interface (ROM/SRAM/NAND)

RADDR[25:0] O RADDR[25:0] (Address Bus) outputs the memory address of the

corresponding bank . RDATA[15:0] IO RDATA[15:0] (Data Bus) inputs data during memory read and outputs

data during memory write. The bus width is programmable among 8/16-

bit. nRCS[5:0] O nRCS[5:0] (Chip Select) are activated when the address of a memory is

within the address region of each bank. The number of access cycles and

the bank size can be programmed. nRWE O nRWE (Write Enable) indicates that the current bus cycle is a write cycle. nROE O nOE (Output Enable) indicates that the current bus cycle is a read cycle.

1-23

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Signal In/Out Description

nRBE[1:0] O Upper byte/lower byte enable (In case of 16-bit SRAM) nWAIT I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L,

the current bus cycle cannot be completed. If nWAIT signal isn’t used in your system, nWAIT signal must be tied on pull-up resistor.

SDRAM I/F

SADDR[15:0] O SDRAM Address bus SDATA[31:0] IO SDRAM Data Bus nSRAS O SDRAM row address strobe nSCAS O SDRAM column address strobe nSWE O SDRAM write enable nSCS[1:0] O SDRAM chip select DQM[3:0] O SDRAM data mask DQS[1:0] O mDDR/DDR2 Data Strobe SCLK O SDRAM clock nSCLK O mDDR/DDR2 Conversion clock SCKE O SDRAM clock enable NAND Flash FCLE O Command latch enable FALE O Address latch enable nFCE O Nand flash chip enable nFRE O Nand flash read enable nFWE O Nand flash write enable FRnB I Nand flash ready/busy

SMC/OneNAND

RSMCLK I/O SMC Clock RSMVAD O SMC Address Valid RSMBWAIT O SMC Burst Wait

LCD Control Unit

RGB_VD/SYS_VD[23:0] O RGB I/F Video Data: RGB_VD[23:0]

i80 I/F Video DataSYS_VD[17:0]

RGB_VCLK/SYS_WR O RGB I/F LCD Clock

i80 I/F Write Enable

RGB_VSYNC/SYS_CS1 O RGB I/F Vertical Sync. Signal

i80 I/F Sub LCD Select

RGB_HSYNC/SYS_CS0 O RGB I/F Horizontal Sync. Signal

i80 I/F Main LCD Select

RGB_VDEN/SYS_RS O RGB I/F Data Enable

i80 I/F Register/ State select

1-24

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Signal In/Out Description

RGB_LEND/SYS_OE O RGB I/F Line End Signal

i80 I/F Output Enable Interrupt Control Unit EINT[15:0] I External interrupt request External I/F nXDREQ[1:0] I External DMA request nXDACK[1:0] O External DMA acknowledge nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request

control of the local bus. nXBACK active indicates that bus control has

been granted. nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C2416X has

surrendered control of the local bus to another bus master.

UART

RXD[3:0] I UART receives data input (ch. 0/1/2) TXD[3:0] O UART transmits data output (ch. 0/1/2) nCTS[2:0] I UART clear to send input signal (ch. 0/1) nRTS[2:0] O UART request to send output signal (ch. 0/1) EXTUARTCLK I External clock input for UART

TSADC

AIN[9:0] AI ADC input [9:0]. If do not use ADC function, AIN [9] and AIN [7] pins are

tied to VDDA_ADC. Others are tied to GND.

When touch screen device is used, A[6], A[7] , A[8] and A[9] are used as

YM, YP, XM and XP, respectively. Vref AI ADC reference voltage IIC-Bus IICSDA IO IIC-bus data IICSCL IO IIC-bus clock

IIS-Multi Audio Interface

I2SLRCK IO IIS-bus channel select clock I2SSCLK IO IIS-bus serial clock I2SCDCLK IO CODEC system clock I2SSDI I IIS-bus serial data input I2SSDO O IIS-bus serial data output(Front Left, Right) I2SSDO_1 O IIS-bus serial data output(Front Center, LFE) I2SSDO_2 O IIS-bus serial data output(Rear Left, Right)

AC’97

AC_nRESET IO AC’97 Master H/W Reset AC_SYNC IO 12.288MHz serial data clock AC_BIT_CLK0 O 48kHz fixed rate sample sync

1-25

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Signal In/Out Description

AC_SDI0 I Serial, time division multiplexed, AC’97 input stream AC_SDO0 O Serial, time division multiplexed, AC’97 output stream

PCM

PCM0_SCLK O Serial shift clock PCM0_FSYNC O Serial data indicator and synchronizer PCM0_SDI I Serial PCM input data PCM0_SDO O Serial PCM output data PCM0_CDCLK I Optional External Clock source

USB Host

DN IO DP IO

DATA(–) from USB host. (Need to 15kΩ pull-down)

DATA(+) from USB host. (Need to 15kΩ pull-down) USB Device DM_UDEV IO DATA(–) for USB peripheral. DP_UDEV IO DATA(+) for USB peripheral. REXT O External Resistor ( 44.2ohm +/- 1%) XO_UDEV OSC Crystal output XI_UDEV OSC Crystal input SPI SPIMISO IO SPIMISO is the master data input line, when SPI is configured as a

master.

When SPI is configured as a slave, these pins reverse its role. SPIMOSI IO SPIMOSI is the master data output line, when SPI is configured as a

master.

When SPI is configured as a slave, these pins reverse its role. SPICLK IO SPI clock nSS I SPI chip select (only for slave mode)

SDMMC Interface

SD1_DAT[3:0] IO SD1 receive/transmit data SD1_CMD IO SD1 receive response/ transmit command SD1_CLK O SD1 clock SD0_DAT[3:0] IO SD0 receive/transmit data SD0_CMD IO SD0 receive response/ transmit command SD0_CLK O SD0 clock

General Port

GPn[137:0] IO General input/output ports, which are multiplexed with other function pins

(some ports are output only).

TIMMER/PWM

TOUT[3:0] O Timer output[3:0] TCLK I External timer clock input

1-26

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Signal In/Out Description

JTAG TEST LOGIC

nTRST I nTRST (TAP Controller Reset) resets the TAP controller at start.

If debugger is used, A 10K pull-up resistor has to be connected. If debugger (black ICE) is not used, nTRST pin must be issued by a low active pulse (Typically connected to nRESET).

TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP

controller's states. TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic. TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and

data. TDO O TDO (TAP Controller Data Output) is the serial output for test instructions

and data. RTCK O Returned Clock Power VDDalive P S3C2416X reset block and port status register VDD.

It should be always supplied whether in normal mode or in Sleep mode. VDDiarm P S3C2416X core logic VDD for ARM core. VDDi P S3C2416X core logic VDD for Internal block. VDDA_MPLL P S3C2416X MPLL analog and digital VDD. VDDA_EPLL P S3C2416X EPLL analog and digital VDD VDD_SDRAM P S3C2416X SDRAM I/O Power (1.8V/ 2.5V) VDD_SRAM P S3C2416X ROM/SRAM I/O Power VDD_OP1 P S3C2416X System I/O Power 1 (1.8 ~ 3.3V) VDD_OP2 P S3C2416X System I/O Power 2 ( 1.8 ~ 3.3V) VDD_OP3 P S3C2416X System I/O Power 3 ( 1.8 ~ 3.3V) VDD_LCD P S3C2416X LCD I/O Power (1.8 ~ 3.3V) VDD_SD P S3C2416X SD/MMC I/O Power (1.8 ~ 3.3V) VDD_RTC P RTC VDD (3.0V, Input range: 1.8 ~ 3.6V)

This pin must be connected to power properly if RTC isn't used. VDDA_ADC P S3C2416X ADC VDD(3.3V) VSSi/VSSiarm G S3C2416X core logic VSS VSSA_MPLL G S3C2416X MPLL analog and digital VSS. VSSA_EPLL G S3C2416X EPLL analog and digital VSS VSS_SDRAM G S3C2416X SDRAM I/O Ground VSS_SRAM G S3C2416X ROM/SRAM I/O Ground VSS_OP1 G S3C2416X System I/O Ground VSS_OP2 G S3C2416X System I/O Ground VSS_OP3 G S3C2416X System I/O Ground VSS_LCD G S3C2416X LCD I/O Ground VSS_SD G S3C2416X SD/MMC I/O Ground

1-27

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Signal In/Out Description

VSSA_ADC G S3C2416X ADC VSS VDD_USBOSC P USB 2.0 Oscillator Power(1.8 ~ 3.3V) VDDI_UDEV P USB 2.0 PHY Power ( 1.2V) VSSI_UDEV G USB 2.0 PHY Ground VDDA33C/VDDA33T1 P USB 2.0 PHY Power ( 3.3V) VSSA33C/VSSA33T2 G USB 2.0 PHY Ground

NOTE: I/O : Input/Output. AI/AO : Analog I/O. ST : Schmitt-trigger. P : Power. G : Ground.

1-28

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

4.2 S3C2416X OPERATION MODE DESCRIPTION

Table 1-5. S3C2416X Operation Mode Description

OM[4] OM[3] OM[2] OM[1] OM[0] OM[4] OM[3] OM[2] OM[1] OM[0]

0 1 0 0

1 0

0 X-TAL 1

iROM

EXTCLK 0 Reserved Reserved 1 JTAG JTAG 0 X-TAL 1 0 X-TAL 1

OneNAND/

ROM

0 X-TAL 1

OneNAND

(Muxed)

ROM/

OneNAND

(Demuxed)

16-bit

EXTCLK

8-bit

EXTCLK

16-bit

EXTCLK

* OM[0] selects the clock source of MPLL/EPLL

( You can select different EPLL clock source with that of MPLL by software setting – refer to SYSCON)

Operation

Mode

iROM

OneNAND

(Muxed)

ROM/

OneNAND

(Demuxed)

1-29

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

4.3 S3C2416X MEMORY MAP AND BASE ADDRESS OF SPECIAL REGISTERS

4.3.1 Memory Map

0x40000_0000

0x3800_0000

0x3000_0000

0x2800_0000

0x2000_0000

0x1800_0000

0x1000_0000

0x0800_0000

SRAM

(64KB)

SDRAM (nSCS1)

SDRAM (nSCS0)

SROM

(nRCS5)

SROM

(nRCS4)

SROM

(nRCS3)

SROM

(nRCS2)

SROM

(nRCS1)

MPORT1

MPORT0

SRAM

(8KB)

(64KB)

SDRAM (nSCS1)

SDRAM (nSCS0)

SROM

(nRCS5)

SROM

(nRCS4)

ROM

(nRCS3)

SROM

(nRCS2)

SROM

(nRCS1)

0x0000_0000

SROM

(nRCS0)

Using OneNAND

for boot ROM

Figure 1-3. Memory Map

Internal

iROM

Using iROM for

boot ROM

1-30

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-6. Base Address of Special Registers

Address Module Address Module

0x4E00_0000 NFCON 0x5E00_0000 Reserved 0x4D80_0000 Reserved 0x5D00_0000 Reserved

0x4D40_8000 2D 0x5C00_0100 Reserved 0x4D00_0000 Reserved 0x5C00_0000 PCM

0x4C80_0000 LCD 0x5B00_0000 AC97 0x4C00_0000 SYSCON 0x5A00_0000 Reserved

0x4B80_0000 Reserved 0x5900_0000 Reserved 0x4B00_0700 Reserved 0x5800_0000 TSADC 0x4B00_0600 Reserved 0x5700_0000 RTC 0x4B00_0500 DMA5 0x5600_0000 IO Port 0x4B00_0400 DMA4 0x5500_0100 Reserved 0x4B00_0300 DMA3 0x5500_0000 IIS0 0x4B00_0200 DMA2 0x5400_0100 Reserved 0x4B00_0100 DMA1 0x5400_0000 IIC0 0x4B00_0000 DMA0 0x5300_0000 WDT

0x4AC0_0000 HS-MMC0 0x5200_0000 HS-SPI0

0x4A80_0000 HS-MMC1 0x5100_0000 PWM 0x4A00_0000 INTC 0x5000_0000 UART 0x4980_0000 USB Device 0x4F80_0000 Reserved

0x4900_0000 USB HOST 0x4F00_0000 SSMC 0x4880_0000 EBI 0x4E80_0000 MATRIX 0x4800_0000 SDRAM

1-31

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

Table 1-7. S3C2416X Special Registers

cc.

DRAM Controller

BANKCFG 0x48000000 0x00099F0D W R/W Mobile DRAM configuration register BANKCON1 0x48000004 0x00000008 W R/W Mobile DRAM control register BANKCON2 0x48000008 0x00000008 W R/W Mobile DRAM timing control register BANKCON3 0x4800000C 0x00000008 W R/W Mobile DRAM (E)MRS Register REFRESH 0x48000010 0x00000020 W R/W Mobile DRAM refresh control register TIMEOUT 0x48000014 0x00000000 W R/W Write Buffer Time out control register

MATRIX & EBI

BPRIORITY0 0X4E800000 0x0000_0004 W R/W Matrix Core 0 priority control register BPRIORITY1 0X4E800004 0x0000_0004 W R/W Matrix Core 1 priority control register EBICON 0X4E800008 0x0000_0004 W R/W EBI control register

Memory Controllers ( SSMC )

SMBIDCYR0 0x4F000000 0x0000000F W R/W Bank0 idle cycle control register SMBIDCYR1 0x4F000020 0x0000000F W R/W Bank1 idle cycle control register SMBIDCYR2 0x4F000040 0x0000000F W R/W Bank2 idle cycle control register SMBIDCYR3 0x4F000060 0x0000000F W R/W Bank3 idle cycle control register SMBIDCYR4 0x4F000080 0x0000000F W R/W Bank4 idle cycle control register SMBIDCYR5 0x4F0000A0 0x0000000F W R/W Bank5 idle cycle control register SMBWSTRDR0 0x4F000004 0x0000001 W R/W Bank0 read wait state control register SMBWSTRDR1 0x4F000024 0x0000001F W R/W Bank1 read wait state control register SMBWSTRDR2 0x4F000044 0x0000001F W R/W Bank2 read wait state control register SMBWSTRDR3 0x4F000064 0x0000001F W R/W Bank3 read wait state control register SMBWSTRDR4 0x4F000084 0x0000001F W R/W Bank4 read wait state control register SMBWSTRDR5 0x4F0000A4 0x0000001F W R/W Bank5 read wait state control register SMBWSTWRR0 0x4F000008 0x0000001F W R/W Bank0 write wait state control register SMBWSTWRR1 0x4F000028 0x0000001F W R/W Bank1 write wait state control register SMBWSTWRR2 0x4F000048 0x0000001F W R/W Bank2 write wait state control register SMBWSTWRR3 0x4F000068 0x0000001F W R/W Bank3 write wait state control register SMBWSTWRR4 0x4F000088 0x0000001F W R/W Bank4 write wait state control register SMBWSTWRR5 0x4F0000A8 0x0000001F W R/W Bank5 write wait state control register SMBWSTOENR0 0x4F00000C 0x00000002 W R/W Bank0 output enable assertion delay

SMBWSTOENR1 0x4F00002C 0x00000002 W R/W Bank1 output enable assertion delay

SMBWSTOENR2 0x4F00004C 0x00000002 W R/W Bank2 output enable assertion delay

Unit

Read/

Write

Function

control register

1-32

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

SMBWSTOENR3 0x4F00006C 0x00000002 W R/W Bank3 output enable assertion delay

SMBWSTOENR4 0x4F00008C 0x00000002 W R/W Bank4 output enable assertion delay

SMBWSTOENR5 0x4F0000AC 0x00000002 W R/W Bank5 output enable assertion delay

SMBWSTWENR0 0x4F000010 0x00000002 W R/W Bank0 write enable assertion delay control

SMBWSTWENR1 0x4F000030 0x00000002 W R/W Bank1 write enable assertion delay control

SMBWSTWENR2 0x4F000050 0x00000002 W R/W Bank2 write enable assertion delay control

SMBWSTWENR3 0x4F000070 0x00000002 W R/W Bank3 write enable assertion delay control

SMBWSTWENR4 0x4F000090 0x00000002 W R/W Bank4 write enable assertion delay control

SMBWSTWENR5 0x4F0000B0 0x00000002 W R/W Bank5 write enable assertion delay control

SMBCR0 0x4F000014 - W R/W Bank0 control register SMBCR1 0x4F000034 0x00303000 W R/W Bank1 control register SMBCR2 0x4F000054 0x00303010 W R/W Bank2 control register SMBCR3 0x4F000074 0x00303000 W R/W Bank3 control register SMBCR4 0x4F000094 0x00303010 W R/W Bank4 control register SMBCR5 0x4F0000B4 0x00303010 W R/W Bank5 control register SMBSR0 0x4F000018 0x00000000 W R/W Bank0 status register SMBSR1 0x4F000038 0x00000000 W R/W Bank1 status register SMBSR2 0x4F000058 0x00000000 W R/W Bank2 status register SMBSR3 0x4F000078 0x00000000 W R/W Bank3 status register SMBSR4 0x4F000098 0x00000000 W R/W Bank4 status register SMBSR5 0x4F0000B8 0x00000000 W R/W Bank5 status register SMBWSTBRDR0 0x4F00001C 0x0000001F W R/W Bank0 burst read wait delay control register SMBWSTBRDR1 0x4F00003C 0x0000001F W R/W Bank1 burst read wait delay control register SMBWSTBRDR2 0x4F00005C 0x0000001F W R/W Bank2 burst read wait delay control register SMBWSTBRDR3 0x4F00007C 0x0000001F W R/W Bank3 burst read wait delay control register SMBWSTBRDR4 0x4F00009C 0x0000001F W R/W Bank4 burst read wait delay control register SMBWSTBRDR5 0x4F0000BC 0x0000001F W R/W Bank5 burst read wait delay control register SMBONETYPER 0x4F000100 - W R/W SMC Bank OneNAND type selection

SMCSR 0x4F000200 0x00000000 W R/W SMC status register SMCCR 0x4F000204 0x00000003 W R/W SMC Control register

Unit

Read/

Write

Function

control register

1-33

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

Interrupt Controller SRCPND1 0X4A000000 0x00000000 W R/W Interrupt request status INTMOD1 0X4A000004 0x00000000 W R/W Interrupt mode control INTMSK1 0X4A000008 0xFFFFFFFF W R/W Interrupt mask control INTPND1 0X4A000010 0x00000000 W R/W Interrupt request status INTOFFSET1 0X4A000014 0x00000000 W R Interrupt request source offset SUBSRCPND 0X4A000018 0xFFFFFFFF W R/W Sub source pending INTSUBMSK 0X4A00001C 0x00000000 W R/W Interrupt sub mask PRIORITY_MODE1 0X4A000030 0x00000000 W R/W Priority mode register PRIORITY_UPDATE1 0X4A000034 0xFFFFFFFF W R/W Priority update register SRCPND2 0X4A000040 0x00000000 W R/W Interrupt request status 2 INTMOD2 0X4A000044 0x00000000 W R/W Interrupt mode control 2 INTMSK2 0X4A000048 0xFFFFFFFF W R/W Interrupt mask control 2 INTPND2 0X4A000050 0x00000000 W R/W Interrupt request status 2 INTOFFSET2 0X4A000054 0x00000000 W R Interrupt request source offset 2 PRIORITY_MODE2 0X4A000070 0x00000000 W R/W Priority mode register 2 PRIORITY_UPDATE2 0X4A000074 0x0000007F W R/W Priority update register 2

USB Host Controller

HcRevision 0x49000000 W R/W Control and status group HcControl 0x49000004 R/W HcCommonStatus 0x49000008 R/W HcInterruptStatus 0x4900000C R/W HcInterruptEnable 0x49000010 R/W HcInterruptDisable 0x49000014 R/W HcHCCA 0x49000018 R/W Memory pointer group HcPeriodCuttentED 0x4900001C R/W HcControlHeadED 0x49000020 R/W HcControlCurrentED 0x49000024 R/W HcBulkHeadED 0x49000028 R/W HcBulkCurrentED 0x4900002C R/W HcDoneHead 0x49000030 R/W Frame counter group HcRmInterval 0x49000034 R/W HcFmRemaining 0x49000038 R/W HcFmNumber 0x4900003C R/W HcPeriodicStart 0x49000040 R/W HcLSThreshold 0x49000044 R/W HcRhDescriptorA 0x49000048 R/W Root hub group

Unit

Read/

Write

Function

1-34

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

HcRhDescriptorB 0x4900004C R/W HcRhStatus 0x49000050 R/W HcRhPortStatus1 0x49000054 R/W HcRhPortStatus2 0x49000058 R/W DMA DISRC0 0x4B000000 W R/W DMA 0 initial source DISRCC0 0x4B000004 R/W DMA 0 initial source control DIDST0 0x4B000008 R/W DMA 0 initial destination DIDSTC0 0x4B00000C R/W DMA 0 initial destination control DCON0 0x4B000010 R/W DMA 0 control DSTAT0 0x4B000014 R DMA 0 count DCSRC0 0x4B000018 R DMA 0 current source DCDST0 0x4B00001C R DMA 0 current destination DMASKTRIG0 0x4B000020 R/W DMA 0 mask trigger DMAREQSEL0 0x4B000024 R/W DMA0 Request Selection Register DISRC1 0x4B000100 W R/W DMA 1 initial source DISRCC1 0x4B000104 R/W DMA 1 initial source control DIDST1 0x4B000108 R/W DMA 1 initial destination DIDSTC1 0x4B00010C R/W DMA 1 initial destination control DCON1 0x4B000110 R/W DMA 1 control DSTAT1 0x4B000114 R DMA 1 count DCSRC1 0x4B000118 R DMA 1 current source DCDST1 0x4B00011C R DMA 1 current destination DMASKTRIG1 0x4B000120 R/W DMA 1 mask trigger DMAREQSEL1 0x4B000124 R/W DMA1 Request Selection Register DISRC2 0x4B000200 W R/W DMA 2 initial source DISRCC2 0x4B000204 R/W DMA 2 initial source control DIDST2 0x4B000208 R/W DMA 2 initial destination DIDSTC2 0x4B00020C R/W DMA 2 initial destination control DCON2 0x4B000210 R/W DMA 2 control DSTAT2 0x4B000214 R DMA 2 count DCSRC2 0x4B000218 R DMA 2 current source DCDST2 0x4B00021C R DMA 2 current destination DMASKTRIG2 0x4B000220 R/W DMA 2 mask trigger DMAREQSEL2 0x4B000224 R/W DMA2 Request Selection Register DISRC3 0x4B000300 W R/W DMA 3 initial source DISRCC3 0x4B000304 R/W DMA 3 initial source control

Unit

Read/

Write

Function

1-35

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

DIDST3 0x4B000308 R/W DMA 3 initial destination DIDSTC3 0x4B00030C R/W DMA 3 initial destination control DCON3 0x4B000310 R/W DMA 3 control DSTAT3 0x4B000314 R DMA 3 count DCSRC3 0x4B000318 R DMA 3 current source DCDST3 0x4B00031C R DMA 3 current destination DMASKTRIG3 0x4B000320 R/W DMA 3 mask trigger DMAREQSEL3 0x4B000324 R/W DMA3 Request Selection Register DISRC4 0x4B000400 W R/W DMA 4 initial source DISRCC4 0x4B000404 R/W DMA 4 initial source control DIDST4 0x4B000408 R/W DMA 4 initial destination DIDSTC4 0x4B00040C R/W DMA 4 initial destination control DCON4 0x4B000410 R/W DMA 4 control DSTAT4 0x4B000414 R DMA 4 count DCSRC4 0x4B000418 R DMA 4 current source DCDST4 0x4B00041C R DMA 4 current destination DMASKTRIG4 0x4B000420 R/W DMA 4 mask trigger DMAREQSEL4 0x4B000424 R/W DMA4 Request Selection Register DISRC5 0x4B000500 W R/W DMA 5 initial source DISRCC5 0x4B000504 R/W DMA 5 initial source control DIDST5 0x4B000508 R/W DMA 5 initial destination DIDSTC5 0x4B00050C R/W DMA 5 initial destination control DCON5 0x4B000510 R/W DMA 5 control DSTAT5 0x4B000514 R DMA 5 count DCSRC5 0x4B000518 R DMA 5 current source DCDST5 0x4B00051C R DMA 5 current destination DMASKTRIG5 0x4B000520 R/W DMA 5 mask trigger DMAREQSEL5 0x4B000524 R/W DMA5 Request Selection Register System Controller LOCKCON0 0x4C00_0000 0x0000_FFFF W R/W MPLL lock time count register LOCKCON1 0x4C00_0004 0x0000_FFFF EPLL lock time count register OSCSET 0x4C00_0008 0x0000_8000 Oscillator stabilization control register MPLLCON 0x4C00_0010 0x0185_40C0 MPLL configuration register EPLLCON 0x4C00_0018 0x0120_0102 EPLL configuration register EPLLCON_K 0x4C00_001C 0x0000_0000 EPLL configuration register

CLKSRC 0x4C00_0020 0x0000_0000 Clock source control register

Unit

Read/

Write

Function

for K Value

1-36

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

CLKDIV0 0x4C00_0024 0x0000_000C Clock divider ratio control register0 CLKDIV1 0x4C00_0028 0x0000_0000 Clock divider ratio control register1 CLKDIV2 0x4C00_002C 0x0000_0000 Clock divider ratio control register2 HCLKCON 0x4C00_0030 0xFFFF_FFFF HCLK enable register PCLKCON 0x4C00_0034 0xFFFF_FFFF PCLK enable register SCLKCON 0x4C00_0038 0xFFFF_DFFF Special clock enable register PWRMODE 0x4C00_0040 0x0000_0000 Power mode control register SWRST 0x4C00_0044 0x0000_0000 Software reset control register BUSPRI0 0x4C00_0050 0x0000_0000 Bus priority control register 0 PWRCFG 0x4C00_0060 0x0000_0000 Power management configuration register RSTCON 0x4C00_0064 0x0006_0101 R Reset control register RSTSTAT 0x4C00_0068 0x0000_0001 R/W Reset status register WKUPSTAT 0x4C00_006C 0x0000_0000 Wake-up status register INFORM0 0x4C00_0070 0x0000_0000 R SLEEP mode information register 0 INFORM1 0x4C00_0074 0x0000_0000 R/W SLEEP mode information register 1 INFORM2 0x4C00_0078 0x0000_0000 SLEEP mode information register 2 INFORM3 0x4C00_007C 0x0000_0000 SLEEP mode information register 3 PHYCTRL 0x4C00_0080 0x0000_0000 USB PHY control register PHYPWR 0x4C00_0084 0x0000_0000 USB PHY power control register URSTCON 0x4C00_0088 0x0000_0000 USB PHY Reset control register UCLKCON 0x4C00_008C 0x0000_0000 USB PHY clock control register

LCD Controller

VIDCON0 0x4C80_0000 0x0000_0000 W R/W Video control 0 register VIDCON1 0x4C80_0004 0x0000_0000 W R/W Video control 1 register VIDTCON0 0x4C80_0008 0x0000_0000 W R/W Video time control 0 register VIDTCON1 0x4C80_000C 0x0000_0000 W R/W Video time control 1 register VIDTCON2 0x4C80_0010 0x0000_0000 W R/W Video time control 2 register WINCON0 0x4C80_0014 0x0000_0000 W R/W Window control 0 register WINCON1 0x4C80_0018 0x0000_0000 W R/W Window control 1 register VIDOSD0A 0x4C80_0028 0x0000_0000 W R/W Video Window 0’s position control register VIDOSD0B 0x4C80_002C 0x0000_0000 W R/W Video Window 0’s position control register VIDOSD1A 0x4C80_0034 0x0000_0000 W R/W Video Window 1’s position control register VIDOSD1B 0x4C80_0038 0x0000_0000 W R/W Video Window 1’s position control register VIDOSD1C 0x4C80_003C 0x0000_0000 W R/W Video Window 1’s alpha value register VIDW00ADD0B0 0x4C80_0064 0x0000_0000 W R/W Window 0’s buffer start address register,

Unit

Read/

Write

Function

buffer 0

1-37

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

VIDW00ADD0B1 0x4C80_0068 0x0000_0000 W R/W Window 0’s buffer start address register,

VIDW01ADD0 0x4C80_006C 0x0000_0000 W R/W Window 1’s buffer start address register VIDW00ADD1B0 0x4C80_007C 0x0000_0000 W R/W Window 0’s buffer end address register,

VIDW00ADD1B1 0x4C80_0080 0x0000_0000 W R/W Window 0’s buffer end address register,

VIDW01ADD1 0x4C80_0084 0x0000_0000 W R/W Window 1’s buffer end address register VIDW00ADD2B0 0x4C80_0094 0x0000_0000 W R/W Window 0’s buffer size register, buffer 0 VIDW00ADD2B1 0x4C80_0098 0x0000_0000 W R/W Window 0’s buffer size register, buffer 1 VIDW01ADD2 0x4C80_009C 0x0000_0000 W R/W Window 1’s buffer size register VIDINTCON 0x4C80_00AC 0x03F0_0000 W R/W Indicate the Video interrupt control register W1KEYCON0 0x4C80_00B0 0x0000_0000 W R/W Color key control register W1KEYCON1 0x4C80_00B4 0x0000_0000 W R/W Color key value (transparent value) register W2KEYCON0 0x4C80_00B8 0x0000_0000 W R/W Color key control register W2KEYCON1 0x4C80_00BC 0x0000_0000 W R/W Color key value (transparent value) register W3KEYCON0 0x4C80_00C0 0x0000_0000 W R/W Color key control register W3KEYCON1 0x4C80_00C4 0x0000_0000 W R/W Color key value (transparent value) register W4KEYCON0 0x4C80_00C8 0x0000_0000 W R/W Color key control register W4KEYCON1 0x4C80_00CC 0x0000_0000 W R/W Color key value (transparent value) register WIN0MAP 0x4C80_00D0 0x0000_0000 W R/W Window color control WIN1MAP 0x4C80_00D4 0x0000_0000 W R/W Window color control WPALCON 0x4C80_00E4 0x0000_0000 W R/W Window Palette control register SYSIFCON0 0x4C80_0130 0x0000_0000 W R/W System Interface control for Main LDI SYSIFCON1 0x4C80_0134 0x0000_0000 W R/W System Interface control for Sub LDI DITHMODE 0x4C80_0138 0x0000_0000 W R/W Dithering mode register. SIFCCON0 0x4C80_013C 0x0000_0000 W R/W System interface command control SIFCCON1 0x4C80_0140 0x0000_0000 W R/W SYS IF command data write control SIFCCON2 0x4C80_0144 0x0000_0000 W R SYS IF command data read control CPUTRIGCON2 0x4C80_0160 0x0000_0000 W R/W CPU trigger source mask WIN0 Palette RAM 0x4C80_0400~

0x4C80_07FC

WIN1 Palette RAM 0x4C80_0800~

0x4C80_0BFC NAND Flash NFCONF 0x4E000000 0x*000100* W R/W Configuration register NFCONT 0x4E000004 0x000100C6 W R/W Control register NFCMMD 0x4E000008 0x00000000 W R/W Command register

Undefined W R/W Window 0’s palette entry 0~255 address

Unit

Read/

Write

Function

buffer 1

buffer 0

buffer 1

1-38

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

NFADDR 0x4E00000C 0x00000000 W R/W Address register NFDATA 0x4E000010 - B/W R/W Data register NFMECCD0 0x4E000014 0x00000000 W R/W 1st and 2nd main ECC data register NFMECCD1 0x4E000018 0x00000000 W R/W 3rd and 4th main ECC data register NFSECCD 0x4E00001C 0x00000000 W R/W Spare ECC read register NFSBLK 0x4E000020 0x00000000 W R/W Programmable start block address register NFEBLK 0x4E000024 0x00000000 W R/W Programmable end block address register NFSTAT 0x4E000028 0x0080001D W R NAND status registet NFECCERR0 0x4E00002C - W R ECC error status0 register NFECCERR1 0x4E000030 0x00000000 W R ECC error status1 register NFMECC0 0x4E000034 - W R Generated ECC status0 register NFMECC1 0x4E000038 - W R Generated ECC status1 register NFSECC 0x4E00003C - W R Generated Spare area ECC status register NFMLCBITPT 0x4E000040 0x00000000 W R 4-bit ECC error bit pattern register NF8ECCERR0 0x4E000044 0x40000000 W R 8bit ECC error status0 register NF8ECCERR1 0x4E000048 0x00000000 W R 8bit ECC error status1 register NF8ECCERR2 0x4E00004C 0x00000000 W R 8bit ECC error status2 register NFM8ECC0 0x4E000050 - W R Generated 8-bit ECC status0 register NFM8ECC1 0x4E000054 - W R Generated 8-bit ECC status1 register NFM8ECC2 0x4E000058 - W R Generated 8-bit ECC status2 register NFM8ECC3 0x4E00005C - W R Generated 8-bit ECC status3 register NFMLC8BITPT0 0x4E000060 0x00000000 W R 8-bit ECC error bit pattern 0 register NFMLC8BITPT1 0x4E000064 0x00000000 W R 8-bit ECC error bit pattern 1 register

UART

ULCON0 0x50000000 W R/W UART 0 line control UCON0 0x50000004 UART 0 control UFCON0 0x50000008 UART 0 FIFO control UMCON0 0x5000000C UART 0 modem control UTRSTAT0 0x50000010 R UART 0 Tx/Rx status UERSTAT0 0x50000014 UART 0 Rx error status UFSTAT0 0x50000018 UART 0 FIFO status UMSTAT0 0x5000001C UART 0 modem status UTXH0 0x50000020 B W UART 0 transmission hold URXH0 0x50000024 R UART 0 receive buffer UBRDIV0 0x50000028 W R/W UART 0 baud rate divisor UDIVSLOT0 0x5000002C Baud rate divisior(decimal place)

Unit

Read/

Write

Function

1-39

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

ULCON1 0x50004000 UART 1 line control UCON1 0x50004004 UART 1 control UFCON1 0x50004008 UART 1 FIFO control UMCON1 0x5000400C UART 1 modem control UTRSTAT1 0x50004010 R UART 1 Tx/Rx status UERSTAT1 0x50004014 UART 1 Rx error status UFSTAT1 0x50004018 UART 1 FIFO status UMSTAT1 0x5000401C UART 1 modem status UTXH1 0x50004020 B W UART 1 transmission hold URXH1 0x50004024 R UART 1 receive buffer UBRDIV1 0x50004028 W R/W UART 1 baud rate divisor UDIVSLOT1 0x500402C Baud rate divisior(decimal place)

ULCON2 0x50008000 UART 2 line control UCON2 0x50008004 UART 2 control UFCON2 0x50008008 UART 2 FIFO control UTRSTAT2 0x50008010 R UART 2 Tx/Rx status UERSTAT2 0x50008014 UART 2 Rx error status UFSTAT2 0x50008018 UART 2 FIFO status UTXH2 0x50008020 B W UART 2 transmission hold URXH2 0x50008024 R UART 2 receive buffer UBRDIV2 0x50008028 W R/W UART 2 baud rate divisor UDIVSLOT2 0x500802C Baud rate divisior(decimal place)

ULCON3 0x5000C000 UART 3 line control UCON3 0x5000C004 UART 3 control UFCON3 0x5000C008 UART 3 FIFO control UTRSTAT3 0x5000C010 R UART 3 Tx/Rx status UERSTAT3 0x5000C014 UART 3 Rx error status UFSTAT3 0x5000C018 UART 3 FIFO status UTXH3 0x5000C020 B W UART 3 transmission hold URXH3 0x5000C024 R UART 3 receive buffer UBRDIV3 0x5000C028 W R/W UART 3 baud rate divisor UDIVSLOT3 0x500C02C Baud rate divisior(decimal place) register 3 PWM Timer TCFG0 0x51000000 0x0 W R/W Timer configuration TCFG1 0x51000004 0x0 W R/W Timer configuration

Unit

Read/

Write

Function

1-40

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

TCON 0x51000008 0x0 W R/W Timer control TCNTB0 0x5100000C 0x0 W R/W Timer count buffer 0 TCMPB0 0x51000010 0x0 W R/W Timer compare buffer 0 TCNTO0 0x51000014 0x0 W R Timer count observation 0 TCNTB1 0x51000018 0x0 W R/W Timer count buffer 1 TCMPB1 0x5100001C 0x0 W R/W Timer compare buffer 1 TCNTO1 0x51000020 0x0 W R Timer count observation 1 TCNTB2 0x51000024 0x0 W R/W Timer count buffer 2 TCMPB2 0x51000028 0x0 W R/W Timer compare buffer 2 TCNTO2 0x5100002C 0x0 W R Timer count observation 2 TCNTB3 0x51000030 0x0 W R/W Timer count buffer 3 TCMPB3 0x51000034 0x0 W R/W Timer compare buffer 3 TCNTO3 0x51000038 0x0 W R Timer count observation 3 TCNTB4 0x5100003C 0x0 W R/W Timer count buffer 4 TCNTO4 0x51000040 0x0 W R Timer count observation 4 USB Device IR 0x4980_0000 0x0 R/W Index Register EIR 0x4980_0004 0x0 R/W Endpoint Interrupt Register EIER 0x4980_0008 0x0 R/W Endpoint Interrupt Enable Register FAR 0x4980_000C 0x0 R Function Address Register EDR 0x4980_0014 0x0 R/W Endpoint Direction Register TR 0x4980_0018 0x0 R/W Test Register SSR 0x4980_001C 0x0 R/W System Status Register SCR 0x4980_0020 0x0 R/W System Control Register EP0SR 0x4980_0024 0x0 R/W EP0 Status Register EP0CR 0x4980_0028 0x0 R/W EP0 Control Register EP0BR 0x4980_0060 0x0 R/W EP0 Buffer Register EP1BR 0x4980_0064 0x0 R/W EP1 Buffer Register EP2BR 0x4980_0068 0x0 R/W EP2 Buffer Register EP3BR 0x4980_006C 0x0 R/W EP3 Buffer Register EP4BR 0x4980_0070 0x0 R/W EP4 Buffer Register EP5BR 0x4980_0074 0x0 R/W EP5 Buffer Register EP6BR 0x4980_0078 0x0 R/W EP6 Buffer Register EP7BR 0x4980_007C 0x0 R/W EP7 Buffer Register EP8BR 0x4980_0080 0x0 R/W EP8 Buffer Register FCON 0x4980_0100 0x0 R/W Burst FIFO-DMA Control FSTAT 0x4980_0104 0x0 R Burst FIFO status

Unit

Read/

Write

Function

1-41

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

ESR 0x4980_002C 0x0 R/W Endpoints Status Register ECR 0x4980_0030 0x0 R/W Endpoints Control Register BRCR 0x4980_0034 0x0 R Byte Read Count Register BWCR 0x4980_0038 0x0 R/W Byte Write Count Register MPR 0x4980_003C 0x0 R/W Max Packet Register DCR 0x4980_0040 0x0 R/W DMA Control Register DTCR 0x4980_0044 0x0 R/W DMA Transfer Counter Register DFCR 0x4980_0048 0x0 R/W DMA FIFO Counter Register DTTCR1 0x4980_004C 0x0 R/W DMA Total Transfer Counter1 Register DTTCR2 0x4980_0050 0x0 R/W DMA Total Transfer Counter2 Register MICR 0x4980_0084 0x0 R/W Master Interface Control Register MBAR 0x4980_0088 0x0 R/W Memory Base Address Register MCAR 0x4980_008C 0x0 R Memory Current Address Register Watchdog Timer WTCON 0x53000000 0x0000_8021 W R/W Watchdog timer mode WTDAT 0x53000004 0x0000_8000 Watchdog timer data WTCNT 0x53000008 0x0000_8000 Watchdog timer count IIC IICCON0 0x54000000 W R/W IIC0 control IICSTAT0 0x54000004 IIC0 status IICADD0 0x54000008 IIC0 address IICDS0 0x5400000C IIC0 data shift IICLC0 0x54000010 IIC0 multi-master line control

IIS Multi Audio Interface

IISCON 0x55000000 0xC600 W R/W IIS control IISMOD 0x55000004 0x0 IIS mode I2SFIC 0x55000008 0x0 I2S interface FIFO control register I2SPSR 0x5500000C 0x0 I2S interface clock divider control register I2STXD 0x55000010 0x0 W I2S interface transmit data register I2SRXD 0x55000014 0x0 R I2S interface receive data register I/O port GPACON 0x56000000 0xFFFFFF W R/W Port A control GPADAT 0x56000004 0x0 W R/W Port A data GPBCON 0x56000010 0x0 W R/W Port B control GPBDAT 0x56000014 0x0 W R/W Port B data GPBUDP 0x56000018 0x00155555 W R/W Pull-up/down control B GPBSEL 0x5600001c 0x1 W R/W Selects the function of port B

Unit

Read/

Write

Function

1-42

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

GPCCON 0x56000020 0x0 W R/W Port C control GPCDAT 0x56000024 0x0 W R/W Port C data GPCUDP 0x56000028 0x55555555 W R/W Pull-up/down control C GPDCON 0x56000030 0x0 W R/W Port D control GPDDAT 0x56000034 0x0 W R/W Port D data GPDUDP 0x56000038 0x55555555 W R/W Pull-up/down control D GPECON 0x56000040 0x0 W R/W Port E control GPEDAT 0x56000044 0x0 W R/W Port E data GPEUDP 0x56000048 0x55555555 W R/W Pull-up/down control E GPESEL 0x5600004c 0x0 W R/W Selects the function of port E GPFCON 0x56000050 0x0 W R/W Port F control GPFDAT 0x56000054 0x0 W R/W Port F data GPFUDP 0x56000058 0x5555 W R/W Pull-up/down control F GPGCON 0x56000060 0x0 W R/W Port G control GPGDAT 0x56000064 0x0 W R/W Port G data GPGUDP 0x56000068 0x55555555 W R/W Pull-up/down control G GPHCON 0x56000070 0x0 W R/W Port H control GPHDAT 0x56000074 0x0 W R/W Port H data GPHUDP 0x56000078 0x15555555 W R/W Pull-up/down control H GPJCON 0x560000D0 0x0 W R/W Port J control GPJDAT 0x560000D4 0x0 W R/W Port J data GPJUDP 0x560000D8 0x55555555 W R/W Pull-up/down control J GPJSEL 0x560000dc 0x0 W R/W Selects the function of port J GPKCON 0x560000E0 0xAAAAAAAA W R/W Port K control GPKDAT 0x560000E4 0x0 W R/W Port K data GPKUDP 0x560000E8 0x55555555 W R/W Pull-up/down control K GPLCON 0x560000F0 0x0 W R/W Port L control GPLDAT 0x560000F4 0x0 W R/W Port L data GPLUDP 0x560000F8 0x15555555 W R/W Pull-up/down control L GPLSEL 0x560000F C 0x0 W R/W Selects the function of port L GPMCON 0x56000100 0xA W R/W Port M control GPMDAT 0x56000104 0x0 R R Port M data GPMUDP 0x56000108 0x0 W R/W Pull-up/down control M MISCCR 0x56000080 0xD0010020 W R/W Miscellaneous control DCLKCON 0x56000084 0x0 W R/W DCLK0/1 control EXTINT0 0x56000088 0x000000 W R/W External interrupt control register 0 EXTINT1 0x5600008C 0x000000 W R/W External interrupt control register 1

Unit

Read/

Write

Function

1-43

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

EXTINT2 0x56000090 0x000000 W R/W External interrupt control register 2 EINTFLT2 0x5600009c 0x000000 W R/W External interrupt control register 2 EINTFLT3 0x560000a0 0x000000 W R/W External interrupt control register 3 EINTMASK 0x560000a4 0x00FFFFF0 W R/W External interrupt mask register EINTPEND 0x560000a8 0x00 W R/W External interrupt pending register GSTATUS0 0x560000ac - W R External pin status GSTATUS1 0x560000b0 0x32440001 W R Chip ID DSC0 0x560000c0 0x2AAAAAAA W R/W Strength control register 0 DSC1 0x560000c4 0xAAAAAAA W R/W Strength control register 1 DSC2 0x560000c8 0xAAAAAAA W R/W Strength control register 2 DSC3 0x56000010 0x2AA W R/W Strength control register 3 PDDMCON 0x56000114 0x00411540 W R/W Memory I/F control register PDSMCON 0x56000118 0x05451500 W R/W Memory I/F control register RTC RTCCON 0x57000040 0x00 HW R/W RTC control TICNT0 0x57000044 0x0 B R/W Tick time count register 0 TICNT1 0x57000048 0x0 B R/W Tick time count register 1 TICNT2 0x5700004C 0x0 W R/W Tick time count register 2 RTCALM 0x57000050 0x0 B R/W RTC alarm control ALMSEC 0x57000054 0x0 B R/W Alarm second ALMMIN 0x57000058 0x00 B R/W Alarm minute ALMHOUR 0x5700005C 0x0 B R/W Alarm hour ALMDATE 0x57000060 0x01 B R/W Alarm day ALMMON 0x57000064 0x01 B R/W Alarm month ALMYEAR 0x57000068 0x0 B R/W Alarm year BCDSEC 0x57000070 B R/W BCD second BCDMIN 0x57000074 B R/W BCD minute BCDHOUR 0x57000078 B R/W BCD hour BCDDATE 0x5700007C B R/W BCD day BCDDAY 0x57000080 B R/W BCD date BCDMON 0x57000084 B R/W BCD month BCDYEAR 0x57000088 B R/W BCD year TICKCNT 0x57000090 0x0 W R Internal tick time counter A/D Converter ADCCON 0x58000000 W R/W ADC control ADCTSC 0x58000004 ADC touch screen control ADCDLY 0x58000008 ADC start or interval delay

Unit

Read/

Write

Function

1-44

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

ADCDAT0 0x5800000C R ADC conversion data ADCDAT1 0x58000010 ADC conversion data ADCUPDN 0x58000014 R/W Stylus up or down interrupt status ADCMUX 0x58000018 R/W Analog input channel select HSSPI(SPI Channel 0) CH_CFG 0x52000000 0x40 R/W SPI configuration register Clk_CFG 0x52000004 0x0 R/W Clock configuration register MODE_CFG 0x52000008 0x0 R/W SPI FIFO control register Slave_slection_reg 0x5200000C 0x1 R/W Slave selection signal SPI_INT_EN 0x52000010 0x0 R/W SPI Interrupt Enable register SPI_STATUS 0x52000014 0x0 R SPI status register SPI_TX_DATA 0x52000018 0x0 W SPI TX DATA register SPI_RX_DATA 0x5200001C 0x0 R SPI RX DATA register Packet_Count_reg 0x52000020 0x0 R/W Count how many data master gets Pending_clr_reg 0x52000024 0x0 R/W Pending clear register SWAP_CFG 0x52000028 0x0 R/W SWAP config register FB_Clk_sel 0x5200002C 0x3 R/W Feedback clock selecting register.

HSMMC Channel 0

SYSAD 0x4AC00000 0x00000000 W R/W SDI control register BLKSIZE 0x4AC00004 0x00000000 HW R/W Host DMA Buffer Boundary and Transfer

BLKCNT 0x4AC00006 0x00000000 HW R/W Blocks Count For Current Transfer ARGUMENT 0x4AC00008 0x00000000 HW R/W Command Argument Register TRNMOD 0x4AC0000C 0x00000000 HW R/W Transfer Mode Setting Register CMDREG 0x4AC0000E 0x00000000 HW R/W Command Register RSPREG0 0x4AC00010 0x00000000 W ROC Response Register 0 RSPREG1 0x4AC00014 0x00000000 W ROC Response Register 1 RSPREG2 0x4AC00018 0x00000000 W ROC Response Register 2 RSPREG3 0x4AC0001C 0x00000000 W ROC Response Register 3 BDATA 0x4AC00020 Not fixed W ROC Buffer Data Register PRNSTS 0x4AC00024 0x00000000 W ROC Present State Register HOSTCTL 0x4AC00028 0x00000000 B R/W Present State Register PWRCON 0x4AC00029 0x00000000 B R/W Present State Register BLKGAP 0x4AC0002A 0x00000000 B R/W Block Gap Control Register WAKCON 0x4AC0002B 0x00000000 B R/W Wakeup Control Register CLKCON 0x4AC0002C 0x00000000 HW R/W Command Register TIMEOUTCON 0x4AC0002E 0x00000000 B R/W Timeout Control Register

Unit

Read/

Write

Function

Block Size Register

1-45

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

SWRST 0x4AC0002F 0x00000000 B R/W Software Reset Register NORINTSTS 0x4AC00030 0x00000000 HW ROC/

ERRINTSTS 0x4AC00032 0x00000000 HW ROC/

NORINTSTSEN 0x4AC00034 0x00000000 HW R/W Normal Interrupt Status Enable Register ERRINTSTSEN 0x4AC00036 0x00000000 HW R/W Error Interrupt Status Enable Register NORINTSIGEN 0x4AC00038 0x00000000 HW R/W Normal Interrupt Signal Enable Register ERRINTSIGEN 0x4AC0003A 0x00000000 HW R/W Error Interrupt Signal Enable Register ACMD12ERRSTS 0x4AC0003C 0x00000000 HW ROC Auto CMD12 Error Status Register CAPAREG 0x4AC00040 0x05E80080 W HWInit Capabilities Register MAXCURR 0x4AC00048 0x00000000 W HWInit Maximum Current Capabilities Register FEAER 0x4AC00050 0x00000000 HW WO Force Event Auto CMD12 Error Interrupt

FEERR 0x4AC00052 0x00000000 HW WO Force Event Error Interrupt Register Error

ADMAERR 0x4AC00054 0x00000000 W R/W ADMA Error Status Register ADMASYSADDR 0x4AC00058 0x00000000 W R/W ADMA System Address Register CONTROL2 0x4AC00080 0x00000000 W R/W Control register 2 CONTROL3 0x4AC00084 0x7F5F3F1F W R/W FIFO Interrupt Control

DEBUG 0x4AC00088 Not fixed W R/W Debug register CONTROL4 0x4AC0008C 0x00000000 W R/W HCVER 0x4AC000FE 0x00000401 HW HWInit Host Controller Version Register

HSMMC Channel 1

SYSAD 0x4A800000 0x00000000 W R/W SDI control register BLKSIZE 0x4A800004 0x00000000 HW R/W Host DMA Buffer Boundary and Transfer

BLKCNT 0x4A800006 0x00000000 HW R/W Blocks Count For Current Transfer ARGUMENT 0x4A800008 0x00000000 HW R/W Command Argument Register TRNMOD 0x4A80000C 0x00000000 HW R/W Transfer Mode Setting Register CMDREG 0x4A80000E 0x00000000 HW R/W Command Register RSPREG0 0x4A800010 0x00000000 W ROC Response Register 0 RSPREG1 0x4A800014 0x00000000 W ROC Response Register 1 RSPREG2 0x4A800018 0x00000000 W ROC Response Register 2 RSPREG3 0x4A80001C 0x00000000 W ROC Response Register 3 BDATA 0x4A800020 Not fixed W ROC Buffer Data Register PRNSTS 0x4A800024 0x00000000 W ROC Present State Register HOSTCTL 0x4A800028 0x00000000 B R/W Present State Register

Unit

Read/

Write

RW1C

Function

Normal Interrupt Status Register

Error Interrupt Status Register

Interrupt

(Control Register 3)

Block Size Register

1-46

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

PWRCON 0x4A800029 0x00000000 B R/W Present State Register BLKGAP 0x4A80002A 0x00000000 B R/W Block Gap Control Register WAKCON 0x4A80002B 0x00000000 B R/W Wakeup Control Register CLKCON 0x4A80002C 0x00000000 HW R/W Command Register TIMEOUTCON 0x4A80002E 0x00000000 B R/W Timeout Control Register SWRST 0x4A80002F 0x00000000 B R/W Software Reset Register NORINTSTS 0x4A800030 0x00000000 HW ROC/

ERRINTSTS 0x4A800032 0x00000000 HW ROC/

NORINTSTSEN 0x4A800034 0x00000000 HW R/W Normal Interrupt Status Enable Register ERRINTSTSEN 0x4A800036 0x00000000 HW R/W Error Interrupt Status Enable Register NORINTSIGEN 0x4A800038 0x00000000 HW R/W Normal Interrupt Signal Enable Register ERRINTSIGEN 0x4A80003A 0x00000000 HW R/W Error Interrupt Signal Enable Register ACMD12ERRSTS 0x4A80003C 0x00000000 HW ROC Auto CMD12 Error Status Register CAPAREG 0x4A800040 0x05E80080 W HWInit Capabilities Register MAXCURR 0x4A800048 0x00000000 W HWInit Maximum Current Capabilities Register FEAER 0x4A800050 0x00000000 HW WO Force Event Auto CMD12 Error Interrupt

FEERR 0x4A800052 0x00000000 HW WO Force Event Error Interrupt Register Error

ADMAERR 0x4A800054 0x00000000 W R/W ADMA Error Status Register ADMASYSADDR 0x4A800058 0x00000000 W R/W ADMA System Address Register CONTROL2 0x4A800080 0x00000000 W R/W Control register 2 CONTROL3 0x4A800084 0x7F5F3F1F W R/W FIFO Interrupt Control

DEBUG 0x4A800088 Not fixed W R/W Debug register CONTROL4 0x4A80008C 0x00000000 W R/W HCVER 0x4A8000FE 0x00000401 HW HWInit Host Controller Version Register

AC97 Audio-CODEC Interface

AC_GLBCTRL 0x5B000000 0x0 W R/W AC97 global control register AC_GLBSTAT 0x5B000004 0x1 R AC97 global status register AC_CODEC_CMD 0x5B000008 0x0 R/W AC97 codec command register AC_CODEC_STAT 0x5B00000C 0x0 R AC97 codec status register AC_PCMADDR 0x5B000010 0x0 R AC97 PCM out/in channel FIFO address

AC_MICADDR 0x5B000014 0x0 R AC97 mic in channel FIFO address register AC_PCMDATA 0x5B000018 0x0 R/W AC97 PCM out/in channel FIFO data

Unit

Read/

Write

RW1C

Function

Normal Interrupt Status Register

Error Interrupt Status Register

Interrupt

(Control Register 3)

1-47

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

AC_MICDATA 0x5B00001C 0x0 R AC97 MIC in channel FIFO data register

PCM Audio Interface

PCM_CTL0 0x5C000000 0x0 W R/W PCM0 Main Control PCM_CLKCTL0 0x5C000004 0x0 R/W PCM0 Clock and Shift control PCM_TXFIFO0 0x5C000008 0x0 R/W PCM0 TxFIFO write port PCM_RXFIFO0 0x5C00000C 0x0 R/W PCM0 RxFIFO read port PCM_IRQ_CTL0 0x5C000010 0x0 R/W PCM0 Interrupt Control PCM_IRQ_STAT0 0x5C000014 0x0 R PCM0 Interrupt Status PCM_FIFO_STAT0 0x5C000018 0x0 R PCM0 Tx Default Value PCM_CLRINT0 0x5C000020 0x0 W PCM0 INTERRUPT CLEAR

CONTROL_REG 0x4D408000 0x0000_0000 W W Control register. INTEN_REG 0x4D408004 0x0000_0000 R/W Interrupt Enable register. FIFO_INTC_REG 0x4D408008 0x0000_0018 R/W Interrupt Control register. INTC_PEND_REG 0x4D40800C 0x0000_0000 R/W Interrupt Control Pending register. FIFO_STAT_REG 0x4D408010 0x0000_0600 R Command FIF O Status reg CMD0_REG 0x4D408100 - W Command register for Line/Point drawing. CMD1_REG 0x4D408104 - W Command register for BitBLT. CMD2_REG 0x4D408108 - W Command register for Host to Screen Bitblt

CMD3_REG 0x4D40810C - W Command register for Host to Screen Bitblt

CMD4_REG 0x4D408110 - W Command register for Color Expansion.

CMD5_REG 0x4D408114 - W Command register for Color Expansion.

CMD6_REG 0x4D408118 - W Reserved CMD7_REG 0x4D40811C - W Command register for Color Expansion.

SRC_ RES_REG 0x4D408200 0x0000_0000 R/W Source Image Resolution SRC_HORI_RES_REG 0x4D408204 0x0000_0000 R/W Source Image Horizontal Resolution SRC_VERT_RES_REG 0x4D408208 0x0000_0000 R/W Source Image Vertical Resolution SC_RES_REG 0x4D408210 0x0000_0000 R/W Screen Resolution SC_HORI_RES _REG 0x4D408214 0x0000_0000 R/W Screen Horizontal Resolution SC_VERT_RES _REG 0x4D408218 0x0000_0000 R/W Screen Vertical Resolution CW_LT_REG 0x4D408200 0x0000_0000 R/W LeftTop coordinates of Clip Window. CW_LT_X_REG 0x4D408204 0x0000_0000 R/W Left X coordinate of Clip Window. CW_LT_Y_REG 0x4D408228 0x0000_0000 R/W Top Y coordinate of Clip Window.

Unit

Read/

Write

Function

transfer start.

transfer continue.

(Host to Screen, Font Start)

(Host to Screen, Font Continue)

(Memory to Screen)

1-48

S3C2416X RISC MICROPROCESSOR PRODUCT OVERVIEW

cc.

CW_RB_REG 0x4D408230 0x0000_0000 R/W RightBottom coordinate of Clip Window. CW_RB_X_REG 0x4D408234 0x0000_0000 R/W Right X coordinate of Clip Window. CW_RB_Y_REG 0x4D408238 0x0000_0000 R/W Bottom Y coordinate of Clip Window. COORD0_REG 0x4D408300 0x0000_0000 R/W Coordinates 0 register. COORD0_X_REG 0x4D408304 0x0000_0000 R/W X coordinate of Coordinates 0. COORD0_Y_REG 0x4D408308 0x0000_0000 R/W Y coordinate of Coordinates 0. COORD1_REG 0x4D408310 0x0000_0000 R/W Coordinates 1 register. COORD1_X_REG 0x4D408314 0x0000_0000 R/W X coordinate of Coordinates 1. COORD1_Y_REG 0x4D408318 0x0000_0000 R/W Y coordinate of Coordinates 1. COORD2_REG 0x4D408320 0x0000_0000 R/W Coordinates 2 register. COORD2_X_REG 0x4D408324 0x0000_0000 R/W X coordinate of Coordinates 2. COORD2_Y_REG 0x4D408328 0x0000_0000 R/W Y coordinate of Coordinates 2. COORD3_REG 0x4D408330 0x0000_0000 R/W Coordinates 3 register. COORD3_X_REG 0x4D408334 0x0000_0000 R/W X coordinate of Coordinates 3. COORD3_Y_REG 0x4D408338 0x0000_0000 R/W Y coordinate of Coordinates 3. ROT_OC_REG 0x4D408340 0x0000_0000 R/W Rotation Origin Coordinates. ROT_OC_X_REG 0x4D408344 0x0000_0000 R/W X coordinate of Rotation Origin

ROT_OC_Y_REG 0x4D408348 0x0000_0000 R/W Y coordinate of Rotation Origin

ROTATE_REG 0x4D40834C 0x0000_0001 R/W Rotation Mode register. X_INCR_REG 0x4D408400 0x0000_0000 R/W X Increment register. Y_INCR_REG 0x4D408404 0x0000_0000 R/W Y Increment register. ROP_REG 0x4D408410 0x0000_0000 R/W Raster Operation register. ALPHA_REG 0x4D408420 0x0000_0000 R/W Alpha value, Fading offset. FG_COLOR_REG 0x4D408500 0x0000_0000 R/W Foreground Color / Alpha register. BG_COLOR_REG 0x4D408504 0x0000_0000 R/W Background Color register BS_COLOR_REG 0x4D408508 0x0000_0000 R/W Blue Screen Color register SRC_COLOR_MODE_REG 0x4D408510 0x0000_0000 R/W Src Image Color Mode register. DEST_COLOR_MODE_REG 0x4D408514 0x0000_0000 R/W Dest Image Color Mode register PATTERN_REG[0:31] 0x4D408600 ~

0x4D80867C PATOFF_REG 0x4D408700 0x0000_0000 R/W Pattern Offset XY register. PATOFF_X_REG 0x4D408704 0x0000_0000 R/W Pattern Offset X register. PATOFF_Y_REG 0x4D408708 0x0000_0000 R/W Pattern Offset Y register. STENCIL_CNTL_REG 0x4D408720 0x0000_0000 R/W Stencil control register STENCIL_DR_MIN_REG 0x4D408724 0x0000_0000 W Stencil decision reference MIN register STENCIL_DR_MAX_REG 0x4D408728 0xFFFF_FFFF W Stencil decision reference MAX register

0x0000_0000 R/W Pattern memory.

Unit

Read/

Write

Function

Coordinates.

1-49

PRODUCT OVERVIEW S3C2416X RISC MICROPROCESSOR

cc.

SRC_BASE_ADDR_REG 0x4D408730 0x0000_0000 R/W Source Image Base Address register DEST_BASE_ADDR_REG 0x4D408734 0x0000_0000 R/W Dest Image Base Address register (in most

Unit

Read/

Write

Function

cases, frame buffer address)

Cautions on S3C2416X Special Registers

1. S3C2416X does not support the big endian mode.

2. The special registers have to be accessed for each recommended access unit.

3. All registers except ADC registers, RTC registers and UART registers must be read/write in word unit (32-bit).

4. Make sure that the ADC registers, RTC registers and UART registers be read/write by the specified access unit and the specified address.

5. W : 32-bit register, which must be accessed by LDR/STR or int type pointer (int *). HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer (short int *). B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer (char int *).

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S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

2 SYSTEM CONTROLLER

1 OVERVIEW

The system controller consists of three parts; reset control, system clock control, and system power-management control. The system clock control logic in S3C2461 can generate the required system clock signals which are the inputs of ARM926EJ, several AHB blocks, and APB blocks. There are two PLLs in S3C2416 to generate internal clocks. One is for general functional blocks, which include ARM, AHB, and APB. The other is for the special functional clocks which are the USB, I2S. Software program control the operating frequency of the PLLs, internal clock sources and enabled or disabled the clocks to reduce the power consumption.

S3C2416 has various power-down modes to keep optimal power consumption for a given task. The power-down modes consists of four modes; NORMAL mode, IDLE mode, STOP mode, and SLEEP mode. In NORMAL mode, the input clock of each block is enabled or disabled according to the software to eliminate the power consumption of unused blocks for a certain application. For example, if an UART is not needed, the software can disable the input clock independently. The major power dissipation of S3C2416 is due to ARM core, since the operating speed is relative higher than that of the other blocks. Typically, the operating frequency of the ARM core is 400MHz, while the AHB blocks and the APB blocks operate on 133MHz and 66MHz, respectively. Thus, the power control of the ARM core is major issue to reduce the overall power dissipation in S3C2416, and IDLE mode is supported for this purpose. In IDLE mode, the ARM core is not operated until the external interrupts or internal interrupts. The STOP mode freezes all clocks to all peripherals as well as the ARM core by disabling PLLs. The power consumption is only due to the leakage current and the minimized alive block in S3C2416. SLEEP mode is intended to disconnect the internal power. So, the power consumption due to the ARM core and the internal logic except the wake-up logic will be nearly zero in the SLEEP mode. In order to use the SLEEP mode two indenpendent power sources are required. One of the two power soruces supp lies the power for the wake-up logic. The other one supplies the normal functional blocks including the ARM core. It should be controlled in order to turn ON/OFF with a special pin in S3C2416. The detailed description of the power-saving modes such as the entering sequence to the specific power-down mode or the wake-up sequence from a power-down mode is given in the following Power Management section.

2 FEATURE

• Include two on-chip PLLs called main PLL(MPLL), extra PLL(EPLL)

• MPLL generates the system reference clock

• EPLL generates the clocks for the special functional blocks

• Independent clock ON/OFF control to reduce power consumption

• Support three power-down modes, IDLE, STOP, and SLEEP, to optimize the power dissipation

• Wake-up by one of external Interrupt, RTC alarm, Tick interrupt and BATT_FLT.(Stop and Sleep mode)

• Control internal bus arbitration priority

2-1

SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

3 BLOCK DIAGRAM

off-part alive-part

Clocks

Clock

Generator

AHB

Glue

Power Management

Signal

Masking

Glue

Power Management

Reset

Control

Reset

Power ON/OFF

Figure 2-1. System Controller Block Diagram

Figure 2-1 shows the system controller block diagram. The system controller is divided into two blocks, which are the OFF block and the ON block. Since the system controller must be alive when the external power supply is disabled. The ALIVE-part is supplied by an auxiliary power source and waits until external/internal interrupts. However, the OFF-part is disabled when the power-down mode is SLEEP. The clock generator makes all internal clocks, which include ARMCLK for the ARM core, HCLK for the AHB blocks, PCLK for the APB block, and other special clocks. The special functional registers (SFR) are located at the register blocks, and their values are configured through AHB interface. If a software want to change into a power-down mode, then the power management blocks detect the values within the SFR and change the mode. In addition, they assert the external power ON/OFF signal if required. All reset signals are generated at the reset control block.

The detailed explanations for each block will be described in the following sections.

2-2

S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

4 FUNCTIONAL DESCRIPTIONS

The system controller for S3C2416 has three functions, which in clude the reset management, the clock generation, and the power management. In this section, the behavior will be described.

4.1 RESET MANAGEMENT AND TYPES

S3C2416 has four types of resets and reset controller in system controller can place the sy stem into the predefined states with one of the following four resets.

• Hardware Reset − It is generated when nRESET pin is asserted. It is an uncompromised, unmaskable, and complete reset, which is used when you need no information in system any more.

• Watchdog Reset − The watchdog timer monitors the device state and generates the watchdog reset when the state is abnormal.

• Software Reset − Software can initialize the internal state by writing the special control register (SWRST).

• Wakeup Reset − When the system wakes up from SLEEP mode, it generates reset signals. And When the

system wakes up from Deep-STOP mode, it generates ARM reset only.

4.2 HARDWARE RESET

When S3C2416 is power-ON, the external device must assert nRESET to initialize internal states. Hardware reset is invoked when the nRESET pin is asserted and all units in the system (except RTC) are

initialized to known states. During the hardware reset, the following actions will occur:

• All internal registers and ARM926EJ core goes into their pre-defined initial state.

• All pins get their reset state, and BATT_FLT pin is ignored.

• The nRSTOUT pin is asserted while the reset is progressed.

When the unmaskable nRESET pin is asserted as low, the internal hardware reset signal is generated. Upon assertion of nRESET, S3C2416 enters reset state regardless of the previous state. To enter hardware reset state, nRESET must be held long enough to allow internal stabilization and propagation of the reset state.

Caution: An external power source, regulator, for S3C2416 must be stable prior to the deassertion of nRESET. Otherwise, it damages to S3C2416 and its operation will not be guaranteed.

Figure 2-2 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds after the power source supplies enough power-level to S3C2416. Initially, two internal PLLs (MPLL and EPLL) stop. The nRESET pin should be released after the fully settle-down of the power supplylevel. S3C2416 requires a hazard-free system clock (SYSCLK, ARMCLK, HCLK, and PCLK) to operate properly when the system reset is released. Since the PLL does not work initially, the PLL input clock (F SYSCLK instead of the PLL output clock (F

). Software must configure MPLLCON and EPLLCON register to

OUT

) is directly fed to

use each PLL. The PLL begins the lockup sequence toward the new frequency only after the S/W configures the PLL with a new frequency-value. The PLL output is immediately fed to SYSCLK after lock time.

You should be aware that the crystal oscillator settle-down time is not explicitly added by the hardware during the power-up sequence and the crystal oscillation must be settle-down during this period. However, S3C2416 will explicitly add the crystal oscillator settle-down time (OSCWAIT) when it wakes up from the STOP mode.

The EPLL output clock is directly fed to some special clocks for TFT Controller, I2S, HS-MMC, USB host and UART. Since the EPLL input clock is initially fed to the input clocks for them, software must configure EPLLCON register to use the EPLL.

2-3

SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

POWER

nRESET EXTCLK

or XTIpll

PLL is configured by S/W first time

Clock

disable

Lock time

VCO is adapte to new clock frequency

VCO

output

SYSCLK

The logic is operarted by EXTCLK or XTIpll

SYSCLK is FOUT

Figure 2-2. Power-On Reset Sequence

4.3 WATCHDOG RESET

Watchdog reset is invoked when software fails to prevent the watchdog timer from timing out. During the watchdog reset, the following actions occur :

• All units(except some blocks listed in table 2-1 ) go into their pre-defined reset state.

• All pins get their reset state, and BATT_FLT pin is ignored.

• The nRSTOUT pin is asserted during watchdog reset.

Watchdog reset can be activated in normal and idle mode because watchdog timer can expire with clock. Watchdog reset is invoked when watchdog timer and reset are enabled (WTCON[5] = 1, WT CON[0]=1) and

watchdog timer is expired. Watchdog reset is invoked then, the following sequence occurs. :

1. Watchdog reset source asserts.

2. Internal reset signals and nRSTOUT are asserted and reset counter is activated.

3. Reset counter is expired then, internal reset signals and nRSTOUT are deasserted.

2-4

S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

4.4 SOFTWARE RESET

Software can initialize the device state itself when it writes “0x533C_2416” to SWRST register. During the software reset, the following actions occur :

• All units(except some blocks listed in table 2-1 ) go into their pre-defined reset state.

• All pins get their reset state, and BATT_FLT pin is ignored.

• The nRSTOUT pin is asserted during software reset.

Software reset is invoked then, the following sequence occurs. :

1. User write “0x533C_2416” to SWRST register.

2. System controller request bus controller to finish current transactions.

3. Bus controller send acknowledge to system controller after completed bus transactions.

4. System controller request memory controller to enter into self refresh mode.

5. System controller wait for self refresh acknowledge from memory controller.

6. Internal reset signals and nRSTOUT are asserted and reset counter is activated.

7. Reset counter is expired then, internal reset signals and nRSTOUT are deasserted.

4.5 WAKEUP RESET

When S3C2416 is woken up from SLEEP mode by wakeup event, the wakeup reset is invoked. The detail description will be explained in the power management mode section.

Table 2-1 lists alive registers which are not influenced various reset sources except nRESET. With the exception of below registers (in table 2-1), All S3C2416’s internal registers are reset by above-mentioned reset sources.

Table 2-1. Registers & GPIO Status in RESET (R: reset, S: sustain previous value)

Region Registers

Wakeup

SYSCON

GPIO

OSCSET , PWRCFG, RSTCON, RSTSTAT, WKUPSTAT, INFORM0, INFORM1, INFORM2, INFORM3

GPFCON, GPFUDP, GPFDAT, GPGCON[7:0], GPGUDP, GPGDAT[7:0], EXTINT0 ~ EXTINT15

Software

S S S R

R S R R

Watchdog

nRESET

2-5

SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

5 CLOCK MANAGEMENT

5.1 CLOCK GENERATION OVERVIEW

Figure 2-3 shows the block diagram of the clock generation module. The main clock source comes from an external crystal (XTI) or external clock (EXTCLK). EPLL’s input clock is one of the XTI or EXTCLK. Clock selectio n can be done by configuring MUX selection signal. When both XTI and EXTCLK are running, GFM(Glitch Free Mux)’s output can be configured easily without generating glitch. But if you change or select EPLL input clock when either XTI or EXTCLK is running, disabled clock should be have logic LOW.

XTI clock source can be reference of PLL after oscillated at PAD. User can configure stabilization time by setting OSCSET register and ON/OFF when power-down mode by setting PWRCFG register. The clock generator consists of two PLLs (Phase-Locked-Loop) which generate the high-frequency clock sig nals required in S3C2416.

Figure 2-3. Clock Generator Block Diagram

5.2 CLOCK SOURCE SELECTION

Table 2-2 and 2-3 show the relationship between the combination of mode control pins OM[0] and the selection of source clock for S3C2416.

Table 2-2. Clock source selection for the main PLL and clock generation logic

OM[0]

MPLL Reference Clock

(Main clock source)

0 XTI 1 EXTCLK

2-6

S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

Table 2-3. Clock Source Selection for the EPLL

CLKSRC[8] (register) CLKSRC[7] (register) OM[0] EPLL Reference Clock

0 X 0 XTI 0 X 1 EXTCLK 1 0 X XTI 1 1 X EXTCLK

Table 2-4. PLL & Clock Generator Condition

Loop filter capacitance

Fin

Fout

External capacitance used for X-tal

Feedback Resistor used for X-tal

CLF

EXT

MPLLCAP : N/A

EPLLCAP : Typical 1.8nF 5%

MPLL: 10 − 30 MHz

EPLL: 10 − 40 MHz

MPLL: 40 − 1600 MHz

EPLL: 20 − 600 MHz

15 pF

1MΩ

Figure 2-4. Main Oscillator Circuit Examples

2-7

SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

5.3 PLL (PHASE-LOCKED-LOOP)

The PLL (Phase-Locked Loop) frequency synthesizer is constructed in CMOS on single monolithic structure. The PLL provides frequency multiplication capabilities.

MPLL generates the clock sources for ARMCLK, HCLK, PCLK, DDRCLK and SSMCCLK and EPLL generates clock sources for USBHOSTCLK and so forth.

The following sections describe the operation of the PLL, that includes the phase difference detector, charge pump, VCO (Voltage controlled oscillator), and loop filter.

Refer to MPLLCON and EPLLCON registers to change PLL output frequency.

Off-chip loop filter

Fin Pre-Divider

PFD

Charge

Pump

Main

Divider

VCO

Post

Scaler

Fout

Figure 2-5. PLL(Phase-Locked Loop) Block Diagram

5.4 CHANGE PLL SETTINGS IN NORMAL OPERATION

During the operation of S3C2416 in NORMAL mode, if the user wants to change the frequency by writing the PMS value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the internal blocks in S3C2416. The timing diagram is as follow.

MPLL_clk

PMS setting

PLL Locktime

SYSCLK

It changes to LOW value during

lock time automatically

It changes to new PLL clock after lock time automatically

Figure 2-6. The Case that Changes Slow Clock by Setting PMS Value

2-8

S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

5.5 SYSTEM CLOCK CONTROL

The ARMCLK is used for ARM926EJ core, the main CPU of S3C2416. The HCLK is the reference clock for internal AHB bus and peripherals such as the memory controller, the interrupt controller, LCD controller, the DMA, USB host block, System Controller, Power down controller and etc. The PCLK is used for internal APB bus and peripherals such as WDT, IIS, I2C, PWM timer, ADC, UART, GPIO, RTC and SPI etc. DDRCLK is the data strobe clock for mDDR/DDR2 memories. HCLKCON and PCLKCON registers are use d for clock gating of HCLK, PCLK respectively. SCLKCON register is responsible for EPLLclk clock gating on related modules.

Figure 2-7. The Clock Distribution Block Diagram

Figure 2-8 shows MPLL Based clock domain.

Figure 2-8. MPLL Based Clock Domain

2-9

SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

5.6 ARM & BUS CLOCK DIVIDE RATIO

The MSysClk is the base clock for S3C2416 system clock, such as ARMCLK, HCLK, PCLK, DDRCLK, etc. The Table 2-5 shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is determined by

ARMDIV, PREDIV, HCLKDIV and PCLKDIV bits of CLKDIV0 control register. ARMCLK has to faster or equal with HCLK and synchronous. The Table 2-5 shows that DDRCLK, PCLK,

ARMCLK divide ratio with regard HCLK ratio. The fraction in the cell is ratio to MSysClk and the value in the round bracket means maximum frequency value.

Table 2-5. Clock Division Ratio of MPLL Region

MSysClk (800MHz)

HCLK

(133MHz)

DDRCLK (266MHz)

PCLK, SSMC

(133MHz)

ARMCLK (400MHz)

1/1 1/1 1/1 or 1/2 1/1 1/2 1/1 1/2 or 1/4 1/1 or 1/2 1/3 1/1 1/3 or 1/6 1/1 or 1/3 1/4 1/2 1/4 or 1/8 1/1 or 1/2 or 1/4 1/6 1/3 1/6 or 1/12 1/1 or 1/2 or 1/3 or 1/6 1/8 1/4 1/8 or 1/16 1/1 or 1/2 or 1/4 or 1/8 1/12 1/6 1/12 or 1/24 1/1 or 1/2 or 1/3 or 1/4 or 1/6 1/16 1/8 1/16 or 1/32 1/1 or 1/2 or 1/4 or 1/8

2-10

S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

5.7 EXAMPLES FOR CONFIGURING CLOCK REGITER TO PRODUCE SPECIFIC FREQUENCY OF AMBA

CLOCKS.

When PLL output frequency = 800MHz Target frqeuency ARMCLK = 400MHz, HCLK = 133MHz, PCLK = 66MHz, DDRCLK = 266MHz

SSMCCLK = 66MHz Register value ARMDIV = 4’b0001, PREDIV = 2’b10, HCLKDIV = 2’b01, PCLKDIV = 1’b1

HALKHCLK = 1’b1

When PLL output frequency = 533MHz Target frqeuency ARMCLK = 266MHz, HCLK = 133MHz, PCLK = 66MHz, DDRCLK = 266MHz

SSMCCLK = 66MHz Register value ARMDIV = 4’b0001, PREDIV = 2’b01, HCLKDIV = 2’b01, PCLKDIV = 1’b1

HALKHCLK = 1’b1

2-11

SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

Figure 2-9 shows EPLL and special clocks for various peripherals

Figure 2-9. EPLL Based Clock Domain

5.8 ESYSCLK CONTROL

Clocks of the EPLL can be used for various peripherals. Each divider value is configured in CLKDIV1 register and all clocks are enabled or disabled by accessing SCLKCON register. According to USB host interface, If you want to get the clock with exact 50% duty cycle, then make EPLL generate 96MHz and divide the clock.

EPLL will be turned off during STOP and SLEEP mode automatically. Also, EPLL will be generated clock to ESYSCLK, after exiting STOP and SLEEP mode if corresponding bits are enabled in SCLKCON register.

Table 2-6. ESYSCLK Control

Condition ESYSCLK state EPLL state

After reset EPLL reference clock off

After configuring EPLL

During PLL lock time: LOW

After PLL lock time: EPLL output

2-12

S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

6 POWER MANAGEMENT

The power management block controls the system clocks by software for the reduction of power consumption in S3C2416. These schemes are related to PLL, clock control logic(ARMCLK, HCLK, PCLK) and wake-up signal. S3C2416 has four power-down modes. The following section describes each power management mode.

Related registers are PWRMODE, PWRCFG and WKUPSTAT.

6.1 POWER MODE STATE DIAGRAM

Figure 2-10 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering conditions are set by the main CPU.

Normal

(General Clock

STANDBYWFI CMD

Gating Mode)

ID L E

One of

wakeup

source

CMD

One of

wakeup

source

Reset

restricted

wakeup

evants.

or DEEP-STOP

SLEEP

Figure 2-10. Power Mode State Diagram

STOP

2-13

SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

6.2 POWER SAVING MODES

S3C2416 can support various power saving modes. These are Normal mode, idle mode, Stop mode, De ep-stop mode and Sleep mode.

6.2.1 Normal Mode (General Clock Gating Mode)

In General Clock Gating mode, the On/Off clock gating of the individual clock source of each IP block is performed by controlling of each corresponding clock source enable bit. The Clock Gating is applied instantly whenever the corresponding bit (or bits) is changed. (these bits are set or cleared by the main CPU.)

6.2.2 IDLE Mode

In IDLE mode, the clock to CPU core is stopped. To enter the idle mode, User must use ARM926EJ CP15 command (MCR p15, 0, Rd, c7, c0, 4). If user order this command, ARM core prepare to enter into power down mode. These are draining write buffer, letting memory system is in a quiescent state and confirming all external interface(AHB interface) is in idle state. After completing above operation, ARM asserted STANBYWFI signal. So, System Controller of S3C2416 check STANDBYWFI signal is asserted and disabe ARM clock. By doing that, System can go into idle mode safely. To exit the idle mode, All interrupt sources, RTC ALARM, RTC Tick Counter, Battery Fault signal should be activated.

6.2.3 STOP mode (Normal and Deep-stop)

In STOP mode, all clocks are stopped for minimum power consumption. Therefore, the PLL and oscillator circuit are also stopped(oscillator circuit is stopped optionally, see PWRCFG register). The STOP Mode is activated after the execution of the STORE instruction that enables the STOP Mode bit. The STOP Mode bit should be cleared after the wake-up from the STOP state for the entering of next STOP Mode. The H/W logic only detects the lowto-high triggering of the STOP Mode bit.

In Deep-STOP mode ARM core’s power is off by using internal power gating. By this way, the static current will be reduced remarkably compared with STOP mode. To enter the Deep-STOP mode, PWRMODE[18] register should be configured before entering STOP mode. After waking up from Deep-STOP mode, System controller resets ARM core only.

To exit from STOP mode, External interrupt, RTC alarm, RTC Tick, or nRESET has to be activated. During the wake-up sequences, the crystal oscillator and PLL may begin to operate. The crystal-oscillator settle-down-time and the PLL locking-time is required to provide stabilized ARMCLK. Those time-waits are automatically inserted by the hardware of S3C2416. During these time-waits, the clock is not supplied to the internal logic circuitry.

STOP mode Entering sequence is as follows

1. Set the STOP Mode bit (by the main CPU)

2. System controller requests bus controller to finish bus transactions of ARM Core.

3. System controller disable ARM clock after getting ARM Down acknowledge.

4. System controller requests bus controller to finish current transactions.

5. Bus controller send acknowledge to system controller after completed bus transactions.

2-14

S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

6. System controller request memory controller to enter self refresh mode. It is for preserving contents in SDRAM.

7. System controller wait for self refresh acknowledge from memory controller.

8. After receiving the self-refresh acknowledge, system controller disables system clocks, and switches SYSCLK’s source to MPLL reference clock.

9. Disables PLLs and Crystal(XTI) oscillation. If OSC_EN_STOP bit in PWRCFG register is ‘high’ then system controller doesn’t disable crystal oscillation.

10. When PWRMODE[18] register is configured as ‘1’ (Deep-STOP Enabled), ARM_PWRENn signal change to enable ARM power gating. ARM Core is reset state during STOP mode.

STOP mode Exiting sequence is as follows

1. Enable X-tal Oscillator if it is used, and wait the OSC settle down (around 1ms).

2. After the Oscillator settle-down, the System Clock is fed using the PLL input clock and also enable the PLLs and waits the PLL locking time

3. Switching the clock source, now the PLL is the clock source.

4. When waking up from Deep-STOP mode, ARM_PWRENn is restored to release ARM power gating. After producing SYSCLK ARM_RESETn will be released to let ARM work normally.

NOTE

DRAM has to be in self-refresh mode during STOP and SLEEP mode to retain valid memory data. LCD must be stopped before STOP and SLEEP mode, because DRAM can't be accessed when it is in selfrefresh mode.

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SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

6.2.4 SLEEP MODE

In the SLEEP Mode, all the clock sources are off and also the internal logic-power is not supplied except for the wake-up logic circuitry. In this mode, the static power-dissipation of internal logic can be minimized.

SLEEP Mode Entering sequence is as follows.

1. User writes command into the system controller’s PWRMODE[15:0] register to let system enter into the SLEEP Mode.

2. System controller requests bus controller to finish bus transactions of ARM Core.

3. System controller disable ARM clock after getting ARM Down acknowledge.

4. System controller requests bus controller to finish current transactions.

5. Bus controller send acknowledge to system controller after completed bus transactions.

6. System controller request memory controller to enter self refresh mode. It is for preserving contents in SDRAM.

7. System controller wait for self refresh acknowledge from memory controller.

8. After receiving the self-refresh acknowledge, System controller disable system clocks(HCLK, PCLK and so on).

9. System controller asserts control signals to mask unknown state of ALIVE logics and to preserve data of retention Pads.

10. System controller asserts PWR_EN pin and disables the X-tal and PLL oscillation. PWR_EN pin is used to indicate the readiness for external power OFF and to enable and disable of of the power regulator which produces internal-logic power.

SLEEP Mode Exiting sequence is as follows.

1. System controller enable external power source by deactivation of the PWR_EN pin and wait power settle down time (it is programmable by a register in the PWRSETCNT field of RSTCON register).

2. System controller asserts HRESETn and consequently all bus down, self refresh requests and acknowledge signals will be their reset state.

3. System controller release the HRESETn(synchronously, relatively to the system clock) after the power supply is stabilized.

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S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

Figure 2-11. Entering STOP Mode and Exiting STOP Mode (wake-up)

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SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

ARM Down Req. & Ack.

ARMCLK

BUS Down Req. & Ack.

DRAM Self Refresh Req. & Ack.

CKE (DRAM)

SYSCLK

PWR_EN

Figure 2-12. Entering SLEEP Mode and Exiting SLEEP Mode (wake-up)

SLEEP mode is initiated

Wake-up event

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S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

6.3 WAKE-UP EVENT

When S3C2416 wakes up from the STOP Mode by an External Interrupt, a RTC alarm interrupt and other interrupts, the PLL is turned on automatically. The initial-state of S3C2416 after wake-up from the SLEEP Mode is almost the same as the Power-On-Reset state except for the contents of the external DRAM is preserved. In contrast, S3C2416 automatically recovers the previous working state after wake-up from the STOP Mode. The following table shows the states of PLLs and internal clocks after wake-ups from the power-saving modes.

Table 2-7. The Status of PLL and ARMCLK After Wake-up

Mode before

wake-up

PLL on/off after

wake-up

SYSCLK after wake-up

and before the lock time

SYSCLK after the lock

time by internal logic

IDLE Unchanged PLL output PLL output

STOP

PLL state ahead of entering STOP mode

(PLL ON or not)

PLL reference clock

SYSCLK ahead of entering STOP mode

(PLL output or not)

SLEEP Off PLL reference clock PLL reference(input) clock

6.4 OUTPUT PORT STATE AND STOP AND SLEEP MODE

Refer to GPIO chapter.

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SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

6.5 POWER SAVING MODE ENTERING/EXITING CONDITION

Table 2-8 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering conditions are set by the main CPU.

Pleas refer to power-related registers(PWRMODE, PWRCFG and WKUPSTAT) before adopting power sav i ng scheme on your system.

In dealing with sleep mode, It is good for you to know following two restrictions. To enter sleep mode by BATT_FLT, you have to configure BATF_CFG bits of PWRCFG register. Not to exit from sleep mode when BATT_FLT is LOW, you have to configure SLEEP_CFG bit of PWRCFG register.

Table 2-8. Power Saving Mode Entering/Exiting Condition

Power down mode Enter Exit

Clock Gating at NORMAL

Clear a respective clock on/off bit for each IP to save power.

Set a respective clock on/off bit for each IP to operate normally

1. All interrupt sources

IDLE STANDBYWFI

2. RTC alarm

3. RTC Tick

4. BATT_FLT

1. EINT[15:0] (External Interrupt)

STOP CMD

2. RTC alarm

3. RTC Tick

4. BATT_FLT

1. EINT[15:0] (External Interrupt)

SLEEP CMD

2. RTC alarm

3. RTC Tick

4. BATT_FLT

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S3C2416X RISC MICROPROCESSOR SYSTEM CONTROLLER

7 REGISTER DESCRIPTIONS

The system controller registers are divided into seven categories; clock source control, clo ck control, power management, reset control, system controller status, bus configuration, and misc. The following section will describe the behavior of the system controller.

7.1 ADDRESS MAP

Table 2-9 summarizes the address map of the system controller.

Table 2-9. System Controller Address Map

LOCKCON0 0x4C00_0000 R/W MPLL lock time count register X 0x0000_FFFF LOCKCON1 0x4C00_0004 R/W EPLL lock time count register X 0x0000_FFFF

OSCSET 0x4C00_0008 R/W Oscillator stabilization control register O 0x0000_8000

MPLLCON 0x4C00_0010 R/W MPLL configuration register X 0x0185_40C0

EPLLCON 0x4C00_0018 R/W EPLL configuration register X 0x0120_0102

EPLLCON_K 0x4C00_001C R/W EPLL configuration register for K value X 0x0000_0000

CLKSRC 0x4C00_0020 R/W Clock source control register X 0x0000_0000 CLKDIV0 0x4C00_0024 R/W Clock divider ratio control register0 X 0x0000_000C CLKDIV1 0x4C00_0028 R/W Clock divider ratio control register1 X 0x0000_0000 CLKDIV2 0x4C00_002C R/W Clock divider ratio control register2 X 0x0000_0000

HCLKCON 0x4C00_0030 R/W HCLK enable register X 0xFFFF_FFFF PCLKCON 0x4C00_0034 R/W PCLK enable register X 0xFFFF_FFFF SCLKCON 0x4C00_0038 R/W Special clock enable register X 0xFFFF_DFFF

PWRMODE 0x4C00_0040 R/W Power mode control register X 0x0000_0000

SWRST 0x4C00_0044 R/W Software reset control register X 0x0000_0000

BUSPRI0 0x4C00_0050 R/W Bus priority control register 0 X 0x0000_0000 PWRCFG 0x4C00_0060 R/W

RSTCON 0x4C00_0064 R/W Reset control register O 0x0006_0101

RSTSTAT 0x4C00_0068 R Reset status register O 0x0000_0001

WKUPSTAT 0x4C00_006C R/W Wake-up status re gister O 0x0000_0000

INFORM0 0x4C00_0070 R/W SLEEP mode information register 0 O 0x0000_0000 INFORM1 0x4C00_0074 R/W SLEEP mode information register 1 O 0x0000_0000 INFORM2 0x4C00_0078 R/W SLEEP mode information register 2 O 0x0000_0000 INFORM3 0x4C00_007C R/W SLEEP mode information register 3 O 0x0000_0000

USB_PHYCTRL 0x4C00_0080 R/W USB PHY control register X 0x0000_0000

USB_PHYPWR 0x4C00_0084 R/W USB PHY power control register X 0x0000_0000 USB_RSTCON 0x4C00_0088 R/W USB PHY reset control register X 0x0000_0000 USB_CLKCON 0x4C00_008C R/W USB PHY clock control register X 0x0000_0000

Power management configuration register

O 0x0000_0000

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SYSTEM CONTROLLER S3C2416X RISC MICROPROCESSOR

8 INDIVIDUAL REGISTER DESCRIPTIONS

8.1 CLOCK SOURCE CONTROL REGISTERS (LOCKCON0, LOCKCON1, OSCSET, MPLLCON, AND EPLLCON)

The six registers control two internal PLLs and an external oscillator. The output frequency of the PLL is determined by the divider values of MPLLCON and EPLLCON. The stabilization time for PLLs and the oscillator is controlled by LOCKCON0/1 and OSCSET, respectively.

LOCKCON0 0x4C00_0000 R/W MPLL lock time count register 0x0000_FFFF LOCKCON1 0x4C00_0004 R/W EPLL lock time count register 0x0000_FFFF

OSCSET 0x4C00_0008 R/W Oscillator stabilization control register 0x0000_8000

MPLLCON 0x4C00_0010 R/W MPLL configuration register 0x0185_40C0

EPLLCON 0x4C00_0018 R/W EPLL configuration register 0x0120_0102

EPLLCON_K 0x4C00_001C R/W EPLL configuration register for K value 0x0000_0000

Conventional PLL requires stabilization duration after the PLL is ON. The duration can be varied according to the device variation. Thus, software must adjust these fields with appropriate values in the LOCKCON0/1 register whose values mean the number of the external reference clock.

LOCKCON0 Bit Description Initial Value

RESERVED [31:16] RESERVED 0x0000 M_LTIME [15:0]

MPLL lock time count value for ARMCLK, HCLK, and PCLK Typically, M_LTIME must be longer than 300 usec.

0xFFFF

LOCKCON1 Bit Description Initial Value

RESERVED [31:16] RESERVED 0x0000 E_LTIME [15:0]

EPLL lock time count value for UARTCLK, SPICLK and etc. Typically, E_LTIME must be longer than 300 usec.

0xFFFF

In general, an oscillator requires stabilization time. This register specifies the duration based on the reference clock.

OSCSET Bit Description Initial Value

RESERVED [31:0] RESERVED 0x0000 XTALWAIT [15:0]

Crystal oscillator settle-down wait time, this value is valid when s3c2416 is wakeup by stop mode

0x8000

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SAMSUNG S3C2416 User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

Important Notice

NOTIFICATION OF REVISIONS

Table of Contents

1 INTRODUCTION

2 FEATURES

3 BLOCK DIAGRAM

4 PIN ASSIGNMENTS

1 OVERVIEW

2 FEATURE

3 BLOCK DIAGRAM

4 FUNCTIONAL DESCRIPTIONS

5 CLOCK MANAGEMENT

6 POWER MANAGEMENT

7 REGISTER DESCRIPTIONS

8 INDIVIDUAL REGISTER DESCRIPTIONS