Samsung S3C2410A User Manual

21-S3-C2410A-032004

USER'S MANUAL

S3C2410A – 200MHz & 266MHz

32-Bit RISC

Microprocessor

Revision 1.0

S3C2410A

200MHz & 266MHz

32-BIT RISC

MICROPROCESSOR

USER'S MANUAL

Revision 1.0

Important Notice

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This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

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"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.

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S3C2410A – 200MHz & 266MHz 32-Bit RISC Microprocessor User's Manual, Revision 1.0 (March 2004) Publication Number: 21-S3-C2410A-032004

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Home Page: http://www.samsung.com Printed in the Republic of Korea

Table of Contents

Chapter 1 Product Overview

Introduction.........................................................................................................................................1-1

Features.............................................................................................................................................1-2

Block Diagram ....................................................................................................................................1-5

Pin Assignments .................................................................................................................................1-6

Signal Descriptions ......................................................................................................................1-20

S3C2410A Special Registers ........................................................................................................1-26

Chapter 2 Programmer's model

Overview.............................................................................................................................................2-1

Processor Operating States .........................................................................................................2-1

Switching State...........................................................................................................................2-1

Memory Formats .........................................................................................................................2-1

Big-Endian Format .......................................................................................................................2-2

Little-Endian Format ....................................................................................................................2-2

Instruction Length........................................................................................................................2-2

Operating Modes.........................................................................................................................2-3

Registers....................................................................................................................................2-3

The Program Status Registers......................................................................................................2-7

Exceptions .................................................................................................................................2-10

Interrupt Latencies.......................................................................................................................2-15

Reset .........................................................................................................................................2-15

S3C2410A MICROPROCESSOR iii

Table of Contents (Continued)

Chapter 3 ARM Instruction set

Instruction Set Summay .......................................................................................................................3-1

Format Summary ........................................................................................................................3-1

Instruction Summary ....................................................................................................................3-2

The Condition Field ..............................................................................................................................3-4

Branch and Exchange (BX) ...................................................................................................................3-5

Instruction Cycle Times ................................................................................................................3-5

Assembler Syntax.......................................................................................................................3-5

Using R15 as an Operand ............................................................................................................3-5

Branch and Branch with Link (B, Bl) ......................................................................................................3-7

The Link Bit ................................................................................................................................3-7

Instruction Cycle Times ................................................................................................................3-7

Assembler Syntax.......................................................................................................................3-8

Data Processing..................................................................................................................................3-9

CPSR Flags ................................................................................................................................3-11

Shifts .........................................................................................................................................3-12

Immediate Operand Rotates .........................................................................................................3-16

Writing to R15 .............................................................................................................................3-16

Using R15 as an Operandy ...........................................................................................................3-16

TEQ, TST, CMP and CMN Opcodes ..............................................................................................3-16

Instruction Cycle Times ................................................................................................................3-16

Assembler Syntax.......................................................................................................................3-17

Examples ...................................................................................................................................3-17

PSR Transfer (MRS, MSR) ...................................................................................................................3-18

Operand Restrictions ...................................................................................................................3-18

Reserved Bits..............................................................................................................................3-20

Examples ...................................................................................................................................3-20

Instruction Cycle Times ................................................................................................................3-20

Assembly Syntax........................................................................................................................3-21

Examples ...................................................................................................................................3-21

Multiply and Multiply-Accumulate (MUL, MLA) .......................................................................................3-22

CPSR Flags ................................................................................................................................3-24

Instruction Cycle Times ................................................................................................................3-24

Assembler Syntax.......................................................................................................................3-24

Examples ...................................................................................................................................3-24

Multiply Long and Multiply-Accumulate Long (MULL, MLAL)....................................................................3-25

Operand Restrictions ...................................................................................................................3-26

CPSR Flags ................................................................................................................................3-26

Instruction Cycle Times ................................................................................................................3-26

Assembler Syntax.......................................................................................................................3-27

Examples ...................................................................................................................................3-27

iv S3C2410A MICROPROCESSOR

Table of Contents (Continued)

Chapter 3 ARM Instruction set (Continued)

Single Data Transfer (LDR, STR) ...........................................................................................................3-28

Offsets And Auto-Indexing ............................................................................................................3-29

Shifted Register Offset .................................................................................................................3-29

Bytes and Words ........................................................................................................................3-29

Use of R15..................................................................................................................................3-31

Example:....................................................................................................................................3-31

Data Aborts ................................................................................................................................3-31

Instruction Cycle Times ................................................................................................................3-31

Assembler Syntax.......................................................................................................................3-32

Examples ...................................................................................................................................3-33

Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH) ...........................................................3-34

Offsets and Auto-Indexing ............................................................................................................3-35

Halfword Load and Stores .............................................................................................................3-36

Use of R15..................................................................................................................................3-37

Data Aborts ................................................................................................................................3-37

Instruction Cycle Times ................................................................................................................3-37

Assembler Syntax.......................................................................................................................3-38

Examples ...................................................................................................................................3-39

Block Data Transfer (LDM, STM)...........................................................................................................3-40

The Register List.........................................................................................................................3-40

Addressing Modes .......................................................................................................................3-41

Address Alignment ......................................................................................................................3-41

Use of the S Bit...........................................................................................................................3-43

Use of R15 as the Base ...............................................................................................................3-43

Inclusion of the Base in the Register List.......................................................................................3-44

Data Aborts ................................................................................................................................3-44

Instruction Cycle Times ................................................................................................................3-44

Assembler Syntax.......................................................................................................................3-45

Examples ...................................................................................................................................3-46

Single Data Swap (SWP) .....................................................................................................................3-47

Bytes and Words ........................................................................................................................3-47

Use of R15..................................................................................................................................3-48

Data Aborts ................................................................................................................................3-48

Instruction Cycle Times ................................................................................................................3-48

Assembler Syntax.......................................................................................................................3-48

Software Interrupt (SWI).......................................................................................................................3-49

Return from the Supervisor ...........................................................................................................3-49

Comment Field............................................................................................................................3-49

Instruction Cycle Times ................................................................................................................3-49

Assembler Syntax.......................................................................................................................3-50

Coprocessor Data Operations (CDP) .....................................................................................................3-51

Coprocessor Instructions ..............................................................................................................3-51

Instruction Cycle Times ................................................................................................................3-52

Examples ...................................................................................................................................3-52

S3C2410A MICROPROCESSOR v

Table of Contents (Continued)

Chapter 3 ARM Instruction set (Continued)

Coprocessor Data Transfers (LDC, STC) ................................................................................................3-53

The Coprocessor Fields ...............................................................................................................3-54

Addressing Modes .......................................................................................................................3-54

Address Alignment ......................................................................................................................3-54

Data Aborts ................................................................................................................................3-54

Assembler Syntax.......................................................................................................................3-55

Examples ...................................................................................................................................3-55

Coprocessor Register Transfers (MRC, MCR).................................................................................3-56

The Coprocessor Fields ...............................................................................................................3-56

Transfers to R15 ..........................................................................................................................3-57

Transfers from R15 ......................................................................................................................3-57

Instruction Cycle Times ................................................................................................................3-57

Assembler Syntax.......................................................................................................................3-57

Examples ...................................................................................................................................3-57

Undefined Instruction ...................................................................................................................3-58

Instruction Cycle Times ................................................................................................................3-58

Assembler Syntax.......................................................................................................................3-58

Instruction Set Examples .............................................................................................................3-59

Using the Conditional Instructions .................................................................................................3-59

Pseudo-Random Binary Sequence Generator.................................................................................3-61

Multiplication by Constant Using the Barrel Shifter..........................................................................3-61

Loading a Word from an Unknown Alignment .................................................................................3-63

Chapter 4 Thumb Instruction Set

Thumb Instruction Set Format ...............................................................................................................4-1

Format Summary ........................................................................................................................4-2

Opcode Summary .......................................................................................................................4-3

Format 1: Move Shifted Register...........................................................................................................4-5

Operation....................................................................................................................................4-5

Instruction Cycle Times ................................................................................................................4-6

Examples ...................................................................................................................................4-6

Format 2: Add/Subtract........................................................................................................................4-7

Operation....................................................................................................................................4-7

Instruction Cycle Times ................................................................................................................4-8

Examples ...................................................................................................................................4-8

Format 3: Move/Compare/Add/Subtract Immediate .................................................................................4-9

Operations..................................................................................................................................4-9

Instruction Cycle Times ................................................................................................................4-10

Examples ...................................................................................................................................4-10

Format 4: ALU Operations ....................................................................................................................4-11

Operation....................................................................................................................................4-11

Instruction Cycle Times ................................................................................................................4-12

Examples ...................................................................................................................................4-12

vi S3C2410A MICROPROCESSOR

Table of Contents (Continued)

Chapter 4 Thumb Instruction Set (Continued)

Format 5: Hi-Register Operations/Branch Exchange...............................................................................4-13

Operation....................................................................................................................................4-13

Instruction Cycle Times ................................................................................................................4-14

The Bx Instruction .......................................................................................................................4-14

Examples ...................................................................................................................................4-15

Using R15 as an Operand ............................................................................................................4-15

Format 6: Pc-Relative Load ..................................................................................................................4-16

Operation....................................................................................................................................4-16

Instruction Cycle Times ................................................................................................................4-17

Examples ...................................................................................................................................4-17

Format 7: Load/Store with Register Offset ..............................................................................................4-18

Operation....................................................................................................................................4-19

Instruction Cycle Times ................................................................................................................4-19

Examples ...................................................................................................................................4-19

Format 8: Load/Store Sign-Extended Byte/Halfword................................................................................4-20

Operation....................................................................................................................................4-20

Instruction Cycle Times ................................................................................................................4-21

Examples ...................................................................................................................................4-21

Format 9: Load/Store With Immediate Offset ..........................................................................................4-22

Operation....................................................................................................................................4-23

Instruction Cycle Times ................................................................................................................4-23

Examples ...................................................................................................................................4-23

Format 10: Load/Store Halfword ............................................................................................................4-24

Operation....................................................................................................................................4-24

Instruction Cycle Times ................................................................................................................4-25

Examples ...................................................................................................................................4-25

Format 11: Sp-Relative Load/Store ........................................................................................................4-26

Operation....................................................................................................................................4-26

Instruction Cycle Times ................................................................................................................4-27

Examples ...................................................................................................................................4-27

Format 12: Load Address .....................................................................................................................4-28

Operation....................................................................................................................................4-28

Instruction Cycle Times ................................................................................................................4-29

Examples ...................................................................................................................................4-29

Format 13: Add Offset To Stack Pointer ................................................................................................4-30

Operation....................................................................................................................................4-30

Instruction Cycle Times ................................................................................................................4-30

Examples ...................................................................................................................................4-30

Format 14: Push/Pop Registers............................................................................................................4-31

Operation....................................................................................................................................4-31

Instruction Cycle Times ................................................................................................................4-32

Examples ...................................................................................................................................4-32

Format 15: Multiple Load/Store .............................................................................................................4-33

Operation....................................................................................................................................4-33

Instruction Cycle Times ................................................................................................................4-33

Examples ...................................................................................................................................4-33

S3C2410A MICROPROCESSOR vii

Table of Contents (Continued)

Chapter 4 Thumb Instruction Set (Continued)

Format 16: Conditional Branch..............................................................................................................4-34

Operation....................................................................................................................................4-34

Instruction Cycle Times ................................................................................................................4-35

Examples ...................................................................................................................................4-35

Format 17: Software Interrupt ................................................................................................................4-36

Operation....................................................................................................................................4-36

Instruction Cycle Times ................................................................................................................4-36

Examples ...................................................................................................................................4-36

Format 18: Unconditional Branch ..........................................................................................................4-37

Operation....................................................................................................................................4-37

Examples ...................................................................................................................................4-37

Format 19: Long Branch With Link........................................................................................................4-38

Operation....................................................................................................................................4-38

Instruction Cycle Times ................................................................................................................4-39

Examples ...................................................................................................................................4-39

Instruction Set Examples .....................................................................................................................4-40

Multiplication by a Constant Using Shifts and Adds ........................................................................4-40

General Purpose Signed Divide .....................................................................................................4-41

Division by a Constant .................................................................................................................4-43

Chapter 5 Memory Controller

Overview.............................................................................................................................................5-1

Function Description ............................................................................................................................5-3

Bank0 Bus Width ........................................................................................................................5-3

Memory (SROM/SDRAM) Address Pin Connections .......................................................................5-3

Sdram Bank Address Pin Connection............................................................................................5-4

Nwait Pin Operation .....................................................................................................................5-5

Programmable Access Cycle .......................................................................................................5-11

Bus Width & Wait Control Register (BWSCON) .............................................................................5-13

Bank Control Register (BANKCONN: NGCS0-NGCS5)....................................................................5-15

Bank Control Register (BANKCONN: NGCS6-NGCS7)....................................................................5-16

Refresh Control Register ..............................................................................................................5-17

Banksize Register.......................................................................................................................5-18

SDRAM Mode Register Set Register (MRSR) ................................................................................5-19

viii S3C2410A MICROPROCESSOR

Table of Contents (Continued)

Chapter 6 NAND Flash Controller

Overview.............................................................................................................................................6-1

Features.....................................................................................................................................6-1

Block Diagram ............................................................................................................................6-2

Operation Scheme.......................................................................................................................6-2

Auto Boot Mode Sequence...........................................................................................................6-3

Nand Flash Mode Configuration ....................................................................................................6-3

Nand Flash Memory Timing ..........................................................................................................6-3

Pin Configuration.........................................................................................................................6-4

Boot and Nand Flash Configurations ..............................................................................................6-4

512-Byte Ecc Parity Code Assignment Table .................................................................................6-4

Nand Flash Memory Mapping.......................................................................................................6-5

Special Function Registers ...................................................................................................................6-6

Nand Flash Configuration (NFCONF) Register................................................................................6-6

Nand Flash Command Set (NFCMD) Register ................................................................................6-7

Nand Flash Address Set (NFADDR) Register .................................................................................6-7

Nand Flash Data (NFDATA) Register.............................................................................................6-7

Nand Flash Operation Status (NFSTAT) Register ...........................................................................6-8

Nand Flash ECC (NFECC) Register ..............................................................................................6-8

Chapter 7 Clock & Power Management

Overview.............................................................................................................................................7-1

Functional Description .........................................................................................................................7-2

Clock Architecture .......................................................................................................................7-2

Clock Source Selection................................................................................................................7-2

Phase Locked Loop (PLL)............................................................................................................7-4

Clock Control Logic .....................................................................................................................7-6

Power Management.....................................................................................................................7-9

Clock Generator & Power Management Special Register ........................................................................7-19

Lock Time Count Register (LOCKTIME).........................................................................................7-19

PLL Value Selection Table ...........................................................................................................7-20

Clock Control Register (CLKCON) .................................................................................................7-21

Clock Slow Control (CLKSLOW) Register......................................................................................7-22

Clock Divider Control (CLKDIVN) Register ......................................................................................7-22

S3C2410A MICROPROCESSOR ix

Table of Contents (Continued)

Chapter 8 DMA

Overview.............................................................................................................................................8-1

DMA Request Sources ........................................................................................................................8-2

DMA Operation ...................................................................................................................................8-2

External DMA DREQ/DACK Protocol............................................................................................8-3

Examples ...................................................................................................................................8-6

DMA Special Registers........................................................................................................................8-7

DMA Initial Source (DISRC) Register .............................................................................................8-7

DMA Initial Source Control (DISRCC) Register ...............................................................................8-7

DMA Initial Destination (DIDST) Register .......................................................................................8-8

DMA Initial Destination Control (DIDSTC) Register ..........................................................................8-8

DMA Control (DCON) Register ......................................................................................................8-9

DMA Status (DSTAT) Register......................................................................................................8-11

DMA Current Source (DCSRC) Register ........................................................................................8-11

Current Destination (DCDST) Register...........................................................................................8-12

DMA Mask Trigger (DMASKTRIG) Register....................................................................................8-13

Chapter 9 I/O Ports

Overview.............................................................................................................................................9-1

Port Control Descriptions .....................................................................................................................9-7

Port Configuration Register (GPACON-GPHCON) ...........................................................................9-7

Port Data Register (GPADAT-GPHDAT) ........................................................................................9-7

Port Pull-up Register (GPBUP-GPHUP).........................................................................................9-7

Miscellaneous Control Register.....................................................................................................9-7

External Interrupt Control Register (EXTINTN) .................................................................................9-7

Power_Off Mode and I/O Ports......................................................................................................9-7

I/O Port Control Register......................................................................................................................9-8

Port A Control Registers (GPACON/GPADAT) ...............................................................................9-8

Port B Control Registers (GPBCON, GPBDAT, and GPBUP)..........................................................9-9

Port C Control Registers (GPCCON, GPCDAT, and GPCUP)..........................................................9-10

Port D Control Registers (GPDCON, GPDDAT, and GPDUP)..........................................................9-12

Port E Control Registers (GPECON, GPEDAT, and GPEUP)..........................................................9-14

Port F Control Registers (GPFCON, GPFDAT, and GPFPU) ...........................................................9-16

Port G Control Registers (GPGCON, GPGDAT, and GPGUP).........................................................9-17

Port H Control Registers (GPHCON, GPHDAT, and GPHUP)..........................................................9-19

Miscellaneous Control Register (MISCCR).....................................................................................9-20

Dclk Control Registers (DCLKCON)...............................................................................................9-21

External Interrupt Control Register (EXTINTN) .................................................................................9-22

External Interrupt Filter Register (EINTFLTN) ..................................................................................9-25

External Interrupt Mask Register (EINTMASK)...............................................................................9-26

External Interrupt Pending Register (EINTPENDN) ..........................................................................9-27

General Status Register (GSTATUSN)...........................................................................................9-28

x S3C2410A MICROPROCESSOR

Table of Contents (Continued)

Chapter 10 PWM Timer

Overview.............................................................................................................................................10-1

Feature.......................................................................................................................................10-1

Pwm Timer Operation ..........................................................................................................................10-3

Prescaler & Divider......................................................................................................................10-3

Basic Timer Operation .................................................................................................................10-3

Auto Reload & Double Buffering....................................................................................................10-4

Timer Initialization Using Manual Update Bit and Inverter Bit............................................................10-5

Timer Operation...........................................................................................................................10-6

Pulse Width Modulation (PWM) ....................................................................................................10-7

Output Level Control ....................................................................................................................10-8

Dead Zone Generator ...................................................................................................................10-9

Dma Request Mode .....................................................................................................................10-10

PWM Timer Control Registers ..............................................................................................................10-11

Timer Configuration Register 0 (TCFG0) .........................................................................................10-11

Timer Configuration Register 1 (TCFG1) .........................................................................................10-12

Timer Control (TCON) Register......................................................................................................10-13

Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)...................................10-15

Timer 0 Count Observation Register (TCNTO0)...............................................................................10-15

Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)...................................10-16

Timer 1 Count Observation Register (TCNTO1)...............................................................................10-16

Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)...................................10-17

Timer 2 Count Observation Register (TCNTO2)...............................................................................10-17

Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)...................................10-18

Timer 3 Count Observation Register (TCNTO3)...............................................................................10-18

Timer 4 Count Buffer Register (TCNTB4)........................................................................................10-19

Timer 4 Count Observation Register (TCNTO4)...............................................................................10-19

Chapter 11 UART

Overview.............................................................................................................................................11-1

Features.....................................................................................................................................11-1

Block Diagram ....................................................................................................................................11-2

Uart Operation.............................................................................................................................11-3

Uart Special Registers .........................................................................................................................11-10

Uart Line Control Register ............................................................................................................11-10

Uart Control Register ...................................................................................................................11-11

Uart FIFO Control Register...........................................................................................................11-13

Uart Modem Control Register........................................................................................................11-14

Uart Tx/Rx Status Register...........................................................................................................11-15

Uart Error Status Register............................................................................................................11-16

Uart FIFO Status Register ............................................................................................................11-17

Uart Modem Status Register ........................................................................................................11-18

Uart Transmit Buffer Register (Holding Register & FIFO Register).....................................................11-19

Uart Receive Buffer Register (Holding Register & FIFO Register) ......................................................11-19

Uart Baud Rate Divisor Register ....................................................................................................11-20

S3C2410A MICROPROCESSOR xi

Table of Contents (Continued)

Chapter 12 USB Host Controller

Overview.............................................................................................................................................12-1

USB Host Controller Special Registers..........................................................................................12-2

Chapter 13 USB Device Controller

Overview.............................................................................................................................................13-1

Feature.......................................................................................................................................13-1

USB Device Controller Special Registers ...............................................................................................13-3

Function Address Register (Func_Addr_Reg) .................................................................................13-5

Power Management Register (Pwr_Reg) ........................................................................................13-6

Interrupt Register (Ep_Int_Reg/Usb_Int_Reg)..................................................................................13-7

Interrupt Enable Register (Ep_Int_En_Reg/Usb_Int_En_Reg)...........................................................13-9

Frame Number Register (Fpame_Num1_Reg/Frame_Num2_Reg) ....................................................13-10

Index Register (Index_Reg)...........................................................................................................13-11

End Point0 Control Status Register (Ep0_Csr) ...............................................................................13-12

End Point In Control Status Register (In_Csr1_Reg/In_Csr2_Reg)....................................................13-14

End Point Out Control Status Register (Out_Csr1_Reg/Out_Csr2_Reg) ............................................13-16

End Point FIFO Register (Epn_Fifo_Reg) .......................................................................................13-18

Max Packet Register (Maxp_Reg).................................................................................................13-19

End Point Out Write Count Register (Out_Fifo_Cnt1_Reg/Out_Fifo_Cnt2_Reg) .................................13-20

DMA Interface Control Register (Epn_Dma_Con)............................................................................13-21

DMA Unit Counter Register (Epn_Dma_Unit)..................................................................................13-22

DMA FIFO Counter Register (Epn_Dma_FIFO)...............................................................................13-23

DMA Total Transfer Counter Register (Epn_Dma_Ttc_L, M, H).........................................................13-24

xii S3C2410A MICROPROCESSOR

Table of Contents (Continued)

Chapter 14 Interrupt Controller

Overview.............................................................................................................................................14-1

Interrupt Controller Operation........................................................................................................14-2

Interrupt Sources.........................................................................................................................14-3

Interrupt Priority Generating Block.................................................................................................14-4

Interrupt Priority...........................................................................................................................14-5

Interrupt Controller Special Registers .....................................................................................................14-6

Source Pending (SRCPND) Register.............................................................................................14-6

Interrupt Mode (INTMOD) Register.................................................................................................14-8

Interrupt Mask (INTMSK) Register .................................................................................................14-10

Priority Register (PRIORITY).........................................................................................................14-12

Interrupt Pending (INTPND) Register..............................................................................................14-14

Interrupt Offset (INTOFFSET) Register ...........................................................................................14-16

Sub Source Pending (SUBSRCPND) Register................................................................................14-17

Interrupt Sub Mask (INTSUBMSK) Register ...................................................................................14-18

Chapter 15 LCD Controller

Overview.............................................................................................................................................15-1

Features.....................................................................................................................................15-1

Common Features.......................................................................................................................15-2

External Interface Signal ..............................................................................................................15-2

Block Diagram ............................................................................................................................15-3

STN LCD Controller Operation ..............................................................................................................15-4

Timing Generator (TIMEGEN) .......................................................................................................15-4

Video Operation ..........................................................................................................................15-5

Dithering and Frame Rate Control .................................................................................................15-7

Memory Data Format (STN, BSWP = 0) ........................................................................................15-9

TFT LCD Controller Operation...............................................................................................................15-15

Video Operation ..........................................................................................................................15-15

Memory Data Format (TFT) ..........................................................................................................15-16

256 Palette Usage (TFT) ..............................................................................................................15-20

Samsung TFT LCD Panel (3.5″ Portrait / 256k Color /Reflective A-SI TFT LCD).................................15-23

Virtual Display (TFT/STN) .............................................................................................................15-24

LCD Power Enable (STN/TFT) .......................................................................................................15-25

LCD Controller Special Registers ..................................................................................................15-26

Frame Buffer Start Address 1 Register ..........................................................................................15-32

S3C2410A MICROPROCESSOR xiii

Table of Contents (Continued)

Chapter 16 ADC & Touch Screen Interface

Overview.............................................................................................................................................16-1

Features.....................................................................................................................................16-1

ADC & Touch Screen Interface Operation ..............................................................................................16-2

Block Diagram ............................................................................................................................16-2

Example for Touch Screen ...........................................................................................................16-3

Function Descriptions ..................................................................................................................16-4

ADC and Touch Screen Interface Special Registers................................................................................16-7

ADC Control (ADCCON) Register ..................................................................................................16-7

ADC Touch Screen Control (ADCTSC) Register..............................................................................16-8

ADC Start Delay (ADCDLY) Register.............................................................................................16-9

ADC Conversion Data (ADCDAT0) Register....................................................................................16-10

ADC Conversion Data (ADCDAT1) Register....................................................................................16-11

Chapter 17 Real Time Clock (RTC)

Overview.............................................................................................................................................17-1

Features.....................................................................................................................................17-1

Real Time Clock Operation ...........................................................................................................17-2

Leap Year Generator....................................................................................................................17-2

Read/Write Registers ...................................................................................................................17-3

Backup Battery Operation............................................................................................................17-3

Alarm Function............................................................................................................................17-3

Tick Time Interrupt.......................................................................................................................17-3

Round Reset Function .................................................................................................................17-3

32.768kHz X-Tal Connection Example..........................................................................................17-4

Real Time Clock Special Registers .......................................................................................................17-5

Real Time Clock Control (RTCCON) Register .................................................................................17-5

Tick Time Count (TICNT) Register .................................................................................................17-5

RTC Alarm Control (RTCALM) Register..........................................................................................17-6

Alarm Second Data (ALMSEC) Register ........................................................................................17-7

Alarm Min Data (ALMMIN) Register...............................................................................................17-7

Alarm Hour Data (ALMHOUR) Register..........................................................................................17-7

Alarm Date Data (ALMDATE) Register ..........................................................................................17-8

Alarm Mon Data (ALMMON) Register ............................................................................................17-8

Alarm Year Data (ALMYEAR) Register ..........................................................................................17-8

RTC Round Reset (RTCRST) Register...........................................................................................17-9

BCD Second (BCDSEC) Register .................................................................................................17-9

BCD Minute (BCDMIN) Register....................................................................................................17-9

BCD Hour (BCDHOUR) Register...................................................................................................17-10

BCD Date (BCDDATE) Register ....................................................................................................17-10

BCD Day (BCDDAY) Register.......................................................................................................17-10

BCD Month (BCDMON) Register...................................................................................................17-11

BCD Year (BCDYEAR) Register ...................................................................................................17-11

xiv S3C2410A MICROPROCESSOR

Table of Contents (Continued)

Chapter 18 WatchDog Timer

Overview.............................................................................................................................................18-1

Features.....................................................................................................................................18-1

Watchdog Timer Operation ...........................................................................................................18-2

WTDAT & WTCNT.......................................................................................................................18-2

Consideration of Debugging Environment .......................................................................................18-2

Watchdog Timer Special Registers .......................................................................................................18-3

Watchdog Timer Control (WTCON) Register...................................................................................18-3

Watchdog Timer Data (WTDAT) Register .......................................................................................18-4

Watchdog Timer Count (WTCNT) Register.....................................................................................18-4

Chapter 19 MMC/SD/SDIO Host controller

Overview.............................................................................................................................................19-1

Features.....................................................................................................................................19-1

Block Diagram ............................................................................................................................19-2

SDI Operation .............................................................................................................................19-3

SDIO Operation ...........................................................................................................................19-4

SDI Special Registers..................................................................................................................19-5

Chapter 20 IIC-BUS Interface

Overview.............................................................................................................................................20-1

IIC-Bus Interface..........................................................................................................................20-3

Start and Stop Conditions ............................................................................................................20-3

Data Transfer Format ...................................................................................................................20-4

ACK Signal Transmission.............................................................................................................20-5

Read-Write Operation ..................................................................................................................20-6

Bus Arbitration Procedures ...........................................................................................................20-6

Abort Conditions ..........................................................................................................................20-6

Configuring IIC-Bus ......................................................................................................................20-6

Flowcharts of Operations in Each Mode.........................................................................................20-7

IIC-Bus Interface Special Registers .......................................................................................................20-11

Multi-Master IIC-Bus Control (IICCON) Register..............................................................................20-11

Multi-Master IIC-Bus Control/Status (IICSTAT) Register...................................................................20-12

Multi-Master IIC-Bus Address (IICADD) Register.............................................................................20-13

Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register ...................................................20-13

S3C2410A MICROPROCESSOR xv

Table of Contents (Continued)

Chapter 21 IIS-BUS Interface

Overview.............................................................................................................................................21-1

Block Diagram ....................................................................................................................................21-2

Functional Descriptions ........................................................................................................................21-2

Transmit or Receive Only Mode ....................................................................................................21-2

Audio Serial Interface Format ................................................................................................................21-3

IIS-Bus Format............................................................................................................................21-3

MSB (Left) Justified .....................................................................................................................21-3

Sampling Frequency and Master Clock .........................................................................................21-4

IIS-Bus Interface Special Registers .......................................................................................................21-5

IIS Control (IISCON) Register ........................................................................................................21-5

IIS Mode Register (IISMOD) Register.............................................................................................21-6

IIS Prescaler (IISPSR) Register.....................................................................................................21-7

IIS FIFO Control (IISFCON) Register..............................................................................................21-8

IIS FIFO (IISFIFO) Register...........................................................................................................21-8

Chapter 22 SPI Interface

Overview.............................................................................................................................................22-1

Features.....................................................................................................................................22-1

Block Diagram ............................................................................................................................22-2

SPI Operation .............................................................................................................................22-3

SPI Special Registers..........................................................................................................................22-7

SPI Control Register....................................................................................................................22-7

SPI Status Register .....................................................................................................................22-8

SPI Pin Control Register ..............................................................................................................22-9

xvi S3C2410A MICROPROCESSOR

Table of Contents (Continued)

Chapter 23 BUS Priorities

Overview.............................................................................................................................................23-1

Bus Priority Map .........................................................................................................................23-1

Chapter 24 Electrical Data

Absolute Maximum Ratings ..................................................................................................................24-1

Recommended Operating Conditions .....................................................................................................24-1

D.C. Electrical Characteristics ..............................................................................................................24-2

A.C. Electrical Characteristics ..............................................................................................................24-4

Chapter 25 Mechanical Data

Package Dimensions...........................................................................................................................25-1

S3C2410A MICROPROCESSOR xvii

Table of Contents (Continued)

Appendix 1- ARM920T Introduction

Abuot the Introduction ..........................................................................................................................1-1

Processor Functional Block Diagram.....................................................................................................1-2

Appendix 2- Programmer's Model

About rhe Programmer's Model .............................................................................................................2-1

About rhe ARM9TDMI Programmer's Model ...........................................................................................2-2

Data Abort Model ........................................................................................................................2-2

Instruction Set Extension Spaces .................................................................................................2-3

Cp15 Register Map Summary...............................................................................................................2-4

Accessing Cp15 Registers ...........................................................................................................2-5

Register 0: ID Code Register ........................................................................................................2-7

Register 0: Cache Type Register...................................................................................................2-8

Register 1: Control Register..........................................................................................................2-10

Register 2: Translation Table Base (TTB) Register..........................................................................2-12

Register 3: Domain Access Control Register..................................................................................2-13

Register 4: Reserved....................................................................................................................2-14

Register 5: Fault Status Registers ................................................................................................2-14

Register 6: Fault Address Register................................................................................................2-15

Register 7: Cache Operations.......................................................................................................2-15

Register 8: TLB Operations ..........................................................................................................2-18

Register 9: Cache Lock Down Register..........................................................................................2-19

Register 10: TLB Lock Down Register ...........................................................................................2-21

Registers 11-12 & 14: Reserved ....................................................................................................2-22

Register 13: Process ID...............................................................................................................2-22

Register 15: Test Configuration Register........................................................................................2-24

Appendix 3- MMU

About the MMU...................................................................................................................................3-1

Access Permissions And Domains ...............................................................................................3-1

Translated Entries .......................................................................................................................3-2

Mmu Program Accessible Registers .....................................................................................................3-3

Address Translation .............................................................................................................................3-4

Hardware Translation Process ..............................................................................................................3-6

Translation Table Base.................................................................................................................3-6

Level One Fetch ..........................................................................................................................3-7

Level One Descriptor............................................................................................................................3-8

Section Descriptor ...............................................................................................................................3-9

Coarse Page Table Descriptor ..............................................................................................................3-9

Fine Page Table Descriptor ..................................................................................................................3-9

Translating Section References .............................................................................................................3-10

xviii S3C2410A MICROPROCESSOR

Table of Contents (Concluded)

Appendix 3- MMU (Continued)

Level Two Descriptor ............................................................................................................................3-11

Translating Large Page References .......................................................................................................3-12

Translating Small Page References.......................................................................................................3-14

Translating Tiny Page References .........................................................................................................3-15

Sub-Pages..........................................................................................................................................3-17

Mmu Faults and CPU Aborts ................................................................................................................3-17

Fault Address and Fault Status Registers ..............................................................................................3-18

Fault Status................................................................................................................................3-18

Domain Access Control .......................................................................................................................3-19

Fault Checking Sequence....................................................................................................................3-21

Alignment Fault ...........................................................................................................................3-22

Translation Fault..........................................................................................................................3-22

Domain Fault ..............................................................................................................................3-22

Permission Fault.........................................................................................................................3-23

External Aborts...................................................................................................................................3-24

Interaction of the MMU and Caches .......................................................................................................3-25

Enabling the MMU.......................................................................................................................3-25

Disabling the MMU ......................................................................................................................3-25

Appendix 4- Caches, Write Buffer

About the Caches and Write Buffer .......................................................................................................4-1

Instruction Cache ................................................................................................................................4-2

Instruction Cache Enable/Disable..................................................................................................4-3

Instruction Cache Operation .........................................................................................................4-3

Instruction Cache Replacement Algorithm......................................................................................4-4

Instruction Cache Lockdown .........................................................................................................4-4

Data Cache and Write Buffer ................................................................................................................4-5

Data Cache and Write Buffer Enable/Disable..................................................................................4-6

Data Cache and Write Buffer Operation .........................................................................................4-6

Data Cache Replacement Algorithm ..............................................................................................4-8

Swap Instructions........................................................................................................................4-8

Data Cache Organization .............................................................................................................4-9

Data Cache Lockdown.................................................................................................................4-9

Cache Coherence................................................................................................................................4-10

Cache Cleaning when Lockdown is in Use .............................................................................................4-12

Implementation Notes ..........................................................................................................................4-12

Physical Address TAG RAM ................................................................................................................4-12

Appendix 5- Clock Modes

Overview.............................................................................................................................................5-1

Fastbus Mode .....................................................................................................................................5-2

Synchronous Mode..............................................................................................................................5-2

Asynchronous Mode ............................................................................................................................5-3

S3C2410A MICROPROCESSOR xix

List of Figures

Figure Title Page Number Number

1-1 S3C2410A Block Diagram ....................................................................................1-5

1-2 S3C2410A Pin Assignments (272-FBGA) ..............................................................1-6

2-1 Big-Endian Addresses of Bytes within Words .........................................................2-2

2-2 Little-Endian Addresses of Bytes within Words ......................................................2-2

2-3 Register Organization in ARM State......................................................................2-4

2-4 Register Organization in THUMB state..................................................................2-5

2-5 Mapping of THUMB State Registers onto ARM State Registers ...............................2-6

2-6 Program Status Register Formats .........................................................................2-7

3-1 ARM Instruction Set Format .................................................................................3-1

3-2 Branch and Exchange Instructions........................................................................3-5

3-3 Branch Instructions ..............................................................................................3-7

3-4 Data Processing Instructions................................................................................3-9

3-5 ARM Shift Operations ..........................................................................................3-12

3-6 Logical Shift Left ..................................................................................................3-12

3-7 Logical Shift Right ...............................................................................................3-13

3-8 Arithmetic Shift Right...........................................................................................3-13

3-9 Rotate Right ........................................................................................................3-14

3-10 Rotate Right Extended .........................................................................................3-14

3-11 PSR Transfer ......................................................................................................3-19

3-12 Multiply Instructions .............................................................................................3-22

3-13 Multiply Long Instructions .....................................................................................3-25

3-14 Single Data Transfer Instructions ...........................................................................3-28

3-15 Little-Endian Offset Addressing .............................................................................3-30

3-16 Halfword and Signed Data Transfer with Register Offset ...........................................3-34

3-17 Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing.............3-35

3-18 Block Dat a Transfer Instructions ...........................................................................3-40

3-19 Post-Increment Addressing ..................................................................................3-41

3-20 Pre-Increment Addressing....................................................................................3-42

3-21 Post-Decrement Addressing .................................................................................3-42

3-22 Pre-Decrement Addressing...................................................................................3-43

3-23 Swap Instruction..................................................................................................3-47

3-24 Software Interrupt Instruction ................................................................................3-49

3-25 Coprocessor Data Operation Instruction.................................................................3-51

3-26 Coprocessor Data Transfer Instructions .................................................................3-53

3-27 Coprocessor Register Transfer Instructions ............................................................3-56

3-28 Undefined Instruction ...........................................................................................3-58

S3C2410A MICROPROCESSOR xxi

List of Figures (Continued)

Figure Title Page Number Number

4-1 THUMB Instruction Set Formats ...........................................................................4-2

4-2 Format 1.............................................................................................................4-5

4-3 Format 2.............................................................................................................4-7

4-4 Format 3.............................................................................................................4-9

4-5 Format 4.............................................................................................................4-11

4-6 Format 5.............................................................................................................4-13

4-7 Format 6.............................................................................................................4-16

4-8 Format 7.............................................................................................................4-18

4-9 Format 8.............................................................................................................4-20

4-10 Format 9.............................................................................................................4-22

4-11 Format 10 ...........................................................................................................4-24

4-12 Format 11 ...........................................................................................................4-26

4-13 Format 12 ...........................................................................................................4-28

4-14 Format 13 ...........................................................................................................4-30

4-15 Format 14 ...........................................................................................................4-31

4-16 Format 15 ...........................................................................................................4-33

4-17 Format 16 ...........................................................................................................4-34

4-18 Format 17 ...........................................................................................................4-36

4-19 Format 18 ...........................................................................................................4-37

4-20 Format 19 ...........................................................................................................4-38

5-1 S3C2410A Memory Map after Reset .....................................................................5-2

5-2 S3C2410A External nWAIT Timing Diagram (Tacc = 4)...........................................5-5

5-3 S3C2410A nXBREQ/nXBACK Timing Diagram .......................................................5-6

5-4 Memory Interface with 8-bit ROM..........................................................................5-7

5-5 Memory Interface with 8-bit ROM × 2....................................................................5-7

5-6 Memory Interface with 8-bit ROM × 4....................................................................5-8

5-7 Memory Interface with 16-bit ROM ........................................................................5-8

5-8 Memory Interface with 16-bit SRAM ......................................................................5-9

5-9 Memory Interface with 16-bit SRAM × 2.................................................................5-9

5-10 Memory Interface with 16-bit SDRAM(8MB: 1Mb × 16 × 4banks).............................5-10

5-11 Memory Interface with 16-bit SDRAM (16MB: 1Mb × 16 × 4banks × 2ea) .................5-10

5-12 S3C2410A nGCS Timing Diagram .........................................................................5-11

5-13 S3C2410A SDRAM Timing Diagram ......................................................................5-12

xxii S3C2410A MICROPROCESSOR

List of Figures (Continued)

Figure Title Page Number Number

6-1 NAND Flash Controller Block Diagram...................................................................6-2

6-2 NAND Flash Operation Scheme............................................................................6-2

6-3 TACLS = 0, TWRPH0 = 1, TWRPH1 = 0 ...............................................................6-3

6-4 NAND Flash Memory Mapping..............................................................................6-5

7-1 Clock Generator Block Diagram ............................................................................7-3

7-2 PLL (Phase-Locked Loop) Block Diagram ..............................................................7-5

7-3 Main Oscillator Circuit Examples ..........................................................................7-5

7-4 Power-On Reset Sequence (when the external clock source is a crystal oscillator) ...7-6

7-5 Changing Slow Clock by Setting PMS Value..........................................................7-7

7-6 Changing CLKDIVN Register Value.......................................................................7-8

7-7 The Clock Distribution Block Diagram....................................................................7-9

7-8 Power Management State Diagram.......................................................................7-10

7-9 Issuing Exit_from_Slow_mode Command in PLL on State.......................................7-12

7-10 Issuing Exit_from_Slow_mode Command After Lock Time.......................................7-12

7-11 Issuing Exit_from_Slow_mode Command and the Instant PLL_on

Command Simultaneously....................................................................................7-13

7-12 Power_OFF Mode ...............................................................................................7-16

8-1 Basic DMA Timing Diagram..................................................................................8-3

8-2 Demand/Handshake Mode Comparison.................................................................8-4

8-3 Burst 4 Transfer Size ...........................................................................................8-5

8-4 Single service in Demand Mode with Unit Transfer Size...........................................8-6

8-5 Single service in Handshake Mode with Unit Transfer Size......................................8-6

8-6 Whole service in Handshake Mode with Unit Transfer Size ......................................8-6

10-1 16-bit PWM Timer Block Diagram.........................................................................10-2

10-2 Timer Operations.................................................................................................10-3

10-3 Example of Double Buffering Function ...................................................................10-4

10-4 Example of a Timer Operation...............................................................................10-6

10-5 Example of PWM ................................................................................................10-7

10-6 Inverter On/Off.....................................................................................................10-8

10-7 The Wave form when a Dead Zone Feature is Enabled............................................10-9

10-8 Timer4 DMA Mode Operation................................................................................10-10

11-1 UART Block Diagram (with FIFO) ..........................................................................11-2

11-2 UART AFC Interface............................................................................................11-4

11-3 UART Receiving 4 Characters with 1 Error .............................................................11-6

11-4 IrDA Function Block Diagram................................................................................11-8

11-5 Serial I/O Frame Timing Diagram (Normal UART) ....................................................11-9

11-6 Infra-Red Transmit Mode Frame Timing Diagram.....................................................11-9

11-7 Infra-Red Receive Mode Frame Timing Diagram ......................................................11-9

11-8 nCTS and Delta CTS Timing Diagram....................................................................11-18

12-1 USB Host Controller Block Diagram......................................................................12-1

13-1 USB Device Controller Block Diagram ...................................................................13-2

S3C2410A MICROPROCESSOR xxiii

List of Figures (Continued)

Figure Title Page Number Number

14-1 Interrupt Process Diagram ....................................................................................14-1

14-2 Priority Generating Block .....................................................................................14-4

15-1 LCD Controller Block Diagram ..............................................................................15-3

15-2 Monochrome Display Types (STN)........................................................................15-11

15-3 Color Display Types (STN) ...................................................................................15-12

15-4 8-bit Single Scan Display Type STN LCD Timing....................................................15-14

15-5 16BPP Display Types (TFT) .................................................................................15-21

15-6 TFT LCD Timing Example.....................................................................................15-22

15-7 Example of Scrolling in Virtual Display (Single Scan) ..............................................15-24

15-8 Example of PWREN Function (PWREN = 1, INVPWREN = 0) ................................15-25

16-1 ADC and Touch Screen Interface Block Diagram....................................................16-2

16-2 Example of ADC and Touch Screen Interface .........................................................16-3

16-3 Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode.........................16-6

17-1 Real Time Clock Block Diagram............................................................................17-2

17-2 Main Oscillator Circuit Example ............................................................................17-4

18-1 Watchdog Timer Block Diagram............................................................................18-2

19-1 Block Diagram ....................................................................................................19-2

20-1 IIC-Bus Block Diagram .........................................................................................20-2

20-2 Start and Stop Condition......................................................................................20-3

20-3 IIC-Bus Interface Data Format...............................................................................20-4

20-4 Data Transfer on the IIC-Bus.................................................................................20-5

20-5 Acknowledge on the IIC-Bus.................................................................................20-5

20-8 Operations for Slave/Transmitter Mode ..................................................................20-9

20-9 Operations for Slave/Receiver Mode ......................................................................20-10

21-1 IIS-Bus Block Diagram .........................................................................................21-2

21-2 IIS-Bus and MSB (Left)-justified Data Interface Formats ..........................................21-4

22-1 SPI Block Diagram..............................................................................................22-2

22-2 SPI Transfer Format .............................................................................................22-4

24-1 XTIpll Clock Timing ..............................................................................................24-4

24-2 EXTCLK Clock Input Timing ..................................................................................24-4

24-3 EXTCLK/HCLK in case that EXTCLK is used without the PLL..................................24-4

24-4 HCLK/CLKOUT/SCLK in case that EXTCLK is used ...............................................24-5

24-5 Manual Reset Input Timing...................................................................................24-5

24-6 Power-On Oscillation Setting Timing .....................................................................24-6

24-7 Power_OFF Mode Return Oscillation Setting Timing ...............................................24-7

xxiv S3C2410A MICROPROCESSOR

List of Figures (Continued)

Figure Title Page Number Number

24-8 ROM/SRAM Burst READ Timing(I) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0,

Tcah = 0, PMC = 0, ST = 0, DW = 16-bit)..............................................................24-8

24-9 ROM/SRAM Burst READ Timing(II) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0,

Tcah = 0, PMC = 0, ST = 1, DW = 16-bit)..............................................................24-9

24-10 External Bus Request in ROM/SRAM Cycle (Tacs = 0, Tcos = 0, Tacc = 8,

Tcoh = 0, Tcah = 0, PMC = 0, ST = 0) ..................................................................24-10

24-11 ROM/SRAM READ Timing (I) (Tacs = 2,Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2,

PMC = 0, ST = 0) ................................................................................................24-11

24-12 ROM/SRAM READ Timing (II) (Tacs = 2, Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2,

PMC = 0, ST = 1) ................................................................................................24-12

24-13 ROM/SRAM WRITE Timing (I) (Tacs = 2,Tcos = 2,Tacc = 4,Tcoh = 2, Tcah = 2,

PMC = 0, ST = 0.................................................................................................24-13

24-14 ROM/SRAM WRITE Timing (II) (Tacs = 2, Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2,

PMC = 0, ST = 1) ................................................................................................24-14

24-15 External nWAIT READ Timing (Tacs = 1, Tcos = 1, Tacc = 4, Tcoh = 0, Tcah = 1,

PMC = 0, ST = 0) ................................................................................................24-15

24-16 External nWAIT WRITE Timing (Tacs = 0, Tcos = 0, Tacc = 4, Tcoh = 0, Tcah = 0,

PMC = 0, ST = 0) ................................................................................................24-15

24-17 Masked-ROM Single READ Timing

(Tacs = 2, Tcos = 2, Tacc = 8, PMC = 01/10/11)....................................................24-16

24-18 Masked-ROM Consecutive READ Timing (Tacs = 0, Tcos = 0, Tacc = 3, Tpac = 2,

PMC = 01/10/11) .................................................................................................24-16

24-19 SDRAM Single Burst READ Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit)...........24-17

24-20 External Bus Request in SDRAM Timing (Trp = 2, Trcd = 2, Tcl = 2) ........................24-18

24-21 SDRAM MRS Timing...........................................................................................24-19

24-22 SDRAM Single READ Timing(I) (Trp = 2, Trcd = 2, Tcl = 2) .....................................24-20

24-23 SDRAM Single READ Timing(II) (Trp = 2, Trcd = 2, Tcl = 3).....................................24-21

24-24 SDRAM Auto Refresh Timing (Trp = 2, Trc = 4)......................................................24-22

24-25 SDRAM Page Hit-Miss READ Timing (Trp = 2, Trcd = 2, Tcl = 2).............................24-23

24-26 SDRAM Self Refresh Timing (Trp = 2, Trc = 4) .......................................................24-24

24-27 SDRAM Single Write Timing (Trp = 2, Trcd = 2) .....................................................24-25

24-28 SDRAM Page Hit-Miss Write Timing (Trp = 2, Trcd = 2, Tcl = 2) ..............................24-26

24-29 External DMA Timing (Handshake, Single transfer) .................................................24-27

24-30 TFT LCD Controller Timing....................................................................................24-27

24-31 IIS Interface Timing..............................................................................................24-28

24-32 IIC Interface Timing..............................................................................................24-28

24-33 SD/MMC Interface Timing.....................................................................................24-29

24-34 SPI Interface Timing (CPHA = 1, CPOL = 1) ..........................................................24-29

24-35 NAND Flash Address/Command Timing ................................................................24-30

24-36 NAND Flash Timing.............................................................................................24-30

25-1 272-FBGA-1414 Package Dimension 1 (Top View) .................................................25-1

25-2 272-FBGA-1414 Package Dimension 2 (Bottom View)............................................25-2

S3C2410A MICROPROCESSOR xxv

List of Figures (Concluded)

Figure Title Page Number Number

1-1 ARM920T Functional Block Diagram.....................................................................1-2

2-1 CP15 MRC and MCR Bit Pattern ..........................................................................2-5

2-2 Register 7 MVA Format .......................................................................................2-17

2-3 Register 7 Index Format.......................................................................................2-17

2-4 Register 8 MVA Format .......................................................................................2-18

2-5 Register 9...........................................................................................................2-20

2-6 Register 10.........................................................................................................2-21

2-7 Register 13.........................................................................................................2-22

2-8 Address Mapping Using CP15 Register 13.............................................................2-23

3-1 Translating Page Tables.......................................................................................3-5

3-2 Translation Table Base Register............................................................................3-6

3-3 Accessing the Translation Table Level One Descriptors ...........................................3-7

3-4 Level One Descriptors..........................................................................................3-8

3-5 Section Translation ..............................................................................................3-10

3-6 Page Table Entry (Level One Descriptor)................................................................3-11

3-7 Large Page Translation from a Coarse Page Table ..................................................3-13

3-8 Small Page Translation from a Coarse Page Table..................................................3-14

3-9 Tiny Page Translation from a Fine Page Table ........................................................3-16

3-10 Domain Access Control Register Format...............................................................3-19

3-11 Sequence for Checking Faults..............................................................................3-21

xxvi S3C2410A MICROPROCESSOR

List of Tables

Table Title Page Number Number

1-1 272-Pin FBGA Pin Assignments – Pin Number Order.............................................1-7

1-2 272-Pin FBGA Pin Assignments ...........................................................................1-10

1-3 S3C2410A Signal Descriptions .............................................................................1-20

1-4 S3C2410A Special Registers ................................................................................1-26

2-1 PSR Mode Bit Values..........................................................................................2-9

2-2 Exception Entry/Exit............................................................................................2-11

2-3 Exception Vectors...............................................................................................2-13

3-1 The ARM Instruction Set ......................................................................................3-2

3-2 Condition Code Summary .....................................................................................3-4

3-3 ARM Data Processing Instructions ........................................................................3-11

3-4 Incremental Cycle Times......................................................................................3-16

3-5 Assembler Syntax Descriptions............................................................................3-27

3-6 Addressing Mode Names .....................................................................................3-45

4-1 THUMB Instruction Set Opcodes ..........................................................................4-3

4-2 Summary of Format 1 Instructions ........................................................................4-5

4-3 Summary of Format 2 Instructions ........................................................................4-7

4-4 Summary of Format 3 Instructions ........................................................................4-9

4-5 Summary of Format 4 Instructions ........................................................................4-11

4-6 Summary of Format 5 Instructions ........................................................................4-13

4-7 Summary of PC-Relative Load Instruction ..............................................................4-16

4-8 Summary of Format 7 Instructions ........................................................................4-19

4-9 Summary of format 8 instructions ..........................................................................4-20

4-10 Summary of Format 9 Instructions ........................................................................4-23

4-11 Halfword Data Transfer Instructions .......................................................................4-24

4-12 SP-Relative Load/Store Instructions ......................................................................4-26

4-13 Load Address......................................................................................................4-28

4-14 The ADD SP Instruction.......................................................................................4-30

4-15 PUSH and POP Instructions .................................................................................4-31

4-16 The Multiple Load/Store Instructions ......................................................................4-33

4-17 The Conditional Branch Instructions ......................................................................4-34

4-18 The SWI Instruction.............................................................................................4-36

4-19 Summary of Branch Instruction .............................................................................4-37

4-20 The BL Instruction ...............................................................................................4-39

5-1 Bank 6/7 Addresses ............................................................................................5-2

5-2 SDRAM Bank Address Configuration.....................................................................5-4

7-1 Clock Source Selection at Boot-Up.......................................................................7-2

7-2 Clock and Power State in Each Power Mode .........................................................7-10

7-3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock..................................7-11

S3C2410A MICROPROCESSOR xxvii

List of Tables (Continued)

Table Title Page Number Number

8-1 DMA Request Sources for Each Channel...............................................................8-2

8-2 DMA Controller Module Signal Timing Constants ....................................................8-3

9-1 S3C2410A Port Configuration ...............................................................................9-2

11-1 Interrupts in Connection with FIFO ........................................................................11-5

12-1 OHCI Registers for USB Host Controller ................................................................12-2

15-1 Relation Between VCLK and CLKVAL (STN, HCLK = 60 MHz) ................................15-5

15-2 Dither Duty Cycle Examples .................................................................................15-7

15-3 Relation Between VCLK and CLKVAL (TFT, HCLK = 60 MHz).................................15-15

15-4 5:6:5 Format .......................................................................................................15-20

15-5 5:5:5:1 Format ....................................................................................................15-20

15-6 MV Value for Each Display Mode..........................................................................15-39

16-1 Condition of Touch Screen Panel Pads in Separate X/Y Position Conversion Mode ....16-4

16-2 Condition of Touch Screen Panel Pads in Auto (Sequential) X/Y Position

Conversion Mode.................................................................................................16-5

16-3 Condition of Touch Screen Panel Pads in Waiting for Interrupt Mode. .......................16-5

21-1 CODEC clock (CODECLK = 256 or 384fs) .............................................................21-4

21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs)................................21-5

24-1 Absolute Maximum Rating ...................................................................................24-1

24-2 Recommended Operating Conditions .....................................................................24-1

24-3 Normal I/O PAD DC Electrical Characteristics........................................................24-2

24-4 USB DC Electrical Characteristics........................................................................24-3

24-5 S3C2410A Power Supply Voltage and Current .......................................................24-3

24-6 Clock Timing Constants.......................................................................................24-31

24-7 ROM/SRAM Bus Timing Constants.......................................................................24-32

24-8 Memory Interface Timing Constants (3.3V).............................................................24-32

24-9 External Bus Request Timing Constants................................................................24-33

24-10 DMA Controller Module Signal Timing Constants ....................................................24-33

24-11 TFT LCD Controller Module Signal Timing Constants ..............................................24-34

24-12 IIS Controller Module Signal Timing Constants .......................................................24-34

24-13 IIC BUS Controller Module Signal Timing ...............................................................24-35

24-14 SD/MMC Interface Transmit/Receive Timing Constants...........................................24-35

24-15 SPI Interface Transmit/Receive Timing Constants...................................................24-36

24-16 USB Electrical Specifications ...............................................................................24-36

24-17 USB Full Speed Output Buffer Electrical Characteristics .........................................24-37

24-18 USB Low Speed Output Buffer Electrical Characteristics .........................................24-37

24-19 NAND Flash Interface Timing Constants................................................................24-38

xxviii S3C2410A MICROPROCESSOR

List of Table (Concluded)

Figure Title Page Number Number

2-1 ARM9TDMI Im plementation Option........................................................................2-2

2-2 CP15 Register Map .............................................................................................2-4

2-3 CP15 Abbreviations .............................................................................................2-5

2-4 Address Types in ARM920 ...................................................................................2-6

2-5 Register 0: ID Code .............................................................................................2-7

2-6 Cache Type Register Format ................................................................................2-8

2-7 Cache Size Encoding ..........................................................................................2-9

2-8 Cache associativity encoding................................................................................2-9

2-9 Line Length Encoding ..........................................................................................2-10

2-10 Control Register 1-bit Functions............................................................................2-11

2-11 Clocking Modes ..................................................................................................2-11

2-12 Register 2: Translation Table Base........................................................................2-12

2-13 Register 3: Domain Access Control.......................................................................2-13

2-14 Fault Status Register ...........................................................................................2-14

2-15 Function Descriptions Register 7..........................................................................2-15

2-16 Cache Operations Register 7................................................................................2-16

2-17 TLB Operations Register 8...................................................................................2-18

2-18 Accessing the Cache Lock Down Register 9..........................................................2-20

2-19 Accessing the TLB Lock Down Register 10............................................................2-21

3-1 CP15 Register Functions .....................................................................................3-3

3-2 Interpreting Level One Descriptor Bits [1:0] ............................................................3-8

3-3 Interpreting Page Table Entry Bits 1:0...................................................................3-11

3-4 Priority Encoding of Fault Status ...........................................................................3-18

3-5 Interpreting Access Control Bits in Domain Access Control Register ........................3-19

3-6 Interpreting Access Permission (AP) Bits..............................................................3-20

4-1 Data Cache and Write Buffer Configuration.............................................................4-7

5-1 ARM920T Clocking ..............................................................................................5-1

5-2 Synchronous Clocking Mode................................................................................5-2

5-3 Switching from FCLK to BCLK in Synchronous Mode .............................................5-2

5-4 Asynchronous Clocking Mode ..............................................................................5-3

5-5 Switching from FCLK to BCLK in Asynchronous Mode............................................5-3

S3C2410A MICROPROCESSOR xxix

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