Page 1
21-S3-C2410A-032004
USER'S MANUAL
S3C2410A – 200MHz & 266MHz
32-Bit RISC
Microprocessor
Revision 1.0
Page 2
S3C2410A
200MHz & 266MHz
32-BIT RISC
MICROPROCESSOR
USER'S MANUAL
Revision 1.0
Page 3
Important Notice
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checked and is believed to be entirely accurate at the
time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
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products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
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semiconductor devices described herein any license
under the patent rights of Samsung or others.
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product or circuit and specifically disclaims any and
all liability, including without limitation any
consequential or incidental damages.
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S3C2410A – 200MHz & 266MHz 32-Bit RISC Microprocessor
User's Manual, Revision 1.0 (March 2004)
Publication Number: 21-S3-C2410A-032004
2004 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any
form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written
consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-9001
certification (BSI Certificate No. FM24653). All semiconductor products are designed
and manufactured in accordance with the highest quality standards and objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung- Eup
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Home Page: http://www.samsung.com
Printed in the Republic of Korea
Page 4
Table of Contents
Chapter 1 Product Overview
Introduction.........................................................................................................................................1-1
Features.............................................................................................................................................1-2
Block Diagram ....................................................................................................................................1-5
Pin Assignments .................................................................................................................................1-6
Signal Descriptions ......................................................................................................................1-20
S3C2410A Special Registers ........................................................................................................1-26
Chapter 2 Programmer's model
Overview.............................................................................................................................................2-1
Processor Operating States .........................................................................................................2-1
Switching State...........................................................................................................................2-1
Memory Formats .........................................................................................................................2-1
Big-Endian Format .......................................................................................................................2-2
Little-Endian Format ....................................................................................................................2-2
Instruction Length........................................................................................................................2-2
Operating Modes.........................................................................................................................2-3
Registers....................................................................................................................................2-3
The Program Status Registers......................................................................................................2-7
Exceptions .................................................................................................................................2-10
Interrupt Latencies.......................................................................................................................2-15
Reset .........................................................................................................................................2-15
S3C2410A MICROPROCESSOR iii
Page 5
Table of Contents (Continued)
Chapter 3 ARM Instruction set
Instruction Set Summay .......................................................................................................................3-1
Format Summary ........................................................................................................................3-1
Instruction Summary ....................................................................................................................3-2
The Condition Field ..............................................................................................................................3-4
Branch and Exchange (BX) ...................................................................................................................3-5
Instruction Cycle Times ................................................................................................................3-5
Assembler Syntax.......................................................................................................................3-5
Using R15 as an Operand ............................................................................................................3-5
Branch and Branch with Link (B, Bl) ......................................................................................................3-7
The Link Bit ................................................................................................................................3-7
Instruction Cycle Times ................................................................................................................3-7
Assembler Syntax.......................................................................................................................3-8
Data Processing..................................................................................................................................3-9
CPSR Flags ................................................................................................................................3-11
Shifts .........................................................................................................................................3-12
Immediate Operand Rotates .........................................................................................................3-16
Writing to R15 .............................................................................................................................3-16
Using R15 as an Operandy ...........................................................................................................3-16
TEQ, TST, CMP and CMN Opcodes ..............................................................................................3-16
Instruction Cycle Times ................................................................................................................3-16
Assembler Syntax.......................................................................................................................3-17
Examples ...................................................................................................................................3-17
PSR Transfer (MRS, MSR) ...................................................................................................................3-18
Operand Restrictions ...................................................................................................................3-18
Reserved Bits..............................................................................................................................3-20
Examples ...................................................................................................................................3-20
Instruction Cycle Times ................................................................................................................3-20
Assembly Syntax........................................................................................................................3-21
Examples ...................................................................................................................................3-21
Multiply and Multiply-Accumulate (MUL, MLA) .......................................................................................3-22
CPSR Flags ................................................................................................................................3-24
Instruction Cycle Times ................................................................................................................3-24
Assembler Syntax.......................................................................................................................3-24
Examples ...................................................................................................................................3-24
Multiply Long and Multiply-Accumulate Long (MULL, MLAL)....................................................................3-25
Operand Restrictions ...................................................................................................................3-26
CPSR Flags ................................................................................................................................3-26
Instruction Cycle Times ................................................................................................................3-26
Assembler Syntax.......................................................................................................................3-27
Examples ...................................................................................................................................3-27
iv S3C2410A MICROPROCESSOR
Page 6
Table of Contents (Continued)
Chapter 3 ARM Instruction set (Continued)
Single Data Transfer (LDR, STR) ...........................................................................................................3-28
Offsets And Auto-Indexing ............................................................................................................3-29
Shifted Register Offset .................................................................................................................3-29
Bytes and Words ........................................................................................................................3-29
Use of R15..................................................................................................................................3-31
Example:....................................................................................................................................3-31
Data Aborts ................................................................................................................................3-31
Instruction Cycle Times ................................................................................................................3-31
Assembler Syntax.......................................................................................................................3-32
Examples ...................................................................................................................................3-33
Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH) ...........................................................3-34
Offsets and Auto-Indexing ............................................................................................................3-35
Halfword Load and Stores .............................................................................................................3-36
Use of R15..................................................................................................................................3-37
Data Aborts ................................................................................................................................3-37
Instruction Cycle Times ................................................................................................................3-37
Assembler Syntax.......................................................................................................................3-38
Examples ...................................................................................................................................3-39
Block Data Transfer (LDM, STM)...........................................................................................................3-40
The Register List.........................................................................................................................3-40
Addressing Modes .......................................................................................................................3-41
Address Alignment ......................................................................................................................3-41
Use of the S Bit...........................................................................................................................3-43
Use of R15 as the Base ...............................................................................................................3-43
Inclusion of the Base in the Register List.......................................................................................3-44
Data Aborts ................................................................................................................................3-44
Instruction Cycle Times ................................................................................................................3-44
Assembler Syntax.......................................................................................................................3-45
Examples ...................................................................................................................................3-46
Single Data Swap (SWP) .....................................................................................................................3-47
Bytes and Words ........................................................................................................................3-47
Use of R15..................................................................................................................................3-48
Data Aborts ................................................................................................................................3-48
Instruction Cycle Times ................................................................................................................3-48
Assembler Syntax.......................................................................................................................3-48
Software Interrupt (SWI).......................................................................................................................3-49
Return from the Supervisor ...........................................................................................................3-49
Comment Field............................................................................................................................3-49
Instruction Cycle Times ................................................................................................................3-49
Assembler Syntax.......................................................................................................................3-50
Coprocessor Data Operations (CDP) .....................................................................................................3-51
Coprocessor Instructions ..............................................................................................................3-51
Instruction Cycle Times ................................................................................................................3-52
Examples ...................................................................................................................................3-52
S3C2410A MICROPROCESSOR v
Page 7
Table of Contents (Continued)
Chapter 3 ARM Instruction set (Continued)
Coprocessor Data Transfers (LDC, STC) ................................................................................................3-53
The Coprocessor Fields ...............................................................................................................3-54
Addressing Modes .......................................................................................................................3-54
Address Alignment ......................................................................................................................3-54
Data Aborts ................................................................................................................................3-54
Assembler Syntax.......................................................................................................................3-55
Examples ...................................................................................................................................3-55
Coprocessor Register Transfers (MRC, MCR).................................................................................3-56
The Coprocessor Fields ...............................................................................................................3-56
Transfers to R15 ..........................................................................................................................3-57
Transfers from R15 ......................................................................................................................3-57
Instruction Cycle Times ................................................................................................................3-57
Assembler Syntax.......................................................................................................................3-57
Examples ...................................................................................................................................3-57
Undefined Instruction ...................................................................................................................3-58
Instruction Cycle Times ................................................................................................................3-58
Assembler Syntax.......................................................................................................................3-58
Instruction Set Examples .............................................................................................................3-59
Using the Conditional Instructions .................................................................................................3-59
Pseudo-Random Binary Sequence Generator.................................................................................3-61
Multiplication by Constant Using the Barrel Shifter..........................................................................3-61
Loading a Word from an Unknown Alignment .................................................................................3-63
Chapter 4 Thumb Instruction Set
Thumb Instruction Set Format ...............................................................................................................4-1
Format Summary ........................................................................................................................4-2
Opcode Summary .......................................................................................................................4-3
Format 1: Move Shifted Register...........................................................................................................4-5
Operation....................................................................................................................................4-5
Instruction Cycle Times ................................................................................................................4-6
Examples ...................................................................................................................................4-6
Format 2: Add/Subtract........................................................................................................................4-7
Operation....................................................................................................................................4-7
Instruction Cycle Times ................................................................................................................4-8
Examples ...................................................................................................................................4-8
Format 3: Move/Compare/Add/Subtract Immediate .................................................................................4-9
Operations..................................................................................................................................4-9
Instruction Cycle Times ................................................................................................................4-10
Examples ...................................................................................................................................4-10
Format 4: ALU Operations ....................................................................................................................4-11
Operation....................................................................................................................................4-11
Instruction Cycle Times ................................................................................................................4-12
Examples ...................................................................................................................................4-12
vi S3C2410A MICROPROCESSOR
Page 8
Table of Contents (Continued)
Chapter 4 Thumb Instruction Set (Continued)
Format 5: Hi-Register Operations/Branch Exchange...............................................................................4-13
Operation....................................................................................................................................4-13
Instruction Cycle Times ................................................................................................................4-14
The Bx Instruction .......................................................................................................................4-14
Examples ...................................................................................................................................4-15
Using R15 as an Operand ............................................................................................................4-15
Format 6: Pc-Relative Load ..................................................................................................................4-16
Operation....................................................................................................................................4-16
Instruction Cycle Times ................................................................................................................4-17
Examples ...................................................................................................................................4-17
Format 7: Load/Store with Register Offset ..............................................................................................4-18
Operation....................................................................................................................................4-19
Instruction Cycle Times ................................................................................................................4-19
Examples ...................................................................................................................................4-19
Format 8: Load/Store Sign-Extended Byte/Halfword................................................................................4-20
Operation....................................................................................................................................4-20
Instruction Cycle Times ................................................................................................................4-21
Examples ...................................................................................................................................4-21
Format 9: Load/Store With Immediate Offset ..........................................................................................4-22
Operation....................................................................................................................................4-23
Instruction Cycle Times ................................................................................................................4-23
Examples ...................................................................................................................................4-23
Format 10: Load/Store Halfword ............................................................................................................4-24
Operation....................................................................................................................................4-24
Instruction Cycle Times ................................................................................................................4-25
Examples ...................................................................................................................................4-25
Format 11: Sp-Relative Load/Store ........................................................................................................4-26
Operation....................................................................................................................................4-26
Instruction Cycle Times ................................................................................................................4-27
Examples ...................................................................................................................................4-27
Format 12: Load Address .....................................................................................................................4-28
Operation....................................................................................................................................4-28
Instruction Cycle Times ................................................................................................................4-29
Examples ...................................................................................................................................4-29
Format 13: Add Offset To Stack Pointer ................................................................................................4-30
Operation....................................................................................................................................4-30
Instruction Cycle Times ................................................................................................................4-30
Examples ...................................................................................................................................4-30
Format 14: Push/Pop Registers............................................................................................................4-31
Operation....................................................................................................................................4-31
Instruction Cycle Times ................................................................................................................4-32
Examples ...................................................................................................................................4-32
Format 15: Multiple Load/Store .............................................................................................................4-33
Operation....................................................................................................................................4-33
Instruction Cycle Times ................................................................................................................4-33
Examples ...................................................................................................................................4-33
S3C2410A MICROPROCESSOR vii
Page 9
Table of Contents (Continued)
Chapter 4 Thumb Instruction Set (Continued)
Format 16: Conditional Branch..............................................................................................................4-34
Operation....................................................................................................................................4-34
Instruction Cycle Times ................................................................................................................4-35
Examples ...................................................................................................................................4-35
Format 17: Software Interrupt ................................................................................................................4-36
Operation....................................................................................................................................4-36
Instruction Cycle Times ................................................................................................................4-36
Examples ...................................................................................................................................4-36
Format 18: Unconditional Branch ..........................................................................................................4-37
Operation....................................................................................................................................4-37
Examples ...................................................................................................................................4-37
Format 19: Long Branch With Link........................................................................................................4-38
Operation....................................................................................................................................4-38
Instruction Cycle Times ................................................................................................................4-39
Examples ...................................................................................................................................4-39
Instruction Set Examples .....................................................................................................................4-40
Multiplication by a Constant Using Shifts and Adds ........................................................................4-40
General Purpose Signed Divide .....................................................................................................4-41
Division by a Constant .................................................................................................................4-43
Chapter 5 Memory Controller
Overview.............................................................................................................................................5-1
Function Description ............................................................................................................................5-3
Bank0 Bus Width ........................................................................................................................5-3
Memory (SROM/SDRAM) Address Pin Connections .......................................................................5-3
Sdram Bank Address Pin Connection............................................................................................5-4
Nwait Pin Operation .....................................................................................................................5-5
Programmable Access Cycle .......................................................................................................5-11
Bus Width & Wait Control Register (BWSCON) .............................................................................5-13
Bank Control Register (BANKCONN: NGCS0-NGCS5)....................................................................5-15
Bank Control Register (BANKCONN: NGCS6-NGCS7)....................................................................5-16
Refresh Control Register ..............................................................................................................5-17
Banksize Register.......................................................................................................................5-18
SDRAM Mode Register Set Register (MRSR) ................................................................................5-19
viii S3C2410A MICROPROCESSOR
Page 10
Table of Contents (Continued)
Chapter 6 NAND Flash Controller
Overview.............................................................................................................................................6-1
Features.....................................................................................................................................6-1
Block Diagram ............................................................................................................................6-2
Operation Scheme.......................................................................................................................6-2
Auto Boot Mode Sequence...........................................................................................................6-3
Nand Flash Mode Configuration ....................................................................................................6-3
Nand Flash Memory Timing ..........................................................................................................6-3
Pin Configuration.........................................................................................................................6-4
Boot and Nand Flash Configurations ..............................................................................................6-4
512-Byte Ecc Parity Code Assignment Table .................................................................................6-4
Nand Flash Memory Mapping.......................................................................................................6-5
Special Function Registers ...................................................................................................................6-6
Nand Flash Configuration (NFCONF) Register................................................................................6-6
Nand Flash Command Set (NFCMD) Register ................................................................................6-7
Nand Flash Address Set (NFADDR) Register .................................................................................6-7
Nand Flash Data (NFDATA) Register.............................................................................................6-7
Nand Flash Operation Status (NFSTAT) Register ...........................................................................6-8
Nand Flash ECC (NFECC) Register ..............................................................................................6-8
Chapter 7 Clock & Power Management
Overview.............................................................................................................................................7-1
Functional Description .........................................................................................................................7-2
Clock Architecture .......................................................................................................................7-2
Clock Source Selection................................................................................................................7-2
Phase Locked Loop (PLL)............................................................................................................7-4
Clock Control Logic .....................................................................................................................7-6
Power Management.....................................................................................................................7-9
Clock Generator & Power Management Special Register ........................................................................7-19
Lock Time Count Register (LOCKTIME).........................................................................................7-19
PLL Value Selection Table ...........................................................................................................7-20
Clock Control Register (CLKCON) .................................................................................................7-21
Clock Slow Control (CLKSLOW) Register......................................................................................7-22
Clock Divider Control (CLKDIVN) Register ......................................................................................7-22
S3C2410A MICROPROCESSOR ix
Page 11
Table of Contents (Continued)
Chapter 8 DMA
Overview.............................................................................................................................................8-1
DMA Request Sources ........................................................................................................................8-2
DMA Operation ...................................................................................................................................8-2
External DMA DREQ/DACK Protocol............................................................................................8-3
Examples ...................................................................................................................................8-6
DMA Special Registers........................................................................................................................8-7
DMA Initial Source (DISRC) Register .............................................................................................8-7
DMA Initial Source Control (DISRCC) Register ...............................................................................8-7
DMA Initial Destination (DIDST) Register .......................................................................................8-8
DMA Initial Destination Control (DIDSTC) Register ..........................................................................8-8
DMA Control (DCON) Register ......................................................................................................8-9
DMA Status (DSTAT) Register......................................................................................................8-11
DMA Current Source (DCSRC) Register ........................................................................................8-11
Current Destination (DCDST) Register...........................................................................................8-12
DMA Mask Trigger (DMASKTRIG) Register....................................................................................8-13
Chapter 9 I/O Ports
Overview.............................................................................................................................................9-1
Port Control Descriptions .....................................................................................................................9-7
Port Configuration Register (GPACON-GPHCON) ...........................................................................9-7
Port Data Register (GPADAT-GPHDAT) ........................................................................................9-7
Port Pull-up Register (GPBUP-GPHUP).........................................................................................9-7
Miscellaneous Control Register.....................................................................................................9-7
External Interrupt Control Register (EXTINTN) .................................................................................9-7
Power_Off Mode and I/O Ports......................................................................................................9-7
I/O Port Control Register......................................................................................................................9-8
Port A Control Registers (GPACON/GPADAT) ...............................................................................9-8
Port B Control Registers (GPBCON, GPBDAT, and GPBUP)..........................................................9-9
Port C Control Registers (GPCCON, GPCDAT, and GPCUP)..........................................................9-10
Port D Control Registers (GPDCON, GPDDAT, and GPDUP)..........................................................9-12
Port E Control Registers (GPECON, GPEDAT, and GPEUP)..........................................................9-14
Port F Control Registers (GPFCON, GPFDAT, and GPFPU) ...........................................................9-16
Port G Control Registers (GPGCON, GPGDAT, and GPGUP).........................................................9-17
Port H Control Registers (GPHCON, GPHDAT, and GPHUP)..........................................................9-19
Miscellaneous Control Register (MISCCR).....................................................................................9-20
Dclk Control Registers (DCLKCON)...............................................................................................9-21
External Interrupt Control Register (EXTINTN) .................................................................................9-22
External Interrupt Filter Register (EINTFLTN) ..................................................................................9-25
External Interrupt Mask Register (EINTMASK)...............................................................................9-26
External Interrupt Pending Register (EINTPENDN) ..........................................................................9-27
General Status Register (GSTATUSN)...........................................................................................9-28
x S3C2410A MICROPROCESSOR
Page 12
Table of Contents (Continued)
Chapter 10 PWM Timer
Overview.............................................................................................................................................10-1
Feature.......................................................................................................................................10-1
Pwm Timer Operation ..........................................................................................................................10-3
Prescaler & Divider......................................................................................................................10-3
Basic Timer Operation .................................................................................................................10-3
Auto Reload & Double Buffering....................................................................................................10-4
Timer Initialization Using Manual Update Bit and Inverter Bit............................................................10-5
Timer Operation...........................................................................................................................10-6
Pulse Width Modulation (PWM) ....................................................................................................10-7
Output Level Control ....................................................................................................................10-8
Dead Zone Generator ...................................................................................................................10-9
Dma Request Mode .....................................................................................................................10-10
PWM Timer Control Registers ..............................................................................................................10-11
Timer Configuration Register 0 (TCFG0) .........................................................................................10-11
Timer Configuration Register 1 (TCFG1) .........................................................................................10-12
Timer Control (TCON) Register......................................................................................................10-13
Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)...................................10-15
Timer 0 Count Observation Register (TCNTO0)...............................................................................10-15
Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)...................................10-16
Timer 1 Count Observation Register (TCNTO1)...............................................................................10-16
Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)...................................10-17
Timer 2 Count Observation Register (TCNTO2)...............................................................................10-17
Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)...................................10-18
Timer 3 Count Observation Register (TCNTO3)...............................................................................10-18
Timer 4 Count Buffer Register (TCNTB4)........................................................................................10-19
Timer 4 Count Observation Register (TCNTO4)...............................................................................10-19
Chapter 11 UART
Overview.............................................................................................................................................11-1
Features.....................................................................................................................................11-1
Block Diagram ....................................................................................................................................11-2
Uart Operation.............................................................................................................................11-3
Uart Special Registers .........................................................................................................................11-10
Uart Line Control Register ............................................................................................................11-10
Uart Control Register ...................................................................................................................11-11
Uart FIFO Control Register...........................................................................................................11-13
Uart Modem Control Register........................................................................................................11-14
Uart Tx/Rx Status Register...........................................................................................................11-15
Uart Error Status Register............................................................................................................11-16
Uart FIFO Status Register ............................................................................................................11-17
Uart Modem Status Register ........................................................................................................11-18
Uart Transmit Buffer Register (Holding Register & FIFO Register).....................................................11-19
Uart Receive Buffer Register (Holding Register & FIFO Register) ......................................................11-19
Uart Baud Rate Divisor Register ....................................................................................................11-20
S3C2410A MICROPROCESSOR xi
Page 13
Table of Contents (Continued)
Chapter 12 USB Host Controller
Overview.............................................................................................................................................12-1
USB Host Controller Special Registers..........................................................................................12-2
Chapter 13 USB Device Controller
Overview.............................................................................................................................................13-1
Feature.......................................................................................................................................13-1
USB Device Controller Special Registers ...............................................................................................13-3
Function Address Register (Func_Addr_Reg) .................................................................................13-5
Power Management Register (Pwr_Reg) ........................................................................................13-6
Interrupt Register (Ep_Int_Reg/Usb_Int_Reg)..................................................................................13-7
Interrupt Enable Register (Ep_Int_En_Reg/Usb_Int_En_Reg)...........................................................13-9
Frame Number Register (Fpame_Num1_Reg/Frame_Num2_Reg) ....................................................13-10
Index Register (Index_Reg)...........................................................................................................13-11
End Point0 Control Status Register (Ep0_Csr) ...............................................................................13-12
End Point In Control Status Register (In_Csr1_Reg/In_Csr2_Reg)....................................................13-14
End Point Out Control Status Register (Out_Csr1_Reg/Out_Csr2_Reg) ............................................13-16
End Point FIFO Register (Epn_Fifo_Reg) .......................................................................................13-18
Max Packet Register (Maxp_Reg).................................................................................................13-19
End Point Out Write Count Register (Out_Fifo_Cnt1_Reg/Out_Fifo_Cnt2_Reg) .................................13-20
DMA Interface Control Register (Epn_Dma_Con)............................................................................13-21
DMA Unit Counter Register (Epn_Dma_Unit)..................................................................................13-22
DMA FIFO Counter Register (Epn_Dma_FIFO)...............................................................................13-23
DMA Total Transfer Counter Register (Epn_Dma_Ttc_L, M, H).........................................................13-24
xii S3C2410A MICROPROCESSOR
Page 14
Table of Contents (Continued)
Chapter 14 Interrupt Controller
Overview.............................................................................................................................................14-1
Interrupt Controller Operation........................................................................................................14-2
Interrupt Sources.........................................................................................................................14-3
Interrupt Priority Generating Block.................................................................................................14-4
Interrupt Priority...........................................................................................................................14-5
Interrupt Controller Special Registers .....................................................................................................14-6
Source Pending (SRCPND) Register.............................................................................................14-6
Interrupt Mode (INTMOD) Register.................................................................................................14-8
Interrupt Mask (INTMSK) Register .................................................................................................14-10
Priority Register (PRIORITY).........................................................................................................14-12
Interrupt Pending (INTPND) Register..............................................................................................14-14
Interrupt Offset (INTOFFSET) Register ...........................................................................................14-16
Sub Source Pending (SUBSRCPND) Register................................................................................14-17
Interrupt Sub Mask (INTSUBMSK) Register ...................................................................................14-18
Chapter 15 LCD Controller
Overview.............................................................................................................................................15-1
Features.....................................................................................................................................15-1
Common Features.......................................................................................................................15-2
External Interface Signal ..............................................................................................................15-2
Block Diagram ............................................................................................................................15-3
STN LCD Controller Operation ..............................................................................................................15-4
Timing Generator (TIMEGEN) .......................................................................................................15-4
Video Operation ..........................................................................................................................15-5
Dithering and Frame Rate Control .................................................................................................15-7
Memory Data Format (STN, BSWP = 0) ........................................................................................15-9
TFT LCD Controller Operation...............................................................................................................15-15
Video Operation ..........................................................................................................................15-15
Memory Data Format (TFT) ..........................................................................................................15-16
256 Palette Usage (TFT) ..............................................................................................................15-20
Samsung TFT LCD Panel (3.5″ Portrait / 256k Color /Reflective A-SI TFT LCD).................................15-23
Virtual Display (TFT/STN) .............................................................................................................15-24
LCD Power Enable (STN/TFT) .......................................................................................................15-25
LCD Controller Special Registers ..................................................................................................15-26
Frame Buffer Start Address 1 Register ..........................................................................................15-32
S3C2410A MICROPROCESSOR xiii
Page 15
Table of Contents (Continued)
Chapter 16 ADC & Touch Screen Interface
Overview.............................................................................................................................................16-1
Features.....................................................................................................................................16-1
ADC & Touch Screen Interface Operation ..............................................................................................16-2
Block Diagram ............................................................................................................................16-2
Example for Touch Screen ...........................................................................................................16-3
Function Descriptions ..................................................................................................................16-4
ADC and Touch Screen Interface Special Registers................................................................................16-7
ADC Control (ADCCON) Register ..................................................................................................16-7
ADC Touch Screen Control (ADCTSC) Register..............................................................................16-8
ADC Start Delay (ADCDLY) Register.............................................................................................16-9
ADC Conversion Data (ADCDAT0) Register....................................................................................16-10
ADC Conversion Data (ADCDAT1) Register....................................................................................16-11
Chapter 17 Real Time Clock (RTC)
Overview.............................................................................................................................................17-1
Features.....................................................................................................................................17-1
Real Time Clock Operation ...........................................................................................................17-2
Leap Year Generator....................................................................................................................17-2
Read/Write Registers ...................................................................................................................17-3
Backup Battery Operation............................................................................................................17-3
Alarm Function............................................................................................................................17-3
Tick Time Interrupt.......................................................................................................................17-3
Round Reset Function .................................................................................................................17-3
32.768kHz X-Tal Connection Example..........................................................................................17-4
Real Time Clock Special Registers .......................................................................................................17-5
Real Time Clock Control (RTCCON) Register .................................................................................17-5
Tick Time Count (TICNT) Register .................................................................................................17-5
RTC Alarm Control (RTCALM) Register..........................................................................................17-6
Alarm Second Data (ALMSEC) Register ........................................................................................17-7
Alarm Min Data (ALMMIN) Register...............................................................................................17-7
Alarm Hour Data (ALMHOUR) Register..........................................................................................17-7
Alarm Date Data (ALMDATE) Register ..........................................................................................17-8
Alarm Mon Data (ALMMON) Register ............................................................................................17-8
Alarm Year Data (ALMYEAR) Register ..........................................................................................17-8
RTC Round Reset (RTCRST) Register...........................................................................................17-9
BCD Second (BCDSEC) Register .................................................................................................17-9
BCD Minute (BCDMIN) Register....................................................................................................17-9
BCD Hour (BCDHOUR) Register...................................................................................................17-10
BCD Date (BCDDATE) Register ....................................................................................................17-10
BCD Day (BCDDAY) Register.......................................................................................................17-10
BCD Month (BCDMON) Register...................................................................................................17-11
BCD Year (BCDYEAR) Register ...................................................................................................17-11
xiv S3C2410A MICROPROCESSOR
Page 16
Table of Contents (Continued)
Chapter 18 WatchDog Timer
Overview.............................................................................................................................................18-1
Features.....................................................................................................................................18-1
Watchdog Timer Operation ...........................................................................................................18-2
WTDAT & WTCNT.......................................................................................................................18-2
Consideration of Debugging Environment .......................................................................................18-2
Watchdog Timer Special Registers .......................................................................................................18-3
Watchdog Timer Control (WTCON) Register...................................................................................18-3
Watchdog Timer Data (WTDAT) Register .......................................................................................18-4
Watchdog Timer Count (WTCNT) Register.....................................................................................18-4
Chapter 19 MMC/SD/SDIO Host controller
Overview.............................................................................................................................................19-1
Features.....................................................................................................................................19-1
Block Diagram ............................................................................................................................19-2
SDI Operation .............................................................................................................................19-3
SDIO Operation ...........................................................................................................................19-4
SDI Special Registers..................................................................................................................19-5
Chapter 20 IIC-BUS Interface
Overview.............................................................................................................................................20-1
IIC-Bus Interface..........................................................................................................................20-3
Start and Stop Conditions ............................................................................................................20-3
Data Transfer Format ...................................................................................................................20-4
ACK Signal Transmission.............................................................................................................20-5
Read-Write Operation ..................................................................................................................20-6
Bus Arbitration Procedures ...........................................................................................................20-6
Abort Conditions ..........................................................................................................................20-6
Configuring IIC-Bus ......................................................................................................................20-6
Flowcharts of Operations in Each Mode.........................................................................................20-7
IIC-Bus Interface Special Registers .......................................................................................................20-11
Multi-Master IIC-Bus Control (IICCON) Register..............................................................................20-11
Multi-Master IIC-Bus Control/Status (IICSTAT) Register...................................................................20-12
Multi-Master IIC-Bus Address (IICADD) Register.............................................................................20-13
Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register ...................................................20-13
S3C2410A MICROPROCESSOR xv
Page 17
Table of Contents (Continued)
Chapter 21 IIS-BUS Interface
Overview.............................................................................................................................................21-1
Block Diagram ....................................................................................................................................21-2
Functional Descriptions ........................................................................................................................21-2
Transmit or Receive Only Mode ....................................................................................................21-2
Audio Serial Interface Format ................................................................................................................21-3
IIS-Bus Format............................................................................................................................21-3
MSB (Left) Justified .....................................................................................................................21-3
Sampling Frequency and Master Clock .........................................................................................21-4
IIS-Bus Interface Special Registers .......................................................................................................21-5
IIS Control (IISCON) Register ........................................................................................................21-5
IIS Mode Register (IISMOD) Register.............................................................................................21-6
IIS Prescaler (IISPSR) Register.....................................................................................................21-7
IIS FIFO Control (IISFCON) Register..............................................................................................21-8
IIS FIFO (IISFIFO) Register...........................................................................................................21-8
Chapter 22 SPI Interface
Overview.............................................................................................................................................22-1
Features.....................................................................................................................................22-1
Block Diagram ............................................................................................................................22-2
SPI Operation .............................................................................................................................22-3
SPI Special Registers..........................................................................................................................22-7
SPI Control Register....................................................................................................................22-7
SPI Status Register .....................................................................................................................22-8
SPI Pin Control Register ..............................................................................................................22-9
xvi S3C2410A MICROPROCESSOR
Page 18
Table of Contents (Continued)
Chapter 23 BUS Priorities
Overview.............................................................................................................................................23-1
Bus Priority Map .........................................................................................................................23-1
Chapter 24 Electrical Data
Absolute Maximum Ratings ..................................................................................................................24-1
Recommended Operating Conditions .....................................................................................................24-1
D.C. Electrical Characteristics ..............................................................................................................24-2
A.C. Electrical Characteristics ..............................................................................................................24-4
Chapter 25 Mechanical Data
Package Dimensions...........................................................................................................................25-1
S3C2410A MICROPROCESSOR xvii
Page 19
Table of Contents (Continued)
Appendix 1- ARM920T Introduction
Abuot the Introduction ..........................................................................................................................1-1
Processor Functional Block Diagram.....................................................................................................1-2
Appendix 2- Programmer's Model
About rhe Programmer's Model .............................................................................................................2-1
About rhe ARM9TDMI Programmer's Model ...........................................................................................2-2
Data Abort Model ........................................................................................................................2-2
Instruction Set Extension Spaces .................................................................................................2-3
Cp15 Register Map Summary...............................................................................................................2-4
Accessing Cp15 Registers ...........................................................................................................2-5
Register 0: ID Code Register ........................................................................................................2-7
Register 0: Cache Type Register...................................................................................................2-8
Register 1: Control Register..........................................................................................................2-10
Register 2: Translation Table Base (TTB) Register..........................................................................2-12
Register 3: Domain Access Control Register..................................................................................2-13
Register 4: Reserved....................................................................................................................2-14
Register 5: Fault Status Registers ................................................................................................2-14
Register 6: Fault Address Register................................................................................................2-15
Register 7: Cache Operations.......................................................................................................2-15
Register 8: TLB Operations ..........................................................................................................2-18
Register 9: Cache Lock Down Register..........................................................................................2-19
Register 10: TLB Lock Down Register ...........................................................................................2-21
Registers 11-12 & 14: Reserved ....................................................................................................2-22
Register 13: Process ID...............................................................................................................2-22
Register 15: Test Configuration Register........................................................................................2-24
Appendix 3- MMU
About the MMU...................................................................................................................................3-1
Access Permissions And Domains ...............................................................................................3-1
Translated Entries .......................................................................................................................3-2
Mmu Program Accessible Registers .....................................................................................................3-3
Address Translation .............................................................................................................................3-4
Hardware Translation Process ..............................................................................................................3-6
Translation Table Base.................................................................................................................3-6
Level One Fetch ..........................................................................................................................3-7
Level One Descriptor............................................................................................................................3-8
Section Descriptor ...............................................................................................................................3-9
Coarse Page Table Descriptor ..............................................................................................................3-9
Fine Page Table Descriptor ..................................................................................................................3-9
Translating Section References .............................................................................................................3-10
xviii S3C2410A MICROPROCESSOR
Page 20
Table of Contents (Concluded)
Appendix 3- MMU (Continued)
Level Two Descriptor ............................................................................................................................3-11
Translating Large Page References .......................................................................................................3-12
Translating Small Page References.......................................................................................................3-14
Translating Tiny Page References .........................................................................................................3-15
Sub-Pages..........................................................................................................................................3-17
Mmu Faults and CPU Aborts ................................................................................................................3-17
Fault Address and Fault Status Registers ..............................................................................................3-18
Fault Status................................................................................................................................3-18
Domain Access Control .......................................................................................................................3-19
Fault Checking Sequence....................................................................................................................3-21
Alignment Fault ...........................................................................................................................3-22
Translation Fault..........................................................................................................................3-22
Domain Fault ..............................................................................................................................3-22
Permission Fault.........................................................................................................................3-23
External Aborts...................................................................................................................................3-24
Interaction of the MMU and Caches .......................................................................................................3-25
Enabling the MMU.......................................................................................................................3-25
Disabling the MMU ......................................................................................................................3-25
Appendix 4- Caches, Write Buffer
About the Caches and Write Buffer .......................................................................................................4-1
Instruction Cache ................................................................................................................................4-2
Instruction Cache Enable/Disable..................................................................................................4-3
Instruction Cache Operation .........................................................................................................4-3
Instruction Cache Replacement Algorithm......................................................................................4-4
Instruction Cache Lockdown .........................................................................................................4-4
Data Cache and Write Buffer ................................................................................................................4-5
Data Cache and Write Buffer Enable/Disable..................................................................................4-6
Data Cache and Write Buffer Operation .........................................................................................4-6
Data Cache Replacement Algorithm ..............................................................................................4-8
Swap Instructions........................................................................................................................4-8
Data Cache Organization .............................................................................................................4-9
Data Cache Lockdown.................................................................................................................4-9
Cache Coherence................................................................................................................................4-10
Cache Cleaning when Lockdown is in Use .............................................................................................4-12
Implementation Notes ..........................................................................................................................4-12
Physical Address TAG RAM ................................................................................................................4-12
Appendix 5- Clock Modes
Overview.............................................................................................................................................5-1
Fastbus Mode .....................................................................................................................................5-2
Synchronous Mode..............................................................................................................................5-2
Asynchronous Mode ............................................................................................................................5-3
S3C2410A MICROPROCESSOR xix
Page 21
Page 22
List of Figures
Figure Title Page
Number Number
1-1 S3C2410A Block Diagram ....................................................................................1-5
1-2 S3C2410A Pin Assignments (272-FBGA) ..............................................................1-6
2-1 Big-Endian Addresses of Bytes within Words .........................................................2-2
2-2 Little-Endian Addresses of Bytes within Words ......................................................2-2
2-3 Register Organization in ARM State......................................................................2-4
2-4 Register Organization in THUMB state..................................................................2-5
2-5 Mapping of THUMB State Registers onto ARM State Registers ...............................2-6
2-6 Program Status Register Formats .........................................................................2-7
3-1 ARM Instruction Set Format .................................................................................3-1
3-2 Branch and Exchange Instructions........................................................................3-5
3-3 Branch Instructions ..............................................................................................3-7
3-4 Data Processing Instructions................................................................................3-9
3-5 ARM Shift Operations ..........................................................................................3-12
3-6 Logical Shift Left ..................................................................................................3-12
3-7 Logical Shift Right ...............................................................................................3-13
3-8 Arithmetic Shift Right...........................................................................................3-13
3-9 Rotate Right ........................................................................................................3-14
3-10 Rotate Right Extended .........................................................................................3-14
3-11 PSR Transfer ......................................................................................................3-19
3-12 Multiply Instructions .............................................................................................3-22
3-13 Multiply Long Instructions .....................................................................................3-25
3-14 Single Data Transfer Instructions ...........................................................................3-28
3-15 Little-Endian Offset Addressing .............................................................................3-30
3-16 Halfword and Signed Data Transfer with Register Offset ...........................................3-34
3-17 Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing.............3-35
3-18 Block Dat a Transfer Instructions ...........................................................................3-40
3-19 Post-Increment Addressing ..................................................................................3-41
3-20 Pre-Increment Addressing....................................................................................3-42
3-21 Post-Decrement Addressing .................................................................................3-42
3-22 Pre-Decrement Addressing...................................................................................3-43
3-23 Swap Instruction..................................................................................................3-47
3-24 Software Interrupt Instruction ................................................................................3-49
3-25 Coprocessor Data Operation Instruction.................................................................3-51
3-26 Coprocessor Data Transfer Instructions .................................................................3-53
3-27 Coprocessor Register Transfer Instructions ............................................................3-56
3-28 Undefined Instruction ...........................................................................................3-58
S3C2410A MICROPROCESSOR xxi
Page 23
List of Figures (Continued)
Figure Title Page
Number Number
4-1 THUMB Instruction Set Formats ...........................................................................4-2
4-2 Format 1.............................................................................................................4-5
4-3 Format 2.............................................................................................................4-7
4-4 Format 3.............................................................................................................4-9
4-5 Format 4.............................................................................................................4-11
4-6 Format 5.............................................................................................................4-13
4-7 Format 6.............................................................................................................4-16
4-8 Format 7.............................................................................................................4-18
4-9 Format 8.............................................................................................................4-20
4-10 Format 9.............................................................................................................4-22
4-11 Format 10 ...........................................................................................................4-24
4-12 Format 11 ...........................................................................................................4-26
4-13 Format 12 ...........................................................................................................4-28
4-14 Format 13 ...........................................................................................................4-30
4-15 Format 14 ...........................................................................................................4-31
4-16 Format 15 ...........................................................................................................4-33
4-17 Format 16 ...........................................................................................................4-34
4-18 Format 17 ...........................................................................................................4-36
4-19 Format 18 ...........................................................................................................4-37
4-20 Format 19 ...........................................................................................................4-38
5-1 S3C2410A Memory Map after Reset .....................................................................5-2
5-2 S3C2410A External nWAIT Timing Diagram (Tacc = 4)...........................................5-5
5-3 S3C2410A nXBREQ/nXBACK Timing Diagram .......................................................5-6
5-4 Memory Interface with 8-bit ROM..........................................................................5-7
5-5 Memory Interface with 8-bit ROM × 2....................................................................5-7
5-6 Memory Interface with 8-bit ROM × 4....................................................................5-8
5-7 Memory Interface with 16-bit ROM ........................................................................5-8
5-8 Memory Interface with 16-bit SRAM ......................................................................5-9
5-9 Memory Interface with 16-bit SRAM × 2.................................................................5-9
5-10 Memory Interface with 16-bit SDRAM(8MB: 1Mb × 16 × 4banks).............................5-10
5-11 Memory Interface with 16-bit SDRAM (16MB: 1Mb × 16 × 4banks × 2ea) .................5-10
5-12 S3C2410A nGCS Timing Diagram .........................................................................5-11
5-13 S3C2410A SDRAM Timing Diagram ......................................................................5-12
xxii S3C2410A MICROPROCESSOR
Page 24
List of Figures (Continued)
Figure Title Page
Number Number
6-1 NAND Flash Controller Block Diagram...................................................................6-2
6-2 NAND Flash Operation Scheme............................................................................6-2
6-3 TACLS = 0, TWRPH0 = 1, TWRPH1 = 0 ...............................................................6-3
6-4 NAND Flash Memory Mapping..............................................................................6-5
7-1 Clock Generator Block Diagram ............................................................................7-3
7-2 PLL (Phase-Locked Loop) Block Diagram ..............................................................7-5
7-3 Main Oscillator Circuit Examples ..........................................................................7-5
7-4 Power-On Reset Sequence (when the external clock source is a crystal oscillator) ...7-6
7-5 Changing Slow Clock by Setting PMS Value..........................................................7-7
7-6 Changing CLKDIVN Register Value.......................................................................7-8
7-7 The Clock Distribution Block Diagram....................................................................7-9
7-8 Power Management State Diagram.......................................................................7-10
7-9 Issuing Exit_from_Slow_mode Command in PLL on State.......................................7-12
7-10 Issuing Exit_from_Slow_mode Command After Lock Time.......................................7-12
7-11 Issuing Exit_from_Slow_mode Command and the Instant PLL_on
Command Simultaneously....................................................................................7-13
7-12 Power_OFF Mode ...............................................................................................7-16
8-1 Basic DMA Timing Diagram..................................................................................8-3
8-2 Demand/Handshake Mode Comparison.................................................................8-4
8-3 Burst 4 Transfer Size ...........................................................................................8-5
8-4 Single service in Demand Mode with Unit Transfer Size...........................................8-6
8-5 Single service in Handshake Mode with Unit Transfer Size......................................8-6
8-6 Whole service in Handshake Mode with Unit Transfer Size ......................................8-6
10-1 16-bit PWM Timer Block Diagram.........................................................................10-2
10-2 Timer Operations.................................................................................................10-3
10-3 Example of Double Buffering Function ...................................................................10-4
10-4 Example of a Timer Operation...............................................................................10-6
10-5 Example of PWM ................................................................................................10-7
10-6 Inverter On/Off.....................................................................................................10-8
10-7 The Wave form when a Dead Zone Feature is Enabled............................................10-9
10-8 Timer4 DMA Mode Operation................................................................................10-10
11-1 UART Block Diagram (with FIFO) ..........................................................................11-2
11-2 UART AFC Interface............................................................................................11-4
11-3 UART Receiving 4 Characters with 1 Error .............................................................11-6
11-4 IrDA Function Block Diagram................................................................................11-8
11-5 Serial I/O Frame Timing Diagram (Normal UART) ....................................................11-9
11-6 Infra-Red Transmit Mode Frame Timing Diagram.....................................................11-9
11-7 Infra-Red Receive Mode Frame Timing Diagram ......................................................11-9
11-8 nCTS and Delta CTS Timing Diagram....................................................................11-18
12-1 USB Host Controller Block Diagram......................................................................12-1
13-1 USB Device Controller Block Diagram ...................................................................13-2
S3C2410A MICROPROCESSOR xxiii
Page 25
List of Figures (Continued)
Figure Title Page
Number Number
14-1 Interrupt Process Diagram ....................................................................................14-1
14-2 Priority Generating Block .....................................................................................14-4
15-1 LCD Controller Block Diagram ..............................................................................15-3
15-2 Monochrome Display Types (STN)........................................................................15-11
15-3 Color Display Types (STN) ...................................................................................15-12
15-4 8-bit Single Scan Display Type STN LCD Timing....................................................15-14
15-5 16BPP Display Types (TFT) .................................................................................15-21
15-6 TFT LCD Timing Example.....................................................................................15-22
15-7 Example of Scrolling in Virtual Display (Single Scan) ..............................................15-24
15-8 Example of PWREN Function (PWREN = 1, INVPWREN = 0) ................................15-25
16-1 ADC and Touch Screen Interface Block Diagram....................................................16-2
16-2 Example of ADC and Touch Screen Interface .........................................................16-3
16-3 Timing Diagram in Auto (Sequential) X/Y Position Conversion Mode.........................16-6
17-1 Real Time Clock Block Diagram............................................................................17-2
17-2 Main Oscillator Circuit Example ............................................................................17-4
18-1 Watchdog Timer Block Diagram............................................................................18-2
19-1 Block Diagram ....................................................................................................19-2
20-1 IIC-Bus Block Diagram .........................................................................................20-2
20-2 Start and Stop Condition......................................................................................20-3
20-3 IIC-Bus Interface Data Format...............................................................................20-4
20-4 Data Transfer on the IIC-Bus.................................................................................20-5
20-5 Acknowledge on the IIC-Bus.................................................................................20-5
20-8 Operations for Slave/Transmitter Mode ..................................................................20-9
20-9 Operations for Slave/Receiver Mode ......................................................................20-10
21-1 IIS-Bus Block Diagram .........................................................................................21-2
21-2 IIS-Bus and MSB (Left)-justified Data Interface Formats ..........................................21-4
22-1 SPI Block Diagram..............................................................................................22-2
22-2 SPI Transfer Format .............................................................................................22-4
24-1 XTIpll Clock Timing ..............................................................................................24-4
24-2 EXTCLK Clock Input Timing ..................................................................................24-4
24-3 EXTCLK/HCLK in case that EXTCLK is used without the PLL..................................24-4
24-4 HCLK/CLKOUT/SCLK in case that EXTCLK is used ...............................................24-5
24-5 Manual Reset Input Timing...................................................................................24-5
24-6 Power-On Oscillation Setting Timing .....................................................................24-6
24-7 Power_OFF Mode Return Oscillation Setting Timing ...............................................24-7
xxiv S3C2410A MICROPROCESSOR
Page 26
List of Figures (Continued)
Figure Title Page
Number Number
24-8 ROM/SRAM Burst READ Timing(I) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0,
Tcah = 0, PMC = 0, ST = 0, DW = 16-bit)..............................................................24-8
24-9 ROM/SRAM Burst READ Timing(II) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0,
Tcah = 0, PMC = 0, ST = 1, DW = 16-bit)..............................................................24-9
24-10 External Bus Request in ROM/SRAM Cycle (Tacs = 0, Tcos = 0, Tacc = 8,
Tcoh = 0, Tcah = 0, PMC = 0, ST = 0) ..................................................................24-10
24-11 ROM/SRAM READ Timing (I) (Tacs = 2,Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2,
PMC = 0, ST = 0) ................................................................................................24-11
24-12 ROM/SRAM READ Timing (II) (Tacs = 2, Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2,
PMC = 0, ST = 1) ................................................................................................24-12
24-13 ROM/SRAM WRITE Timing (I) (Tacs = 2,Tcos = 2,Tacc = 4,Tcoh = 2, Tcah = 2,
PMC = 0, ST = 0.................................................................................................24-13
24-14 ROM/SRAM WRITE Timing (II) (Tacs = 2, Tcos = 2, Tacc = 4, Tcoh = 2, Tcah = 2,
PMC = 0, ST = 1) ................................................................................................24-14
24-15 External nWAIT READ Timing (Tacs = 1, Tcos = 1, Tacc = 4, Tcoh = 0, Tcah = 1,
PMC = 0, ST = 0) ................................................................................................24-15
24-16 External nWAIT WRITE Timing (Tacs = 0, Tcos = 0, Tacc = 4, Tcoh = 0, Tcah = 0,
PMC = 0, ST = 0) ................................................................................................24-15
24-17 Masked-ROM Single READ Timing
(Tacs = 2, Tcos = 2, Tacc = 8, PMC = 01/10/11)....................................................24-16
24-18 Masked-ROM Consecutive READ Timing (Tacs = 0, Tcos = 0, Tacc = 3, Tpac = 2,
PMC = 01/10/11) .................................................................................................24-16
24-19 SDRAM Single Burst READ Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit)...........24-17
24-20 External Bus Request in SDRAM Timing (Trp = 2, Trcd = 2, Tcl = 2) ........................24-18
24-21 SDRAM MRS Timing...........................................................................................24-19
24-22 SDRAM Single READ Timing(I) (Trp = 2, Trcd = 2, Tcl = 2) .....................................24-20
24-23 SDRAM Single READ Timing(II) (Trp = 2, Trcd = 2, Tcl = 3).....................................24-21
24-24 SDRAM Auto Refresh Timing (Trp = 2, Trc = 4)......................................................24-22
24-25 SDRAM Page Hit-Miss READ Timing (Trp = 2, Trcd = 2, Tcl = 2).............................24-23
24-26 SDRAM Self Refresh Timing (Trp = 2, Trc = 4) .......................................................24-24
24-27 SDRAM Single Write Timing (Trp = 2, Trcd = 2) .....................................................24-25
24-28 SDRAM Page Hit-Miss Write Timing (Trp = 2, Trcd = 2, Tcl = 2) ..............................24-26
24-29 External DMA Timing (Handshake, Single transfer) .................................................24-27
24-30 TFT LCD Controller Timing....................................................................................24-27
24-31 IIS Interface Timing..............................................................................................24-28
24-32 IIC Interface Timing..............................................................................................24-28
24-33 SD/MMC Interface Timing.....................................................................................24-29
24-34 SPI Interface Timing (CPHA = 1, CPOL = 1) ..........................................................24-29
24-35 NAND Flash Address/Command Timing ................................................................24-30
24-36 NAND Flash Timing.............................................................................................24-30
25-1 272-FBGA-1414 Package Dimension 1 (Top View) .................................................25-1
25-2 272-FBGA-1414 Package Dimension 2 (Bottom View)............................................25-2
S3C2410A MICROPROCESSOR xxv
Page 27
List of Figures (Concluded)
Figure Title Page
Number Number
1-1 ARM920T Functional Block Diagram.....................................................................1-2
2-1 CP15 MRC and MCR Bit Pattern ..........................................................................2-5
2-2 Register 7 MVA Format .......................................................................................2-17
2-3 Register 7 Index Format.......................................................................................2-17
2-4 Register 8 MVA Format .......................................................................................2-18
2-5 Register 9...........................................................................................................2-20
2-6 Register 10.........................................................................................................2-21
2-7 Register 13.........................................................................................................2-22
2-8 Address Mapping Using CP15 Register 13.............................................................2-23
3-1 Translating Page Tables.......................................................................................3-5
3-2 Translation Table Base Register............................................................................3-6
3-3 Accessing the Translation Table Level One Descriptors ...........................................3-7
3-4 Level One Descriptors..........................................................................................3-8
3-5 Section Translation ..............................................................................................3-10
3-6 Page Table Entry (Level One Descriptor)................................................................3-11
3-7 Large Page Translation from a Coarse Page Table ..................................................3-13
3-8 Small Page Translation from a Coarse Page Table..................................................3-14
3-9 Tiny Page Translation from a Fine Page Table ........................................................3-16
3-10 Domain Access Control Register Format...............................................................3-19
3-11 Sequence for Checking Faults..............................................................................3-21
xxvi S3C2410A MICROPROCESSOR
Page 28
List of Tables
Table Title Page
Number Number
1-1 272-Pin FBGA Pin Assignments – Pin Number Order.............................................1-7
1-2 272-Pin FBGA Pin Assignments ...........................................................................1-10
1-3 S3C2410A Signal Descriptions .............................................................................1-20
1-4 S3C2410A Special Registers ................................................................................1-26
2-1 PSR Mode Bit Values..........................................................................................2-9
2-2 Exception Entry/Exit............................................................................................2-11
2-3 Exception Vectors...............................................................................................2-13
3-1 The ARM Instruction Set ......................................................................................3-2
3-2 Condition Code Summary .....................................................................................3-4
3-3 ARM Data Processing Instructions ........................................................................3-11
3-4 Incremental Cycle Times......................................................................................3-16
3-5 Assembler Syntax Descriptions............................................................................3-27
3-6 Addressing Mode Names .....................................................................................3-45
4-1 THUMB Instruction Set Opcodes ..........................................................................4-3
4-2 Summary of Format 1 Instructions ........................................................................4-5
4-3 Summary of Format 2 Instructions ........................................................................4-7
4-4 Summary of Format 3 Instructions ........................................................................4-9
4-5 Summary of Format 4 Instructions ........................................................................4-11
4-6 Summary of Format 5 Instructions ........................................................................4-13
4-7 Summary of PC-Relative Load Instruction ..............................................................4-16
4-8 Summary of Format 7 Instructions ........................................................................4-19
4-9 Summary of format 8 instructions ..........................................................................4-20
4-10 Summary of Format 9 Instructions ........................................................................4-23
4-11 Halfword Data Transfer Instructions .......................................................................4-24
4-12 SP-Relative Load/Store Instructions ......................................................................4-26
4-13 Load Address......................................................................................................4-28
4-14 The ADD SP Instruction.......................................................................................4-30
4-15 PUSH and POP Instructions .................................................................................4-31
4-16 The Multiple Load/Store Instructions ......................................................................4-33
4-17 The Conditional Branch Instructions ......................................................................4-34
4-18 The SWI Instruction.............................................................................................4-36
4-19 Summary of Branch Instruction .............................................................................4-37
4-20 The BL Instruction ...............................................................................................4-39
5-1 Bank 6/7 Addresses ............................................................................................5-2
5-2 SDRAM Bank Address Configuration.....................................................................5-4
7-1 Clock Source Selection at Boot-Up.......................................................................7-2
7-2 Clock and Power State in Each Power Mode .........................................................7-10
7-3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock..................................7-11
S3C2410A MICROPROCESSOR xxvii
Page 29
List of Tables (Continued)
Table Title Page
Number Number
8-1 DMA Request Sources for Each Channel...............................................................8-2
8-2 DMA Controller Module Signal Timing Constants ....................................................8-3
9-1 S3C2410A Port Configuration ...............................................................................9-2
11-1 Interrupts in Connection with FIFO ........................................................................11-5
12-1 OHCI Registers for USB Host Controller ................................................................12-2
15-1 Relation Between VCLK and CLKVAL (STN, HCLK = 60 MHz) ................................15-5
15-2 Dither Duty Cycle Examples .................................................................................15-7
15-3 Relation Between VCLK and CLKVAL (TFT, HCLK = 60 MHz).................................15-15
15-4 5:6:5 Format .......................................................................................................15-20
15-5 5:5:5:1 Format ....................................................................................................15-20
15-6 MV Value for Each Display Mode..........................................................................15-39
16-1 Condition of Touch Screen Panel Pads in Separate X/Y Position Conversion Mode ....16-4
16-2 Condition of Touch Screen Panel Pads in Auto (Sequential) X/Y Position
Conversion Mode.................................................................................................16-5
16-3 Condition of Touch Screen Panel Pads in Waiting for Interrupt Mode. .......................16-5
21-1 CODEC clock (CODECLK = 256 or 384fs) .............................................................21-4
21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs)................................21-5
24-1 Absolute Maximum Rating ...................................................................................24-1
24-2 Recommended Operating Conditions .....................................................................24-1
24-3 Normal I/O PAD DC Electrical Characteristics........................................................24-2
24-4 USB DC Electrical Characteristics........................................................................24-3
24-5 S3C2410A Power Supply Voltage and Current .......................................................24-3
24-6 Clock Timing Constants.......................................................................................24-31
24-7 ROM/SRAM Bus Timing Constants.......................................................................24-32
24-8 Memory Interface Timing Constants (3.3V).............................................................24-32
24-9 External Bus Request Timing Constants................................................................24-33
24-10 DMA Controller Module Signal Timing Constants ....................................................24-33
24-11 TFT LCD Controller Module Signal Timing Constants ..............................................24-34
24-12 IIS Controller Module Signal Timing Constants .......................................................24-34
24-13 IIC BUS Controller Module Signal Timing ...............................................................24-35
24-14 SD/MMC Interface Transmit/Receive Timing Constants...........................................24-35
24-15 SPI Interface Transmit/Receive Timing Constants...................................................24-36
24-16 USB Electrical Specifications ...............................................................................24-36
24-17 USB Full Speed Output Buffer Electrical Characteristics .........................................24-37
24-18 USB Low Speed Output Buffer Electrical Characteristics .........................................24-37
24-19 NAND Flash Interface Timing Constants................................................................24-38
xxviii S3C2410A MICROPROCESSOR
Page 30
List of Table (Concluded)
Figure Title Page
Number Number
2-1 ARM9TDMI Im plementation Option........................................................................2-2
2-2 CP15 Register Map .............................................................................................2-4
2-3 CP15 Abbreviations .............................................................................................2-5
2-4 Address Types in ARM920 ...................................................................................2-6
2-5 Register 0: ID Code .............................................................................................2-7
2-6 Cache Type Register Format ................................................................................2-8
2-7 Cache Size Encoding ..........................................................................................2-9
2-8 Cache associativity encoding................................................................................2-9
2-9 Line Length Encoding ..........................................................................................2-10
2-10 Control Register 1-bit Functions............................................................................2-11
2-11 Clocking Modes ..................................................................................................2-11
2-12 Register 2: Translation Table Base........................................................................2-12
2-13 Register 3: Domain Access Control.......................................................................2-13
2-14 Fault Status Register ...........................................................................................2-14
2-15 Function Descriptions Register 7..........................................................................2-15
2-16 Cache Operations Register 7................................................................................2-16
2-17 TLB Operations Register 8...................................................................................2-18
2-18 Accessing the Cache Lock Down Register 9..........................................................2-20
2-19 Accessing the TLB Lock Down Register 10............................................................2-21
3-1 CP15 Register Functions .....................................................................................3-3
3-2 Interpreting Level One Descriptor Bits [1:0] ............................................................3-8
3-3 Interpreting Page Table Entry Bits 1:0...................................................................3-11
3-4 Priority Encoding of Fault Status ...........................................................................3-18
3-5 Interpreting Access Control Bits in Domain Access Control Register ........................3-19
3-6 Interpreting Access Permission (AP) Bits..............................................................3-20
4-1 Data Cache and Write Buffer Configuration.............................................................4-7
5-1 ARM920T Clocking ..............................................................................................5-1
5-2 Synchronous Clocking Mode................................................................................5-2
5-3 Switching from FCLK to BCLK in Synchronous Mode .............................................5-2
5-4 Asynchronous Clocking Mode ..............................................................................5-3
5-5 Switching from FCLK to BCLK in Asynchronous Mode............................................5-3
S3C2410A MICROPROCESSOR xxix
Page 31
S3C2410A PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
INTRODUCTION
This manual describes SAMSUNG's S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide
hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller
solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate
16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT),
NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch
Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS
Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
The S3C2410A was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its
low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It
adopts a new bus architecture called Advanced Microcontroller Bus Architecture (AMBA).
The S3C2410A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by
Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with
separate 16KB instruction and 16KB data caches, each with an 8-word line length.
By providing a complete set of common system peripherals, the S3C2410A minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in this
document include:
• 1.8V/2.0V int., 3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU
• External memory controller (SDRAM Control and Chip Select logic)
• LCD controller (up to 4K color STN and 256K color TFT) with 1-ch LCD-dedicated DMA
• 4-ch DMAs with external request pins
• 3-ch UART (IrDA1.0, 16-Byte Tx FIFO, and 16-Byte Rx FIFO) / 2-ch SPI
• 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller
• SD Host interface version 1.0 & Multi-Media Card Protocol version 2.11 compatible
• 2-port USB Host /1- port USB Device (ver 1.1)
• 4-ch PWM timers & 1-ch internal timer
• Watch Dog Timer
• 117-bit general purpose I/O ports / 24-ch external interrupt source
• Power control: Normal, Slow, Idle and Power-off mode
• 8-ch 10-bit ADC and Touch screen interface
• RTC with calendar function
• On-chip clock generator with PLL
1-1
Page 32
PRODUCT OVERVIEW S3C2410A
FEATURES
Architecture
• Integrated system for hand-held devices and
general embedded applications
• 16/32-Bit RISC architecture and powerful
instruction set with ARM920T CPU core
• Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux
• Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect of
main memory bandwidth and latency on
performance
• ARM920T CPU core supports the ARM debug
architecture.
• Internal Advanced Microcontroller Bus Architecture
(AMBA) (AMBA2.0, AHB/APB)
System Manager
• Little/Big Endian support
• Address space: 128M bytes for each bank (total
1G bytes)
• Supports programmable 8/16/32-bit data bus width
for each bank
• Fixed bank start address from bank 0 to bank 6
• Programmable bank start address and bank size
for bank 7
• Eight memory banks:
– Six memory banks for ROM, SRAM, and others.
– Two memory banks for ROM/SRAM/
Synchronous DRAM
• Fully Programmable access cycles for all memory
banks
• Supports external wait signals to expend the bus
cycle
• Supports self-refresh mode in SDRAM for power-
down
NAND Flash Boot Loader
• Supports booting from NAND flash memory
• 4KB internal buffer for booting
• Supports storage memory for NAND flash memory
after booting
Cache Memory
• 64-way set-associative cache with I-Cache (16KB)
and D-Cache (16KB)
• 8words length per line with one valid bit and two
dirty bits per line
• Pseudo random or round robin replacement
algorithm
• Write-through or write-back cache operation to
update the main memory
• The write buffer can hold 16 words of data and four
addresses.
Clock & Power Manager
• On-chip MPLL and UPLL:
UPLL generates the clock to operate USB
Host/Device.
MPLL generates the clock to operate MCU at
maximum 266MHz @ 2.0V.
• Clock can be fed selectively to each function block
by software.
• Power mode: Normal, Slow, Idle, and Power-off
mode
Normal mode: Normal operating mode
Slow mode: Low frequency clock without PLL
Idle mode: The clock for only CPU is stopped.
Power-off mode: The Core power including all
peripherals is shut down.
• Woken up by EINT[15:0] or RTC alarm interrupt
from Power-Off mode
• Supports various types of ROM for booting
(NOR/NAND Flash, EEPROM, and others)
1-2
Page 33
S3C2410A PRODUCT OVERVIEW
FEATURES (Continued)
Interrupt Controller
• 55 Interrupt sources
(One Watch dog timer, 5 timers, 9 UARTs, 24
external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2
SPI, 1 SDI, 2 USB, 1 LCD, and 1 Battery Fault)
• Level/Edge mode on external interrupt source
• Programmable polarity of edge and level
• Supports Fast Interrupt request (FIQ) for very
urgent interrupt request
Timer with Pulse Width Modulation (PWM)
• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal
timer with DMA-based or interrupt-based operation
• Programmable duty cycle, frequency, and polarity
• Dead-zone generation
• Supports external clock sources
RTC (Real Time Clock)
• Full clock feature: second, minute, hour, date,
day, month, and year
DMA Controller
• 4-ch DMA controller
• Supports memory to memory, IO to memory,
memory to IO, and IO to IO transfers
• Burst transfer mode to enhance the transfer rate
A/D Converter & Touch Screen Interface
• 8-ch multiplexed ADC
• Max. 500KSPS and 10-bit Resolution
LCD Controller STN LCD Displays Feature
• Supports 3 types of STN LCD panels: 4-bit dual
scan, 4-bit single scan, 8-bit single scan display
type
• Supports monochrome mode, 4 gray levels, 16
gray levels, 256 colors and 4096 colors for STN
LCD
• Supports multiple screen size
• Typical actual screen size: 640x480, 320x240,
160x160, and others
• 32.768 KHz operation
• Alarm interrupt
• Time tick interrupt
General Purpose Input/Output Ports
• 24 external interrupt ports
• multiplexed input/output ports
UART
• 3-channel UART with DMA-based or interrupt-
based operation
• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit/receive (Tx/Rx)
• Supports external clocks for the UART operation
(UEXTCLK)
• Programmable baud rate
• Supports IrDA 1.0
• Loopback mode for testing
• Each channel has internal 16-byte Tx FIFO and
16-byte Rx FIFO.
• Maximum virtual screen size is 4 Mbytes.
• Maximum virtual screen size in 256 color
mode: 4096x1024, 2048x2048, 1024x4096,
and others
TFT(Thin Film Transistor) Color Displays Feature
• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette
color displays for color TFT
• Supports 16 bpp non-palette true-color displays
for color TFT
• Supports maximum 16M color TFT at 24 bpp
mode
• Supports multiple screen size
• Typical actual screen size: 640x480, 320x240,
160x160, and others
• Maximum virtual screen size is 4Mbytes.
• Maximum virtual screen size in 64K color mode:
2048x1024, and others
1-3
Page 34
PRODUCT OVERVIEW S3C2410A
FEATURES (Continued)
Watchdog Timer
• 16-bit Watchdog Timer
• Interrupt request or system reset at time-out
IIC-Bus Interface
• 1-ch Multi-Master IIC-Bus
• Serial, 8-bit oriented and bi-directional data
transfers can be made at up to 100 Kbit/s in
Standard mode or up to 400 Kbit/s in Fast mode.
IIS-Bus Interface
• 1-ch IIS-bus for audio interface with DMA-based
operation
• Serial, 8-/16-bit per channel data transfers
• 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx
• Supports IIS format and MSB-justified data format
USB Host
• 2-port USB Host
• Complies with OHCI Rev. 1.0
SD Host Interface
• Compatible with SD Memory Card Protocol
version 1.0
• Compatible with SDIO Card Protocol version 1.0
• Bytes FIFO for Tx/Rx
• DMA based or Interrupt based operation
• Compatible with Multimedia Card Protocol version
2.11
SPI Interface
• Compatible with 2-ch Serial Peripheral Interface
Protocol version 2.11
• 2x8 bits Shift register for Tx/Rx
• DMA-based or interrupt-based operation
Operating Voltage Range
• Core: 1.8V for 200MHz (S3C2410A-20)
2.0V for 266MHz (S3C2410A-26)
• Memory & IO: 3.3V
• Compatible with USB Specification version 1.1
USB Device
• 1-port USB Device
• 5 Endpoints for USB Device
• Compatible with USB Specification version 1.1
Operating Frequency
• Up to 266MHz
Package
• 272-FBGA
1-4
Page 35
S3C2410A PRODUCT OVERVIEW
BLOCK DIAGRAM
JTAG
ARM920T
Instruction
MMU
IVA[31:0]
ARM9TDMI
Processor core
(Internal Embedded ICE)
Data
MMU
LCD
CONT.
ExtMaster
NAND CONT.
NAND Flash Boot
Loader
C13
C13
IPA[31:0]
DPA[31:0]
LCD
DMA
ID[31:0]
DD[31:0]
DVA[31:0]DVA[31:0]
Instruction
CACHE
(16KB)
CP15
Data
CACHE
(16KB)
A
H
B
B
U
S Memory CONT.
External
Coproc
Interface
Write
Buffer
WriteBack
PA Tag
RAM
BUS CONT.
Arbitor/Decode
Interrupt CONT.USB Host CONT.
Power
Management
SRAM/NOR/SDRAM
AMBA
Bus
I/F
WBPA[31:0]
Clock Generator
(M PLL)
Bridge & DMA (4Ch)
UART 0, 1, 2
USB Device
SDI/MMC
Watchdog
Timer
BUS CONT.
Arbitor/Decode
SPI 0, 1
SPI
A
P
B
B
U
S
Figure 1-1. S3C2410A Block Diagram
I2C
I2S
GPIO
RTC
ADC
Timer/PWM
0 ~ 3, 4(Internal)
1-5
Page 36
PRODUCT OVERVIEW S3C2410A
PIN ASSIGNMENTS
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
BOTTOM VIEW
Figure 1-2. S3C2410A Pin Assignments (272-FBGA)
1-6
Page 37
S3C2410A PRODUCT OVERVIEW
Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
A1 DATA19 B14 ADDR0/GPA0 D10 ADDR19/GPA4
A2 DATA18 B15 nSRAS D11 VDDi
A3 DATA16 B16 nBE1:nWBE1:DQM1 D12 ADDR10
A4 DATA15 B17 VSSi D13 ADDR5
A5 DATA11 C1 DATA24 D14 ADDR1
A6 VDDMOP C2 DATA23 D15 VSSMOP
A7 DATA6 C3 DATA21 D16 SCKE
A8 DATA1 C4 VDDi D17 nGCS0
A9 ADDR21/GPA6 C5 DATA12 E1 DATA31
A10 ADDR16/GPA1 C6 DATA7 E2 DATA29
A11 ADDR13 C7 DATA4 E3 DATA28
A12 VSSMOP C8 VDDi E4 DATA30
A13 ADDR6 C9 ADDR25/GPA10 E5 VDDMOP
A14 ADDR2 C10 VSSMOP E6 VSSMOP
A15 VDDMOP C11 ADDR14 E7 DATA3
A16 nBE3:nWBE3:DQM3 C12 ADDR7 E8 ADDR26/GPA11
A17 nBE0:nWBE0:DQM0 C13 ADDR3 E9 ADDR23/GPA8
B1 DATA22 C14 nSCAS E10 ADDR18/GPA3
B2 DATA20 C15 nBE2:nWBE2:DQM2 E11 VDDMOP
B3 DATA17 C16 nOE E12 ADDR11
B4 VDDMOP C17 VDDi E13 nWE
B5 DATA13 D1 DATA27 E14 nGCS3/GPA14
B6 DATA9 D2 DATA25 E15 nGCS1/GPA12
B7 DATA5 D3 VSSMOP E16 nGCS2/GPA13
B8 DATA0 D4 DATA26 E17 nGCS4/GPA15
B9 ADDR24/GPA9 D5 DATA14 F1 TOUT1/GPB1
B10 ADDR17/GPA2 D6 DATA10 F2 TOUT0/GPB0
B11 ADDR12 D7 DATA2 F3 VSSMOP
B12 ADDR8 D8 VDDMOP F4 TOUT2/GPB2
B13 ADDR4 D9 ADDR22/GPA7 F5 VSSOP
1-7
Page 38
PRODUCT OVERVIEW S3C2410A
Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order (Continued)
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
F6 VSSi H4 nXDREQ1/GPB8 K13 TXD2/nRTS1/GPH6
F7 DATA8 H5 nTRST K14 RXD1/GPH5
F8 VSSMOP H6 TCK K15 TXD0/GPH2
F9 VSSi H12 CLE/GPA17 K16 TXD1/GPH4
F10 ADDR20/GPA5 H13 VSSOP K17 RXD0/GPH3
F11 VSSi H14 VDDMOP L1 VD0/GPC8
F12 VSSMOP H15 VSSi L2 VD1/GPC9
F13 SCLK0 H16 XTOpll L3 LCDVF2/GPC7
F14 SCLK1 H17 XTIpll L4 VD2/GPC10
F15 nGCS5/GPA16 J1 TDI L5 VDDiarm
F16 nGCS6:nSCS0 J2 VCLK:LCD_HCLK/GPC1 L6 LCDVF1/GPC6
F17 nGCS7:nSCS1 J3 TMS L7 IICSCL/GPE14
G1 nXBACK/GPB5 J4 LEND:STH/GPC0 L9 EINT11/nSS1/GPG3
G2 nXDACK1/GPB7 J5 TDO L11 VDDi_UPLL
G3 TOUT3/GPB3 J6 VLINE:HSYNC:CPV/GPC2 L12 nRTS0/GPH1
G4 TCLK0/GPB4 J7 VSSiarm L13 UPLLCAP
G5 nXBREQ/GPB6 J11 EXTCLK L14 nCTS0/GPH0
G6 VDDalive J12 nRESET L15 EINT6/GPF6
G7 VDDiarm J13 VDDi L16 UEXTCLK/GPH8
G9 VSSMOP J14 VDDalive L17 EINT7/GPF7
G11 ADDR15 J15 PWREN M1 VSSiarm
G12 ADDR9 J16 nRSTOUT/GPA21 M2 VD5/GPC13
G13 nWAIT J17 nBATT_FLT M3 VD3/GPC11
G14 ALE/GPA18 K1 VDDOP M4 VD4/GPC12
G15 nFWE/GPA19 K2 VM:VDEN:TP/GPC4 M5 VSSiarm
G16 nFRE/GPA20 K3 VDDiarm M6 VDDOP
G17 nFCE/GPA22 K4 VFRAME:VSYNC:STV/GPC3 M7 VDDiarm
H1 VSSiarm K5 VSSOP M8 IICSDA/GPE15
H2 nXDACK0/GPB9 K6 LCDVF0/GPC5 M9 VSSiarm
H3 nXDREQ0/GPB10 K12 RXD2/nCTS1/GPH7 M10 DP1/PDP0
1-8
Page 39
S3C2410A PRODUCT OVERVIEW
Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order (Continued)
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
M11 EINT23/nYPON/GPG15 P8 SPICLK0/GPE13 T5 I2SLRCK/GPE0
M12 RTCVDD P9 EINT12/LCD_PWREN/GPG4 T6 SDCLK/GPE5
M13 VSSi_MPLL P10 EINT18/GPG10 T7 SPIMISO0/GPE11
M14 EINT5/GPF5 P11 EINT20/XMON/GPG12 T8 EINT10/nSS0/GPG2
M15 EINT4/GPF4 P12 VSSOP T9 VSSOP
M16 EINT2/GPF2 P13 DP0 T10 EINT17/GPG9
M17 EINT3/GPF3 P14 VDDi_MPLL T11 EINT22/YMON/GPG14
N1 VD6/GPC14 P15 VDDA_ADC T12 DN0
N2 VD8/GPD0 P16 XTIrtc T13 OM3
N3 VD7/GPC15 P17 MPLLCAP T14 VSSA_ADC
N4 VD9/GPD1 R1 VDDiarm T15 AIN1
N5 VDDiarm R2 VD14/GPD6 T16 AIN3
N6 CDCLK/GPE2 R3 VD17/GPD9 T17 AIN5
N7 SDDAT1/GPE8 R4 VD18/GPD10 U1 VD15/GPD7
N8 VSSiarm R5 VSSOP U2 VD19/GPD11
N9 VDDOP R6 SDDAT0/GPE7 U3 VD21/GPD13
N10 VDDiarm R7 SDDAT3/GPE10 U4 VSSiarm
N11 DN1/PDN0 R8 EINT8/GPG0 U5 I2SSDI/nSS0/GPE3
N12 Vref R9 EINT14/SPIMOSI1/GPG6 U6 I2SSDO/I2SSDI/GPE4
N13 AIN7 R10 EINT15/SPICLK1/GPG7 U7 SPIMOSI0/GPE12
N14 EINT0/GPF0 R11 EINT19/TCLK1/GPG11 U8 EINT9/GPG1
N15 VSSi_UPLL R12 CLKOUT0/GPH9 U9 EINT13/SPIMISO1/GPG5
N16 VDDOP R13 R/nB U10 EINT16/GPG8
N17 EINT1/GPF1 R14 OM0 U11 EINT21/nXPON/GPG13
P1 VD10/GPD2 R15 AIN4 U12 CLKOUT1/GPH10
P2 VD12/GPD4 R16 AIN6 U13 NCON
P3 VD11/GPD3 R17 XTOrtc U14 OM2
P4 VD23/nSS0/GPD15 T1 VD13/GPD5 U15 OM1
P5 I2SSCLK/GPE1 T2 VD16/GPD8 U16 AIN0
P6 SDCMD/GPE6 T3 VD20/GPD12 U17 AIN2
P7 SDDAT2/GPE9 T4 VD22/nSS1/GPD14 – –
1-9
Page 40
PRODUCT OVERVIEW S3C2410A
Table 1-2. 272-Pin FBGA Pin Assignments
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
C3 DATA21 DATA21 Hi-z Hi-z I t12
B1 DATA22 DATA22 Hi-z Hi-z I t12
C2 DATA23 DATA23 Hi-z Hi-z I t12
D3 VSSMOP VSSMOP P P P s3o
E5 VDDMOP VDDMOP P P P d3o
C1 DATA24 DATA24 Hi-z Hi-z I t12
D2 DATA25 DATA25 Hi-z Hi-z I t12
D4 DATA26 DATA26 Hi-z Hi-z I t12
D1 DATA27 DATA27 Hi-z Hi-z I t12
E3 DATA28 DATA28 Hi-z Hi-z I t12
E2 DATA29 DATA29 Hi-z Hi-z I t12
E4 DATA30 DATA30 Hi-z Hi-z I t12
E1 DATA31 DATA31 Hi-z Hi-z I t12
F3 VSSMOP VSSMOP P P P s3o
F5 VSSOP VSSOP P P P s3o
F2 TOUT0/GPB0 GPB0 –/– O(L)/– I t8
I/O Type
F1 TOUT1/GPB1 GPB1 –/– O(L)/– I t8
F4 TOUT2/GPB2 GPB2 –/– O(L)/– I t8
G3 TOUT3/GPB3 GPB3 –/– O(L)/– I t8
G4 TCLK0/GPB4 GPB4 –/– –/– I t8
G1 nXBACK/GPB5 GPB5 –/– –/– I t8
G5 nXBREQ/GPB6 GPB6 –/– –/– I t8
G2 nXDACK1/GPB7 GPB7 –/– –/– I t8
G6 VDDalive VDDalive P P P d1i
G7 VDDiarm VDDiarm P P P d1c
H1 VSSiarm VSSiarm P P P s3i
H4 nXDREQ1/GPB8 GPB8 –/– –/– I t8
H2 nXDACK0/GPB9 GPB9 –/– –/– I t8
H3 nXDREQ0/GPB10 GPB10 –/– –/– I t8
H5 nTRST nTRST I I I is
H6 TCK TCK I I I is
J1 TDI TDI I I I is
J3 TMS TMS I I I is
1-10
Page 41
S3C2410A PRODUCT OVERVIEW
Table 1-2. 272-Pin FBGA Pin Assignments (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
J5 TDO TDO O O O ot
J4 LEND:STH/GPC0 GPC0 –/– O(L)/– I t8
J2 VCLK:LCD_HCLK/GPC1 GPC1 –/– O(L)/– I t8
J6 VLINE:HSYNC:CPV/GPC2 GPC2 –/– O(L)/– I t8
K3 VDDiarm VDDiarm P P P d1c
J7 VSSiarm VSSiarm P P P s3i
K2 VM:VDEN:TP/GPC4 GPC4 –/– O(L)/– I t8
K4 VFRAME:VSYNC:STV/GPC3 GPC3 –/– O(L)/– I t8
K1 VDDOP VDDOP P P P d3o
K5 VSSOP VSSOP P P P s3o
K6 LCDVF0/GPC5 GPC5 –/– O(L)/– I t8
L6 LCDVF1/GPC6 GPC6 –/– O(L)/– I t8
L3 LCDVF2/GPC7 GPC7 –/– O(L)/– I t8
L1 VD0/GPC8 GPC8 –/– O(L)/– I t8
L2 VD1/GPC9 GPC9 –/– O(L)/– I t8
L4 VD2/GPC10 GPC10 –/– O(L)/– I t8
I/O Type
M3 VD3/GPC11 GPC11 –/– O(L)/– I t8
L5 VDDiarm VDDiarm P P P d1c
M1 VSSiarm VSSiarm P P P s3i
M4 VD4/GPC12 GPC12 –/– O(L)/– I t8
M2 VD5/GPC13 GPC13 –/– O(L)/– I t8
N1 VD6/GPC14 GPC14 –/– O(L)/– I t8
N3 VD7/GPC15 GPC15 –/– O(L)/– I t8
N2 VD8/GPD0 GPD0 –/– O(L)/– I t8
N4 VD9/GPD1 GPD1 –/– O(L)/– I t8
P1 VD10/GPD2 GPD2 –/– O(L)/– I t8
P3 VD11/GPD3 GPD3 –/– O(L)/– I t8
P2 VD12/GPD4 GPD4 –/– O(L)/– I t8
R1 VDDiarm VDDiarm P P P d1c
M5 VSSiarm VSSiarm P P P s3i
T1 VD13/GPD5 GPD5 –/– O(L)/– I t8
R2 VD14/GPD6 GPD6 –/– O(L)/– I t8
U1 VD15/GPD7 GPD7 –/– O(L)/– I t8
1-11
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PRODUCT OVERVIEW S3C2410A
Table 1-2. 272-Pin FBGA Pin Assignments (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
T2 VD16/GPD8 GPD8 –/– O(L)/– I t8
R3 VD17/GPD9 GPD9 –/– O(L)/– I t8
R4 VD18/GPD10 GPD10 –/– O(L)/– I t8
U2 VD19/GPD11 GPD11 –/– O(L)/– I t8
T3 VD20/GPD12 GPD12 –/– O(L)/– I t8
U3 VD21/GPD13 GPD13 –/– O(L)/– I t8
T4 VD22/nSS1/GPD14 GPD14 –/– O(L)/– I t8
P4 VD23/nSS0/GPD15 GPD15 –/– O(L)/– I t8
N5 VDDiarm VDDiarm P P P d1c
U4 VSSiarm VSSiarm P P P s3i
M6 VDDOP VDDOP P P P d3o
R5 VSSOP VSSOP P P P s3o
T5 I2SLRCK/GPE0 GPE0 –/– O(L)/– I t8
P5 I2SSCLK/GPE1 GPE1 –/– O(L)/– I t8
N6 CDCLK/GPE2 GPE2 –/– O(L)/– I t8
U5 I2SSDI/nSS0/GPE3 GPE3 –/–/– –/–/– I t8
I/O Type
U6 I2SSDO/I2SSDI/GPE4 GPE4 –/–/– O(L)/–/– I t8
T6 SDCLK/GPE5 GPE5 –/– O(L)/– I t8
P6 SDCMD/GPE6 GPE6 –/– Hi-z/– I t8
R6 SDDAT0/GPE7 GPE7 –/– Hi-z/– I t8
N7 SDDAT1/GPE8 GPE8 –/– Hi-z/– I t8
P7 SDDAT2/GPE9 GPE9 –/– Hi-z/– I t8
R7 SDDAT3/GPE10 GPE10 –/– Hi-z/– I t8
T7 SPIMISO0/GPE11 GPE11 –/– Hi-z/– I t8
U7 SPIMOSI0/GPE12 GPE12 –/– Hi-z/– I t8
P8 SPICLK0/GPE13 GPE13 –/– Hi-z/– I t8
M7 VDDiarm VDDiarm P P P d1c
N8 VSSiarm VSSiarm P P P s3i
L7 IICSCL/GPE14 GPE14 –/– Hi-z/– I d8
M8 IICSDA/GPE15 GPE15 –/– Hi-z/– I d8
R8 EINT8/GPG0 GPG0 –/– –/– I t8
U8 EINT9/GPG1 GPG1 –/– –/– I t8
T8 EINT10/nSS0/GPG2 GPG2 –/–/– –/–/– I t8
1-12
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S3C2410A PRODUCT OVERVIEW
Table 1-2. 272-Pin FBGA Pin Assignments (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
L9 EINT11/nSS1/GPG3 GPG3 –/–/– –/–/– I t8
P9 EINT12/LCD_PWREN/GPG4 GPG4 –/–/– –/O(L)/– I t8
U9 EINT13/SPIMISO1/GPG5 GPG5 –/–/– –/Hi-z/– I t8
R9 EINT14/SPIMOSI1/GPG6 GPG6 –/–/– –/Hi-z/– I t8
T9 VSSOP VSSOP P P P s3o
N9 VDDOP VDDOP P P P d3o
N10 VDDiarm VDDiarm P P P d1c
M9 VSSiarm VSSiarm P P P s3i
R10 EINT15/SPICLK1/GPG7 GPG7 –/–/– –/Hi-z/– I t8
U10 EINT16/GPG8 GPG8 –/– –/– I t6
T10 EINT17/GPG9 GPG9 –/– –/– I t6
P10 EINT18/GPG10 GPG10 –/– –/– I t6
R11 EINT19/TCLK1/GPG11 GPG11 –/–/– –/–/– I t12
P11 EINT20/XMON/GPG12 GPG12 –/–/– –/O(L)/– I t12
U11 EINT21/nXPON/GPG13 GPG13 –/–/– –/O(L)/– I t12
T11 EINT22/YMON/GPG14 GPG14 –/–/– –/O(L)/– I t12
I/O Type
M11 EINT23/nYPON/GPG15 GPG15 –/–/– –/O(L)/– I t12
R12 CLKOUT0/GPH9 GPH9 –/– O(L)/– I t12
U12 CLKOUT1/GPH10 GPH10 –/– O(L)/– I t12
M10 DP1/PDP0 DP1 – – AI us
N11 DN1/PDN0 DN1 – – AI us
P13 DP0 DP0 – – AI us
T12 DN0 DN0 – – AI us
U13 NCON NCON – – I is
R13 R/nB R/nB – – I is
T13 OM3 OM3 – – I is
U14 OM2 OM2 – – I is
U15 OM1 OM1 – – I is
R14 OM0 OM0 – – I is
P12 VSSOP VSSOP P P P s3o
T14 VSSA_ADC VSSA_ADC P P P s3t
N12 Vref Vref – – AI ia
U16 AIN0 AIN0 – – AI r10
1-13
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PRODUCT OVERVIEW S3C2410A
Table 1-2. 272-Pin FBGA Pin Assignments (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
T15 AIN1 AIN1 – – AI r10
U17 AIN2 AIN2 – – AI r10
T16 AIN3 AIN3 – – AI r10
R15 AIN4 AIN4 – – AI r10
T17 AIN5 AIN5 – – AI r10
R16 AIN6 AIN6 – – AI r10
N13 AIN7 AIN7 – – AI r10
P15 VDDA_ADC VDDA_ADC P P P d3t
R17 XTOrtc XTOrtc – – AO gp
P16 XTIrtc XTIrtc – – AI gp
M12 RTCVDD RTCVDD P P P d1i
P14 VDDi_MPLL VDDi_MPLL P P P d1c
M13 VSSi_MPLL VSSi_MPLL P P P s3i
P17 MPLLCAP MPLLCAP – – AI gp
L11 VDDi_UPLL VDDi_UPLL P P P d1c
N15 VSSi_UPLL VSSi_UPLL P P P s3i
I/O Type
L13 UPLLCAP UPLLCAP – – AI gp
N16 VDDOP VDDOP P P P d3o
N14 EINT0/GPF0 GPF0 –/– –/– I t8
N17 EINT1/GPF1 GPF1 –/– –/– I t8
M16 EINT2/GPF2 GPF2 –/– –/– I t8
M17 EINT3/GPF3 GPF3 –/– –/– I t8
M15 EINT4/GPF4 GPF4 –/– –/– I t8
M14 EINT5/GPF5 GPF5 –/– –/– I t8
L15 EINT6/GPF6 GPF6 –/– –/– I t8
L17 EINT7/GPF7 GPF7 –/– –/– I t8
L16 UEXTCLK/GPH8 GPH8 –/– –/– I t8
L14 nCTS0/GPH0 GPH0 –/– –/– I t8
L12 nRTS0/GPH1 GPH1 –/– O(H)/– I t8
K15 TXD0/GPH2 GPH2 –/– O(H)/– I t8
K17 RXD0/GPH3 GPH3 –/– –/– I t8
K16 TXD1/GPH4 GPH4 –/– O(H)/– I t8
K14 RXD1/GPH5 GPH5 –/– –/– I t8
1-14
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S3C2410A PRODUCT OVERVIEW
Table 1-2. 272-Pin FBGA Pin Assignments (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
I/O Type
K13 TXD2/nRTS1/GPH6 GPH6 –/– O(H)/– I t8
K12 RXD2/nCTS1/GPH7 GPH7 –/– –/– I t8
J17 nBATT_FLT nBATT_FLT – – I is
J16 nRSTOUT/GPA21 nRSTOUT –/– O(L)/– O(L) b8
J15 PWREN PWREN O(H) O(L) O(H) b8
J12 nRESET nRESET – – I is
J14 VDDalive VDDalive P P P d1i
J11 EXTCLK EXTCLK – – AI is
J13 VDDi VDDi P P P d1c
H17 XTIpll XTIpll – – AI m26
H16 XTOpll XTOpll – – AO m26
H15 VSSi VSSi P P P s3i
H13 VSSOP VSSOP P P P s3o
H14 VDDMOP VDDMOP P P P d3o
G17 nFCE/GPA22 nFCE O(H)/– O(H)/– O(H) b8
G16 nFRE/GPA20 nFRE O(H)/– O(H)/– O(H) b8
G15 nFWE/GPA19 nFWE O(H)/– O(H)/– O(H) b8
G14 ALE/GPA18 ALE O(L)/– O(L)/– O(L) b8
H12 CLE/GPA17 CLE O(L)/– O(L)/– O(L) b8
G13 nWAIT nWAIT – – I is
F17 nGCS7:nSCS1 nGCS7 Hi-z O(H) O(H) ot
F16 nGCS6:nSCS0 nGCS6 Hi-z O(H) O(H) ot
F15 nGCS5/GPA16 nGCS5 Hi-z O(H)/– O(H) ot
E17 nGCS4/GPA15 nGCS4 Hi-z O(H)/– O(H) ot
E14 nGCS3/GPA14 nGCS3 Hi-z O(H)/– O(H) ot
E16 nGCS2/GPA13 nGCS2 Hi-z O(H)/– O(H) ot
E15 nGCS1/GPA12 nGCS1 Hi-z O(H)/– O(H) ot
D17 nGCS0 nGCS0 Hi-z O(H) O(H) ot
D16 SCKE SCKE Hi-z O(L) O(H) ot
D15 VSSMOP VSSMOP P P P s3o
F14 SCLK1 SCLK1 Hi-z O(L) O(SCLK) t16
C17 VDDi VDDi P P P d1c
F13 SCLK0 SCLK0 Hi-z O(L) O(SCLK) t16
1-15
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PRODUCT OVERVIEW S3C2410A
Table 1-2. 272-Pin FBGA Pin Assignments (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
B17 VSSi VSSi P P P s3i
E13 nWE nWE Hi-z O(H) O(H) ot
C16 nOE nOE Hi-z O(H) O(H) ot
A17 nBE0:nWBE0:DQM0 DQM0 Hi-z O(H) O(H) ot
B16 nBE1:nWBE1:DQM1 DQM1 Hi-z O(H) O(H) ot
C15 nBE2:nWBE2:DQM2 DQM2 Hi-z O(H) O(H) ot
A16 nBE3:nWBE3:DQM3 DQM3 Hi-z O(H) O(H) ot
B15 nSRAS nSRAS Hi-z O(H) O(H) ot
C14 nSCAS nSCAS Hi-z O(H) O(H) ot
A15 VDDMOP VDDMOP P P P d3o
F12 VSSMOP VSSMOP P P P s3o
B14 ADDR0/GPA0 ADDR0 Hi-z/– O(L)/– O(L) ot
D14 ADDR1 ADDR1 Hi-z O(L) O(L) ot
A14 ADDR2 ADDR2 Hi-z O(L) O(L) ot
C13 ADDR3 ADDR3 Hi-z O(L) O(L) ot
B13 ADDR4 ADDR4 Hi-z O(L) O(L) ot
I/O Type
D13 ADDR5 ADDR5 Hi-z O(L) O(L) ot
A13 ADDR6 ADDR6 Hi-z O(L) O(L) ot
C12 ADDR7 ADDR7 Hi-z O(L) O(L) ot
B12 ADDR8 ADDR8 Hi-z O(L) O(L) ot
G12 ADDR9 ADDR9 Hi-z O(L) O(L) ot
A12 VSSMOP VSSMOP P P P s3o
E11 VDDMOP VDDMOP P P P d3o
D12 ADDR10 ADDR10 Hi-z O(L) O(L) ot
E12 ADDR11 ADDR11 Hi-z O(L) O(L) ot
D11 VDDi VDDi P P P d1c
F11 VSSi VSSi P P P s3i
B11 ADDR12 ADDR12 Hi-z O(L) O(L) ot
A11 ADDR13 ADDR13 Hi-z O(L) O(L) ot
C11 ADDR14 ADDR14 Hi-z O(L) O(L) ot
G11 ADDR15 ADDR15 Hi-z O(L) O(L) ot
A10 ADDR16/GPA1 ADDR16 Hi-z O(L)/– O(L) ot
B10 ADDR17/GPA2 ADDR17 Hi-z O(L)/– O(L) ot
1-16
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S3C2410A PRODUCT OVERVIEW
Table 1-2. 272-Pin FBGA Pin Assignments (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
C10 VSSMOP VSSMOP P P P s3o
E10 ADDR18/GPA3 ADDR18 Hi-z/– O(L) O(L) ot
D10 ADDR19/GPA4 ADDR19 Hi-z/– O(L) O(L) ot
F10 ADDR20/GPA5 ADDR20 Hi-z/– O(L) O(L) ot
A9 ADDR21/GPA6 ADDR21 Hi-z/– O(L) O(L) ot
D9 ADDR22/GPA7 ADDR22 Hi-z/– O(L) O(L) ot
E9 ADDR23/GPA8 ADDR23 Hi-z/– O(L) O(L) ot
B9 ADDR24/GPA9 ADDR24 Hi-z/– O(L) O(L) ot
C9 ADDR25/GPA10 ADDR25 Hi-z/– O(L) O(L) ot
E8 ADDR26/GPA11 ADDR26 Hi-z/– O(L) O(L) ot
C8 VDDi VDDi P P P d1c
F9 VSSi VSSi P P P s3i
D8 VDDMOP VDDMOP P P P d3o
G9 VSSMOP VSSMOP P P P s3o
B8 DATA0 DATA0 Hi-z Hi-z Hi-z t12
A8 DATA1 DATA1 Hi-z Hi-z Hi-z t12
I/O Type
D7 DATA2 DATA2 Hi-z Hi-z Hi-z t12
E7 DATA3 DATA3 Hi-z Hi-z Hi-z t12
C7 DATA4 DATA4 Hi-z Hi-z Hi-z t12
B7 DATA5 DATA5 Hi-z Hi-z Hi-z t12
A7 DATA6 DATA6 Hi-z Hi-z Hi-z t12
C6 DATA7 DATA7 Hi-z Hi-z Hi-z t12
A6 VDDMOP VDDMOP P P P d3o
F8 VSSMOP VSSMOP P P P s3o
F7 DATA8 DATA8 Hi-z Hi-z Hi-z t12
B6 DATA9 DATA9 Hi-z Hi-z Hi-z t12
D6 DATA10 DATA10 Hi-z Hi-z Hi-z t12
A5 DATA11 DATA11 Hi-z Hi-z Hi-z t12
C5 DATA12 DATA12 Hi-z Hi-z Hi-z t12
B5 DATA13 DATA13 Hi-z Hi-z Hi-z t12
D5 DATA14 DATA14 Hi-z Hi-z Hi-z t12
A4 DATA15 DATA15 Hi-z Hi-z Hi-z t12
B4 VDDMOP VDDMOP P P P d3o
1-17
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PRODUCT OVERVIEW S3C2410A
Table 1-2. 272-Pin FBGA Pin Assignments (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@PWR-off
I/O State
@nRESET
E6 VSSMOP VSSMOP P P P s3o
C4 VDDi VDDi P P P d1c
F6 VSSi VSSi P P P s3i
A3 DATA16 DATA16 Hi-z Hi-z Hi-z t12
B3 DATA17 DATA17 Hi-z Hi-z Hi-z t12
A2 DATA18 DATA18 Hi-z Hi-z Hi-z t12
A1 DATA19 DATA19 Hi-z Hi-z Hi-z t12
B2 DATA20 DATA20 Hi-z Hi-z Hi-z t12
NOTES:
1. The @BUS REQ. shows the pin states at the external bus, which is used by the other bus master.
2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode.
3. Hi-z or Pre means Hi-z or Previous state and it is determined by the setting of MISCCR register.
4. AI/AO means analog input/analog output.
5. P, I, and O mean power, input and output respectively.
6. The I/O state @nRESET shows the pin status in the @nRESET duration below.
I/O Type
nRESET
FCLK
@nRESET4FCLK
1-18
Page 49
S3C2410A PRODUCT OVERVIEW
7. The table below shows I/O types and the descriptions.
I/O Type Descriptions
d1i(vdd1ih), s3i(vss3i) 1.8V / 2.0V VDD/VSS for internal logic
d1c(vdd1ih_core), s3i(vss3i) 1.8V / 2.0V VDD/VSS for internal logic without input driver
d3o(vdd3op), s3o(vss3op) 3.3V VDD/VSS for external logic
d3t(vdd3t_abb), s3t(vss3t_abb) 3.3V VDD/VSS for analog circuitry
is(phis) Input pad, LVCMOS schmitt-trigger level
us(pbusb) USB pad
ot(phot8) Output pad, tri-state, Io = 8mA
b8(phob8) Output pad, Io = 8mA
t16(phot16sm) Output pad, tri-state, medium slew rate, Io = 16mA
r10(phiar10_abb) Analog input pad with 10Ω resistor
ia(phia_abb) Analog input pad
gp(phgpad_option) Pad for analog pin
m26(phsoscm26) Oscillator cell with enable and feedback resistor
t6(phtbsu100ct6sm) Bi-directional pad, 5V tolerant LVCMOS schmitt-trigger, 100Kohm pull-up
resistor with control, tri-state, Io = 6mA
t8(phbsu100ct8sm) Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with
control, tri-state, Io = 8mA
t12(phbsu100ct12sm) Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with
control, tri-state, Io = 12mA
d8(phbsu100cd8sm) Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with
control, open-drain, Io = 8mA
1-19
Page 50
PRODUCT OVERVIEW S3C2410A
SIGNAL DESCRIPTIONS
Table 1-3. S3C2410A Signal Descriptions
Signal I/O Descriptions
Bus Controller
OM [1:0] I OM [1:0] sets S3C2410A in the TEST mode, which is used only at fabrication. Also, it
determines the bus width of nGCS0. The pull-up/down resistor determines the logic
level during the RESET cycle.
00:Nand-boot 01:16-bit 10:32-bit 11:Test mode
ADDR [26:0] O ADDR [26:0] (Address Bus) outputs the memory address of the corresponding bank.
DATA [31:0] IO DATA [31:0] (Data Bus) inputs data during memory read and outputs data during
memory write. The bus width is programmable among 8/16/32-bit.
nGCS [7:0] O nGCS [7:0] (General Chip Select) are activated when the address of a memory is
within the address region of each bank. The number of access cycles and the bank
size can be programmed.
nWE O nWE (Write Enable) indicates that the current bus cycle is a write cycle.
nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle.
nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request control of the local
bus. BACK active indicates that bus control has been granted.
nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C2410A has surrendered
control of the local bus to another bus master.
nWAIT I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current
bus cycle cannot be completed.
If nWAIT signal isn't used in your system, nWAIT signal must be tied on pull-up
resistor.
SDRAM/SRAM
nSRAS O SDRAM Row Address Strobe
nSCAS O SDRAM Column Address Strobe
nSCS [1:0] O SDRAM Chip Select
DQM [3:0] O SDRAM Data Mask
SCLK [1:0] O SDRAM Clock
SCKE O SDRAM Clock Enable
nBE [3:0] O Upper Byte/Lower Byte Enable (In case of 16-bit SRAM)
nWBE [3:0] O Write Byte Enable
1-20
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S3C2410A PRODUCT OVERVIEW
Table 1-3. S3C2410A Signal Descriptions (Continued)
Signal I/O Descriptions
NAND Flash
CLE O Command Latch Enable
ALE O Address Latch Enable
nFCE O NAND Flash Chip Enable
nFRE O NAND Flash Read Enable
nFWE O NAND Flash Write Enable
NCON I NAND Flash Configuration.
If NAND Flash Controller isn't used, it has to be tied on pull-up resistor.
R/nB I NAND Flash Ready/Busy.
If NAND Flash Controller isn't used, it has to be tied on pull-up resistor.
LCD Control Unit
VD [23:0] O STN/TFT/SEC TFT: LCD Data Bus
LCD_PWREN O STN/TFT/SEC TFT: LCD panel power enable control signal
VCLK O STN/TFT: LCD clock signal
VFRAME O STN: LCD Frame signal
VLINE O STN: LCD line signal
VM O STN: VM alternates the polarity of the row and column voltage
VSYNC O TFT: Vertical synchronous signal
HSYNC O TFT: Horizontal synchronous signal
VDEN O TFT: Data enable signal
LEND O TFT: Line End signal
STV O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
CPV O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
LCD_HCLK O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
TP O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
STH O SEC TFT: SEC (Samsung Electronics Company) TFT LCD panel control signal
LCDVF [2:0] O SEC TFT: Timing control signal for specific TFT LCD (OE/REV/REVB)
Interrupt Control Unit
EINT [23:0] I External Interrupt request
DMA
nXDREQ [1:0] I External DMA request
nXDACK [1:0] O External DMA acknowledge
1-21
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PRODUCT OVERVIEW S3C2410A
Table 1-3. S3C2410A Signal Descriptions (Continued)
Signal I/O Descriptions
UART
RxD [2:0] I UART receives data input
TxD [2:0] O UART transmits data output
nCTS [1:0] I UART clear to send input signal
nRTS [1:0] O UART request to send output signal
UEXTCLK I UART clock signal
ADC
AIN [7:0] AI ADC input [7:0]. If it isn't used pin, it has to be in Ground.
Vref AI ADC Vref
IIC-Bus
IICSDA IO IIC-bus data
IICSCL IO IIC-bus clock
IIS-Bus
I2SLRCK IO IIS-bus channel select clock
I2SSDO O IIS-bus serial data output
I2SSDI I IIS-bus serial data input
I2SSCLK IO IIS-bus serial clock
CDCLK O CODEC system clock
Touch Screen
nXPON O Plus X-axis on-off control signal
XMON O Minus X-axis on-off control signal
nYPON O Plus Y-axis on-off control signal
YMON O Minus Y-axis on-off control signal
USB Host
DN [1:0] IO
DP [1:0] IO
DATA (–) from USB host. (15Kohm pull-down)
DATA (+) from USB host. (15Kohm pull-down)
USB Device
PDN0 IO
PDP0 IO
DATA (–) for USB peripheral. (470Kohm pull-down)
DATA (+) for USB peripheral. (1.5Kohm pull-up)
SPI
SPIMISO [1:0] IO SPIMISO is the master data input line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role.
SPIMOSI [1:0] IO SPIMOSI is the master data output line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role.
SPICLK [1:0] IO SPI clock
nSS [1:0] I SPI chip select (only for slave mode)
1-22
Page 53
S3C2410A PRODUCT OVERVIEW
Table 1-3. S3C2410A Signal Descriptions (Continued)
Signal I/O Description
SD
SDDAT [3:0] IO SD receive/transmit data
SDCMD IO SD receive response/ transmit command
SDCLK O SD clock
General Port
GPn [116:0] IO General input/output ports (some ports are output only)
TIMMER/PWM
TOUT [3:0] O Timer Output [3:0]
TCLK [1:0] I External timer clock input
JTAG TEST LOGIC
nTRST I nTRST (TAP Controller Reset) resets the TAP controller at start.
If debugger is used, A 10K pull-up resistor has to be connected.
If debugger (black ICE) is not used, nTRST pin must be issued by a low active pulse
(Typically connected to nRESET).
TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's
states. A 10K pull-up resistor has to be connected to TMS pin.
TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.
A 10K pull-up resistor must be connected to TCK pin.
TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data.
A 10K pull-up resistor must be connected to TDI pin.
TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and data.
Reset, Clock & Power
nRESET ST nRESET suspends any operation in progress and places S3C2410A into a known
reset state. For a reset, nRESET must be held to L level for at least 4 FCLK after the
processor power has been stabilized.
nRSTOUT O For external device reset control
(nRSTOUT = nRESET & nWDTRST & SW_RESET)
PWREN O 2.0V core power on-off control signal
nBATT_FLT I Probe for battery state (Does not wake up at power-off mode in case of low battery
state). If it isn't used, it has to be High (3.3V).
OM [3:2] I OM [3:2] determines how the clock is made.
OM [3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source.
OM [3:2] = 01b, Crystal is used for MPLL CLK source
and EXTCLK is used for UPLL CLK source.
OM [3:2] = 10b, EXTCLK is used for MPLL CLK source
and Crystal is used for UPLL CLK source.
OM [3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
1-23
Page 54
PRODUCT OVERVIEW S3C2410A
Table 1-3. S3C2410A Signal Descriptions (Continued)
Signal I/O Description
Reset, Clock & Power (Continued)
EXTCLK I External clock source.
When OM [3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
When OM [3:2] = 10b, EXTCLK is used for MPLL CLK source only.
When OM [3:2] = 01b, EXTCLK is used for UPLL CLK source only.
If it isn't used, it has to be High (3.3V).
XTIpll AI Crystal Input for internal osc circuit.
When OM [3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.
When OM [3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM [3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, XTIpll has to be High (3.3V).
XTOpll AO Crystal Output for internal osc circuit.
When OM [3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.
When OM [3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM [3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, it has to be a floating pin.
MPLLCAP AI Loop filter capacitor for main clock.
UPLLCAP AI Loop filter capacitor for USB clock.
XTIrtc AI 32.768 kHz crystal input for RTC. If it isn't used, it has to be in High (RTCVDD = 1.8V).
XTOrtc AO 32.768 kHz crystal output for RTC. If it isn't used, it has to be Float.
CLKOUT [1:0] O Clock output signal. The CLKSEL of MISCCR register configures the clock output
mode among the MPLL CLK, UPLL CLK, FCLK, HCLK and PCLK.
1-24
Page 55
S3C2410A PRODUCT OVERVIEW
Table 1-3. S3C2410A Signal Descriptions (Continued)
Signal I/O Description
Power
VDDalive P S3C2410A reset block and port status register VDD (1.8V / 2.0V).
It should be always supplied whether in normal mode or in power-off mode.
VDDi/VDDiarm P S3C2410A core logic VDD (1.8V / 2.0V) for CPU.
VSSi/VSSiarm P S3C2410A core logic V
SS
VDDi_MPLL P S3C2410A MPLL analog and digital VDD (1.8V / 2.0V).
VSSi_MPLL P S3C2410A MPLL analog and digital VSS.
VDDOP P S3C2410A I/O port VDD (3.3V)
VDDMOP P S3C2410A Memory I/O V
DD
3.3V: SCLK up to 133MHz
VSSMOP P S3C2410A Memory I/O V
VSSOP P S3C2410A I/O port V
SS
SS
RTCVDD P RTC VDD (1.8 V, Not support 2.0 and 3.3V)
(This pin must be connected to power properly if RTC isn't used)
VDDi_UPLL P S3C2410A UPLL analog and digital VDD (1.8V / 2.0V)
VSSi_UPLL P S3C2410A UPLL analog and digital V
SS
VDDA_ADC P S3C2410A ADC VDD (3.3V)
VSSA_ADC P S3C2410A ADC V
NOTES:
1. I/O means input/output.
2. AI/AO means analog input/analog output.
3. ST means schmitt-trigger.
4. P means power.
SS
1-25
Page 56
PRODUCT OVERVIEW S3C2410A
S3C2410A SPECIAL REGISTERS
Table 1-4. S3C2410A Special Registers
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
Memory Controller
BWSCON 0x48000000 ← W R/W Bus Width & Wait Status Control
BANKCON0 0x48000004 Boot ROM Control
BANKCON1 0x48000008 BANK1 Control
BANKCON2 0x4800000C BANK2 Control
BANKCON3 0x48000010 BANK3 Control
BANKCON4 0x48000014 BANK4 Control
BANKCON5 0x48000018 BANK5 Control
BANKCON6 0x4800001C BANK6 Control
BANKCON7 0x48000020 BANK7 Control
REFRESH 0x48000024 DRAM/SDRAM Refresh Control
BANKSIZE 0x48000028 Flexible Bank Size
MRSRB6 0x4800002C Mode register set for SDRAM
MRSRB7 0x48000030 Mode register set for SDRAM
1-26
Page 57
S3C2410A PRODUCT OVERVIEW
Table 1-4. S3C2410A Special Registers (Continued)
Register Name Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
USB Host Controller
HcRevision 0x49000000 ← W Control and Status Group
HcControl 0x49000004
HcCommonStatus 0x49000008
HcInterruptStatus 0x4900000C
HcInterruptEnable 0x49000010
HcInterruptDisable 0x49000014
HcHCCA 0x49000018 Memory Pointer Group
HcPeriodCuttentED 0x4900001C
HcControlHeadED 0x49000020
HcControlCurrentED 0x49000024
HcBulkHeadED 0x49000028
HcBulkCurrentED 0x4900002C
HcDoneHead 0x49000030
HcRmInterval 0x49000034 Frame Counter Group
HcFmRemaining 0x49000038
HcFmNumber 0x4900003C
HcPeriodicStart 0x49000040
HcLSThreshold 0x49000044
HcRhDescriptorA 0x49000048 Root Hub Group
HcRhDescriptorB 0x4900004C
HcRhStatus 0x49000050
HcRhPortStatus1 0x49000054
HcRhPortStatus2 0x49000058
Interrupt Controller
SRCPND 0X4A000000 ← W R/W Interrupt Request Status
INTMOD 0X4A000004 W Interrupt Mode Control
INTMSK 0X4A000008 R/W Interrupt Mask Control
PRIORITY 0X4A00000C W IRQ Priority Control
INTPND 0X4A000010 R/W Interrupt Request Status
INTOFFSET 0X4A000014 R Interrupt request source offset
SUBSRCPND 0X4A000018 R/W Sub source pending
INTSUBMSK 0X4A00001C R/W Interrupt sub mask
1-27
Page 58
PRODUCT OVERVIEW S3C2410A
Table 1-4. S3C2410A Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
DMA
DISRC0 0x4B000000 ← W R/W DMA 0 Initial Source
DISRCC0 0x4B000004 DMA 0 Initial Source Control
DIDST0 0x4B000008 DMA 0 Initial Destination
DIDSTC0 0x4B00000C DMA 0 Initial Destination Control
DCON0 0x4B000010 DMA 0 Control
DSTAT0 0x4B000014 R DMA 0 Count
DCSRC0 0x4B000018 DMA 0 Current Source
DCDST0 0x4B00001C DMA 0 Current Destination
DMASKTRIG0 0x4B000020 ← W R/W DMA 0 Mask Trigger
DISRC1 0x4B000040 DMA 1 Initial Source
DISRCC1 0x4B000044 DMA 1 Initial Source Control
DIDST1 0x4B000048 DMA 1 Initial Destination
DIDSTC1 0x4B00004C DMA 1 Initial Destination Control
DCON1 0x4B000050 DMA 1 Control
DSTAT1 0x4B000054 R DMA 1 Count
DCSRC1 0x4B000058 DMA 1 Current Source
DCDST1 0x4B00005C ← W DMA 1 Current Destination
DMASKTRIG1 0x4B000060 R/W DMA 1 Mask Trigger
DISRC2 0x4B000080 DMA 2 Initial Source
DISRCC2 0x4B000084 DMA 2 Initial Source Control
DIDST2 0x4B000088 DMA 2 Initial Destination
DIDSTC2 0x4B00008C DMA 2 Initial Destination Control
DCON2 0x4B000090 DMA 2 Control
DSTAT2 0x4B000094 R DMA 2 Count
DCSRC2 0x4B000098 ← W DMA 2 Current Source
DCDST2 0x4B00009C DMA 2 Current Destination
DMASKTRIG2 0x4B0000A0 R/W DMA 2 Mask Trigger
DISRC3 0x4B0000C0 ← W R/W DMA 3 Initial Source
DISRCC3 0x4B0000C4 DMA 3 Initial Source Control
DIDST3 0x4B0000C8 DMA 3 Initial Destination
DIDSTC3 0x4B0000CC DMA 3 Initial Destination Control
DCON3 0x4B0000D0 DMA 3 Control
DSTAT3 0x4B0000D4 R DMA 3 Count
DCSRC3 0x4B0000D8 DMA 3 Current Source
DCDST3 0x4B0000DC DMA 3 Current Destination
DMASKTRIG3 0x4B0000E0 R/W DMA 3 Mask Trigger
1-28
Page 59
S3C2410A PRODUCT OVERVIEW
Table 1-4. S3C2410A Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
Clock & Power Management
LOCKTIME 0x4C000000 ← W R/W PLL Lock Time Counter
MPLLCON 0x4C000004 MPLL Control
UPLLCON 0x4C000008 UPLL Control
CLKCON 0x4C00000C Clock Generator Control
CLKSLOW 0x4C000010 Slow Clock Control
CLKDIVN 0x4C000014 Clock divider Control
LCD Controller
LCDCON1 0X4D000000 ← W R/W LCD Control 1
LCDCON2 0X4D000004 LCD Control 2
LCDCON3 0X4D000008 LCD Control 3
LCDCON4 0X4D00000C LCD Control 4
LCDCON5 0X4D000010 LCD Control 5
LCDSADDR1 0X4D000014 STN/TFT: Frame Buffer Start Address1
LCDSADDR2 0X4D000018 STN/TFT: Frame Buffer Start Address2
LCDSADDR3 0X4D00001C STN/TFT: Virtual Screen Address Set
REDLUT 0X4D000020 STN: Red Lookup Table
GREENLUT 0X4D000024 STN: Green Lookup Table
BLUELUT 0X4D000028 STN: Blue Lookup Table
DITHMODE 0X4D00004C STN: Dithering Mode
TPAL 0X4D000050 TFT: Temporary Palette
LCDINTPND 0X4D000054 LCD Interrupt Pending
LCDSRCPND 0X4D000058 LCD Interrupt Source
LCDINTMSK 0X4D00005C LCD Interrupt Mask
LPCSEL 0X4D000060 LPC3600 Control
NAND Flash
NFCONF 0x4E000000 ← W R/W NAND Flash Configuration
NFCMD 0x4E000004 NAND Flash Command
NFADDR 0x4E000008 NAND Flash Address
NFDATA 0x4E00000C NAND Flash Data
NFSTAT 0x4E000010 R NAND Flash Operation Status
NFECC 0x4E000014 R/W NAND Flash ECC
1-29
Page 60
PRODUCT OVERVIEW S3C2410A
Table 1-4. S3C2410A Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
UART
ULCON0 0x50000000 ← W R/W UART 0 Line Control
UCON0 0x50000004 UART 0 Control
UFCON0 0x50000008 UART 0 FIFO Control
UMCON0 0x5000000C UART 0 Modem Control
UTRSTAT0 0x50000010 R UART 0 Tx/Rx Status
UERSTAT0 0x50000014 UART 0 Rx Error Status
UFSTAT0 0x50000018 UART 0 FIFO Status
UMSTAT0 0x5000001C UART 0 Modem Status
UTXH0 0x50000023 0x50000020 B W UART 0 Transmission Hold
URXH0 0x50000027 0x50000024 R UART 0 Receive Buffer
UBRDIV0 0x50000028 ← W R/W UART 0 Baud Rate Divisor
ULCON1 0x50004000 ← W R/W UART 1 Line Control
UCON1 0x50004004 UART 1 Control
UFCON1 0x50004008 UART 1 FIFO Control
UMCON1 0x5000400C UART 1 Modem Control
UTRSTAT1 0x50004010 R UART 1 Tx/Rx Status
UERSTAT1 0x50004014 UART 1 Rx Error Status
UFSTAT1 0x50004018 UART 1 FIFO Status
UMSTAT1 0x5000401C UART 1 Modem Status
UTXH1 0x50004023 0x50004020 B W UART 1 Transmission Hold
URXH1 0x50004027 0x50004024 R UART 1 Receive Buffer
UBRDIV1 0x50004028 ← W R/W UART 1 Baud Rate Divisor
ULCON2 0x50008000 ← W R/W UART 2 Line Control
UCON2 0x50008004 UART 2 Control
UFCON2 0x50008008 UART 2 FIFO Control
UTRSTAT2 0x50008010 R UART 2 Tx/Rx Status
UERSTAT2 0x50008014 UART 2 Rx Error Status
UFSTAT2 0x50008018 UART 2 FIFO Status
UTXH2 0x50008023 0x50008020 B W UART 2 Transmission Hold
URXH2 0x50008027 0x50008024 R UART 2 Receive Buffer
UBRDIV2 0x50008028 ← W R/W UART 2 Baud Rate Divisor
1-30
Page 61
S3C2410A PRODUCT OVERVIEW
Table 1-4. S3C2410A Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
PWM Timer
TCFG0 0x51000000 ← W R/W Timer Configuration
TCFG1 0x51000004 Timer Configuration
TCON 0x51000008 Timer Control
TCNTB0 0x5100000C Timer Count Buffer 0
TCMPB0 0x51000010 Timer Compare Buffer 0
TCNTO0 0x51000014 R Timer Count Observation 0
TCNTB1 0x51000018 R/W Timer Count Buffer 1
TCMPB1 0x5100001C Timer Compare Buffer 1
TCNTO1 0x51000020 R Timer Count Observation 1
TCNTB2 0x51000024 R/W Timer Count Buffer 2
TCMPB2 0x51000028 Timer Compare Buffer 2
TCNTO2 0x5100002C R Timer Count Observation 2
TCNTB3 0x51000030 R/W Timer Count Buffer 3
TCMPB3 0x51000034 Timer Compare Buffer 3
TCNTO3 0x51000038 R Timer Count Observation 3
TCNTB4 0x5100003C R/W Timer Count Buffer 4
TCNTO4 0x51000040 R Timer Count Observation 4
1-31
Page 62
PRODUCT OVERVIEW S3C2410A
Table 1-4. S3C2410A Special Registers (Continued)
Register Name Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
USB Device
FUNC_ADDR_REG 0x52000143 0x52000140 B R/W Function Address
PWR_REG 0x52000147 0x52000144 Power Management
EP_INT_REG 0x5200014B 0x52000148 EP Interrupt Pending and Clear
USB_INT_REG 0x5200015B 0x52000158 USB Interrupt Pending and Clear
EP_INT_EN_REG 0x5200015F 0x5200015C Interrupt Enable
USB_INT_EN_REG 0x5200016F 0x5200016C Interrupt Enable
FRAME_NUM1_REG 0x52000173 0x52000170 R Frame Number Lower Byte
INDEX_REG 0x5200017B 0x52000178 R/W Register Index
EP0_CSR 0x52000187 0x52000184 Endpoint 0 Status
IN_CSR1_REG 0x52000187 0x52000184 In Endpoint Control Status
IN_CSR2_REG 0x5200018B 0x52000188 In Endpoint Control Status
MAXP_REG 0x52000183 0x52000180 Endpoint Max Packet
OUT_CSR1_REG 0x52000193 0x52000190 Out Endpoint Control Status
OUT_CSR2_REG 0x52000197 0x52000194 Out Endpoint Control Status
OUT_FIFO_CNT1_REG 0x5200019B 0x52000198 R Endpoint Out Write Count
OUT_FIFO_CNT2_REG 0x5200019F 0x5200019C Endpoint Out Write Count
EP0_FIFO 0x520001C3 0x520001C0 R/W Endpoint 0 FIFO
EP1_FIFO 0x520001C7 0x520001C4 Endpoint 1 FIFO
EP2_FIFO 0x520001CB 0x520001C8 Endpoint 2 FIFO
EP3_FIFO 0x520001CF 0x520001CC Endpoint 3 FIFO
EP4_FIFO 0x520001D3 0x520001D0 Endpoint 4 FIFO
EP1_DMA_CON 0x52000203 0x52000200 EP1 DMA Interface Control
EP1_DMA_UNIT 0x52000207 0x52000204 EP1 DMA Tx Unit Counter
EP1_DMA_FIFO 0x5200020B 0x52000208 EP1 DMA Tx FIFO Counter
EP1_DMA_TTC_L 0x5200020F 0x5200020C EP1 DMA Total Tx Counter
EP1_DMA_TTC_M 0x52000213 0x52000210 EP1 DMA Total Tx Counter
EP1_DMA_TTC_H 0x52000217 0x52000214 EP1 DMA Total Tx Counter
1-32
Page 63
S3C2410A PRODUCT OVERVIEW
Table 1-4. S3C2410A Special Registers (Continued)
Register Name Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/W
rite
Function
USB Device (Continued)
EP2_DMA_CON 0x5200021B 0x52000218 B R/W EP2 DMA Interface Control
EP2_DMA_UNIT 0x5200021F 0x5200021C EP2 DMA Tx Unit Counter
EP2_DMA_FIFO 0x52000223 0x52000220 EP2 DMA Tx FIFO Counter
EP2_DMA_TTC_L 0x52000227 0x52000224 EP2 DMA Total Tx Counter
EP2_DMA_TTC_M 0x5200022B 0x52000228 EP2 DMA Total Tx Counter
EP2_DMA_TTC_H 0x5200022F 0x5200022C EP2 DMA Total Tx Counter
EP3_DMA_CON 0x52000243 0x52000240 EP3 DMA Interface Control
EP3_DMA_UNIT 0x52000247 0x52000244 EP3 DMA Tx Unit Counter
EP3_DMA_FIFO 0x5200024B 0x52000248 EP3 DMA Tx FIFO Counter
EP3_DMA_TTC_L 0x5200024F 0x5200024C EP3 DMA Total Tx Counter
EP3_DMA_TTC_M 0x52000253 0x52000250 EP3 DMA Total Tx Counter
EP3_DMA_TTC_H 0x52000257 0x52000254 EP3 DMA Total Tx Counter
EP4_DMA_CON 0x5200025B 0x52000258 EP4 DMA Interface Control
EP4_DMA_UNIT 0x5200025F 0x5200025C EP4 DMA Tx Unit Counter
EP4_DMA_FIFO 0x52000263 0x52000260 EP4 DMA Tx FIFO Counter
EP4_DMA_TTC_L 0x52000267 0x52000264 EP4 DMA Total Tx Counter
EP4_DMA_TTC_M 0x5200026B 0x52000268 EP4 DMA Total Tx Counter
EP4_DMA_TTC_H 0x5200026F 0x5200026C EP4 DMA Total Tx Counter
Watchdog Timer
WTCON 0x53000000 ← W R/W Watchdog Timer Mode
WTDAT 0x53000004 Watchdog Timer Data
WTCNT 0x53000008 Watchdog Timer Count
IIC
IICCON 0x54000000 ← W R/W IIC Control
IICSTAT 0x54000004 IIC Status
IICADD 0x54000008 IIC Address
IICDS 0x5400000C IIC Data Shift
IIS
IISCON 0x55000000,02 0x55000000 HW,W R/W IIS Control
IISMOD 0x55000004,06 0x55000004 HW,W IIS Mode
IISPSR 0x55000008,0A 0x55000008 HW,W IIS Prescaler
IISFCON 0x5500000C,0E 0x5500000C HW,W IIS FIFO Control
IISFIFO 0x55000012 0x55000010 HW IIS FIFO Entry
1-33
Page 64
PRODUCT OVERVIEW S3C2410A
Table 1-4. S3C2410A Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
I/O port
GPACON 0x56000000 ← W R/W Port A Control
GPADAT 0x56000004 Port A Data
GPBCON 0x56000010 Port B Control
GPBDAT 0x56000014 Port B Data
GPBUP 0x56000018 Pull-up Control B
GPCCON 0x56000020 Port C Control
GPCDAT 0x56000024 Port C Data
GPCUP 0x56000028 Pull-up Control C
GPDCON 0x56000030 Port D Control
GPDDA1T 0x56000034 Port D Data
GPDUP 0x56000038 Pull-up Control D
GPECON 0x56000040 Port E Control
GPEDAT 0x56000044 Port E Data
GPEUP 0x56000048 Pull-up Control E
GPFCON 0x56000050 Port F Control
GPFDAT 0x56000054 Port F Data
GPFUP 0x56000058 Pull-up Control F
GPGCON 0x56000060 Port G Control
GPGDAT 0x56000064 Port G Data
GPGUP 0x56000068 Pull-up Control G
GPHCON 0x56000070 Port H Control
GPHDAT 0x56000074 Port H Data
GPHUP 0x56000078 Pull-up Control H
MISCCR 0x56000080 ← W R/W Miscellaneous Control
DCLKCON 0x56000084 DCLK0/1 Control
EXTINT0 0x56000088 External Interrupt Control Register 0
EXTINT1 0x5600008C External Interrupt Control Register 1
EXTINT2 0x56000090 External Interrupt Control Register 2
EINTFLT0 0x56000094 Reserved
EINTFLT1 0x56000098 Reserved
EINTFLT2 0x5600009C External Interrupt Filter Control Register 2
EINTFLT3 0x560000A0 External Interrupt Filter Control Register 3
EINTMASK 0x560000A4 External Interrupt Mask
EINTPEND 0x560000A8 External Interrupt Pending
GSTATUS0 0x560000AC External Pin Status
GSTATUS1 0x560000B0 External Pin Status
1-34
Page 65
S3C2410A PRODUCT OVERVIEW
Table 1-4. S3C2410A Special Registers (Continued)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
RTC
RTCCON 0x57000043 0x57000040 B R/W RTC Control
TICNT 0x57000047 0x57000044 Tick time count
RTCALM 0x57000053 0x57000050 RTC Alarm Control
ALMSEC 0x57000057 0x57000054 Alarm Second
ALMMIN 0x5700005B 0x57000058 Alarm Minute
ALMHOUR 0x5700005F 0x5700005C Alarm Hour
ALMDATE 0x57000063 0x57000060 Alarm Day
ALMMON 0x57000067 0x57000064 Alarm Month
ALMYEAR 0x5700006B 0x57000068 Alarm Year
RTCRST 0x5700006F 0x5700006C RTC Round Reset
BCDSEC 0x57000073 0x57000070 BCD Second
BCDMIN 0x57000077 0x57000074 BCD Minute
BCDHOUR 0x5700007B 0x57000078 BCD Hour
BCDDATE 0x5700007F 0x5700007C BCD Day
BCDDAY 0x57000083 0x57000080 BCD Date
BCDMON 0x57000087 0x57000084 BCD Month
BCDYEAR 0x5700008B 0x57000088 BCD Year
A/D converter
ADCCON 0x58000000 ← W R/W ADC Control
ADCTSC 0x58000004 ADC Touch Screen Control
ADCDLY 0x58000008 ADC Start or Interval Delay
ADCDAT0 0x5800000C R ADC Conversion Data
ADCDAT1 0x58000010 ADC Conversion Data
SPI
SPCON0,1 0x59000000,20 ← W R/W SPI Control
SPSTA0,1 0x59000004,24 R SPI Status
SPPIN0,1 0x59000008,28 R/W SPI Pin Control
SPPRE0,1 0x5900000C,2C SPI Baud Rate Prescaler
SPTDAT0,1 0x59000010,30 SPI Tx Data
SPRDAT0,1 0x59000014,34 R SPI Rx Data
1-35
Page 66
PRODUCT OVERVIEW S3C2410A
Table 1-4. S3C2410A Special Registers (Continued)
Register Name Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
SD interface
SDICON 0x5A000000 ← W R/W SDI Control
SDIPRE 0x5A000004 SDI Baud Rate Prescaler
SDICmdArg 0x5A000008 SDI Command Argument
SDICmdCon 0x5A00000C SDI Command Control
SDICmdSta 0x5A000010 R/(C) SDI Command Status
SDIRSP0 0x5A000014 R SDI Response
SDIRSP1 0x5A000018 SDI Response
SDIRSP2 0x5A00001C SDI Response
SDIRSP3 0x5A000020 SDI Response
SDIDTimer 0x5A000024 R/W SDI Data / Busy Timer
SDIBSize 0x5A000028 SDI Block Size
SDIDatCon 0x5A00002C SDI Data control
SDIDatCnt 0x5A000030 R SDI Data Remain Counter
SDIDatSta 0x5A000034 R/(C) SDI Data Status
SDIFSTA 0x5A000038 R SDI FIFO Status
SDIDAT 0x5A00003F 0x5A00003C B R/W SDI Data
SDIIntMsk 0x5A000040 ← W SDI Interrupt Mask
Cautions on S3C2410A Special Registers
1. In the little endian mode, L. endian address must be used. In the big endian mode, B. endian address must be
used.
2. The special registers have to be accessed for each recommended access unit.
3. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32-bit)
at little/big endian.
4. Make sure that the ADC registers, RTC registers and UART registers be read/written by the specified access
unit and the specified address. Moreover, one must carefully consider which endian mode is used.
5. W : 32-bit register, which must be accessed by LDR/STR or int type pointer(int *).
HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer(short int *).
B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer(char int *).
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S3C2410A PROGRAMMER'S MODEL
2 PROGRAMMER'S MODEL
OVERVIEW
S3C2410A has been developed using the advanced ARM920T core, which has been designed by Advanced RISC
Machines, Ltd.
PROCESSOR OPERATING STATES
From the programmer's point of view, the ARM920T can be in one of two states:
• ARM state which executes 32-bit, word-aligned ARM instructions.
• THUMB state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1 to
select between alternate halfwords.
NOTE
Transition between these two states does not affect the processor mode or the contents of the registers.
SWITCHING STATE
Entering THUMB State
Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand
register.
Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT,
SWI etc.), if the exception was entered with the processor in THUMB state.
Entering ARM State
Entry into ARM state happens:
• On execution of the BX instruction with the state bit clear in the operand register.
• On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is
placed in the exception mode's link register, and execution commences at the exception's vector address.
MEMORY FORMATS
ARM920T views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first
stored word, bytes 4 to 7 the second and so on. ARM920T can treat words in memory as being stored either in BigEndian or Little-Endian format.
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PROGRAMMER'S MODEL S3C2410A
BIG-ENDIAN FORMAT
In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31
through 24.
Higher Address
Lower Address
31
8
4
0
Most significant byte is at lowest address.
Word is addressed by byte address of most significant byte.
23
24 1516
9
5
1
10
6
2
8 7 0
11
7
3
Word Address
8
4
0
Figure 2-1. Big-Endian Addresses of Bytes within Words
LITTLE-ENDIAN FORMAT
In Little-Endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the
highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7
through 0.
Higher Address
31 23 8 7 0
24 1516
Word Address
8
4
0
Lower Address
11
7
3
Least significant byte is at lowest address.
Word is addressed by byte address of least significant byte.
10
6
2
9
5
1
8
4
0
Figure 2-2. Little-Endian Addresses of Bytes within Words
INSTRUCTION LENGTH
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
Data Types
ARM920T supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to four-byte
boundaries and half words to two-byte boundaries.
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S3C2410A PROGRAMMER'S MODEL
OPERATING MODES
ARM920T supports seven modes of operation:
• User (usr): The normal ARM program execution state
• FIQ (fiq): Designed to support a data transfer or channel process
• IRQ (irq): Used for general-purpose interrupt handling
• Supervisor (svc): Protected mode for the operating system
• Abort mode (abt): Entered after a data or instruction prefetch abort
• System (sys): A privileged user mode for the operating system
• Undefined (und): Entered when an undefined instruction is executed
Mode changes may be made under software control, or may be brought about by external interrupts or exception
processing. Most application programs will execute in User mode. The non-user modes' known as privileged modesare entered in order to service interrupts or exceptions, or to access protected resources.
REGISTERS
ARM920T has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot
all be seen at once. The processor state and operating mode dictate which registers are available to the programmer.
The ARM State Register Set
In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (nonUser) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in each
mode: the banked registers are marked with a shaded triangle.
The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are generalpurpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register
used to store status information.
Register 14 is used as the subroutine link register. This receives a copy of R15 when a Branch and
Link (BL) instruction is executed. At all other times it may be treated as a generalpurpose register. The corresponding banked registers R14_svc, R14_irq, R14_fiq,
R14_abt and R14_und are similarly used to hold the return values of R15 when
interrupts and exceptions arise, or when Branch and Link instructions are executed
within interrupt or exception routines.
Register 15 holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits
[31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC.
Register 16 is the CPSR (Current Program Status Register). This contains condition code flags
and the current mode bits.
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not
need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to
R13 and R14, allowing each of these modes to have a private stack pointer and link registers.
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PROGRAMMER'S MODEL S3C2410A
ARM State General Registers and Program Counter
System & User
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
CPSR CPSR
FIQ
R0
R1
R2
R3
R4
R5
R6
R7
R8_
fiq
R9_
fiq
R10_
fiq
R11_
fiq
R12_
fiq
R13_
fiq
R14_
fiq
R15 (PC)
Supervisor IRQAbort Undefined
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_
svc
R14_
svc
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_
R14_
R15 (PC)
ARM State Program Status Registers
CPSR
SPSR_
SPSR_
fiq
CPSR
SPSR_
svc
abt
abt
abt
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_
irq
R14_
irq
R15 (PC)
CPSR
SPSR_irq
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_
R14_
R15 (PC)
CPSR
SPSR_
und
und
und
2-4
= banked register
Figure 2-3. Register Organization in ARM State
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S3C2410A PROGRAMMER'S MODEL
The THUMB State Register Set
The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general
registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the
CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each
privileged mode. This is shown in Figure 2-4.
THUMB State General Registers and Program Counter
System & User
R0
R1
R2
R3
R4
R5
R6
R7
SP
LR
PC
CPSR CPSR
= banked register
FIQ
R0
R1
R2
R3
R4
R5
R6
R7
SP_
LR_
PC
fiq
fiq
Supervisor IRQAbort Undefined
R0
R1
R2
R3
R4
R5
R6
R7
SP_
LR_
PC
svc
svc
R0
R1
R2
R3
R4
R5
R6
R7
SP_
LR_
PC
abt
abt
THUMB State Program Status Registers
SPSR_
fiq
CPSR
SPSR_
svc
CPSR
SPSR_
abt
R0
R1
R2
R3
R4
R5
R6
R7
SP_
LR_
und
PC
CPSR
SPSR_
und
irq
R0
R1
R2
R3
R4
R5
R6
R7
SP_
LR_
fiq
PC
CPSR
SPSR_
fiq
und
Figure 2-4. Register Organization in THUMB state
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PROGRAMMER'S MODEL S3C2410A
The relationship between ARM and THUMB state registers
The THUMB state registers relate to the ARM state registers in the following way:
• THUMB state R0-R7 and ARM state R0-R7 are identical
• THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical
• THUMB state SP maps onto ARM state R13
• THUMB state LR maps onto ARM state R14
• The THUMB state Program Counter maps onto the ARM state Program Counter (R15)
This relationship is shown in Figure 2-5.
THUMB state ARM state
R0
R1
R2
R3
R4
R5
R6
R7
Stack Pointer (SP)
Link register (LR)
Program Counter (PC)
CPSR
SPSR
Stack Pointer (R13)
Link register (R14)
Program Counter (R15)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
CPSR
SPSR
Lo-registersHi-registers
Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers
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S3C2410A PROGRAMMER'S MODEL
Accessing Hi-Registers in THUMB State
In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly
language programmer has limited access to them, and can use them for fast temporary storage.
A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register, and from a Hi register to
a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or
added to Lo register values with the CMP and ADD instructions. For more information, refer to Figure 3-34.
THE PROGRAM STATUS REGISTERS
The ARM920T contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers
(SPSRs) for use by exception handlers. These register's functions are:
• Hold information about the most recently performed ALU operation
• Control the enabling and disabling of interrupts
• Set the processor operating mode
The arrangement of bits is shown in Figure 2-6.
Condition Code Flags
31
30 29 2728 26 25 24 23 8 7 6 5 4 3 2 1 0
N Z C V I F T M4 M3 M2 M1 M0
Overflow
Carry/Borrow/Extend
Zero
Negative/Less Than
(Reserved) Control Bits
~
~
~
~
Mode bits
State bit
FIQ disable
IRQ disable
Figure 2-6. Program Status Register Formats
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PROGRAMMER'S MODEL S3C2410A
The Condition Code Flags
The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical
operations, and may be tested to determine whether an instruction should be executed.
In ARM state, all instructions may be executed conditionally: see Table 3-2 for details.
In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details.
The Control Bits
The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will be
changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated
by software.
The T bit This reflects the operating state. When this bit is set, the processor is executing in THUMB
state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal.
Note that the software must never change the state of the TBIT in the CPSR. If this
happens, the processor will enter an unpredictable state.
Interrupt disable
bits
The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ
interrupts respectively.
The mode bits The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the
processor's operating mode, as shown in Table 2-1. Not all combinations of the mode bits
define a valid processor mode. Only those explicitly described shall be used. The user
should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the
processor will enter an unrecoverable state. If this occurs, reset should be applied.
Reserved bits
The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits,
you must ensure that these unused bits are not altered. Also, your program should not rely
on them containing specific values, since in future processors they may read as one or zero.
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S3C2410A PROGRAMMER'S MODEL
Table 2-1. PSR Mode Bit Values
M[4:0] Mode Visible THUMB state registers Visible ARM state registers
10000 User R7..R0,
LR, SP
PC, CPSR
10001 FIQ R7..R0,
LR_fiq, SP_fiq
PC, CPSR, SPSR_fiq
10010 IRQ R7..R0,
LR_irq, SP_irq
PC, CPSR, SPSR_irq
10011 Supervisor R7..R0,
LR_svc, SP_svc,
PC, CPSR, SPSR_svc
10111 Abort R7..R0,
LR_abt, SP_abt,
PC, CPSR, SPSR_abt
11011 Undefined R7..R0
LR_und, SP_und,
PC, CPSR, SPSR_und
11111 System R7..R0,
LR, SP
PC, CPSR
R14..R0,
PC, CPSR
R7..R0,
R14_fiq..R8_fiq,
PC, CPSR, SPSR_fiq
R12..R0,
R14_irq, R13_irq,
PC, CPSR, SPSR_irq
R12..R0,
R14_svc, R13_svc,
PC, CPSR, SPSR_svc
R12..R0,
R14_abt, R13_abt,
PC, CPSR, SPSR_abt
R12..R0,
R14_und, R13_und,
PC, CPSR
R14..R0,
PC, CPSR
Reserved bits The remaining bits in the PSR's are reserved. When changing a PSR's flag or control bits,
you must ensure that these unused bits are not altered. Also, your program should not rely
on them containing specific values, since in future processors they may read as one or
zero.
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PROGRAMMER'S MODEL S3C2410A
EXCEPTIONS
Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an
interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so
that the original program can resume when the handler routine has finished.
It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order.
See Exception Priorities on page 2-14.
Action on Entering an Exception
When handling an exception, the ARM920T:
1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered
from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4
or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from
THUMB state, then the value written into the Link Register is the current PC offset by a value such that the
program resumes from the correct place on return from the exception. This means that the exception handler
need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC,
R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or
THUMB state.
2. Copies the CPSR into the appropriate SPSR
3. Forces the CPSR mode bits to a value which depends on the exception
4. Forces the PC to fetch the next instruction from the relevant exception vector
It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions.
If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the
PC is loaded with the exception vector address.
Action on Leaving an Exception
On completion, the exception handler:
1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the
type of exception.)
2. Copies the SPSR back to the CPSR
3. Clears the interrupt disable flags, if they were set on entry
NOTE
An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR
automatically sets the T bit to the value it held immediately prior to the exception.
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S3C2410A PROGRAMMER'S MODEL
Exception Entry/Exit Summary
Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended
instruction for exiting the exception handler.
Table 2-2. Exception Entry/Exit
Return Instruction Previous State Notes
ARM R14_x THUMB R14_x
BL MOV PC, R14 PC + 4 PC + 2 1
SWI MOVS PC, R14_svc PC + 4 PC + 2 1
UDEF MOVS PC, R14_und PC + 4 PC + 2 1
FIQ SUBS PC, R14_fiq, #4 PC + 4 PC + 4 2
IRQ SUBS PC, R14_irq, #4 PC + 4 PC + 4 2
PABT SUBS PC, R14_abt, #4 PC + 4 PC + 4 1
DABT SUBS PC, R14_abt, #8 PC + 8 PC + 8 3
RESET NA – – 4
NOTES:
1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort.
2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority.
3. Where PC is the address of the Load or Store instruction which generated the data abort.
4. The value saved in R14_svc upon reset is unpredictable.
FIQ
The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM
state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context
switching).
FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or
asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ
are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the
processor flow.
Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt
by executing
SUBS PC,R14_fiq,#4
FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is
clear, ARM920T checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction.
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IRQ
The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a
lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting
the I bit in the CPSR, though this can only be done from a privileged (non-User) mode.
Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the
interrupt by executing
SUBS PC,R14_irq,#4
Abort
An abort indicates that the current memory access cannot be completed. It can be signaled by the external ABORT
input. ARM920T checks for the abort exception during memory access cycles.
There are two types of abort:
• Prefetch abort: occurs during an instruction prefetch.
• Data abort: occurs during a data access.
If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the
instruction reaches the head of the pipeline. If the instruction is not executed - for example because a branch occurs
while it is in the pipeline - the abort does not take place.
If a data abort occurs, the action taken depends on the instruction type:
• Single data transfer instructions (LDR, STR) write back modified base registers: the Abort handler must be aware
of this.
• The swap instruction (SWP) is aborted as though it had not been executed.
• Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the instruction
would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All
register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last
register to be transferred) is preserved in an aborted LDM instruction.
The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the
processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory
Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the
requested data available, and retry the aborted instruction. The application program needs no knowledge of the
amount of memory available to it, nor is its state in any way affected by the abort.
After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or
Thumb):
SUBS PC,R14_abt,#4 ; for a prefetch abort, or
SUBS PC,R14_abt,#8 ; for a data abort
This restores both the PC and the CPSR, and retries the aborted instruction.
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S3C2410A PROGRAMMER'S MODEL
Software Interrupt
The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular
supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb):
MOV PC,R14_svc
This restores the PC and CPSR, and returns to the instruction following the SWI.
NOTE
nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM920T CPU core.
Undefined Instruction
When ARM920T comes across an instruction which it cannot handle, it takes the undefined instruction trap. This
mechanism may be used to extend either the THUMB or ARM instruction set by software emulation.
After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or
Thumb):
MOVS PC,R14_und
This restores the CPSR and returns to the instruction following the undefined instruction.
Exception Vectors
The following table shows the exception vector addresses.
Table 2-3. Exception Vectors
Address Exception Mode in Entry
0x00000000 Reset Supervisor
0x00000004 Undefined instruction Undefined
0x00000008 Software Interrupt Supervisor
0x0000000C Abort (prefetch) Abort
0x00000010 Abort (data) Abort
0x00000014 Reserved Reserved
0x00000018 IRQ IRQ
0x0000001C FIQ FIQ
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PROGRAMMER'S MODEL S3C2410A
Exception Priorities
When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are
handled:
Highest priority:
1. Reset
2. Data abort
3. FIQ
4. IRQ
5. Prefetch abort
Lowest priority:
6. Undefined Instruction, Software interrupt.
Not All Exceptions Can Occur at Once:
Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (nonoverlapping) decodings of the current instruction.
If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM920T
enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause
the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure
that the transfer error does not escape detection. The time for this exception entry should be added to worst-case
FIQ latency calculations.
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S3C2410A PROGRAMMER'S MODEL
INTERRUPT LATENCIES
The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to
pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete
(Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data
abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM920T will be executing the
instruction at 0x1C.
Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is
therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz
processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher
priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for
FIQ or IRQ consists of the shortest time the request can take through the synchronizer (Tsyncmin) plus Tfiq. This is
4 processor cycles.
RESET
When the nRESET signal goes LOW, ARM920T abandons the executing instruction and then continues to fetch
instructions from incrementing word addresses.
When nRESET goes HIGH again, ARM920T:
1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of
the saved PC and SPSR is not defined.
2. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit.
3. Forces the PC to fetch the next instruction from address 0x00.
4. Execution resumes in ARM state.
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NOTES
2-16
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S3C2410A ARM INSTRUCTION SET
Coprocessor Register Transfer
3 ARM INSTRUCTION SET
INSTRUCTION SET SUMMAY
This chapter describes the ARM instruction set in the ARM920T core.
FORMAT SUMMARY
The ARM instruction set formats are shown below.
27 26 2524 23 22 21 20 19 18 17 16 15 1314 12 11 103130 2928 9 8 7 6 5 4 3 2 1 0
Cond Rn Data/Processing/
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
0 0 I S
0 0 0 0 00 A S
0 0 0 0 0 01 B
0 0 0 P U 0 W L
0 0 0 P U 1 W L
0 1 I P U B W L
0 1 I
1 0 0 P U B W L
1 0 L1
1 1 0 P U B W L
1 1 01
1 1 01 L
1 1 11
Opcode
1 00 010 0 0
CP Opc
CP
Opc
Rd
Rd
A SU10 0 00
Rn
11 11 1 1 11
Rn
Rn
Rn
Rn
Rn
CRn
CRn
Rn
Rd
Rd
Rd
Rd
Offset
CRd
CRd
Rd
Ignored by processor
Operand2
Rs
RnRdHi RdLo
0
0
1
1
0
0
Offset Offset
CP#
CP#
CP#
1
1
1
0
0
0
1
1
1
0
0
1
Register List
0
0
0
0
S
H
S
Offset
CP
CP
0
0
0
0
H
Offset
1
1
1
1
1
1
1
0
1
Rm
Rm
Rm
Rn
Rm
CRm
CRm
PSR Transfer
Multiply
Multiply Long
Single Data Swap
Branch and Exchange
Halfword Data Transfer:
register offset
Halfword Data Transfer:
immendiate offset
Single Data Transfer
Undefined
Block Data Transfer
Branch
Coprocessor Data Transfer
Coprocessor Data Operation
Software Interrupt
27 26 2524 23 22 21 20 19 18 17 16 15 1314 12 11 103130 2928 9 8 7 6 5 4 3 2 1 0
Figure 3-1. ARM Instruction Set Format
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ARM INSTRUCTION SET S3C2410A
NOTE
Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for
instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their
action may change in future ARM implementations.
INSTRUCTION SUMMARY
Table 3-1. The ARM Instruction Set
Mnemonic Instruction Action
ADC Add with carry Rd: = Rn + Op2 + Carry
ADD Add Rd: = Rn + Op2
AND AND Rd: = Rn AND Op2
B Branch R15: = address
BIC Bit Clear Rd: = Rn AND NOT Op2
BL Branch with Link R14: = R15, R15: = address
BX Branch and Exchange R15: = Rn, T bit: = Rn[0]
CDP Coprocessor Data Processing (Coprocessor-specific)
CMN Compare Negative CPSR flags: = Rn + Op2
CMP Compare CPSR flags: = Rn - Op2
EOR Exclusive OR Rd: = (Rn AND NOT Op2)
OR (Op2 AND NOT Rn)
LDC Load coprocessor from memory Coprocessor load
LDM Load multiple registers Stack manipulation (Pop)
LDR Load register from memory Rd: = (address)
MCR Move CPU register to coprocessor
cRn: = rRn {<op>cRm}
register
MLA Multiply Accumulate Rd: = (Rm × Rs) + Rn
MOV Move register or constant Rd: = Op2
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S3C2410A ARM INSTRUCTION SET
Table 3-1. The ARM Instruction Set (Continued)
Mnemonic Instruction Action
MRC Move from coprocessor register to
Rn: = cRn {<op>cRm}
CPU register
MRS Move PSR status/flags to register Rn: = PSR
MSR Move register to PSR status/flags PSR: = Rm
MUL Multiply Rd: = Rm × Rs
MVN Move negative register Rd: = 0 × FFFFFFFF EOR Op2
ORR OR Rd: = Rn OR Op2
RSB Reverse Subtract Rd: = Op2 - Rn
RSC Reverse Subtract with Carry Rd: = Op2 - Rn - 1 + Carry
SBC Subtract with Carry Rd: = Rn - Op2 - 1 + Carry
STC Store coprocessor register to memory address: = CRn
STM Store Multiple Stack manipulation (Push)
STR Store register to memory <address>: = Rd
SUB Subtract Rd: = Rn - Op2
SWI Software Interrupt OS call
SWP Swap register with memory Rd: = [Rn], [Rn] := Rm
TEQ Test bitwise equality CPSR flags: = Rn EOR Op2
TST Test bits CPSR flags: = Rn AND Op2
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ARM INSTRUCTION SET S3C2410A
THE CONDITION FIELD
In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the
instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be
executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is
executed, otherwise it is ignored.
There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the
instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which
means the Branch will only be taken if the Z flag is set.
In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved,
and must not be used.
In the absence of a suffix, the condition field of most instructions is set to "Always" (suffix AL). This means the
instruction will always be executed regardless of the CPSR condition codes.
Table 3-2. Condition Code Summary
Code Suffix Flags Meaning
0000 EQ Z set equal
0001 NE Z clear not equal
0010 CS C set unsigned higher or same
0011 CC C clear unsigned lower
0100 MI N set negative
0101 PL N clear positive or zero
0110 VS V set overflow
0111 VC V clear no overflow
1000 HI C set and Z clear unsigned higher
1001 LS C clear or Z set unsigned lower or same
1010 GE N equals V greater or equal
1011 LT N not equal to V less than
1100 GT Z clear AND (N equals V) greater than
1101 LE Z set OR (N not equal to V) less than or equal
1110 AL (ignored) always
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S3C2410A ARM INSTRUCTION SET
BRANCH AND EXCHANGE (BX)
This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.
This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC.
The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the
instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the
instruction stream will be decoded as ARM or THUMB instructions.
31 2427 19 15 8 7 0
28 16 111223 20 4 3
00 0 1 10 0 0 11 1 1 11 1 1 11 1 1 00 0 1Cond Rn
[3:0] Operand Register
If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions
If bit0 of Rn =0, subsequent instructions decoded as ARM instructions
[31:28] Condition Field
Figure 3-2. Branch and Exchange Instructions
INSTRUCTION CYCLE TIMES
The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and nonsequential (N-cycle), respectively.
ASSEMBLER SYNTAX
BX - branch and exchange.
BX {cond} Rn
{cond} Two character condition mnemonic. See Table 3-2.
Rn is an expression evaluating to a valid register number.
USING R15 AS AN OPERAND
If R15 is used as an operand, the behavior is undefined.
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ARM INSTRUCTION SET S3C2410A
Examples
ADR R0, Into_THUMB + 1 ; Generate branch target address
; and set bit 0 high - hence
; arrive in THUMB state.
BX R0 ; Branch and change to THUMB
; state.
CODE16 ; Assemble subsequent code as
Into_THUMB ; THUMB instructions
•
•
•
ADR R5, Back_to_ARM ; Generate branch target to word aligned address
; - hence bit 0 is low and so change back to ARM state.
BX R5 ; Branch and change back to ARM state.
•
•
•
ALIGN ; Word align
CODE32 ; Assemble subsequent code as ARM instructions
Back_to_ARM
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S3C2410A ARM INSTRUCTION SET
BRANCH AND BRANCH WITH LINK (B, BL)
The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction
encoding is shown in Figure 3-3, below.
31 2427
28 23
Cond Offset
25
101 L
0
[24] Link bit
0 = Branch 1 = Branch with link
[31:28] Condition Field
Figure 3-3. Branch Instructions
Branch instructions contain a signed 2's complement 24-bit offset. This is shifted left two bits, sign extended to 32
bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must
take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction.
Branches beyond +/- 32Mbytes must use an offset or absolute destination which has been previously loaded into a
register. In this case the PC should be manually saved in R14 if a Branch with Link type operation is required.
THE LINK BIT
Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14
is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link
instruction. Note that the CPSR is not saved with the PC and R14[1:0] are always cleared.
To return from a routine called by Branch with Link use MOV PC,R14 if the link register is still valid or LDM
Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn.
INSTRUCTION CYCLE TIMES
Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S and N are defined as sequential
(S-cycle) and internal (I-cycle).
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ARM INSTRUCTION SET S3C2410A
ASSEMBLER SYNTAX
Items in {} are optional. Items in <> must be present.
B{L}{cond} <expression>
{L} Used to request the Branch with Link form of the instruction. If absent, R14 will not be
affected by the instruction.
{cond} A two-character mnemonic as shown in Table 3-2. If absent then AL (ALways) will be
used.
<expression> The destination. The assembler calculates the offset.
Examples
here BAL here ; Assembles to 0xEAFFFFFE (note effect of PC offset).
B there ; Always condition used as default.
CMP R1,#0 ; Compare R1 with zero and branch to fred
; if R1 was zero, otherwise continue.
BEQ fred ; Continue to next instruction.
BL sub+ROM ; Call subroutine at computed address.
ADDS R1,#1 ; Add 1 to register 1, setting CPSR flags
; on the result then call subroutine if
BLCC sub ; the C flag is clear, which will be the
; case unless R1 held 0xFFFFFFFF.
3-8
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S3C2410A ARM INSTRUCTION SET
DATA PROCESSING
The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The
instruction encoding is shown in Figure 3-4.
31 2427 19 15
28 16 111221
26 25
Cond Operand2
00 L20OpCode S Rn Rd
[15:12] Destination register
0 = Branch 1 = Branch with link
[19:16] 1st operand register
0 = Branch 1 = Branch with link
[20] Set condition codes
0 = Do not after condition codes 1 = Set condition codes
[24:21] Operation codes
0000 = AND-Rd: = Op1 AND Op2
0001 = EOR-Rd: = Op1 EOR Op2
0010 = SUB-Rd: = Op1-Op2
0011 = RSB-Rd: = Op2-Op1
0100 = ADD-Rd: = Op1+Op2
0101 = ADC-Rd: = Op1+Op2+C
0110 = SBC-Rd: = OP1-Op2+C-1
0111 = RSC-Rd: = Op2-Op1+C-1
1000 = TST-set condition codes on Op1 AND Op2
1001 = TEO-set condition codes on OP1 EOR Op2
1010 = CMP-set condition codes on Op1-Op2
1011 = SMN-set condition codes on Op1+Op2
1100 = ORR-Rd: = Op1 OR Op2
1101 = MOV-Rd: =Op2
1110 = BIC-Rd: = Op1 AND NOT Op2
1111 = MVN-Rd: = NOT Op2
0
[25] Immediate operand
0 = Operand 2 is a register 1 = Operand 2 is an immediate value
[11:0] Operand 2 type selection
311 04
Shift
[3:0] 2nd operand register [11:4] Shift applied to Rm
811 07
Rotate
[7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm
Imm
Rm
[31:28] Condition field
Figure 3-4. Data Processing Instructions
3-9
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ARM INSTRUCTION SET S3C2410A
The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands.
The first operand is always a register (Rn).
The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of
the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this
instruction, according to the value of the S bit in the instruction.
Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to
set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in
Table 3-3.
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S3C2410A ARM INSTRUCTION SET
CPSR FLAGS
The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST,
TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to
produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C
flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will
be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result.
Table 3-3. ARM Data Processing Instructions
Assembler Mnemonic OP Code Action
AND 0000 Operand1 AND operand2
EOR 0001 Operand1 EOR operand2
WUB 0010 Operand1 - operand2
RSB 0011 Operand2 operand1
ADD 0100 Operand1 + operand2
ADC 0101 Operand1 + operand2 + carry
SBC 0110 Operand1 - operand2 + carry - 1
RSC 0111 Operand2 - operand1 + carry - 1
TST 1000 As AND, but result is not written
TEQ 1001 As EOR, but result is not written
CMP 1010 As SUB, but result is not written
CMN 1011 As ADD, but result is not written
ORR 1100 Operand1 OR operand2
MOV 1101 Operand2 (operand1 is ignored)
BIC 1110 Operand1 AND NOT operand2 (Bit clear)
MVN 1111 NOT operand2 (operand1 is ignored)
The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer
(either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in
the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were
considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be
set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be
set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's
complement signed).
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ARM INSTRUCTION SET S3C2410A
SHIFTS
When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the
Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or
rotate right). The amount by which the register should be shifted may be contained in an immediate field in the
instruction, or in the bottom byte of another register (other than R15). The encoding for the different shift types is
shown in Figure 3-5.
456711
0
[6:5] Shift type
00 = logical left 01 = logical right
10 = arithmetic right 11 = rotate right
[11:7] Shift amount
5 bit unsigned integer
0RS
[6:5] Shift type
00 = logical left 01 = logical right
10 = arithmetic right 11 = rotate right
[11:8] Shift register
Shift amount specified in bottom-byte of Rs
456711 8
1
Figure 3-5. ARM Shift Operations
Instruction specified shift amount
When the shift amount is specified in the instruction, it is contained in a 5-bit field which may take any value from 0
to 31. A logical shift left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more
significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not
map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output
which may be latched into the C bit of the CPSR when the ALU operation is in the logical class (see above). For
example, the effect of LSL #5 is shown in Figure 3-6.
31 27 26
Contents of Rm
carry out
Value of Operand 2
Figure 3-6. Logical Shift Left
NOTE
LSL #0 is a special case, where the shifter carry out is the old value of the CPSR C flag. The contents of Rm
are used directly as the second operand. A logical shift right (LSR) is similar, but the contents of Rm are
moved to less significant positions in the result. LSR #5 has the effect shown in Figure 3-7.
3-12
000000
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S3C2410A ARM INSTRUCTION SET
31
45
Contents of Rm
00000
Value of Operand 2
0
carry out
Figure 3-7. Logical Shift Right
The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a
zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift
left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be
specified.
An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm
instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown in Figure
3-8.
31
4530
Contents of Rm
Value of Operand 2
0
carry out
Figure 3-8. Arithmetic Shift Right
The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again
used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or
all zeros, according to the value of bit 31 of Rm.
3-13
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ARM INSTRUCTION SET S3C2410A
Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them
at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example,
ROR #5 is shown in Figure 3-9.
31
45
Contents of Rm
Value of Operand 2
0
carry out
Figure 3-9. Rotate Right
The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel
shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by
appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3-10.
31
Contents of Rm
C
in
01
carry out
3-14
Value of Operand 2
Figure 3-10. Rotate Right Extended
Page 97
S3C2410A ARM INSTRUCTION SET
Register Specified Shift Amount
Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general
register other than R15.
If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the
CPSR C flag will be passed on as the shifter carry output.
If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift
with the same value and shift operation.
If the value in the byte is 32 or more, the result will be a logical extension of the shift described above:
1. LSL by 32 has result zero, carry out equal to bit 0 of Rm.
2. LSL by more than 32 has result zero, carry out zero.
3. LSR by 32 has result zero, carry out equal to bit 31 of Rm.
4. LSR by more than 32 has result zero, carry out zero.
5. ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm.
6. ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm.
7. ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore
repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above.
NOTE
The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause
the instruction to be a multiply or undefined instruction.
3-15
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ARM INSTRUCTION SET S3C2410A
IMMEDIATE OPERAND ROTATES
The immediate operand rotate field is a 4-bit unsigned integer which specifies a shift operation on the 8-bit immediate
value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field.
This enables many common constants to be generated, for example all powers of 2.
WRITING TO R15
When Rd is a register other than R15, the condition code flags in the CPSR may be updated from the ALU flags as
described above.
When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR
is unaffected.
When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the
current mode is moved to the CPSR. This allows state changes which atomically restore both PC and CPSR. This
form of instruction should not be used in User mode.
USING R15 AS AN OPERANDY
If R15 (the PC) is used as an operand in a data processing instruction the register is used directly.
The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift
amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount
the PC will be 12 bytes ahead.
TEQ, TST, CMP AND CMN OPCODES
NOTE
TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in the CPSR. An
assembler should always set the S flag for these instructions even if this is not specified in the mnemonic.
The TEQP form of the TEQ instruction used in earlier ARM processors must not be used: the PSR transfer
operations should be used instead.
The action of TEQP in the ARM920T is to move SPSR_<mode> to the CPSR if the processor is in a privileged mode
and to do nothing if in User mode.
INSTRUCTION CYCLE TIMES
Data Processing instructions vary in the number of incremental cycles taken as follows:
Table 3-4. Incremental Cycle Times
Processing Type Cycles
Normal data processing 1S
Data processing with register specified shift 1S + 1I
Data processing with PC written 2S + 1N
Data processing with register specified shift and PC written 2S + 1N +1I
NOTE: S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively.
3-16
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S3C2410A ARM INSTRUCTION SET
ASSEMBLER SYNTAX
• MOV,MVN (single operand instructions).
<opcode>{cond}{S} Rd,<Op2>
• CMP,CMN,TEQ,TST (instructions which do not produce a result).
<opcode>{cond} Rn,<Op2>
• AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC
<opcode>{cond}{S} Rd,Rn,<Op2>
where:
<Op2> Rm{,<shift>} or,<#expression>
{cond} A two-character condition mnemonic. See Table 3-2.
{S} Set condition codes if S present (implied for CMP, CMN, TEQ, TST).
Rd, Rn and Rm Expressions evaluating to a register number.
<#expression> If this is used, the assembler will attempt to generate a shifted immediate 8-bit field to
match the expression. If this is impossible, it will give an error.
<shift> <Shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit with
extend).
<shiftname>s ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL, they assemble to the same
code.)
EXAMPLES
ADDEQ R2,R4,R5 ; If the Z flag is set make R2:=R4+R5
TEQS R4,#3 ; Test R4 for equality with 3.
; (The S is in fact redundant as the
; assembler inserts it automatically.)
SUB R4,R5,R7,LSR R2 ; Logical right shift R7 by the number in
; the bottom byte of R2, subtract result
; from R5, and put the answer into R4.
MOV PC,R14 ; Return from subroutine.
MOVS PC,R14 ; Return from exception and restore CPSR
; from SPSR_mode.
3-17
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ARM INSTRUCTION SET S3C2410A
PSR TRANSFER (MRS, MSR)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.
The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented
using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11.
These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the
CPSR or SPSR_<mode> to be moved to a general register. The MSR instruction allows the contents of a general
register to be moved to the CPSR or SPSR_<mode> register.
The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags
(N,Z,C and V) of CPSR or SPSR_<mode> without affecting the control bits. In this case, the top four bits of the
specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR.
OPERAND RESTRICTIONS
• In user mode, the control bits of the CPSR are protected from change, so only the condition code flags of the
CPSR can be changed. In other (privileged) modes the entire CPSR can be changed.
• Note that the software must never change the state of the T bit in the CPSR. If this happens, the processor will
enter an unpredictable state.
• The SPSR register which is accessed depends on the mode at the time of execution. For example, only
SPSR_fiq is accessible when the processor is in FIQ mode.
• You must not specify R15 as the source or destination register.
• Also, do not attempt to access an SPSR in User mode, since no such register exists.
3-18
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