Samsung S1T8527C01-Q0R0 Datasheet
1 CHIP CLP SUBSYSTEM IC S1T8527C
INTRODUCTION
48−QFP−1010E
S1T8527C is a monolithic circuit which can be used in high
performance 60MHz MCA type CLP System. The S1T8527C is a
subsystem IC for FM / FSK receiving systems and a complete one chip
FM / FSK receiver IC for 60MHz system. It’s feature includes receiving
functions for FM / FSK systems, a compander to remove external
noise, and PLL ( Phase Lock Loop ) of channel selection which blocks
surrounding frequency interference.
The S1T8527C can be used with a wide range of FM / FSK VHF
bandwidth systems, including cordless phone, and the narrow band
voice and data sending / receiving systems.
To make applications easily and simply, peripheral parts are minimized.
FEATURES
• Operating voltage range: 2.0V — 5.5V
• Typical supply current: 13.5mA at 3.6V
• Built−in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V )
• Built−in speaker amplifier
• Built−in splatter filter
• Built−in dual conversion receiver, compander and universal PLL
• FM Receiver
— Complete dual conversion circuit
— Excellent input sensitivity (0.7µVrms at 12dB SINAD)
• Compader
— Easy gain control to use external component
— Included ALC (Automatic Level Control) circuit
— Included Mute logic
• Universal PLL
— RX (TX) divided counter range: 1/16 — 1/16383
— Reference frequency divided counter range: 1/16 — 1/4095
— Lock detector signal output
— Serial interface with MCU for controlling each block
ORDERING INFORMATION
Device Package Operating Temperature
S1T8527C01-Q0R0 48−QFP−1010E −20°C — + 70°C
1
S1T8527C 1 CHIP CLP SUBSYSTEM IC
BLOCK DIAGRAM
2MI
1MO
1LOI
1LOI
VCO
RX
1MI
1MI
GND
(PLL)
PDR
V
REF
(PLL)
V
(PLL)
TIF
LD
(RX)
GND
30
Meter
Driver
Carrier
Detector
Low
Battery
Detector
29
QCI
RAO
28 27
Limiter
Gain Cell
Rectifier
DSCI
FSK
COMP
DSCO
26
Rectifier
Gain Cell
25
SUM
AMP
MDO
Regulator
(1V)
PRI
+
-
SUM
AMP
SPK
AMP
SPK
AMP
+
-
PRI
ALC
VREF
V
REF
24
(COMP)
23
ALC
22
EPI
21
ERC
EO
20
SAI
19
SAO1
18
SAO2
17
VCC
16
(COMP)
GND
15
(COMP)
CPI+
14
13
CPI -
(RX)
37
2LOI
36
X-tal
OSC
2nd
MIX
35
2LOI
2MO
34 33
IF AMP
(455KHz)
VCC
LI
32 31
Limiting
IF AMP
38
39
40
RX
VCO
Quad
Detector
AMP
41
42
1st
MIX
IF AMP
(10.7MHz)
Regulator
43
44
( 2.15 V )
Buffer
Programmable Counter
45
46
CC
47
48
( RX )
Programmable Counter
( TX )
Programmable Counter
( REF )
4_25 CNT
Splatter
SFI
Filter
SFO
fMCU
CDO/LDT
CONTROL
6
(PLL)
GND
CLK
DATA
EN
LBD
AGIC
Compandor
mute
121110 9 8 754 3 1 2
CRC
RX Phase
Detector
TX Phase
Detector
CO
PDT
2
1 CHIP CLP SUBSYSTEM IC S1T8527C
CDO/LDT
GND
PIN CONFIGURATION
VCO
GND
V
REF(PLL)
V
CC(PLL)
2MI
1MO
1LOI
1LOI
RX
1MI
1MI
(PLL)
PDR
37
38
39
40
41
42
43
44
45
46
47
36
2LOI
35
2LOI
34 33
(RX)
VCC
2MO
LI
LD
32 31
S1T8527C
KB8527B
GND
30
(RX)
29
QCI
RAO
28
27
DSCI
26
DSCO
MDO
25
24
23
22
21
20
19
18
17
16
15
14
V
REF(COMP)
ALC
EPI
ERC
EO
SAI
SAO1
SAO2
VCC
(COMP)
GND
(COMP)
CPI+
TIF
48
1
PDT
2
CO
3
SFI
4
SFO
5 6
(PLL)
7
CLK
8
DATA
9
EN
10
11
LBD
12
AGIC
13
CRC
CPI -
3
S1T8527C 1 CHIP CLP SUBSYSTEM IC
PIN DESCRIPTION
Pin No Symbol Description
1 PDT3 Phase detector output terminal of the transmitter at PLL.
If fTX > f
If fTX < f
if fTX = f
2 CO Compressor output terminal of compander; connected to the splatter filter amp input
terminal.
3 SFI Input terminal of Splatter filter amp.
4 SFO3 Output terminal of Splatter filter amp.
5 LDT/CDO LDT: Output terminal of transmitter lock detector in PLL block. The output is low if PLL
is in lock state and the output is high if PLL is in unlock state.
CDO: As an output terminal of the carrier detector buffer, connected to (RSSI )
terminal of MCU. This pin outputs the contents of Meter Driver buffer which is
turned on / off, according to the signal level detected by Meter Driver.
or fTX is leading → the output is negative pulse
REF
or fTX is lagging → the output is positive Pulse
REF
and the same phase → the output is High Impedance
REF
6 GND
PLL
Ground.
Ground of logic section at PLL.
7
8
9
CLK
DATA
EN
These pins are serial interface terminals for programming reference counter, auxiliary
reference counter, TX channel counter, RX channel counter and control block that
controls internal each block with test mode and power saving mode.
10 LBD Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ). During
the normal operation, output level is low, but it is high at low battery detection. As this
pin is an open collector type, it requires a pull - up resistor.
11 AGIC This pin bypasses AC elements at the feedback loop which come from the SUM amp
block of COMPRESSOR. A capacitor should be connected between this terminal and
GND. ( C = 2.2uF )
12 CRC Converts waveform from the full wave rectifier to DC element at the rectifier block of
Compressor. ( RC = 33msec )
13 CPI - Pre-amp inverting input terminal of Compressor.
Adjusts the negative feedback loop gain. ( in application, gain is 5 )
14 CPI + Pre-amp non-inverting input terminal of Compressor.
Used as an input terminal for voice signals.
15 GND
16 Vcc
(COMP)
(COMP)
Ground of Compander block.
Supply voltage.
Power supply terminal of Compander.
17 SAO 2 Output terminal of speaker amp 2.
This signal is the same as SAO1 output, but phase difference is180° for SAO1.
DC voltage level is ( Vcc — 0.7V ) / 2.
4
1 CHIP CLP SUBSYSTEM IC S1T8527C
PIN DESCRIPTION (Continued)
Pin No Symbol Description
18 SAO 1 Output terminal of Speaker amp 1.
DC voltage level is ( Vcc — 0.7V ) / 2.
19 SAI Speaker Amp 1 input terminal.
Between this terminal and Expander output terminal, uses a AC coupled.
20 EO Output terminal of Expander, from which a regenerated voice signals are emitted.
21 ERC Converts waveform from the full wave rectifier to DC element at the rectifier block of
Expander. ( RC = 33 msec )
22 EPI − Pre-amp inverting input terminal of Expander.
Adjusts the negative feedback loop gain. ( in application, gain is 5 ).
23 ALC Reference current input terminal of Automatic Level Control ( ALC); Adjusts THD of
compressor output voltage to less than 3% or limits the frequency deviation of TX if the
input is higher than a certain level. The ALC circuit may be turned off depending on the
ALC reference current or the magnitude of output voltage may be limited if it is higher
than a certain level.
24 V
REF(COMP)
Reference voltage ( V
= 1V ). Supplies a regulator voltage to the Compressor and
REF
Expander of COMPANDER.
25 MDO Output terminal of the Meter Driver.
Amplitude of RF input signal for useful frequency is detected by Meter Driver circuit.
The Meter Driver circuit has perfect linear characteristic of 60dB range for input signal
level. ( 0.1µA / dB ).
26 DSCO Output terminal of Data Slicing comparator.
Separates Frequency Shift Keying ( FSK ) serial data and executes data shaping and
limiting.
27 DSCI Input terminal of Data slicing comparator.
Non-inverting type with the negative input terminal biased to 1/2 Vcc.
28 RAO Recovered Audio Output terminal. Voice signals detected by the Quadrature Detector
are amplified and then output through this terminal.
29 QCI3 Quadrature coil input terminal.
The 455kHz oscillator circuit is an Lp = 680uH, Cp = 180pF valued LC tank circuit.
Voice signals are detected by mixture of 455kHz ( by phase difference ) which is
converted from mixer 2.
30 GND
RX
Ground .
Ground for Receiver.
31
32
LD
LI
Limiter input and decoupling terminal.
Removes amplitude modulation elements caused by fading or FM signal noise. Limiting
IF amplifies and limits the second intermediate frequency, 455kHz.The input
impedance of the limiting IF amplifier is set to 1.5kΩ. While FM waves are transmitted
with constant magnitude, their magnitudes are slightly modulated due to reflection from
obstacles, fading phenomenon, noise wave, and mixing with AM wave elements before
entering the receiver’s antenna.The limiter makes amplitude uniform by removing these
AM wave elements.
5
S1T8527C 1 CHIP CLP SUBSYSTEM IC
PIN DESCRIPTION (Continued)
Pin No Symbol Description
33 V
CC(RX)
Supply voltage.
Supplies power to the Receiver.
34 2MO3 Output terminal of Mixer 2. Second intermediate frequency ( 455kHz ), generated by
mixing first intermediate frequency ( 10.7MHz ) and Second Local Oscillator is output.
35
36
2LOI
2LOI
Input terminal of second local oscillator. Generates second local oscillator frequency to
convert output from mixer 1 ( 10.7MHz ) into second intermediate frequency. It is an
oscillator with crystal of 10.24MHz and 10.245MHz.
37 2MI Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via
10.7MHz ceramic filter. Second mixer converts frequency to second intermediate
frequency ( 455kHz: AM IF ).
38 1MO3 Output terminal of mixer 1.
The signal from mixer 1 and the frequency of the first local oscillator are mixed to
produce the first intermediate frequency, which is the output through this terminal. The
output terminal is an emitter follower with an output impedance of 330Ω to match the
330Ω input/output impedance of the 10.7MHz ceramic filter.
39
40
1LOI
1LOI
Input terminal of the first local oscillator.
The local oscillator is a voltage controlled oscillator. local oscillation frequency and
received frequency are mixed at mixer 1 and then converted to the first intermediate
frequency of 10.7MHz or 10.695MHz.
41 VCO
RX
The terminal which variable capacitor is included in the chip. Used as an input terminal
where 1st local oscillation frequency is changed by varying the capacitor connected
between 1st local oscillator terminals.The internal variable capacitor has the value of
18.73 ~ 15.86pF depending on the applied voltage. ( 1.0 ~ 2.0 V ).
42
43
44 GND
1MI
1MI
(PLL)
Input terminal of Mixer 1. This mixer is made of double balanced multiplier.
The received signal amplified at RF AMP is input to this terminal.
Ground.
Ground for analog at PLL
45 PDR Phase detector output terminal of the receiver at PLL.
46 V
REF(PLL)
If fRX > f
If fRX < f
If fRX = f
PLL voltage reference output pin.
or fRX is Leading → The output is negative pulse
REF
or fRX is Lagging → The output is positive pulse
REF
and the same phase → The output is high impedance
REF
An internal voltage regulator provides a stable power supply voltage for the RX and TX
PLLs.
47 V
CC(PLL)
Power supply terminal of PLL.
48 TIF Input terminal of TX channel counter.
AC coupling with TX VCO.
Minimum input level is 300mVp-p ( at 60MHz ).
6
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