Samsung Geneva, NP-R700 Schematic
4
B
2
D
1
SAMSUNG PROPRIETARY
COM-22C-015(1996.6.5) REV. 3
C
3
A
D:/tingting/geneva/Geneva_pr_1023
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Table of Contents
Table of Contents
Table of Contents
Table of Contents
Table of Contents
Table of Contents
Table of Contents
Sheet 1 Cover
Sheet 2 Diagram (Block/Power) & Annotations
D
Sheet 8 Clock Generator
Sheet 9 Thermal Sensor & FAN
Sheet 10-12 Merom-4M CPU
Sheet 13-17 Crestline-GMCH
Sheet 18 DDR2 SODIMM A
GENEVA
Sheet 19 DDR2 SODIMM B
Sheet 20-23 ICH8-M
Sheet 24 ICH8-M STRAP
Sheet 25-28 NIVIDIA NB8P
Sheet 29 NIVIDIA NB8P STRAP
CPU :
Chip Set :
Remarks :
MEROM
SANTAROSA CHIPSET
Mobility Platform
Sheet 30 Video Memory Channel A
Sheet 31 Video Memory Channel B
Sheet 32 LCD and Camera Connector
Sheet 33 CRT PORT
Sheet 34 SIO CHIP and Connector
Sheet 35 7 IN 1 Card Reader
Sheet 36 MINI CARD AND ROBSON DVB-T
Sheet 37 Express card
C
Sheet 38 AUDIO - ALC262
Model Name :
PBA Name :
PCB Code :
Dev. Step :
Revision :
T.R. Date :
GENEVA
MAIN
BA41-XXXXX
PV2
Samsung
1.0
Sheet 39 AUDIO - AMP
Sheet 40 AUDIO - HEADPHONE & MIC JACK
Sheet 41 AUDIO - POWER
Sheet 42-43 LAN AND CONNECTOR
Sheet 44-45 MICOM AND MICOM POWER LOGIC
Sheet 46 POWER - SWITCH POWER
Sheet 47 POWER - VCCP P1.25V and P1.2V
Sheet 48 POWER - DDR2 POWER
Sheet 49 POWER - CHARGE & POWER MANAGEMENT
Sheet 50 POWER - P3.3V_ALW & P5V_AUX
Sheet 51 POWER - CPU VRM
Sheet 52 POWER - GFX CORE P1.5V
Sheet 53 HDD & ODD Connector
B
Sheet 54 USB/MDC/BLUETOOTH/TOUCHPAD
Sheet 55 KBD/LID SWITCH/80H/ICT/LED IF/USB /IF
DRAW
4
CHECK
APPROVAL
Confidential
3
Sheet 56
Sheet 57
Sheet 58
Sheet 59
Sheet 60
OTHERS
TOUCHPAD AND LED B’D
SIO AND USB B’D
TEST POINT
TEST POINT
DRAW
CHECK
APPROVAL
MODULE CODE
2
SUN XIAO
WUSHIJIANG
KEVIN LEE
DATE
DEV. STEP
REV
LAST EDIT
6/26/2007
TITLE
PV2
1.0
Gevena
MILAN
COVER
October 23, 2007 10:38:02 AM
1
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
158
PAGE
A
OF
2
SAMSUNG PROPRIETARY
B
A
C
1
4
3
D
COM-22C-015(1996.6.5) REV. 3
D:/tingting/geneva/Geneva_pr_1023
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Clocking
CK-505
PG 8
PG 71
HDMI
Thermistor
FAN
PG 9
CPU
(TBD)
PG 9
Mobile Processor
Merom-4M
(800MHz)
478pin
PG 10,11,12
L2 Cache : 4 MB
FSB
800 MT/S
Channel A (Standard)
GMCH-M
NVIDIA
RJ11
PG 43
PG 22
NB8P / M
PG 25-29
PG 54
PG 55
Modem
SPI ROM
SATA
USB 0,1,2,3
ANT
Bluetooth
MDC
PG 54
HDD
Direct Media Interface
USB 0,1,2,3
USB 5
HD Primary
12P
HD Secondary
Samsung
SATA 0
PATA
PG 32
LCD
PG 33
CRT
High Definition Audio
30PIN
SVHS / RCA
Component
Aud.
AMP
PG 39
LCD/CRT/TV
HDAUDIO
Audio
ALC262
PG 38
PG 40
HEADPHONE
MIC-IN
2P
2P
PG 53
Confidential
SPKR R
SPKR L
4
PG 53
CD-ROM
CD / DVD
PG 55
Pri. IDE slave
3
SPI
80 Port
Crestline-GM
(TBD)
1299 FCBGA
PG 13 - 17
x4, 1.5V
CLINK
ICH8-M
676 BGA
PG 20 - 24
LPC
3.3V LPC, 33MHz
Channel B (Reverse)
PCIE x1
GLCI (Lane5)
LCI
PCIE x1
USB 4
CLINK
FIR(CIR)
PG 54
Dual channel
Lane 0
Lane 1
PG 51
ON BOARD
DDR II 667/533,400
DDR II 667/533,400
52P
MICOM
HD64F2169/2160
TMKBC (TBD)
LED
PG 45
CPU
DC/DC
IMVP-6
PG 51
PG 37
MINI CARD
ROBSON
DVB-T OPTION
2
Charging
Circuit
PG 49
Termination
PG 18,19
DDR II
SODIMM 0
DDR II
SODIMM 1
82566Mx (Nineveh)
82562V
Touch
PG 55
PAD
KBD
PG 55
DRAW
CHECK
APPROVAL
MODULE CODE
PG 18
PG 19
52P
SUN XIAO
WUSHIJIANG
KEVIN LEE
Smart
Battery
Module
PG 49
VCCP / DC-DC
DDR II Power
Marvell
8E8055(GLAN)
PG 42
Mini Card
PG 37
DATE
6/26/2007
DEV. STEP
PV2
REV
LAST EDIT
1.0
DC/DC
46
PG 47
PG 48
TITLE
OPTION
ANT
Kedron
MIO_BUTTON
Gevena
BLOCK DIAGRAM
October 23, 2007 10:38:02 AM
IGFX / EGFX
CORE
PG 52
RJ45
PG 43
PAGE
1
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
OF
D
C
B
A
582
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
BOARD INFORMATION
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
D
PCI Devices
Devices
Cardbus
MiniPCI SLOT
USB
Hub to PCI
LPC bridge/IDE/AC97/SMBUS
Internal MAC
AC Link
GLAN -
IDSEL#
AD25
AD22DT PCI SLOT
AD23
AD29(internal)
AD30(internal)
AD31(internal)
AD24(internal)
-
-
REQ/GNT#
3
1
2 A,B
-
-
-
-
C
Interrupts
B,C,D
B,C,D,C
USB2.0 #0 (USB0) : A
USB2.0 #1 (USB1) : D
USB2.0 #2 (USB4) : C
USB2.0 #3 (USB5) : E
USB2.0 #4 (EHCI) : H
B
E
BF
Voltage Rails
VDC
VCC_CORE
MCH_CORE Core Voltage for CPU
ICH_CORE
P1.05V (VCCP)
P1.25V_M
P3.3V_M
P3.3V_A
MICOM_P3V
P1.5V
P1.5V_AUX
P2.5V
P1.8V_AUX
P0.9V
B
P3.3V
P3.3V_AUX
P5V
P5V_AUX
Primary DC system power supply (7 to 21V)
Core Voltage for CPU
Core Voltage for CPU
VTT for CPU, Crestline & ICH8-M
1.05V switched power rail for ME (on in M0/M1)P1.05V_M
1.25V switched power rail for ME (on in M0/M1)
3.3V switched power rail for ME (on in M0/M1)
3.3V always power rail (by KBC3_ALWS_ON)
3.3V always power rail (for Micom)
3.3V always power rail (for LAN)LAN_3.3V
1.5V switched off power rail (off in S3-S5)
1.5V switched on power rail
2.5V switched off power rail (off in S3-S5)
1.8V switched off power rail (off in S3-S5)P1.8V
1.8V power rail for DDR
0.9V power rail for DDR
3.3V switched off power rail (off in S3-S5)
3.3V switched on power rail
5.0V switched off power rail (off in S3-S5)
5.0V switched on power rail
Samsung
Crystal / Oscillator
TYPE
Crystal
Crystal
Crystal
Crystal
Crystal
Crystal
Crystal
FREQUENCY
32.768KHz
10MHz HD64F2169/2160
14.318MHz CK-505
24.576MHz 1394
25MHz
27MHz (TBD)
24.576MHz (TBD)
LCD Pannel Detect
Devices
2
I C / SMB Address
Devices
ICH8-m
CPU Thermal Sensor
SODIMM0
SODIMM1
Thermal Sensor on SODIMM0
Thermal Sensor on SODIMM1
CK-505M (Clock Generator) 1101 001x
DB400 (PCI Express Clocks)
TBD
TBD : (ALS)
TBD : (AUX DISPLAY)
LAN
TPM
Resolution
Address
Master
1001 110x
1010 000x
1010 010x
0011 000x
0011 010x
1101 110x
0100 1100 Thermal Sensor
0101 1000
0111 0010
0011 110x
1100 1000 82566
TBD
TBD
(TBD)
DEVICE
ICH8-M
MICOM
CLOCK-Generator
Cardbus Controller
LAN
VIDEO
HD Audio
Hex
9Ch
A0h
A4h
30h
34h
D2h
DCh
4Ch
58h
72h
3Ch
C8h
TBD
TBD
USAGE
Real Time Clock
Intel LAN
PEG
Audio
PANNEL_DETECT_0
Bus
SMBUS Master
Thermal Sensor
-
-
-
Clock, Unused Clock Output Disable
Clock Buffer for PCI Express
-TBD : (LVDS BackLight Inverter)
Ambient Light Sensor
EMA
TBDPCI Express Docking
TBD
D
C
B
USB PORT Assign
PORT # ASSIGNED TO
0
SYSTEM PORT 0
SYSTEM PORT 11
DMB
2
3
Expresas Card
DOCKING PORT 0
4
Bluetooth
5
Mini PCI Express
6
7
Aux Display
8
Test Port (RSVD)
9
WWAN/WIBRO (TBD)
A
4
PCI Express Assign
ASSIGNED TO
PORT #
0
PCIE x1 Slot
Mini Card (Golan)
1
Mini Card (WIBRO : RSVD)
2
Expresas Card
3
DOCKING PORT 0
4
5 GLAN
Confidential
REVISION HISTORY
See rev notes for more information.
DRAW
CHECK
APPROVAL
MODULE CODE
3
2
SUN XIAO
WUSHIJIANG
KEVIN LEE
DATE
DEV. STEP
REV
LAST EDIT
6/26/2007
TITLE
Gevena
PV2
1.0
BOARD INFO
October 23, 2007 10:38:02 AM
1
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
358
PAGE
A
OF
HDD
M_PCI
FAN CIRCUIT
AUX DISPLAY
VCCA
P1.5V
Thermal Sensor
SODIMM
FWH
PCMCIA
LEDs
Gevena
1
KBC3_VRON
CPU_CORE
R5C843
PEG
MEROM
MICOM
M_PCI
TPM
LCD
ATI (TBD)
nVidia (TBD)
CRESTLINE
PAGE OF
1
MEROM
SAMSUNG
ELECTRONICS
BA41-XXXXX
584
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
4
AC Adapter
DOCK DC
VDC
KBC3_ALWS_ON
KBC3_MEPWRON
(CHP3_SLPM*)
ME ENABLE
(CHP3_S4_STATE*) or
: KBC3_DDRPWRON (CHP3_SLPS4*)
(CHP3_SLPM*)
P1.8V_AUX (ME)
3
SODIMM (DDR II)
CRESTLINE
KBC3_SUSPWR
(CHP3_S4_STATE*)
ME OPTION
P1.8V_AUX
SODIMM (DDR II)
CRESTLINE
P0.9 (ME)
Battery DC
C C
DDR II-Termination
DDR II for PEG (TBD)
P1.25V_M
CRESTLINE
P1.05V_M
CRESTLINE
MICOM_P3V
MICOM
P5V_AUX
2
KBC3_MEPWRON
(CHP3_SLPM*)
ME DISABLE
P1.25V_M
CRESTLINE
P1.05V_M
CRESTLINE
POWER DIAGRAM
KBC3_PWRON
(CHP3_SLPS3*)
P1.8V
P0.9V
ME OPTION
P1.25V
P1.2V
P1.05V
(VCCP)
P5V
PEG
GDDR-3 for PEG
DDR II-Termination
DDR II for PEG (TBD)
CRESTLINE
ICH8-M
R5C843
PEG
nVidia
MEROM
CRESTLINE
ICH8-M
PCMCIA
ICH8-M
USB
FDD
HEATSINK
CRT
MDC
MICOM
P3.3V_M
CK505
SPI
ICH
Power Sequence by ME On/Off
B
Host Boot / ME Off
(SLPS4* = S4_STATE*) > (SLPM* = SLPS3*)
Host / ME Boot
(SLPS4* = S4_STATE*) > SLPM* > SLPS3*
Host S5 / ME Boot
(SLPS4* = SLPM*) > S4_STATE* > SLPS3*
Power On/Off Table by S-state
Rail
M0
+0.9V
+V* M
S0
ON
ON
ON ON
ON
ON
ON
State
+V*A(LWS)
+V*LAN
+1.8V_AUX
A A
+V*AUX
+V* (CORE)
M1
S3
S4
ON
ON
ON
ON
ON
ON
ON ON ON
4
M off
S4ONS5
S5
S3
ON
ON
ON
ON
ON
ON
ON
P3.3V_LAN
P3.3V_WLL
P1.8V_LAN
P1.0V_LAN
S5-S3/Moff-M0
Samsung
ICH8-M
ICH8-M
LAN
LAN
LAN
INT_VRM_LAN
Confidential
S5-S3
3
P3.3V_ALW
P3.3V_AUX
P3.3V_M
CRESTLINE
CK505
SPI
P1.05V_AUX
P1.5V_AUX
INT_VR_ICH
ICH8-M
ICH8-M
LAN
MDC
BT
S3- S0 S0
S4-S3/M1-M0
DRAW
CHECK
APPROVAL
MODULE CODE
2
P1.5V
P3.3V
P2.5V
VTT3_PWRGD
MCH3_GFX_VR_EN
DATE
SUN XIAO
DEV. STEP
WUSHIJIANG
REV PART NO.
KEVIN LEE
LAST EDIT
6/26/2007
PV2
1.0
CRESTLINE
ICH8-M
CRESTLINE
ICH8-M
SUPER I/O
PEG
MDC
CRESTLINE
ICH8-M
R5C843
PEG
TITLE
EGFX_CORE
IGFX_CPRE
S0/M0
POWER DIAGRAM
October 23, 2007 10:38:02 AM
D
B
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
POWER RAILS ANALYSIS
1
Rev. 0.5
D D
C
B
220V
Adapter
MICOM 3V ( TBD A )
1.8V ( TBD A )
5V_AUX ( TBD A )
3.3V_AUX ( TBD A )
CPU CORE ( TBD A )
1.05V ( TBD A )
1.5V ( TBD A )
2.5V ( TBD A )
3.3V ( TBD A )
5V ( TBD A )
1.8V_AUX ( TBD A )
0.9V_AUX ( TBD A )
P1.8V_ALW (TBD A)
P1.0V_ALW (TBD A)
P3.3V_ALW ( TBD A )
VDC INV ( TBD A )
PEX IO (TBD A)
P1.2V_ALW
P2.5V_ALW
P3.3V_ALW
Battery
RTC_Battery
VGA CORE (TBD A)
TBD A (TBD)
TBD A (TBD)
TBD A (TBD)
This sheet should be updated !!!
LAN (82566)
1.05V
CPU CORE
1.05V (VCCP)
1.5V
1.05V (MCH CORE)
1.05V (VCCP)
1.5V
2.5V
3.3V
1.8V_AUX
1.05V (ICH CORE)
1.05V (VCCP)
1.5V
3.3V
3.3V_AUX
5V
5V_AUX
RTC_Battery
1V-1.2V (VGA CORE)
1.5V
1.8V
2.5V
1.2V (PEX IO)
3.3V
1.8V_AUX
0.9V_AUX
1.8V
3.3V (LCD 3V)
19V (VDC INV)
Confidential
0.1 A (TBD)
24.5 A (TBD)
3 A (TBD)
0.3 A (TBD)
4.8 A (TBD)
2.5 A (TBD)
1.3 A (TBD)
0.2 A (TBD)
0.12 A (TBD)
2.7 A (TBD)
1.3 A (TBD)
0.4 A (TBD)
1.3 A (TBD)
0.2 A (TBD)
0.12 A (TBD)
2.7 A (TBD)
2.7 A (TBD)
0.01 A (TBD)
8 A (TBD)
0.035 A (TBD)
1 A (TBD)
0.28 A (TBD)
1.6 A (TBD)
0.01 A (TBD)
Samsung
3.1 A (TBD)
1 A (TBD)
3.1 A (TBD)
0.67 A (TBD)
0.24 A (TBD)
ITP
Merom-4M
( 34 W )
*1.5V : 13.4 A (TBD)
Crestline
GMCH
(8 - 8.5 W )
ICH8-M
( ~ 2.0 W )
PEG
DDR-2
(Dual slots)
( ~ 5.0 W )
GDDR FAN
LCD
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
5V
5V
0.1 A (TBD)
0.02 A (TBD)
0.2 A (TBD)
0.2 A (TBD)
0.01 A (TBD)
0.02 A (TBD)
0.06 A (TBD)
0.07 A (TBD)
1 A (TBD)
1 A (TBD)
0.22 A (TBD)
0.16 A (TBD)
1 A (TBD)
2 A (TBD)
0.2 A (TBD)
Thermal
Sensor
SIO
CLOCK
KeyBoard
KBD LED
FWH
HD Audio
HDD
PATA
ODD
SATA HDD
Audio AMP
USB (x 4)
Touch Pad
MICOM 3V
3.3V
MICOM 3V
1.8V
3.3V
3.3V_AUX
3.3V_AUX
3.3V_AUX
3.3V_AUX
5V_AUX
3.3V
3.3V_AUX
5V
3.3V
3.3V_AUX
5V
0.08 A (TBD)
0.08 A (TBD)
0.1 A (TBD)
0.14 A (TBD)
0.1 A (TBD)
0.1 A (TBD)
0.6 A (TBD)
0.1 A (TBD)
1.2 A (TBD)
1 A (TBD)
0.7 A (TBD)
0.2 A (TBD)
0.4 A (TBD)
0.3 A (TBD)
0.01 A (TBD)
0.3 A (TBD)
KBC
PWR LED
R5C843
LAN (Intel)
SD Card
Card Bus
Mini PCI
MDC
C
B
A A
Value by Datasheet/Application notes
4
3
(Value by measurement)
DRAW
CHECK
APPROVAL
MODULE CODE
2
SUN XIAO
WUSHIJIANG
KEVIN LEE
DATE
DEV. STEP
REV
LAST EDIT
6/26/2007
TITLE
PV2
1.0
Gevena
POWER RAILS
October 23, 2007 10:38:02 AM
1
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
558
PAGE
OF
30
PEG
Gevena
1
Rev. 0.5
CPU
VRM
DC/DC B’d
9) P1.8V_AUX
16) P1.05V
16) P3.3V
1
26
25) VCC_CORE
25
30) CPU1_CPURST*
29) PLT3_RST*
29
29) PCI3_RST*
SAMSUNG
ELECTRONICS
BA41-XXXXX
658
PAGE OF
KBC
12
4
Host Boot / ME Off
(SLPS4* = S4_STATE*) > (SLPM* = SLPS3*)
M-1) KBC3_DDR_PWRON (TBD) = 8) KBC3_SUSPWR
M-2) KBC3_ME_PWRON = 15) KBC3_PWRON
Host / ME Boot
(SLPS4* = S4_STATE*) > SLPM* > SLPS3*
Host S5 / ME Boot
(SLPS4* = SLPM*) > S4_STATE* > SLPS3*
10
10) CHP3_SLPS5*
11
13
14
8
5
11) CHP3_SLPS4*
12) CHP3_SLPSM*
13) CHP3_S4_STATE*
14) CHP3_SLPS3*
18) KBC3_PWRGD
M-1) KBC3_DDR_PWRON
M-2) KBC3_ME_PWRON
8) KBC3_SUSPWR
15) KBC3_PWRON
(Test Option)
19) KBC3_VRON
18
26) VRM3_CPU_PWRGD
16-PG) VTT3_PWRGD
9-PG) 1.8V_AUX_PWRGD
19
8) KBC3_SUSPWR or M-2) KBC3_ME_PWRON
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
POWER
S/W
DC/DC B’d
4
4) POWER_SW*
C C
3
MICOM_P3V
15
B
A
Adapter
Battery
AC_DC / Battery
MAX 8724
2) VDC
2
P3.3V_LAN & P5V_AUX
MAX 1999
6
Nineveh
Sheet 46-47
6) P3.3V_LAN
LOM
8) KBC3_SUSPWR
5) KBC3_ALWS_ON
7) P1.0V_LAN
7) P1.8V_LAN
4
MIC5219
15) KBC3_PWRON
M-2) KBC3_ME_PWRON
LT1930
GFX VR
9) P5V_AUX
9
FDS6680A
Sheet 40
FDS6680A
Sheet 40
BCP69
Sheet 46
7
16) P2.5V
8) KBC3_SUSPWR
16) P12V
16) GFX_CORE
Samsung
9-M) P3.3V_M
9) P3.3V_AUX
9
Confidential
3
TO BE UPDATED!!
6) P3.3V_LAN(A)
16) ICH_CORE (P1.05V)
27) CHP3_PWROK
PWROK
17
17) CHP3_ME_PWROK
2) VDC
M-1) KBC3_DDR_PWRON
(Test Option)
M-2) KBC3_ME_PWRON
ICH8-M
CL_PWROK
MAX8632
8
2) VDC
M-2) KBC3_ME_PWRON
15) KBC3_PWRON
15
9) P5V_AUX
9) P3.3V_AUX
9) P1.8V_AUX
9-M) P1.25V_M
9-M) P1.05V_M
3
Battery
PRTC
9) P3.3V_AUX
7) P1.05V_AUX
7) P1.5V_AUX
VRMPWRGD
Sheet 22-25
DDR2 POWER
Sheet 50
TPS5130
FDS4435
Sheet 40
FDS6680A
Sheet 40
FDS6680A
Sheet 40
FDS6680A
Sheet 40
FDS6680A
Sheet 40
RTC
1) VCC_RTC
CHP3_RTCRST
PRTC
23
23) CLK3_PWRGD
INTVRMEN
LAN100_SLP
CHP3_VRMPWRGD
28) CPU1_PWRGDCPU
29) PLT3_RST*
20
29) PCI3_RST*
9) P1.8V_AUX
9) 0.9V
9-PG) 1.8V_AUX_PWRGD
9-M) P1.05V_M
9-M) P1.25V_M
16) P1.5V
16) P1.2V
16-PG) VTT3_PWRGD
16) P5V
16) P3.3V
16) P1.8V
16) P1.25V
16) P1.05V
2
1
9-M) P3.3V_M
CK-505
Sheet 8
26) VRM3_CPU_PWRGD
22) CLK3_PWRGD*_INV
29
12
Thermal
Monitor
Sheet 14
9) P1.8V_AUX
9) P0.9V
9-M) P3.3V_M
16
2
POWER SEQUENCE
26) VRM3_CPU_PWRGD
9-M) ME Host Clock
24) Clock Running
PG-2) VTT3_PWRGD
18) KBC3_PWRGD
19) KBC3_VRON
22
28) CPU1_PWRGDCPU
28
27
27) CHP3_PWROK
17) CHP3_ME_PWROK
9-M) P1.05V_M
9-M) P1.25V_M
16) MCH_CORE
16) GFX_CORE
DDR2
Memory
Sheet 20-21
DRAW
CHECK
APPROVAL
MODULE CODE
SUN XIAO
WUSHIJIANG
KEVIN LEE
16) P1.5V
16) P1.05V
DATE
DEV. STEP
REV PART NO.
LAST EDIT
24
PWROK
CL_PWROK
16) P3.3V
16) P1.8V
16) P1.5V
16) P1.2V
2) VDC
16) P3.3V
16) P3.3V
16) P1.8V
16) P1.5V
6/26/2007
PV2
16
Sheet 10-12
Sheet 15-19
TITLE
1.0
21) CLK3_PWRGD*
21
20) KBC3_ALL_PWRGD
20
(Test Option)
CPU
GMCH
PCIe
Devices
PCI
Devices
POWER SEQUENCE
October 23, 2007 10:38:02 AM
D
B
A
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
CLK_3.3V_M
4
P0.8V
FS(2:0)
3
2
CLOCK DISTRIBUTION
1
Rev. 0.8
D
CLK3_PWRGD*
ITP_EN
CPU_STP*
C C
SS(96/100) SEL
Main PLL
PLL3
SSC
SSC
48MHz PLL
B B
SLG8SP513
CK-505M (w/ CLKREQ* & SSDC)
14 MHz
OSC
4
33 MHz
Buffer
Page 8
PCI_STP*
A A
14.318 MHz
2801-003730
200 MHz
100 MHz
MUX
200 MHz
100 MHz
100 MHz
MUX
96 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
48 MHz
100 MHz
MUX
14.318 MHz
33 MHz
33 MHz
33 MHz CLK3_PCLKMICOM
33 MHz CLK3_PCLKCB
33 MHz
33 MHz CLK3_PCLKPORT80
EXP3_CLKREQ*
CLK1_PEG/PEG*
Option For External GFX
PCI Express Gfx
Samsung
CLK3_SIO14
CLK3_PCLKSIO
CLK3_TPMLPC
Confidential
CLK3_PCLKMIN
SIO
TPM 1.2
KBC
CARDBUS
MINI PCI
PORT 80
3
CLK0_HOST_CPU/CPU*
EXPRESS
CARD
CLK0_HOST_GMCH/GMCH*
MCH3_CLKREQ*
CLK1_MCH3GPLL/3GPLL*
CLK1_DREFCLK/CLK*
CLK1_DREFSSC/SSC*
CLK3_GFX_27M/SSC
CLK1_PCIEICH/ICH*
CLK3_USB48
CHP3_SATACLKREQ*
CLK1_SATA/SATA*
CLK3_ICH14
CLK3_PCLKICH33 MHz
32.768 KHz
10 MHz
1394 Clock
24.576 MHz
2801-003898
PEG
CPU
HPLL
MPLL
PCIE PLL
DPLLA
DPLLB
PCIEPLL
USBPLL
SATAPLL
32.768 KHz
OSC
RTC Clock
32.768 KHz
2801-003856
FSB
DMI
BSEL
Crestline
GMCH
100 MHz
100 MHz
100 MHz
ICH8-M
LAN3_PHYCLK
LCI LAN
(Intel)
333/266/200 MHz
333/266/200 MHz
333/266/200 MHz
333/266/200 MHz
PEX3_CLKREQ* (TBD)
PEX3_CLKREQ* (TBD)
PEX3_CLKREQ* (TBD)
AUD3_BCLK
HD 24 MHz
MDC3_BCLK
17.86 MHz
SPI3_CLK
25 MHz
2801-003892
DRAW
CHECK
APPROVAL
MODULE CODE
2
100 MHz
HD Audio
MDC
CLK1_MCLK0/0*
CLK1_MCLK1/1*
CLK1_MCLK3/3*
CLK1_MCLK4/4*
CLK1_DCKLAN*
CLK1_MINIPCIE/PCIE*
CLK1_WIPCIE*
CLK1_NF*100 MHz
SPI
DATE
SUN XIAO
DEV. STEP
WUSHIJIANG
REV
KEVIN LEE
LAST EDIT
667/533/400 MHz
SODIMM #0
SODIMM #1
DCK LAN
MINI PCIE
HDSPA
ROBSON
LAN (3rd Vender)
TITLE
6/26/2007
PV2
1.0
October 23, 2007 10:38:02 AM
CARD
Gevena
CLOCK DIAGRAM
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
758
PAGE
1
OF
D
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
FSB
FSA
D
BSEL0
BSEL1
0
0
0
0
1
1
1
1
C
4
FSC
HOST CLK
BSEL2
0
0
0
1
1
0
0
1 166 MHz
1
CHP3_SATACLKREQ#
266 MHz
1
333 MHz
0
200 MHz
400 MHz
1
133 MHz
0
100 MHz
1
0
RSVD
1
CLK3_USB48
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
CLK3_ICH14
CLK3_SIO14
CHP3_CPUSTP#
CHP3_PCISTP#
CLK3_PWRGD
CLK3_PCLKICH
CLK3_PCLKSIO_DS
CLK3_DBGLPC
CLK3_PCLKSIO
CLK3_PCLKMICOM
MCH3_CLKREQ#
SMB3_CLK
SMB3_DATA
B
R237
R265
R266
R264
R240
R259
R260
R257
R261
R262
R263
VDD_SRC_IO
100nF
C530
R238
2.2K
10K
33
33
100 1%
33
33
33
33
475
14.31818MHz
2
C251
0.033nF
100nF
C528
1%
1%
1%33
1%
1%
Y3
3
100nF
C537
R258
10K
C250
0.033nF
6.3V10000nF
C526
R256
10K
VDD_IO
10000nF 6.3V
100nF
C525
C527
C248 C247
0.047nF
0.033nF
VDD_REF
100nF
C536
U13
SLG8SP513
19
VDD_IO
33
VDD_SRC_IO1
43
VDD_SRC_IO2
52
VDD_SRC_IO3
56
VDD_CPU_IO
27
VDD_PLL3_IO
55
NC
17
USB_FS_A
64
FSB_TESTMODE
5
REF_FS_C_TEST_SEL
44
CPUSTOP#
45
PCISTOP#
63
CLKPWRGD_PWRDN#
14
PCIF_5_ITP_EN
13
PCI_4_SEL_LCDCLK#
12
PCI_3
11
PCI_2
10
PCI_1_CLKREQ_B#
8
PCI_0_CLKREQ_A#
7
SCL
6
SDA
3
XTAL_IN
2
XTAL_OUT
18
VSS_48
59
VSS_CPU
22
VSS_IO
15
VSS_PCI
26
VSS_PLL3
1
VSS_REF
30
VSS_SRC1
36
VSS_SRC2
49
VSS_SRC3
VDD_48
100nF
C540
4700nF 10V
C539
VDD_PCI
100nF
C543
SRC11_CLKREQH#
SRC11#_CLKREQG#
SRC7_CLKREQF#
SRC7#_CLKREQE#
SRC3_CLKREQC#
SRC3#_CLKREQD#
LCDCLK#_27M_SS
SRC0#_DOT96#
VDD_PLL3
100nF
100nF
C534
C541
VDD_REF
VDD_48
VDD_PCI
VDD_PLL3
VDD_SRC
VDD_CPU
CPU0
CPU0#
CPU1_MCH
CPU1_MCH#
SRC10
SRC10#
SRC9
SRC9#
SRC8_ITP
SRC8#_ITP#
SRC6
SRC6#
SRC4
SRC4#
SRC2
SRC2#
LCDCLK_27M
SRC0_DOT96
VDD_CPU_IO
6.3V10000nF
100nF
C531
C529
33
1%
1
C252
0.033nF
NO_STUFF
VDD_PLL3_IO
10000nF 6.3V
100nF
C535
C538
P3.3V
Samsung
C249
0.033nF
VDD_SRC
100nF
C210
4
16
9
23
46
62
61
60
58
57
40
39
41
42
37
38
54
53
51
50
48
47
34
35
31
32
28
29
24
25
20
21
2
VDD_CPU
10V4700nF
C186
R239
P3.3V
B33
BLM18PG181SN1
0
SEL_LCDCLK*
CLK0_HCLK0
CLK0_HCLK0#
CLK0_HCLK1
CLK0_HCLK1#
CLK1_EXPRESSCARD
CLK1_EXPRESSCARD#
CLK1_PCIEICH
CLK1_PCIEICH#
CLK1_ROBSON
CLK1_ROBSON#
CLK1_PCIELAN
CLK1_PCIELAN#
LAN3_CLKREQ#
MIN3_CLKREQ#
CLK1_MINIPCIE
CLK1_MINIPCIE#
CLK1_MCH3GPLL
CLK1_MCH3GPLL#
EXP3_CLKREQ#
CLK1_SATA
CLK1_SATA#
GFX3_27M
GFX3_27M_SS
CLK1_PEG
CLK1_PEG#
LOW
HIGH
DOT_96/DOT_96#
SRC_0/SRC_0#
CLK REQ
CLK REQ A
CLK REQ B
CLK REQ E
CLK REQ F
Pin 20/21
1
LCDCLK/LCDCLK#
DEVICE
SATA
GMCH
MINI CARD
EXPRESS CARD
Pin 24/25
27M & 27M_SS
SRC PORT
SRC2
SRC4
SRC6
SRC8
D
C
B
Place 14.318MHz within
500mils of CK-505
NO_STUFF
Confidential
A
DRAW
CHECK
APPROVAL
MODULE CODE
4
3
2
SUN XIAO
WUSHIJIANG
KEVIN LEE
DATE
DEV. STEP
REV
LAST EDIT
6/26/2007
TITLE
Gevena
PV2
1.0
CLOCK GENERATOR
CK-505
October 23, 2007 10:38:02 AM
1
SAMSUNG
PART NO.
PAGE
ELECTRONICS
BA41-XXXXX
A
588
OF
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
D
P5.0V
C620
10000nF
6.3V
C619
100nF
C625
10000nF
6.3V
NO_STUFF
C
KBC3_PWRGD
R576
100K
1%
R577
56.2K
1%
R578
R579
FAN5_VDD
FAN3_FDBACK#
CPU3_THRMTRIP#
P3.3V_AUX
R1
R2
B
THERMAL SENSOR & FAN CONTROL
P3.3V_AUX
R590
C624
100nF
NO_STUFF
49.9
1%
U511
EMC2102
1
VDD_3V
24
VDD_5V_1
27
VDD_5V_2
14
POWER_OK
16
RESET#
10
0
FAN_MODE
25
FAN_1
26
FAN_2
28
TACH
13
THERMTRIP#
9
0
SHDN_SEL
11
TRIP_SET
8
NC_1
15
NC_2
21
NC_3
SMDATA
SMCLK
ALERT#
SYS_SHDN#
CLK_SEL
CLK_IN
THRM_PAD
DN1
DP1
DN2
DP2
DN3
DP3
GND
P3.3V
22
23
19
12
2
3
4
5
6
7
17
18
20
29
1%
10K
R588
1%
10K
R589
1%
10K
R587
1%
10K
R575
P3.3V_AUX
(Selectable : PWR_SHDN)
C622
0.47nF
C623
0.47nF
C621
2.2nF
KBC3_THERM_SMDATA
KBC3_THERM_SMCLK
THM3_ALERT#
THM3_STP#
CPU2_THERMDC
CPU2_THERMDA
GFX3_THRMDN
GFX3_THRMDP
2
MMBT3904
1
Q516
3
FAN3_FDBACK#
Samsung
FAN5_VDD
C9
10000nF
6.3V
P3.3V
R16
10K
Line Width = 20 mil
1%
MT9
RMNT-2.5-7.0-1P
J30
HDR-4P-1R-SMD
1
2
3
4
MT11
RMNT-2.5-7.0-1P
D
C
B
TRIP_SET pin voltage = (T-75)/21
3.3 * [R2/(R1+R2)] = (T-75)/21
Confidential
CPU1_THRMTRIP#
A
4
GFX3_THERM#
3 2
VCCP_CORE
R580
2K
1%
1
R573
3
Q512
MMBT3904
2
NO_STUFF
NO_STUFF
P3.3V
R574
10K
NO_STUFF
1%
0
CPU3_THRMTRIP#
DRAW
CHECK
APPROVAL
MODULE CODE
SUN XIAO
WUSHIJIANG
KEVIN LEE
A
DATE
DEV. STEP
REV
LAST EDIT
6/26/2007
TITLE
PV2
THERMAL & FAN CONTROL
1.0
Gevena
THERMAL BLOCK
October 23, 2007 10:38:02 AM
1
SAMSUNG
PART NO.
PAGE
ELECTRONICS
BA41-XXXXX
589
OF
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
D
D
VCCP_CORE
1%56.2
J1-1
MEROM-SOCKET
CPU1_A#(16:3)
13-D1
C
CPU1_ADSTB0#
CPU1_A#(35:17)
B
CPU1_ADSTB1#
13-C2
13-D1
13-C2
1 / 4
3
J4
A3*
4
L5
A4*
5
L4
A5*
6
K5
A6*
7
M3
8
N2
9
10
N3
11
12
13
14
15
16
R1
M1
17
18
U5
19
R3
20
W6
21
U4
22
23
U1
24
R4
26
27
W2
28
W5
30
U2
31
32
W3
33
AA4
34
AB2
35
AA3
J1
P5
P2
L2
P4
P1
Y2
Y5
T5
T3
Y4
V4
V1
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
0
ADDR GROUP
1
ADDR GROUP
CONTROL
ICH
ADS*
BNR*
BPRI*
BR0*
DEFER*
DRDY*
DBSY*
IERR*
INIT*
LOCK*
RESET*
RS0*
RS1*
RS2*
TRDY*
HIT*
HITM*
A20M*
FERR*
IGNNE*
STPCLK*
LINT0
LINT1
SMI*
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
R656
H1
E2
G5
F1
H5
F21
E1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
A6
A5
C4
D5
C6
B4
A3
0
K3
1
H2
Samsung
2
K2
3
J3
4
L1
13-C2
13-C2
13-C2
13-C2
13-B2
13-B2
13-B2
20-C1
13-B2
13-B3
13-A2
13-A2
13-A2
13-B2
13-B2
13-B2
20-C1
20-C1
20-C1
20-C1
20-C1
20-C1
20-C1
13-A2
CPU1_ADS#
CPU1_BNR#
CPU1_BPRI#
CPU1_BREQ#
CPU1_DEFER#
CPU1_DRDY#
CPU1_DBSY#
CPU1_INIT#
CPU1_LOCK#
CPU1_CPURST#
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
CPU1_TRDY#
CPU1_HIT#
CPU1_HITM#
CPU1_A20M#
CPU1_FERR#
CPU1_IGNNE#
CPU1_STPCLK#
CPU1_INTR
CPU1_NMI
CPU1_SMI#
CPU1_REQ#(4:0)
CPU1_D#(15:0)
CPU1_DSTBN0#
CPU1_DSTBP0#
CPU1_DBI0#
CPU1_D#(31:16)
CPU1_DSTBN1#
CPU1_DSTBP1#
CPU1_DBI1#
13-D3
13-D3
13-B2
13-B2
13-B2
13-B2
13-B2
13-B2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
J1-2
MEROM-SOCKET
2 / 4
E22
D0*
F24
D1*
E26
D2*
G22
D3*
F23
D4*
G25
D5*
E25
D6*
E23
D7*
K24
D8*
G24
D9*
J24
D10*
J23
D11*
H22
D12*
F26
D13*
K22
D14*
H23
D15*
J26
DSTBN0*
H26
DSTBP0*
H25
DINV0*
N22
D16*
K25
D17*
P26
D18*
R23
D19*
L23
D20*
M24
D21*
L22
D22*
M23
D23*
P25
D24*
P23
D25*
P22
D26*
T24
D27*
R24
D28*
L25
D29*
T25
D30*
N25
D31*
L26
DSTBN1*
M26
DSTBP1*
N24
DINV1*
DATA GRP 0
DATA GRP 2
DSTBN2*
DSTBP2*
DATA GRP 1
DATA GRP 3
DSTBN3*
DSTBP3*
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DINV3*
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
CPU1_D#(47:32)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
5425
55
56
57
5829
59
60
61
62
63
13-D3
13-B2
13-B2
13-B2
13-D3
13-B2
13-B2
13-B2
CPU1_DSTBN2#
CPU1_DSTBP2#
CPU1_DBI2#
CPU1_D#(63:48)
CPU1_DSTBN3#
CPU1_DSTBP3#
CPU1_DBI3#
C
B
CPU CONNECTOR PART NUMBER 3704-001153
MT504
MT505
RMNT-38-70-1PRMNT-38-70-1P
MT508 MT509
RMNT-38-70-1P
RMNT-38-70-1P
A
4
Confidential
TITLE
DRAW
DRAW
CHECK
CHECK
APPROVAL
APPROVAL
MODULE CODE
MODULE CODE
3
2
SUN XIAO
SUN XIAO
WUSHIJIANG
WUSHIJIANG
KEVIN LEE
KEVIN LEE
undefined
undefined
DATE
DATE
DEV. STEP
DEV. STEP
REV
REV
LAST EDIT
LAST EDIT
6/26/2007
6/26/2007
TITLE
PV2
PV2
1.0
1.0
Gevena
Gevena
CPU
CPU
MEROM(1/3)
MEROM(1/3)
October 23, 2007 10:38:02 AM
October 23, 2007 10:38:02 AM
1
SAMSUNG
SAMSUNG
PART NO.
PART NO.
10
10
PAGEPAGE
ELECTRONICS
ELECTRONICS
BA41-XXXXX
BA41-XXXXX
58
58
OF
OF
A
SAMSUNG PROPRIETARY
COM-22C-015(1996.6.5) REV. 3
D:/tingting/geneva/Geneva_pr_1023
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
2
1
D
J1-3
MEROM-SOCKET
A22
60-B412-B4
NO_STUFF
1%
1%27.4
A21
D24
AE6
D21
A24
B25
C21
B23
B22
AD26
AA1
U26
R26
AF7
AE7
C23
D25
C24
AF26
AF1
A26
AE2
AF3
AE3
AF4
AE5
AF5
AD6
D7
B5
E5
D6
C7
Y1
BCLK0
BCLK1
SLP*
DPSLP*
DPRSTP*
DPWR*
PWRGOOD
PSI*
VID_6
VID_5
VID_4
VID_3
VID_2
VID_1
VID_0
PROCHOT*
THRMDA
THRMDC
THERMTRIP*
BSEL2
BSEL1
BSEL0
GTLREF
COMP3
COMP2
COMP1
COMP0
VCCSENSE
VSSSENSE
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
H CLK
3 / 4
THERMAL
XDP/ITP SIGNALS
RSVD
CLK0_HCLK0
CLK0_HCLK0#
CPU1_SLP#
CPU1_DPSLP#
CPU1_DPRSTP#
CPU1_DPWR#
CPU1_PWRGDCPU
CPU1_PSI#
CPU1_VID(6:0)
VCCP_CORE
CPU2_THERMDA
VCCP_CORE
C
CPU2_THERMDC
CPU1_THRMTRIP#
R660
1K
1%
R661
2K
1%
CPU1_BSEL2
CPU1_BSEL1
CPU1_BSEL0
CPU1_VCCSENSE
CPU1_VSSSENSE
R657
56.2
1%
R591
R592
R659
R658
8-C1
8-C1
13-B3
20-C1
14-B1 20-C1 60-C4
13-B2
20-C1
60-B4
6
60-C4
60-B4
5
4
3
2
1
0
9-B4
9-B4
20-C114-B1
8-C4
11-A4
8-C4 11-A4
11-A48-C4
54.9
27.4 1%
54.9 1%
12-C4 60-B4
1%1K
0
0
1K 1%
C680 100nF
R597
R654
R655
B
R653
B26
VCCA_1
C26
VCCA_2
K6
VCCP_1
J6
VCCP_2
M6
VCCP_3
N6
VCCP_4
T6
VCCP_5
R6
VCCP_6
K21
VCCP_7
J21
VCCP_8
M21
VCCP_9
N21
VCCP_10
T21
VCCP_11
R21
VCCP_12
V21
VCCP_13
W21
VCCP_14
V6
VCCP_15
G21
VCCP_16
AC1
PREQ*
AC2
PRDY*
AC4
BPM3*
AD1
BPM2*
AD3
BPM1*
AD4
BPM0*
AC5
TCK
AA6
TDI
AB3
TDO
AB5
TMS
AB6
TRST*
C20
R652
DBR*
D2
RSVD_1
F6
RSVD_2
D3
RSVD_3
D22
RSVD_4
M4
RSVD_5
N5
RSVD_6
T2
RSVD_7
V3
RSVD_8
B2
RSVD_9
C3
RSVD_10
Samsung
C674
10nF
16V
VCCP_CORE
EC509
330uF
2.5V
AL
OXI Cap
Change to 270uF
11-A3
11-A3
11-A3
11-A3
0
22-D4
P1.5V
C673
10000nF
6.3V
C658
100nF
CPU1_TCK
CPU1_TDI
CPU1_TMS
CPU1_TRST#
ITP3_DBRESET#
C640
100nF
C639
100nF
C661
100nF
C659
100nF
C660
100nF
CPU Core Voltage Table
Active Mode
VID(6:0)
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
001
0
1
0
0
0
0
1
00
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
1
0
DPRSLPVR
DPRSTP*
PSI2*
Voltage
1.5000 V
0
0
0
1.4875 V
0
0
1
1
0
1.4750 V
0
1
0
1
1.4625 V
1.4500 V
0
1
1
1
1.4375 V
0
1.4250 V1
0
1
1.4125 V
1
1
1
1
1
0 1.4000 V
0
0
1
1.3875 V
0
0
1
0
0
1.3750 V
1
1
0
1.3625 V
0
0
1
1.3500 V
1
0
1.3375 V
1
1
1
1.3250 V
0
1
1
1.3125 V
1
0
0
0
1.3000 V
0
0
1
1.2875 V
1.2750 V
1
0
0
1.2625 V
0
1
1
1.2500 V
0
0
1
1
1.2375 V
1
0
1.2250 V
0
1
1
1
1.2125 V
1
1
1
1
0
0
1.2000 V
0
0
1.1875 V
1
0
1.1750 V
0
0
1
1.1625 V
1
0
1
1.1500 V
0
1
0
0
1.1375 V
1
1
1
1
1.1250 V
0
1
1
1
1.1125 V
0
0
0
1.1000 V
1
0
0
1.0875 V
1
0
0
1.0750 V
0
1
1
1.0625 V
0
0
1
1.0500 V
1
1
0
1.0375 V
0
1
1
1.0250 V
1
1
1
1
1
1.0125 V
Active
0
1
0 or 1
Active/Deeper Sleep
Dual Mode Region
VID(6:0)
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
1
10
1
DPRSLPVR
DPRSTP*
PSI2*
IMVP-6
0
1
0 1.0000 V
0
0
1
1
0 0.9750 V
1
1
0
1
1
0
1
1
0
1
1
10
1
1
1
1
1
0
0
0
0
0
0 0.8875 V
0
1
0
0
0
1
0
1
0
1
0
1
0
1 0.8250 V
1
1
0
01
0
1
1
0
0
0
1
1
1
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
10
0
0
0
1
0
0
1
1
1
0
1
0
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
Deeper Slp
1
0
0 or 1
Deeper Sleep/Extended Deeper Sleep
Dual Mode Region
Voltage
VID(6:0)
1
0
1
0.9875 V
0
0.9625 V
1
0.9500 V
0
1
0.9375 V
0.9250 V
1
0.9125 V
1
0
0.9000 V
1
0
0.8750 V
0.8625 V
1
0.8500 V
0
1
0.8375 V
0
1
0.8125 V
0.8000 V
0
1
0.7875 V
0
0.7750 V
0.7625 V
1
0
0.7500 V
1
0.7375 V
0.7250 V
0
1
1
0.7125 V
0.7000 V
0
0.6875 V
1
0
0.6750 V
0.6625 V
1
0
0.6500 V
0.6375 V
1
0
0.6250 V
1
0.6125 V
0
0.6000 V
1
0.5875 V
0.5750 V
0
1
0.5625 V
0
0.5500 V
1
0.5375 V
0.5250 V
0
0.5125 V
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 0.0000 V
1
1
1
1
1
1
1
1
1
1
1
1
1
11
*"1111111" : 0V power good asserted.
1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1
0
1
1
1
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
11
0
1
1
0
1
1
0
1
1
1
0
0
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
1
1 0.0000 V
1
1
1
1
1
Voltage
0
0.4875 V
1
1
0
0.4750 V
1
0.4625 V
1
00
0.4500 V
0
0.4375 V
1
1
0.4250 V
0
0.4125 V
11
0
0.4000 V
0
0
0
0.3875 V
1
0.3750 V
10
1
0.3625 V
1
0
0.3500 V
0
1
0.3375 V
0
0.3250 V
10
0.3125 V
1
1
0
0.3000 V
0
0.2875 V
0
1
0
1
0.2750 V
1
1
0.2625 V
0 0.2500 V
0
0 0.2375 V
1
1
0
0.2250 V
1
1
0.2125 V
0
1
0
0.2000 V
0
1
0.1875 V
0
0.1750 V
1
0.1625 V
1
1
0.1500 V
0
0
1
0
0.1375 V
0
1 0.1250 V
0.1125 V
1
1
0
0
0.1000 V
0.0875 V
0
1
1
01
0.0750 V
1
1
0.0625 V
0
0
0.0500 V
0
0.0375 V
1
1
0.0250 V
0
0.0125 V
1
1
0
1
0
0.0000 V
10 0 0.5000 V
0
1
0.0000 V
0
1
0.0000 V
1
0
0
0.0000 V
0
1
1
0.0000 V
0
0.0000 V
1
1
D
C
B
ITP DISABLE
VCCP_CORE
40.2 1%
150 1%
Confidential
R593
R595
27.4 1%
R594
475 1%
R596
A
4
11-C3
11-C3
11-C3
11-C3
CPU1_TDI
CPU1_TMS
CPU1_TCK
CPU1_TRST#
NO_STUFF
3
GTLREF : Keep the Voltage divider within 0.5"
of the first GTLREF0 pin with Zo=55ohm trace.
Minimize coupling of any switching signals to this net.
COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm)
trace shorter than 1/2" to their respective Banias socket pins.
GND test points within 100mil of the VCC/VSSsense at the end of the line.
Route the VCC/VSSsense as a Zo=55ohm traces with equal length.
Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away
(preferred 50mil) from any other signal. And GND via 100mil away
from each of the VCC/VSS test point vias.
DRAW
CHECK
APPROVAL
MODULE CODE
2
SUN XIAO
WUSHIJIANG
KEVIN LEE
DATE
DEV. STEP
REV
LAST EDIT
6/26/2007
TITLE
PV2
1.0
*Yonah Processor (2.33 GHz / 800 MHz : TBD)
Gevena
CPU
MEROM(2/3)
October 23, 2007 10:38:02 AM
PAGE
1
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
11 58
OF
A
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
3
24
1
D
A11
VSS_1
A14
A16
A19
A2
A23
A25
A4
A8
AA11
AA14
AA16
CPU_CORE
NO_STUFF
20%
C
22000nF
C633
100 1%
CPU1_VCCSENSE
CPU1_VSSSENSE
R599
R600
100 1%
20%
22000nF
C665
NO_STUFF
B
20%
22000nF
C631
20%
22000nF
C666
NO_STUFF
NO_STUFF NO_STUFF
20%
20%
22000nF
22000nF
C634
C632
20%
20%
22000nF
22000nF
C663
C662
NO_STUFF
NO_STUFF
20%
22000nF
C653
20%
22000nF
C645
NO_STUFF
20%
22000nF
C654
20%
22000nF
C646
NO_STUFF
20%
22000nF
22000nF
22000nF
22000nF
C638
C635
C637
C636
20%
20%
20%
20%
22000nF
22000nF
22000nF
22000nF
C82
C81
C66
C647
NO_STUFF
Samsung
NO_STUFF
NO_STUFF
22000nF
C67
20%
22000nF
C68
NO_STUFF
22000nF
C664
20%
22000nF
C642
20%
22000nF
C657
20%
22000nF
C641
22000nF
C656
20%
22000nF
C644
22000nF
C655
20%
22000nF
C643
20%
20%
20%
20%
20%
20%
20%
6x 330 uF : CPU VR side
Be Caution the placement of decap!!
AA19
AA22
AA25
AB11
AB13
AB16
AB19
AB26
AC11
AC14
AC16
AC19
AC21
AC24
AD11
AD13
AD16
AD19
AD22
AB23
AD25
AE11
AE14
AE16
AE19
AE23
AE26
AF11
AF13
AF16
AF19
AF21
AA2
AA5
AA8
AB1
AB4
AB8
AC3
AC6
AC8
AD2
AD5
AD8
AE1
AE4
AE8
AF2
CPU_CORE CPU_CORE
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB10
AB12
AB14
AB15
AB17
AB18
AB20
AC10
AC12
AC13
AC15
AC17
AC18
AD10
AD12
AD14
AD15
AD17
AD18
AE10
AE12
AE13
AE15
AE17
AE18
AE20
A10
A12
A13
A15
A17
A18
A20
A7
A9
AA7
AA9
AB7
AB9
AC7
AC9
AD7
AD9
VSS_163
Y6
K23
K26
VSS_121
VSS_122
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VSS_161
VSS_162
Y3
Y24
L21
L24
L3
VSS_123K4VSS_124
VSS_125
VSS_126
VSS_127L6VSS_128M2VSS_129
MEROM-SOCKET
VSS_160
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
V5
W1
W4
Y21
W23
W26
M22
4 / 4
V25
M25
VSS_130
VSS_131M5VSS_132N1VSS_133
J1-4
VSS_152
VSS_153
VSS_154
V2
V22
N23
VSS_150
VSS_151
U3
U6
N26
VSS_134
VSS_135N4VSS_136
VCC_100
VSS_148
VSS_149
U21
U24
P21
P24
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VSS_147
T4
T26
P6
VSS_137
VSS_138P3VSS_139
VSS_144
VSS_145
VSS_146
T1
T23
R22
VSS_140R2VSS_141
AE9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
AF9
B10
B12
B14
B15
B17
B18
B20
B7
B9
C10
C12
C13
C15
C17
C18
C9
D10
D12
D14
D15
D17
D18
D9
E10
E12
E13
E15
E17
E18
E20
E7
E9
F10
F12
F14
F15
F17
F18
F20
F7
F9
VSS_142
VSS_143
R5
R25
VSS_120
VSS_119
VSS_118
VSS_117
VSS_116
VSS_115
VSS_114
VSS_113
VSS_112
VSS_111
VSS_110
VSS_109
VSS_108
VSS_107
VSS_106
VSS_105
VSS_104
VSS_103
VSS_102
VSS_101
VSS_100
VSS_99
VSS_98
VSS_97
VSS_96
VSS_95
VSS_94
VSS_93
VSS_92
VSS_91
VSS_90
VSS_89
VSS_88
VSS_87
VSS_86
VSS_85
VSS_84
VSS_83
VSS_82
VSS_81
VSS_80
VSS_79
VSS_78
VSS_77
VSS_76
VSS_75
VSS_74
VSS_73
VSS_72
VSS_71
VSS_70
VSS_69
VSS_68
VSS_67
VSS_66
VSS_65
VSS_64
VSS_63
VSS_62
VSS_61
K1
J5
J25
J22
J2
H6
H3
H24
H21
G4
G26
G23
G1
F8
F5
F25
F22
F2
F19
F16
F13
F11
E8
E6
E3
E24
E21
E19
E16
E14
E11
D8
D4
D26
D23
D19
D16
D13
D11
D1
C8
C5
C25
C22
C2
C19
C16
C14
C11
B8
B6
B24
B21
B19
B16
B13
B11
AF8
AF6
AF25
D
C
B
Confidential
A
DRAW
CHECK
APPROVAL
MODULE CODE
3
24
SUN XIAO
WUSHIJIANG
KEVIN LEE
DATE
DEV. STEP
REV
LAST EDIT
6/26/2007
TITLE
Gevena
PV2
1.0
CPU
MEROM(3/3)
October 23, 2007 10:38:02 AM
1
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
12 58
PAGE OF
A
24
C
3
COM-22C-015(1996.6.5) REV. 3
SAMSUNG PROPRIETARY
1
D:/tingting/geneva/Geneva_pr_1023
B
A
D
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
VCCP_CORE
C731
2200nF
C733
4700nF
10V
C730
470nF
16V
C732
4700nF
XC501
330uF
10V
NO_STUFF
2.5V
OXI
U13
U12
CPU1_D#(63:0)
VCCP_CORE
R684
221
1%
13-A3
C728
100nF
MCH1_HXSWING
R685
100
1%
VCCP_CORE
R697
1K
R696
1%
C812
100nF
2K
1%
13-A3
MCH1_HVREF
VCCP_CORE
10-C1 10-C2 10-D1 10-D2
Samsung
CPU1_CPURST#
CPU1_SLP#
MCH1_HXSWING
Confidential
MCH1_HVREF
0 4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
10-C3
11-D4
R688
R687
13-C4
R686
13-B4
54.9
54.9
24.9 1%
E2
HD*_0
G2
HD*_1
G7
HD*_2
M6
HD*_3
H7
HD*_4
H3
HD*_5
G4
HD*_6
F3
HD*_7
N8
HD*_8
H2
HD*_9
M10
HD*_10
N12
HD*_11
N9
HD*_12
H5
HD*_13
P13
HD*_14
K9
HD*_15
M2
HD*_16
W10
HD*_17
Y8
HD*_18
V4
HD*_19
M3
HD*_20
J1
HD*_21
N5
HD*_22
N3
HD*_23
W6
HD*_24
W9
HD*_25
N2
HD*_26
Y7
HD*_27
Y9
HD*_28
P4
HD*_29
W3
HD*_30
N1
HD*_31
AD12
HD*_32
AE3
HD*_33
AD9
HD*_34
AC9
HD*_35
AC7
HD*_36
AC14
HD*_37
AD11
HD*_38
AC11
HD*_39
AB2
HD*_40
AD7
HD*_41
AB1
HD*_42
Y3
HD*_43
AC6
HD*_44
AE2
HD*_45
AC5
HD*_46
AG3
HD*_47
AJ9
HD*_48
AH8
HD*_49
AJ14
HD*_50
AE9
HD*_51
AE11
HD*_52
AH12
HD*_53
AJ5
HD*_54
AH5
HD*_55
AJ6
HD*_56
AE7
HD*_57
AJ7
HD*_58
AJ2
HD*_59
AE5
HD*_60
AJ3
HD*_61
AH2
HD*_62
AH13
HD*_63
B6
H_CPURST*
E5
H_CPUSLP*
1%
W1
H_SCOMP
1%
W2
H_SCOMP*
B3
H_SWING
C2
H_RCOMP
A9
H_DVREF
B9
H_AVREF
VCCP_CORE
U11
VTT_1
VTT_2
Host Data Bus
VCC_1
AT35
AT34
VTT_3U9VTT_4U8VTT_5U7VTT_6U5VTT_7U3VTT_8U2VTT_9
VCC_2
4 1
3
VCC_3
AH28
VCC_4
AC32
VCC Core
VCC_5
VCC_6
AK32
AC31
U1
T13
T11
T10
VTT_10
VTT_11
VTT_12
VTT_13T9VTT_14T7VTT_15T6VTT_16T5VTT_17T3VTT_18T2VTT_19
VTT
U32-1
LE88CLPM
1 OF 5
VCC_10
VCC_11
VCC_12
VCC_8
VCC_9
AH32
AH31
AH29
AF32
VCC_13
R30
VCC_7
AJ31
AJ28
R3
VTT LF
VTTLF_1
16V470nF
F2
A7
470nF 16V
C729
C727
R1
VTT_20R2VTT_21
VTT_22
VTTLF_2
VTTLF_3
16V470nF
AH1
C734
HA*_3
HA*_4
HA*_5
HA*_6
HA*_7
HA*_8
HA*_9
HA*_10
HA*_11
HA*_12
HA*_13
HA*_14
HA*_15
HA*_16
HA*_17
HA*_18
HA*_19
HA*_20
HA*_21
HA*_22
Host Address Bus
HA*_23
HA*_24
HA*_25
HA*_26
HA*_27
HA*_28
HA*_29
HA*_30
HA*_31
HA*_32
HA*_33
HA*_34
HA*_35
H_ADS*
H_ADSTB*_0
H_ADSTB*_1
H_BNR*
H_BPRI*
H_BREQ*
H_DEFER*
H_DBSY*
H_DPWR*
H_DRDY*
H_HIT*
H_HITM*
H_LOCK*
H_TRDY*
HPLL_CLK
HPLL_CLK*
H_DINV*_0
H_DINV*_1
H_DINV*_2
H_DINV*_3
H_DSTBN*_0
H_DSTBN*_1
H_DSTBN*_2
H_DSTBN*_3
H_DSTBP*0
H_DSTBP*1
H_DSTBP*2
H_DSTBP*3
H_REQ*_0
H_REQ*_1
H_REQ*_2
H_REQ*_3
H_REQ*_4
H_RS*_0
H_RS*_1
H_RS*_2
2
DRAW
CHECK
APPROVAL
MODULE CODE
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
H8
K7
E4
C6
G10
B7
AM5
AM7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
0
1
2
3
4
SUN XIAO
WUSHIJIANG
KEVIN LEE
10-C3
10-C4
10-B4
10-C3
10-C3
10-C3
10-C3
10-C3
11-D4
10-C3
10-C3
10-C3
10-C3
10-C3
10-C2
10-B2
10-C1
10-B1
10-C2
10-B2
10-C1
10-B1
10-C2
10-B2
10-C1
10-B1
10-B3
10-C3
10-C3
10-C3
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2925
30
31
32
33
34
35
8-C1
8-C1
10-C410-D4
Calero : HA*[35:32] not support
CPU1_ADS#
CPU1_ADSTB0#
CPU1_ADSTB1#
CPU1_BNR#
CPU1_BPRI#
CPU1_BREQ#
CPU1_DEFER#
CPU1_DBSY#
CPU1_DPWR#
CPU1_DRDY#
CPU1_HIT#
CPU1_HITM#
CPU1_LOCK#
CPU1_TRDY#
CLK0_HCLK1
CLK0_HCLK1#
CPU1_DBI0#
CPU1_DBI1#
CPU1_DBI2#
CPU1_DBI3#
CPU1_DSTBN0#
CPU1_DSTBN1#
CPU1_DSTBN2#
CPU1_DSTBN3#
CPU1_DSTBP0#
CPU1_DSTBP1#
CPU1_DSTBP2#
CPU1_DSTBP3#
CPU1_REQ#(4:0)
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
DATE
6/26/2007
DEV. STEP
PV2
REV
1.0
LAST EDIT
CPU1_A#(35:3)
TITLE
October 23, 2007 10:38:02 AM
Gevena
CMCH
CRESTLINE (1/5)
SAMSUNG
PART NO.
13 58
PAGE
D
C
B
A
ELECTRONICS
BA41-XXXXX
OF
D
B
COM-22C-015(1996.6.5) REV. 3
A
SAMSUNG PROPRIETARY
C
D:/tingting/geneva/Geneva_pr_1023
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
3
4
0
32
5
621112
1
72-C4
27-D327-D2
27-C2
27-C3
PM-model
100nFC501
100nFC508
100nFC505
PEG1_RXN(15:0) PEG1_RXP(15:0)
27-C327-D227-D3 27-C272-B4
5
0
1
4
1311
7143
9
10
8
0
12
15
14
72-C4 27-D3 27-D2
27-B327-C2
27-B2
6
2
3
7
11
12
10
8
5
16
13
94
27-C3
100nFC503
C906 100nF
C898 100nF
15
C902 100nF
2
8
13 8
10
14
7
9
100nF
100nF
100nFC513
100nFC515
C511
C911 100nF
C923
C915 100nF
C919 100nF
3
15
0
114
100nFC157
100nFC895
C500 100nF
C926 100nF
C502 100nF
6
47
5
100nF
100nFC904
100nFC900
C507 100nF
C506
100nFC909
92
100nFC914
C510 100nF
10
100nFC918
C512 100nF
12
13
100nFC921
C514 100nF
15
100nFC92511100nFC156
27-C3
72-D4
27-D2
27-C2
27-D3
1
PEG1_TXP(15:0)PEG1_TXN(15:0)
D
24.9 1%
R736
22-D2
22-D2
22-C2
22-C2
22-D2
22-D2
22-C2
22-C2
22-D2
22-D2
22-D2
22-C2
22-D2
22-D2
22-D2
22-C2
22-C2
22-C2
22-B425-C1
22-C2
14-A1
22-D4
60-C4 20-C1 11-D4
34-A4 25-B2
51-C4
22-B4
100
11-C420-C1
22-C460-C4
MCH3_CL_VREF
1
P1.05V_PEG
DMI1_TXN_0
DMI1_TXN_1
DMI1_TXN_2
DMI1_TXN_3
DMI1_TXP_0
DMI1_TXP_1
DMI1_TXP_2
DMI1_TXP_3
DMI1_RXN_0
DMI1_RXN_1
DMI1_RXN_2
DMI1_RXN_3
DMI1_RXP_0
DMI1_RXP_1
DMI1_RXP_2
DMI1_RXP_3
8-B1
CLK1_MCH3GPLL
8-B1
CLK1_MCH3GPLL#
CHP3_CL_CLK_0
CHP3_CL_DATA_0
KBC3_PWRGD
CHP3_CL_RST#_0
MCH3_CL_VREF
MCH3_BMBUSY#
CPU1_DPRSTP#
MCH3_EXTTS0#
MCH3_EXTTS1#
KBC3_PWRGD
1%
PLT3_RST#
CPU1_THRMTRIP#
CHP3_DPRSLPVR
SAMSUNG
PART NO.
PAGE
14-B1
C516
100nF
ELECTRONICS
BA41-XXXXX
C
Connect to GND for PM-model
B
27-C2
28-C3
25-A4
37-A4
38-C2
39-C3
22-B4
21-C1
P1.25V
R502
1K
1%
R501
390
A
5814
OF
M47
U44
T49
J51
L51
N47
MCH3_CLKREQ#
MCH3_ICHSYNC#
R735
R714
22-A4
14-A28-C4
0
20K
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
E33
CRT_VSYNC
H32
CRT_BLUE
G32
CRT_BLUE*
K29
CRT_GREEN
J29
CRT_GREEN*
F29
CRT_RED
E29
CRT_RED*
C32
CRT_TVO_IREF
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
C37
L_DDC_CLK
D35
L_DDC_DATA
E39
L_CTRL_CLK
E40
L_CTRL_DATA
K40
L_VDD_EN
J40
L_BKLT_CTRL
H39
L_BKLT_EN
G51
LVDSA_DATAN_0
E51
LVDSA_DATAN_1
F49
LVDSA_DATAN_2
G50
LVDSA_DATAP_0
E50
LVDSA_DATAP_1
F48
LVDSA_DATAP_2
D46
LVDSA_CLK*
C45
LVDSA_CLK
G44
LVDSB_DATAN_0
B47
LVDSB_DATAN_1
B45
LVDSB_DATAN_2
E44
LVDSB_DATAP_0
A47
LVDSB_DATAP_1
A45
LVDSB_DATAP_2
D44
LVDSB_CLK*
E42
LVDSB_CLK
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
H35
SDVO_CTRL_CLK
K36
SDVO_CTRL_DATA
G39
CLK_REQ*
G40
ICH_SYNC*
A37
TEST_1
1%
R32
TEST_2
T45
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
TV VGA
LVDSMISC
Samsung
Confidential
A35
T50
U40
Y44
Y40
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
RSVD_4
RSVD_2
RSVD_3
RSVD_1
B34
B37
B36
C34
AD44
AD40
AG46
AH49
AB51
W49
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
T14
R20
W13
W14
Y12
AA20
VCC_AXG_2
VCC_AXG_1
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
Y17
Y19
Y20
Y21
Y23
Y24
RSVD_8
RSVD_9
RSVD_5
RSVD_6
RSVD_7
RSVD_10
RSVD_11
BJ29
BJ20
BF23
BK22
BC23
BG23
19-C4
18-C4 18-C2
AG45
AG41
PEG_RXN_14
PEG_RXN_15
AA28
AA23
AA26
VCC_AXG_9
VCC_AXG_7
VCC_AXG_8
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
Y26
Y28
Y29
RSVD_12
RSVD_13
RSVD_14
BE24
BD24
BH39
19-C2
4
3
J50
L50
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
T41
W45
W41
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
AB50
Y48
AC45
AC41
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_RXP_10
AH47
AG49
AH45
AG42
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PCIE GFX
N45
U39
U47
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
Y43
N51
R50
T42
PEG_TXN_6
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
W46
PEG_TXN_7
U32-2
LE88CLPM
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AB21
AB24
AB29
AC20
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
AC21
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_14
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
AF21
AF26
AA31
AH20
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
AH21
AH23
VCC_AXG_28
AH24
AH26
AD31
AJ20
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
T17
AN14
VCC_AXG_34
VCC_AXG_NCTF_1
2 OF 5
GFX VCC NCTF
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
AL16
AK19
RSVD_40
RSVD_41
C48
D47
18-C314-B1
14-A4 8-C4
19-C314-B1
AL17
AL19
AL20
RSVD_42
RSVD_43
B44
C44
D20
AL21
RSVD_44
B51
1%
VCC_AXG_NCTF_60
AL23
RSVD_45
11-A4
11-A4
11-A4
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
AF19
AH15
AH16
RSVD_31
RSVD_32
H10
AR12
AR13
AH17
AH19
RSVD_34
RSVD_35
RSVD_33
AN13
AM12
AJ16
RSVD_36
AR37
VCC_AXG_NCTF_51
AJ19
AJ17
AK16
RSVD_37
RSVD_38
RSVD_39
AL36
AM36
AM37
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
AA16
AA17
AB16
AB19
RSVD_20
RSVD_21
RSVD_22
BJ18
BF19
BK18
BH20
MEM1_BMA(14)
MEM1_AMA(14)
AF16
AC16
AC17
AC19
AD15
AD16
AD17
RVSD CFG
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
RSVD_28
RSVD_29
RSVD_30
J12
P36
P37
R35
N35
BK20
AW20
P3.3V
10K
R713
10K 1%
R711
10K
R712
1%
W38
AD39
AC46
AC49
AC42
AH39
AE49
PEG_TXN_8
PEG_TXN_9
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
T25
U15
T23
T21
T22
T19
T18
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_6
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_3
VCC_AXG_NCTF_2
VCC_AXG_NCTF_67
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
AP15
AM15
AM16
AM19
AM20
AM21
AM23
CFG_2
CFG_3
CFG_4
CFG_5
CFG_0
CFG_1
F23
P27
N24
C21
C23
N27
MCH3_EXTTS0#
MCH3_CLKREQ#
MCH3_EXTTS1#
2
M45
T38
T46
N50
AH44
U16
AP16
N23
R51
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXN_15
U17
U19
U20
U21
U23
U26
V16
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
GFX VCC NCTFGFX VCC
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
AP17
AP19
AP20
AP21
AP23
AP24
AR20
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
J20
J23
L23
E23
C20
R24
G23
DRAW
CHECK
APPROVAL
MODULE CODE
W42
Y47
Y39
AC38
AD47
AC50
U43
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
PEG_TXP_4
PEG_TXP_5
PEG_TXP_10
PEG_TXP_11
Y15
V17
V19
V20
V21
V23
V24
VCC_AXG_NCTF_16
VCC_AXG_NCTF_75
AR21
CFG_13
E20
VCC_AXG_NCTF_23
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
V28
V29
V26
AR23
AR24
AR26
CFG_20
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
L35
L32
K23
N33
M20
M24
SUN XIAO
WUSHIJIANG
KEVIN LEE
AD43
AG39
AE50
AH43
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
Y16
VCC_AXG_NCTF_24
VCC_AXG_NCTF_83
Y31
DATE
6/26/2007
DEV. STEP
REV
LAST EDIT
PEG_COMPI
PEG_COMPO
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
PCIE GFXDMICLK
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
DPLL_REF_CLK
DPLL_REF_CLK*
DPLL_REF_SSCLK
DPLL_REF_SSCLK*
PEG_CLK
PEG_CLK*
CL_DATA
CL_PWROK
MEPMNC
CL_RST*
CL_VREF
PM_BM_BUSY*
PM_DPRSTP*
PM_EXT_TS*_0
PM_EXT_TS*_1
THERMTRIP*
DPRSLPVR
TITLE
PV2
1.0
N43
M43
E35
A39
C38
B39
E36
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
B42
C42
H48
H47
K44
K45
AM49
CL_CLK
AK50
AT43
AN49
AM50
G41
L39
L36
J36
AW49
PWROK
AV20
R698
RSTIN*
N20
G36
BJ51
NC_1
BK51
NC_2
BK50
NC_3
BL50
NC_4
BL49
NC_5
BL3
NC_6
BL2
NC_7
BK1
NC_8
BJ1
NC_9
E1
NC_10
A5
NC_11
C51
NC_12
B50
NC_13
A50
NC_14
A49
NC_15
BK2
NC_16
Gevena
GMCH
CRESTLINE (2/5)
October 23, 2007 10:38:02 AM
B
C
A
D
34 2
COM-22C-015(1996.6.5) REV. 3
1
SAMSUNG PROPRIETARY
D:/tingting/geneva/Geneva_pr_1023
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
MEM1_ADQ(63:0)
MEM1_ABS0
MEM1_ABS1
MEM1_ABS2
MEM1_ADM(7:0)
18-B2
18-B4
MEM1_ADQS#(7:0)
MEM1_ADQS(7:0)
MEM1_AMA(13:0)
18-A4
18-B4
18-C4 18-D2
MEM1_ACAS#
MEM1_ARAS#
MEM1_AWE#
MEM1_CS0#
MEM1_CS1#
MEM1_CS2#
MEM1_CS3#
MEM1_ODT0
MEM1_ODT1
P1.8V_AUX
R129
1K
1%
R128
3.01K
1%
R127
1K
C142
10nF
16V
C143
10nF
16V
P1.8V_AUX
MEM1_ODT2
MEM1_ODT3
R115
R116
C140
2200nF
C139
2200nF
22.6
22.6
18-B2 18-B4
18-B2 18-B4
18-B2
19-C2 19-C4
19-C2 19-C4
18-B2 18-B4
18-B2 18-B4
BB19
18-C4
BK19
18-C418-B2
BF29
18-C418-B2
0
AT45
1
BD44
2
BD42
3
AW38
4
AW13
5
BG8
6
AY5
7
AN6
AT47
BD47
2
BC41
3
BA37
4
BA16
5
BH7
6
BC1
7
AP2
AT46
1
BE48
2
BB43
3
BC37
4
BB16
5
BH6
6
BB2
7
AP3
0
BJ19
1
BD20
2
BK27
3
BH28
4
BL24
5
BK28
6
BJ27
7
BJ25
8
BL28
9
BA28
10
BC19
11
BE28
12
BG30
13
BJ16
BL17
BE18
BA19
18-B4
AY20
BG20
18-C418-C2
BK16
18-C418-C2
BG16
BE13
BH18
BJ15
BJ14
19-B419-B2
BE16
19-B419-B2
1%
BL15
1%
BK14
BK31
BL31
Route as short as possible
4
18-D4
SA_BS_0
SA_BS_1
SA_BS_2
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS*_0
SA_DQS*_1
SA_DQS*_2
SA_DQS*_3
SA_DQS*_4
SA_DQS*_5
SA_DQS*_6
SA_DQS*_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_CAS*
SA_RAS*
SA_WE*
SA_RCVEN*
SM_CS*_0
Samsung
SM_CS*_1
SM_CS*_2
SM_CS*_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP*
SM_RCOMP_VOH
SM_RCOMP_VOL
Confidential
1
AR43
AW44
BA45
SA_DQ_0
SA_DQ_1
4
5
AR41
AY46
SA_DQ_4
SA_DQ_2
SA_DQ_3
6
7
AW47
AR45
AT42
SA_DQ_5
SA_DQ_6
10
9
BB45
BF48
BG47
SA_DQ_7
SA_DQ_8
SA_DQ_9
112
13
BJ45
BB47
SA_DQ_10
SA_DQ_11
SA_DQ_12
20 24 61
14
15
16
BH49
BE45
AW43
SA_DQ_14
SA_DQ_15
SA_DQ_16
BE44
BG42
BE40
SA_DQ_17
SA_DQ_18
BF44
SA_DQ_19
BG50
SA_DQ_13
211119
23
BH45
BG40
BF40
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
27
AR40
AW40
AT39
SA_DQ_24
SA_DQ_25
SA_DQ_26
34
33
280 35
303031
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SYSTEM MEMORY A
36
37
AV11
AU15
AT11
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
41
39
40
BA13
BA11
BE10
SA_DQ_38
SA_DQ_39
SA_DQ_40
4326
42
BD10
BD8
AY9
SA_DQ_41
SA_DQ_42
U32-3
LE88CLPM
3 OF 5
SYSTEM MEMORY ADDR MUX
SYSTEM MEMORY B
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
AP49
AR51
AN51
AW50
AW51
0
2
417
311 51
SB_DQ_6
SB_DQ_4
SB_DQ_5
AV50
AV49
AN50
5
7
SB_DQ_9
SB_DQ_7
SB_DQ_8
BA50
BB50
9
8
SB_DQ_10
SB_DQ_11
SB_DQ_12
BA49
BE50
BA51
12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
BJ50
BJ44
BJ43
BJ41
BJ37
BK49
22
BK43
23
BK42
24
BJ36
BL41
28
26
25
BL43
BF50
BF49
AY49
BK47
155513
20
182516
19 39
21
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
BJ40
BL35
BK41
BK37
BK13
BE11
BK11
BC11
32
34
29
35
31
33 46
36 49627
SB_DQ_37
SB_DQ_38
SB_DQ_35
SB_DQ_36
BE12
BC12
BC13
38
37
SB_DQ_39
SB_DQ_40
SB_DQ_41
BL9
BJ10
BG12
42
41
40
BK5
43
45381781%12 62
5118 22
4932
47
5250 54
460445048 56
BG10
AW9
BD7
SA_DQ_43
SA_DQ_44
SA_DQ_45
SB_DQ_42
SB_DQ_43
SB_DQ_44
BL5
BK9
BK10
44
45
5329
AT5
AT7
AY6
BB7
BB9
BB5
AY7
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_46
SA_DQ_47
SA_DQ_48
SB_DQ_51
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
BJ8
BJ6
BF4
BK3
BH5
BC2
BG1
48
53
47 54352
DRAW DATE
CHECK
APPROVAL
MODULE CODE
23 1
57
AR5
AR8
AR9
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
BJ2
BE4
BD3
56
55
60 63
59
58
AN3
AM8
AN10
SA_DQ_57
SA_DQ_58
SA_DQ_59
SB_DQ_56
SB_DQ_57
SB_DQ_58
BA3
BB3
AR1
5905714
58
SUN XIAO
WUSHIJIANG
KEVIN LEE
AT9
AN9
AM9
SA_DQ_60
SA_DQ_61
SA_DQ_62
SB_DQ_59
SB_DQ_60
SB_DQ_61
AT3
AY2
AY3
62
60
6110
DEV. STEP
REV
LAST EDIT
AN11
SA_DQ_63
SB_DQ_62
SB_DQ_63
AT2
AU2
63
SM_VREF_0
SM_VREF_1
SB_DQS*_0
SB_DQS*_1
SB_DQS*_2
SB_DQS*_3
SB_DQS*_4
SB_DQS*_5
SB_DQS*_6
SB_DQS*_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SYSTEM MEMORY B DDR MUX
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_RCVEN*
19-D4
6/26/2007
PV2
SM_CK*0
SM_CK*1
SM_CK*3
SM_CK*4
SM_CK0
SM_CK1
SM_CK3
SM_CK4
SM_CKE0
SM_CKE1
SM_CKE3
SM_CKE4
SB_BS_0
SB_BS_1
SB_BS_2
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_CAS*
SB_RAS*
SB_WE*
1.0
AR49
AW4
AW30
BA23
AW25
AW23
AV29
BB23
BA25
AV23
BE29
AY32
BD39
BG37
AY17
BG18
BG36
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE17
AV16
BC17
AY18
MEM1_BDQ(63:0)
TITLE
CRESTLINE (3/5)
October 23, 2007 10:38:02 AM
19-C3
18-B4 18-B2
19-C2
19-B4 19-B2
19-C4 19-B2
19-C4 19-B2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Gevena
GMCH
19-A4
19-B4
19-C4
19-D2
19-B219-B4
19-B219-B4
19-B219-B4
18-C3
57-C4
18-C4
18-B4
19-C4
19-B4
18-C4
18-C4
19-C4
19-C4
18-B418-C2
19-B4
19-B219-C4
19-B4
MEM1_VREF
CLK1_MCLK0#
CLK1_MCLK1#
CLK1_MCLK3#
CLK1_MCLK4#
CLK1_MCLK0
CLK1_MCLK1
CLK1_MCLK3
CLK1_MCLK4
MEM1_CKE0
MEM1_CKE1
MEM1_CKE3
MEM1_CKE4
MEM1_BBS0
MEM1_BBS1
MEM1_BBS2
MEM1_BDM(7:0)
MEM1_BDQS#(7:0)
MEM1_BDQS(7:0)
MEM1_BMA(13:0)
MEM1_BCAS#
MEM1_BRAS#
MEM1_BWE#
SAMSUNG
PART NO.
PAGE
ELECTRONICS
BA41-XXXXX
15 58
OF
D
C
B
A
3
C
B
SAMSUNG PROPRIETARY
D
1
A
4
D:/tingting/geneva/Geneva_pr_1023
2
COM-22C-015(1996.6.5) REV. 3
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
T34
VCC AXM NCTFVCC AXM A SMA SM NCTFA SM CKVCC AXD
VCC AXF
T30
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
VCC_SM_LF_7
VCC_SM_LF_5
VCC_SM_LF_6
AT6
AW8
VCCP_CORE
C857
22000nF
20%
C856
C851
100nF
100nF
P1.25V
EC504
100uF
6.3V
AD
C815
22000nF
20%
P1.25V
C859
22000nF
20%
C862
1000nF
6.3V
NO_STUFF
P1.25V
R715
0
C860
22000nF
20%
NO_STUFF
Crestline : 0ohm (No Filter)
Crestline : 5.6 nH (Filter)
C850
220nF
C854
100nF
NO_STUFF
C814
4700nF
10V
C858
1000nF
C864
22000nF
20%
C861
1000nF
6.3V
NO_STUFF
C863
100nF
AL24
AL26
AL28
C855
AL29
220nF
AL31
AL32
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AR31
AR32
AR33
AJ23
AJ26
AK23
AK24
AK29
AT31
AT33
AW18
AV19
AU19
AU18
AU17
AT22
C813
1000nF
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
AU28
AU24
AT30
AT29
AT25
AT23
AR29
B23
B21
A21
P1.25V
Crestline : 22 uF, 5.6 nH
VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
VCC_AXD_NCTF_1
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
C848
100nF
4
U32
U31
U29
T35
U33
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_44
V36
V33
V32
U36
U35
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
Y36
Y35
Y33
Y32
V37
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
AA36
AA35
AA33
Y37
AB33
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_29
AC36
AC35
AC33
AB37
AB36
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC NCTF
AF36
AF33
AD36
AD35
AD33
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
AH36
AH35
AH33
AJ33
AH37
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_14
VCC_NCTF_15
AK36
AK35
AK33
AJ36
AJ35
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_8
AM35
AL35
AL33
AK37
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_4
AP35
AR35
AP36
AR36
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_1
C853
1000nF
C676
220nF
PEGLVDSCRTTVPLLDMIHVTV/CRT
U32-4
LE88CLPM
4 OF 5
Samsung
VCC SMVCC SM CKVCC SM LF
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_LF_4
BD4
BE39
BC39
BD17
AW45
Confidential
C125
100nF
BJ23
BJ24
BK24
BK23
C123
22000nF
20%
VCC_SM_36
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
BL33
BK33
BK34
BK35
R114
1
C124
10000nF
6.3V
VCC_SM_29
VCC_SM_30
VCC_SM_31
BJ32
BJ33
BJ34
BK32
L10
1uH
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
BH32
BH34
BH35
BG35
P1.8V_AUX
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_21
BF34
BF33
BG32
BG33
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
BE32
BE33
BE35
BD35
C145
100nF
VCC_SM_16
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
VCC_SM_LF_1
VCC_SM_LF_2
VCC_SM_LF_3
3
VCC_SM_13
VCC_SM_14
VCC_SM_15
BC32
BC33
BC35
BD32
C144
22000nF
20%
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
BA32
BA33
BA35
BB33
C141
22000nF
20%
AV33
AY35
AW33
AW35
P1.8V_AUX
EC505
330uF
2.5V
AL
VCC_SM_3
AU35
VCC_SM_1
VCC_SM_2
AU33
AU30
AU32
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
VCC_RXR_DMI_1
VCC_RXR_DMI_2
2
VCCP_CORE
C675
C852
22000nF
220nF
20%
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VCCA_PEG_PLL
VCCA_PEG_BG
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
VCCA_LVDS
VCC_TX_LVDS
VCCA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCD_HPLL
VCCD_TVDAC
VCCD_QDAC
AD51
V49
V50
W50
W51
U51
K50
U48
J41
H42
A41
A43
J32
VCC_SYNC
A33
B33
A30
C25
B25
C27
B27
B28
A28
B49
H49
AL2
AM2
AN2
AJ50
VCC_DMI
AH50
AH51
C40
VCC_HV_1
B40
VCC_HV_2
M32
VCCD_CRT
L29
N28
DRAW
CHECK
APPROVAL
MODULE CODE LAST EDIT
270uF
EC503
330uF
2.5V
AL
P1.25V
C849
100nF
SUN XIAO
WUSHIJIANG
KEVIN LEE
C179
10000nF
6.3V
P3.3V
C885
100nF
P1.25V
C927
100nF
B530
MMZ1608S121AT
DATE
DEV. STEP
REV
P1.05V_PEG
P1.25V
C735
100nF
P1.05V_PEG
C158
10000nF
6.3V
P3.3V
R734
C884
100nF
6/26/2007
PV2
1.0
EC501
330uF
2.5V
AL
C886
100nF
C679
100nF
XC500
330uF
2.5V
OXI
12.11%
P1.5V
TITLE
VCCP_CORE
B32
BLM18PG181SN1
R500
1
C509
100nF
C504
10000nF
6.3V
C677
22000nF
20%
B29
BLM18PG181SN1
NO_STUFF
NO_STUFF
D517
BAT54
TP19346
13
Gevena
GMCH
CRESTLINE (4/5)
October 23, 2007 10:38:02 AM
P1.25V
B500
BLM18PG181SN1
220ohm@100MHz
B526MMZ1608S121AT
C678
R689
100nF
1
C736
22000nF
20%
VCCP_CORE
If VCC_PEG = VCC_RXR_DMI
Remove these parts
VCC_ PEG : P1.25V / P1.05V
VCC_RXR_DMI : P1.25V / P1.05V
P1.25V
MMZ1608S121AT
B525
SAMSUNG
PART NO.
16 58
PAGE
1
D
C
B
A
ELECTRONICS
BA41-XXXXX
OF
1
2
4
B
COM-22C-015(1996.6.5) REV. 3
3
A
SAMSUNG PROPRIETARY
D:/tingting/geneva/Geneva_pr_1023
C
D
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
*POCAFEB-11 Only (Remove in MP Model)
AT41
AT49
AU1
AU23
AU29
AU3
AU36
VSS_93
VSS_94
VSS_95
VSS_96
VSS
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
T27
AP28
AR15
AR19
AR28
AU49
AU51
AV25
AV39
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
T37
V31
V35
U24
U28
AV48
AW1
AW12
AW16
AW24
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_191
VSS_NCTF_21
BK8
BL11
AW29
AW32
VSS_107
VSS_108
VSS_109
VSS_192
VSS_193
VSS_194
BL13
BL19
AW5
AW7
VSS_110
VSS_111
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P29
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
W11
W39
W43
W47
W5
W7
Y11
Y13
Y2
Y41
Y45
Y49
Y5
Y50
VSS_195
VSS_196
BL22
BL37
AY24
AY10
VSS_112
VSS_113
VSS_197
VSS_198
C12
BL47
AY37
AY42
VSS_114
VSS_115
VSS_200
VSS_199
C19
C16
AY43
AY45
VSS_116
VSS_117
VSS_201
VSS_202
C28
C29
AY47
AY50
B10
VSS_118
VSS_119
VSS_203
VSS_204
T33
T31
C33
VSS_120
VSS_205
VSS_206
VSS_207
T29
R28
VSS_208
VSS_209
C50
C46
VSS_210
C41
VSS
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AM4
AM41
AM45
AN1
AN38
AN39
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
AA29
AA32
AB20
AB23
AB26
AB28
AB31
AB32
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD32
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF28
AF29
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS
VSSA_LVDS
VSSA_PEG_BG
B41
K49
AN43
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
C36
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
H50
J11
J16
J2
J24
J28
J33
J35
J39
K12
K47
K8
L1
L17
L20
VSS_SCB_5
VSS_SCB_6
C1
BL51
VSS_84
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_1
AB17
AB35
AA19
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS SCB VSS NCTF VSS
VSSA_DAC_BG
VSS_SCB_3
VSS_SCB_4
VSS_SCB_1
VSS_SCB_2
A3
B2
B32
BL1
A51
AT27
VSS_91
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_92
VSS_85
U32-5
LE88CLPM
5 OF 5
VSS
Samsung
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
Confidential
AF17
AF35
AK17
AD37
AM17
AM24
AP26
AD19
CFG#
CFG(5)
CFG(6)
CFG(7)
CFG(9)
CFG(16)
CFG(18)
CFG(19)
CFG(20)
Current Setting
(def. : default Option)
Low
DMIx2
Reserved DDR-II (def.)
DT/Transportable
PEG Reversal
Dynamic ODT
Disabled
VCC 1.05V (def.)
DMI Lane Normal
SDVO or PCIE X1
Only(def.)
High
DMIx4 (def.)
Mobile CPU (def.)
Normal
Dynamic ODT
Enabled (def.)
VCC 1.5V
DMI Lane Reversal
SDVO and PCIE X1
Simultaneously
D
C
B
A
DRAW
CHECK
APPROVAL
MODULE CODE
4
3
2
SUN XIAO
WUSHIJIANG
KEVIN LEE
DATE
DEV. STEP
REV
LAST EDIT
6/26/2007
TITLE
Gevena
PV2
1.0
GMCH
CRESTLINE (5/5)
October 23, 2007 10:38:02 AM
1
SAMSUNG
PART NO.
17 58
PAGE
ELECTRONICS
BA41-XXXXX
OF
A
B
C
4
3
2
D
COM-22C-015(1996.6.5) REV. 3
SAMSUNG PROPRIETARY
1
D:/tingting/geneva/Geneva_pr_1023
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
MEM1_ADQ(63:0)
15-D3
DDR1-1
DDR2-SODIMM-200P-RVS
MEM1_AMA(13:0)
MEM1_AMA(14)
MEM1_ABS2
MEM1_ABS0
MEM1_ABS1
MEM1_CS0#
MEM1_CS1#
CLK1_MCLK0
CLK1_MCLK0#
CLK1_MCLK1
CLK1_MCLK1#
MEM1_CKE0
MEM1_CKE1
MEM1_ACAS#
MEM1_ARAS#
MEM1_AWE#
MEM1_ODT0
MEM1_ODT1
MEM1_ADM(7:0)
SMB3_CLK
SMB3_DATA
R601
R602
15-C4
18-D2
14-A3 18-C2
15-D4 18-B2
15-D4 18-B2
18-B215-D4
15-B4
18-C2
18-C215-B4
15-D1
15-D1
15-D1
15-D1
18-C215-C1
18-B2
15-C1
15-B4 18-B2
18-B215-B4
18-B215-B4
15-B4
15-D4
MEM1_ADQS(7:0)
MEM1_ADQS#(7:0)
EMI2
EMI
CONTACT-PLATE-EMI
EMI3
EMI
CONTACT-PLATE-EMI
15-C4
15-C4
0
102
1
101
2
100
3
4
5
6
7
8
9
10
105
11
12
13
116
107
106
110
115
164
166
113
108
109
10K 1%
198
10K 1%
200
197
22-B119-B4
195
114
18-B2
119
18-B215-B4
0
1
2
3
4
130
5
147
6
170
7
185
0
1
2
3
4
131
5
148
6
169
7
188
0
1
2
3
4
129
5
146
6
167
7
186
EMI1
EMI
CONTACT-PLATE-EMI
1/2
A0
A1
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
A10_AP
90
A11
89
A12
A13
86
A14
84
A15
85
A16_BA2
BA0
BA1
S0*
S1*
30
CK0
32
CK0*
CK1
CK1*
79
CKE0
80
CKE1
CAS*
RAS*
WE*
SA0
SA1
SCL
SDA
ODT0
ODT1
10
DM0
26
DM1
52
DM2
67
DM3
DM4
DM5
DM6
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
DQS4
DQS5
DQS6
DQS7
11
DQS*0
29
DQS*1
49
DQS*2
68
DQS*3
DQS*4
DQS*5
DQS*6
DQS*7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
0
5
1
7
2
17
3
19
4
4
5
6
6
14
7
16
8
23
9
25
10
35
11
37
12
20
13
22
14
36
15
38
16
43
17
45
18
55
19
57
20
44
21
46
22
56
23
58
24
61
25
63
26
73
27
75
28
62
29
64
30
74
31
76
32
123
33
125
34
135
35
137
36
124
37
126
38
134
39
136
40
141
41
143
42
151
43
153
44
140
45
142
46
152
47
154
48
157
49
159
50
173
51
175
52
158
53
160
54
174
55
176
56
179
57
181
58
189
59
191
60
180
61
182
62
192
63
194
4
ME POWER RAIL UNDER ME ENABLE
Array resistors & Single resistors used to improve layout & routing.
P1.8V_AUX
DDR1-2
DDR2-SODIMM-200P-RVS
MCH3_EXTTS0#
MEM1_VREF
P3.3V
C63
100nF
14-B114-A2
C324
100nF
C62
2200nF
57-C419-C315-D1
C992
2200nF
2/2
112
VDD1
111
VDD2
117
VDD3
96
VDD4
95
VDD5
118
VDD6
81
VDD7
82
VDD8
87
VDD9
103
VDD10
88
VDD11
104
VDD12
199
VDDSPD
83
NC1
120
NC2
50
NC3
69
NC4
163
NCTEST
1
VREF
201
GND0
202
GND1
47
VSS1
133
VSS2
183
VSS3
77
VSS4
12
VSS5
48
VSS6
184
VSS7
78
VSS8
71
VSS9
72
VSS10
121
VSS11
122
VSS12
196
VSS13
193
VSS14
8
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
Samsung
ME POWER RAIL UNDER ME ENABLE
P1.8V_AUX
Confidential
NO_STUFF
Place near SO-DIMM0
P0.9V
EC510
330uF
2.5V
AL
C744
100nF
C687
C688
2200nF
2200nF
C681
2200nF
Place one cap close to every 2 pull-up resistors terminated to P0.9V
C743
C685
C746
C745
100nF
100nF
100nF
100nF
C737
C738
2200nF
2200nF
C742 C683
100nF
100nF
3
C682
100nF
C747
100nF
C684
100nF
C750
C748
100nF
100nF
C740
C739
100nF
100nF 100nF
100nF
NO_STUFF
C749
100nF
C741C686
DRAW
CHECK
APPROVAL
MODULE CODE
SUN XIAO
WUSHIJIANG
KEVIN LEE
2
DATE
DEV. STEP
REV
LAST EDIT
MEM1_AMA(13:0)
MEM1_AMA(14)
MEM1_CS0#
MEM1_CS1#
MEM1_CS2#
MEM1_CS3#
MEM1_CKE0
MEM1_CKE1
MEM1_CKE3
MEM1_CKE4
MEM1_ODT0
MEM1_ODT1
MEM1_ODT2
MEM1_ODT3
MEM1_ABS0
MEM1_ABS1
MEM1_ABS2
MEM1_ACAS#
MEM1_ARAS#
MEM1_AWE#
MEM1_BBS0
MEM1_BBS1
MEM1_BBS2
MEM1_BCAS#
MEM1_BRAS#
MEM1_BWE#
6/26/2007
PV2
1.0
15-B4 18-D4
14-A3 18-C4
B
TITLE
October 23, 2007 10:38:02 AM
14-B1 18-C4
14-B1 18-C4
14-B1 18-C2
14-B1 18-C2
18-C414-B1
14-B1 18-C4
14-B1
18-C2
18-C214-B1
18-B414-B1
18-B414-B1
18-B214-B1
14-B1 18-B2
18-C415-D4
18-C415-C4
15-C418-C4
18-C415-B4
18-B415-B4
18-B415-B4
15-D218-C2
15-C218-C2
18-C2
15-C2
15-B2 18-C2
15-B2
18-B2
15-B2
Gevena
SODIMM
DDR2 CH A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RA503-1
RA500-1
RA508-2
RA505-2
RA512-1
RA515-2
RA521-2
RA523-2
RA502-2
RA500-2
RA507-1
RA505-1
RA509-1
RA517-1
RA512-2
RA501-1
RA503-2
RA501-2
RA504-1
RA525-2
RA521-1
RA506-1
RA508-1
RA506-2
RA517-2
RA510-1
RA516-1
RA510-2
RA516-2
RA511-2
RA514-1
RA514-2
RA511-1
RA513-2
RA509-2
RA515-1
RA513-1
RA502-1
R690
12
12
34
34
12
3
34
34
34
34
12
12
12
12
34
12
34
34
12
34
12
12
118-B2
34
1
34
12
12
34
34
34
12
34
12
34
34
12
12
1
56
56
56
56
56
4
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
2
56
56
PAGE
P0.9V
56
56
56
56
56
56
56
56
56
56
56
56
56
2
56
1%56.2
P0.9V
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
OF
D
A
5818
B
C
D
4
3
A
2
1
COM-22C-015(1996.6.5) REV. 3
SAMSUNG PROPRIETARY
D:/tingting/geneva/Geneva_pr_1023
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
DDR SO-DIMM #1
D
Array resistors & Single resistors used to improve layout & routing.
MEM1_BDQ(63:0)
MEM1_BMA(13:0)
MEM1_BMA(14)
MEM1_BBS2
MEM1_BBS0
MEM1_BBS1
MEM1_CS2#
MEM1_CS3#
CLK1_MCLK3
CLK1_MCLK3#
CLK1_MCLK4
CLK1_MCLK4#
MEM1_CKE3
P3.3V
MEM1_CKE4
MEM1_BCAS#
MEM1_BRAS#
MEM1_BWE#
SMB3_CLK
SMB3_DATA
MEM1_ODT2
MEM1_ODT3
MEM1_BDM(7:0)
MEM1_BDQS(7:0)
MEM1_BDQS#(7:0)
R74
R73
15-A1
19-D2
15-B1
15-C1 19-B2
15-B4 19-C2
15-C1
15-D1
15-C1
15-D1
15-C1
15-B1 19-B2
15-A1
18-B4 22-B122-B118-B4
19-B215-B4
15-B4 19-B2
15-C1
15-B1
15-C1
DDR2-1
DDR2-SODIMM-200P-RVS
1/2
0
102
A0
1
101
A1
2
100
A2
3
99
A3
4
98
A4
5
97
A5
6
94
A6
7
92
A7
8
93
A8
9
91
A9
105
A10_AP
11
90
A11
12
89
A12
13
116
A13
86
A14
19-C214-A3
84
A15
85
A16_BA2
107
BA0
19-B215-C1
106
BA1
19-B215-C1
110
S0*
115
S1*
19-C215-B4
30
CK0
32
CK0*
164
CK1
166
CK1*
79
CKE0
19-C215-C1
80
CKE1
19-B2
113
CAS*
19-B215-B1
108
RAS*
109
WE*
19-B2
198
1%10K
SA0
200
1%10K
SA1
197
SCL
195
SDA
114
ODT0
119
ODT1
0
10
DM0
1
26
DM1
2
52
DM2
3
67
DM3
4
130
DM4
5
147
DM5
6
170
DM6
7
185
DM7
0
13
DQS0
1
31
DQS1
2
51
DQS2
3
70
DQS3
4
131
DQS4
5
148
DQS5
6
169
DQS6
7
188
DQS7
0
11
DQS*0
1
29
DQS*1
2
49
DQS*2
3
68
DQS*3
4
129
DQS*4
5
146
DQS*5
6
167
DQS*6
7
186
DQS*7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
0
5
1
7
2
17
3
19
4
4
5
6
6
14
7
16
8
23
9
25
1010
35
11
37
12
20
13
22
14
36
15
38
16
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
MCH3_EXTTS1#
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
MEM1_VREF
Samsung
P1.8V_AUX
Confidential
EMI4
EMI
CONTACT-PLATE-EMI
4
EC502
330uF
2.5V
AL
NO_STUFF
3
P3.3V
14-B114-A2
15-D1 57-C418-C3
EMI5
EMI
CONTACT-PLATE-EMI
P1.8V_AUX
112
111
117
96
95
118
81
82
87
103
88
104
199
83
C648
C649
2200nF
C164
2200nF
120
50
69
163
1
201
202
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
100nF
C163
100nF
Place near SO-DIMM1
C762
2200nF
C697
2200nF
C763
2200nF
DDR2-2
DDR2-SODIMM-200P-RVS
2/2
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDDSPD
NC1
NC2
NC3
NC4
NCTEST
VREF
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
C751
2200nF
C752
2200nF
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
C695
100nF
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
C761
100nF
C696
100nF
C760
100nF
MEM1_BMA(14)
MEM1_BMA(13:0)
2
C754
100nF
SUN XIAO
KEVIN LEE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
C690
100nF
R691
RA525-1
RA518-1
RA524-2
RA518-2
RA524-1
RA519-1
RA522-2
RA522-1
RA519-2
RA520-1
RA504-2
RA523-1
RA520-2
RA507-2
DATEDRAW
DEV. STEP
REV
LAST EDIT
C755
100nF
12
12
34
34
12
12
34
12
34
12
34
12
34
34
C757
100nF
6/26/2007
PV2
1.0
56
56
56
56
56
56
56
56
56
56
56
56
56
56
C691
100nF
TITLE
19-C414-A3
15-B2 18-D2
Place one cap close to every 2 pull-up resistors terminated to P0.9V
P0.9V
C693
C689
100nF
100nF
CHECK
APPROVAL
MODULE CODE
WUSHIJIANG
P0.9V
1%56.2
C692
C694
C753
100nF
100nF
100nF
NO_STUFF
Gevena
SODIMM
DDR2 CH B
October 23, 2007 10:38:02 AM
C756
100nF
1
C759
100nF
C758
100nF
SAMSUNG
PART NO.
PAGE
ELECTRONICS
BA41-XXXXX
5819
OF
C
B
A
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