Samsung N707 Circuit Description [EN]

2.SGH-N707 Circuit Description

1.SGH-N707 RF Circuit Description

1) RX PART

1.FEM(U402(SWITCHPLEXER+FILTER)) → Switching Tx, Rx path for GSM850, and PCS1900 by logic controlling.

2.FEM Control Logic (U402) → Truth Table

	VC1	VC2
DCS / PCS Tx Mode	L	H
GSM Tx Mode	H	L
GSM / PCS Rx Mode	L	L

3. FILTER

To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band.

-GSM FILTER (U402(SWITCHPLEXER+FILTER)) → For filtering the frequency band between 869 ~ 894 MHz

-PCS FILTER(U402(SWITCHPLEXER+FILTER)) → For filtering the frequency band 1930 and 1990 MHz.

4.VC-TCXO (OSC401)

To generate the 13MHz reference clock to drive the logic and RF.

After additional process, the reference clock applies to the U101 Rx IQ demodulator and Tx IQ modulator.

The oscillator for RX IQ demodulator and Tx modulator are controlled by serial data to select channel and use fast lock mode for GPRS high class operation.

5. SI 4205 (U404)

This chip integrates two differential-input LNAs.

The GSM input supports the GSM850, PCS input supports the DCS1900. The LNA inputs are matched to the 200 ohm differential output SAW filters through eternal LC matching network.

Image-reject mixer downconverts the RF signal to a 100 KHz intermediate frequency(IF) with the RFLO from frequency synthesizer. The RFLO frequency is between 1737.8 ~ 1989.9 MHz.

The Mixer output is amplified with an analog programmable gain amplifier(PGA), which is controlled by AGAIN.
The quadrature IF signal is digitized with high resolution A/D converts (ADC).
Also, this chip down-converts the ADC output to baseband with a digital 100 KHz quadrature LO signal. Digital
decimation and IIR filters perform channel selection to remove blocking and reference interface signals.
After channel	selection, the	digital output is scaled with a	digital	PGA,	which is controlled with the DGAIN. DACs	drive
a differential	analog signal	onto the RXIP, RXIN, RXQP,	RXQN	pins	to interface to standard analog-input baseband	IC.

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Circuit Description

2) TX PART

Baseband IQ signal fed into offset PLL, this function is included inside of U404 chip.

SI4205 chip generates modulator signal which power level is about 1.5dBm and fed into Power Amplifier(U403).

The PA output power and power ramping are well controlled by Auto Power Control circuit. We use offset PLL below

		200kHz		offset	GSM	-35dBc
		30	kHz	bandwidth	PCS	-35dBc
	Modulation Spectrum	400kHz offset			GSM	-66dBc
		30	kHz bandwidth		PCS	-65dBc
		600kHz ~ 1.8MHz offset			GSM	-75dBc
		30	kHz bandwidth		PCS	-68dBc

2. Baseband Circuit description of SGH-N707

1) CSP2200B1

1. Power Management

Seven low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimal system performance and long battery life. A programmable LDO provides support for 1.8V, 3.0V SIMs, while a self-resetting, electronically fused switch supplies power to external accessories. Ancillary support functions, such as two LED drivers and two call-alert drivers, aid in reducing both board area and system complexity. A four-wire serial interface unit(SIU) provides access to control and configuration registers. This interface gives a microprocessor full control of the CSP2200B1 and enables system designers to maximize both standby and talk times. Error reporting is provided via an interrupt signal and status register. Supervisory functions. including a reset generator, an input voltage monitor, and a thermal monitor, support reliable system design. These functions work together to ensure proper system behavior during start-up or in the event of a fault condition(low microprocessor voltage, insufficient battery energy, or excessive die temperature).

2. Battery Charge Management

A battery charge management block, incorporating an internal PMOS switch, and an 8-bit ADC, provides fast, efficient charging of single-cell Li-Ion battery. Used in conjunction with a current-limited voltage source, this block safely conditions near-dead cells and provides the option of having fast-charge and top-off controlled internally or by the system's microprocessor.

3. Backlight LED Driver

The backlight LED driver is a low-side, programmable current source designed to control the brightness of the keyboard illumination. LED1_DRV is controlled via LED1_[0:2] and can be programmed to sink from 15mA to 60mA in 7.5mA steps. LED2_DRV is controlled via LED2_[0:2] and can be programmed to sink from 5mA to 40mA in 5mA steps.

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