Samsung MZVLB256HAHQ-00000 User Manual

SAMSUNG CONFIDENTIAL

Rev. 1.1 Sep. 2017

MZVLB256HAHQ-00000/07 MZVLB512HAJQ-00000/07 MZVLB1T0HALR-00000/07 MZVLB2T0HMLB-00000/07

M.2 NVMe PCIe SSD

specification

(PM981)

datasheet

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datasheet

SAMSUNG CONFIDENTIAL

Rev. 1.1

SSD

Revision History

Revision No. History Draft Date Remark Created by Review by

1.0 1. Initial issue Aug 07, 2017 Final K.W Shin

1.1 1.Deleted 128GB and changed the part number of 256GB. Sep. 28, 2017 Final S.J Oh Elly. Shin

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MZVLB256HAHQ-00000/07 MZVLB512HAJQ-00000/07 MZVLB1T0HALR-00000/07 MZVLB2T0HMLB-00000/07

datasheet

SAMSUNG CONFIDENTIAL

Rev. 1.1

SSD

PM981 Series

PART NUMBER

MZVLB256HAHQ-00000/07 256GB 500,118,192

MZVLB512HAJQ-00000/07 512GB 1,000,215,216 MZVLB1T0HALR-00000/07 1TB 2,000,409,264 MZVLB2T0HMLB-00000/07 2TB 4,000,797,360

FEATURES Environmental Specifications

 PCIe Gen3 8Gb/s Interface, up to 4 Lanes  Compliant with PCI Express Base Specification Rev. 3.0  Compliant with PCI Express M.2 Specification Rev. 1.1  Compliant with NVMe Express specification Rev. 1.2a  Power Saving Modes:

- Supporting APST Linear Shock (0.5ms duration with 1/2 sine wave)

- Supporting L1.2 Mode Non-operating 1,500 Gpeak

 Support Admin & NVM Command Set  RoHS Compliant  Hardware based AES-XTS 256-bit Encryption Engine for SED

 TCG OPAL (v2.0) Compliant for SED

Drive Configuration

Capacity 256/512GB/1/2TB From Factor M.2 - Read 5.9W

Interface PCI Express Gen3 x4 - Write 5.7W Bytes per Sector 512Byte

Performance Specifications

Data Transfer Rate (128KB)

Capacity

Temperature

(Typ, RMS)

(Typ.)

Operating Non-operating

Humidity (non-condensing) Non-operating 5 ~ 95%

Vibration Non-operating (20 ~ 2,000 Hz, Sinusoidal) 20 Gpeak

POWER SPECIFICATIONS

Supply Voltage / Tolerance 3.3V ± 5% Voltage Ripple/Noise (max.) 100mV p-p

Active

Idle L1.2 (Typ) 5mW

PHYSICAL DIMENSION

LBA

0°C to 70°C

-40

C to 85°C

30mW

Sequential Read (1TB) Up to 3,200 MB/s Width 22.00 ± 0.15 mm

(512GB) Up to 3,000 MB/s Length 80.00 ± 0.15 mm

(256GB/2TB) Up to TBD MB/s Height

Sequential Write (1TB) Up to 2,400 MB/s - Single Side Max. 2.38 mm

(512GB) Up to 1,800 MB/s Weight Max. 9.0g

(256GB/2TB) Up to TBD MB/s Data I/O Speed (4KB) Random Read (1TB) Up to 380K IOPS

(512GB) Up to 270K IOPS

(256GB/2TB) Up to TBD IOPS

Random Write (1TB) Up to 440K IOPS

(512GB) Up to 420K IOPS

(256GB/2TB) Up to TBD IOPS

Reliability Specifications

UBER MTBF 1.5 Million Hours

< 1 sector per 10

bits read

Specifications are subject to change without notice.

1) 1MB = 1,000,000 Bytes, 1GB = 1,000,000,000 Bytes, Unformatted Capacity. User accessible capacity may vary depending on operating environment and formatting.

2) 1 Sector = 512Bytes, Max. LBA represents the total user addressable sectors in LBA mode and calculated by IDEMA rule

3) Actual performance may vary depending on use conditions and environment. Performance measurements based on TurboWri te technology.

4) Measured by SMART Temperature. Proper airflow recommended.

5) Active power is measured on sequential write and read.

6) Idle Power is measured on Idle status with L1.2+APST/ASPM on.

7) Active/Idle/L1.2 Power are measured up to 1TB.

IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS.

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SAMSUNG CONFIDENTIAL

MZVLB512HAJQ-00000/07 MZVLB1T0HALR-00000/07 MZVLB2T0HMLB-00000/07

datasheet

Table Of Contents

1.0 INTRODUCTION ........................................................................................................................................................5

1.1 General Description................................................................................................................................................5

1.2 Product List..............................................................................................................................................................5

1.3 Ordering Information................................................................................................................................................5

2.0 PRODUCT SPECIFICATION......................................................................................................................................6

2.1 Capacity...................................................................................................................................................................6

2.2 Performance

2.3 Power ......................................................................................................................................................................6

2.4 Reliability.................................................................................................................................................................7

2.4.1 MTBF ....................................... .........................................................................................................................7

2.4.2 UBER................................................................................................................................................................7

2.5 Environmental Specification....................................................................................................................................7

3.0 MECHANICAL SPECIFICATION.............. ... ............................................................................ ..................................8

3.1 Physical dimensions and Weight.............................................................................................................................8

3.2 Form Factor.............................................................................................................................................................8

4.0 INTERFACE SPECIFACION......................................................................................................................................9

4.1 Connector Dimension and Pin Location..................................................................................................................9

4.2 Pin Assignments and Definition...............................................................................................................................9

5.0 PCI and NVM Express registers.................................................................................................................................11

5.1 PCI Express Registers ............................................................................................................................................11

5.1.1 PCI Register Summary .....................................................................................................................................11

5.1.2 PCI Configuration Header Space Registers Detail ...........................................................................................11

5.1.2.1 PCI Configuration Header Space Registers ...............................................................................................11

5.1.3 PCI Capability Registers Detail.........................................................................................................................14

5.1.3.1 PCI Power Management Capability............................................................................................................14

5.1.3.2 Message Signaled Interrupt (MSI) Capability...................................................................... ... ....................15

5.1.3.3 PCI Express Capability.......................................... .....................................................................................17

5.1.3.4 MSI-X Capability...................................... ........................................ ...........................................................21

5.1.4 PCI Extended Capability Details .......................................................................................................................22

5.1.4.1 Advanced Error Reporting Registers..........................................................................................................22

5.1.4.2 Device Serial Number Capability................................................................................................................25

5.1.4.3 Power Budgeting Capability........................................................................................................................26

5.1.4.4 Secondary PCI Express Capability.............................................................................................................27

5.1.4.5 Latency Tolerance Reporting Capability Registers.......................................................................

5.1.4.6 L1 Substates Extended Capability..............................................................................................................29

5.2 NVM Express Registers ..........................................................................................................................................30

5.2.1 Register Summary .................................... .................................... ....................................................................30

5.2.2 Controller Registers ....................................... ... ... .................................... ... ......................................................30

6.0 Supported Command Set ...........................................................................................................................................34

6.1 Admin Command Set ..............................................................................................................................................34

6.1.1 Identify Command............................... ..................................... .. .......................................................................35

6.2 NVM Express I/O Command Set.............................................................................................................................41

6.3 SMART/Health Information......................................................................................................................................42

7.0 PRODUCT COMPLIANCE .........................................................................................................................................43

7.1 Product regulatory compliance and Certifications ...................................................................................................43

8.0 References..................................................................................................................................................................44

..........................................................................................................................................................6

..............28

Rev. 1.1

SSD

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M Z X X X X X X X X X X - X X X X X

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

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datasheet

SAMSUNG CONFIDENTIAL

Rev. 1.1

SSD

1.0 INTRODUCTION

1.1 General Description

This document describes the specification of PM981 SSD which uses PCIe interface. The PM981 is fully consist of semiconductor device and using NAND Flash Memory which has a high reliability and a high technology in a small form factor for using a SSD and supporting Peripheral Component Interconnect Express (PCIe) 3.0 interface standard up to 4 lanes shows much faster performance than previous SATA SSDs. The PM981 provides 256GB, 512GB, 1TB and 2TB capacities. It’s sequential performance is up to 3,200MB/s for read operation and 2,400MB/s for write operation by 4 lanes. It’s random performance is up to 380k IOPS for read and 440k IOPS for write operation by 4 lanes. It could also provide rugged features with an extreme environment with a high MTBF.

1.2 Product List

[Table 1] Product Line-up

Type Capacity Part Number

256GB MZVLB256HAHQ-00000/07

M.2

512GB MZVLB512HAJQ-00000/07

1TB MZVLB1T0HALR-00000/07 2TB MZVLB2T0HMLB-00000/07

1.3 Ordering Information

1. Memory (M)

2. Module Classification

Z: SSD

3. Form Factor

V: PCIeM.2 (22*80, PCIe x4)

4. Line-Up

L: Client/SV (VNAND 3bit MLC)

5. SSD CTRL

B: Phoenix

6~8. SSD Density

256: 256GB 512: 512GB 1T0: 1TB 2T0: 2TB

9. NAND PKG + NAND Voltage

H: BGA (LF,HF)

10. Flash Generation

M: 1st Generation

A: 2nd Generation

11~12. NAND Density

HQ: 1T QDP 4CE JQ: 2T ODP 4CE LR: 4T HDP 4CE LB: 8T HDP 4CE

13. "-"

14. Default

"0"

15. HW revision

0: No revision

16. Packaging type

0: Bulk

17~18. Customer

00: World wide (non-SED) 07: World wide (SED)

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2.0 PRODUCT SPECIFICATION

2.1 Capacity

[Table 2] User Addressable Sectors

Capacity Max LBA

256GB

512GB

1TB 2,000,409,264 2TB 4,000,797,360

NOTE:

1) Gigabyte (GB) = 1,000,000,000 Bytes, 1 Sector = 512Bytes

2) Max. LBA shown in Table 1 represents the total user addressable sectors in LBA mode and calculated by IDEMA rule.

SAMSUNG CONFIDENTIAL

Rev. 1.1

SSD

500,118,192

1,000,215,216

2.2 Performance

[Table 3] Drive Performance  Gen3

Parameter Unit Queue Depth 256GB 512GB 1TB 2TB

Sequential Read

(Up to)

Sequential Write

(Up to)

Random Read

(Up to)

Random Write

(Up to)

NOTE:

1) Performance measured using CDM 5.0.2 on Windows 10 64bit. Actual performance may vary depending on use conditions and en vironment.

2) Sequential performance measured using 128KB data size. (QD=32 by Thread=1)

3) Random performance measured using 4KB data size. (QD=32 by Thread 4, QD=1 by Thread 1)

4) Performance measurements based on TurboWrite technology

MB/s QD = 32 TBD 3,000 3,200 TBD

MB/s QD = 32 TBD 1,800 2,400 TBD

IOPS QD = 1 TBD 12K 12K TBD IOPS QD = 32 TBD 270K 380K TBD IOPS QD = 1 TBD 50K 50K TBD IOPS QD = 32 TBD 420K 440K TBD

2.3 Power

[Table 4] Maximum Ratings

Parameter Specifications

Supply Voltage

Allowable voltage 3.3V ± 5%

Allowable noise/ripple 100mV p-p or less

[Table 5] Power Consumption for M.2 (3.3V Supply)

Parameter Specifications

Active1 (Typical, RMS)

Power Consumption

NOTE:

1) Active power is measured on sequential write and read.

2) Idle Power is measured on Idle status with L1.2+APST/ASPM on.

3) If L1.2 time logging option is enabled, L1.2 Power could be 5mW.

4) Active/Idle/L1.2 Power are measured up to 1TB.

Idle

L1.2

(Typical)

Read 5.9W Write 5.7W

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30mW

5mW

MZVLB256HAHQ-00000/07

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2.4 Reliability

This chapter provides the information for the reliability features of the SSD.

2.4.1 MTBF

MTBF is Mean Time Between Failure, and is the predicted elapsed time between inherent failures of a system during operation. As same word, AFR (annual failure ratio) is 0.4%. MTBF can be calculated as the arithmetic average time between failures of a system.

[Table 6] MTBF Specifications

Capacity MTBF

256GB 512GB

1TB 2TB

2.4.2 UBER

UBER is Uncorrectable Bit Error Rate.

[Table 7] UBER Specifications

Parameter Specification

UBER

1,500,000 Hours

< 1 sector per 10

bits read

Rev. 1.1

SSD

2.5 Environmental Specification

[Table 8] Temperature, Humidity, Shock, Vibration

Parameter Mode Specification

Temperature

Shock

Humidity

Vibration

NOTE:

1) Temperature is measured by SMART Temperature. Proper airflow recommended

2) Humidity is measured in non-condensing

3) Test condition for shock: 0.5ms duration with half sine wave

4) Test condition for vibration: 10Hz to 2000Hz

Operating

Non-operating -40C to 85C Non-operating 5% to 95% Non-operating 1500G

Non-operating 20G

0C to 70C

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3.0 MECHANICAL SPECIFICATION

3.1 Physical dimensions and Weight

[Table 9] Physical dimensions and Weight

Parameter Value

Width 22.00 ± 0.15 mm

Length 80.00 ± 0.15 mm

Thickness Max. 2.38 mm

Weight 256/512GB/1/2TB Max 9.0g

3.2 Form Factor

SAMSUNG CONFIDENTIAL

Rev. 1.1

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[Figure 1] M.2 Package

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4.0 INTERFACE SPECIFACION

4.1 Connector Dimension and Pin Location

[TOP VIEW] [BOTTOM VIEW]

[Figure 2] M.2 Signal and Power pins

4.2 Pin Assignments and Definition

[Table 10] Signal Assignments

Pin# Assignment Description Pin# Assignment Description

1 GND Return current path 2 3.3V 3.3V source 3 GND Return current path 4 3.3V 3.3V source 5 PETn3 PCIe TX 6 N/C N/C 7 PETp3 PCIe TX 8 N/C N/C

9 GND Return current path 10

11 PERn3 PCIe Rx 12 3.3V 3.3V source 13 PERp3 PCIe Rx 14 3.3V 3.3V source 15 GND Return current path 16 3.3V 3.3V source 17 PETn2 PCIe TX 18 3.3V 3.3V source 19 PETp2 PCIe TX 20 N/C N/C 21 GND Return current path 22 N/C N/C 23 PERn2 PCIe Rx 24 N/C N/C 25 PERp2 PCIe Rx 26 N/C N/C 27 GND Return current path 28 N/C N/C 29 PETn1 PCIe TX 30 N/C N/C 31 PETp1 PCIe TX 32 N/C N/C 33 GND Return current path 34 N/C N/C 35 PERn1 PCIe Rx 36 N/C N/C 37 PERp1 PCIe Rx 38 N/C N/C 39 GND Return current path 40 41 PETn0 PCIe TX 42 43 PETp0 PCIe TX 44 45 GND Return current path 46 N/C N/C 47 PERn0 PCIe Rx 48 N/C N/C 49 PERp0 PCIe Rx 50 PERST# PCIe Reset 51 GND Return current path 52 CLKREQ# PCIe Device Clock Request 53 REFCLKN PCIe Reference Clock 54 PEWake# N/C

55 REFCLKP PCIe Reference Clock 56

57 GND Return current path 58 67 N/C N/C 68 SUSCLK DNU (Do Not Use)

69 PEDET N/C 70 3.3V 3.3V source 71 GND Return current path 72 3.3V 3.3V source

LED1#

ALTER#(O)

SMB_DATA (I/O)

SMB_CLK (I/O)

Reserved for

MFG_Data

Reserved for

MFG_CLOCK

Device Active Signal (Refer to [Table 11])

DNU (Do Not Use) DNU (Do Not Use) DNU (Do Not Use)

N/C

Rev. 1.1

SSD

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73 GND Return current path 74 3.3V 3.3V source 75 GND Return current path

NOTE:

1) Not support: open drain with pull-up on platform (1.8V), active low.

2) Not support: open drain with pull-up on platform (1.8V).

[Table 11] Simple Indicator Protocol for SSD LED States (Optional)

Active State (Host send CMD to SSD) Blinking

Idle Low Power standby OFF

State Deep Sleep Power savings OFF

NOTE:

1) ASPM (Active State Power Management)

datasheet

ASPM

Rev. 1.1

SSD

LED Status

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5.0 PCI and NVM Express registers

5.1 PCI Express Registers

5.1.1 PCI Register Summary

[Table 12] PCI Register Summary

Start Address End Address Name Type

00h 3Fh PCI Header PCI Configuration Header Space 40h 47h PCI Power Management Capability PCI Capability 50h 67h MSI Capability PCI Capability 70h A3h PCI Express Capability PCI Capability

B0h BBh MSI-X Capability PCI Capability 100h 12Bh Advanced Error Reporting Capability PCI Extended Capability 148h 153h Device Serial Number Capability PCI Extended Capability 158h 167h Power Budgeting Capability PCI Extended Capability 168h 17Bh Secondary PCI Express Capability PCI Extended Capability 188h 18Fh Latency Tolerance Reporting Capability PCI Extended Capability 190h 19Fh L1 Substates Capability PCI Extended Capability

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5.1.2 PCI Configuration Header Space Registers Detail

5.1.2.1 PCI Configuration Header Space Registers

[Table 13] PCI Header Space Summary

Start Address End Address Symbol Description

00h 03h 04h 05h 06h 07h 08h 08h

09h 0Bh 0Ch 0Ch 0Dh 0Dh 0Eh 0Eh

0Fh 0Fh

10h 13h

14h 17h

18h 1Bh 1Ch 1Fh

20h 23h

24h 27h

28h 2Bh 2Ch 2Fh

30h 33h

34h 34h

35h 3Bh 3Ch 3Dh 3Eh 3Eh

3Fh 3Fh

IDTF Identifiers CMD Command Register

STS Status Register

REVID Revision ID

CC Class Codes CLS Cache Line Size MLT Master Latency Timer

HTYPE Header Type

BIST Built in Self Test MLBAR (BAR0) Memory Register Base Address (lower 32-bit) MUBAR (BAR1) Memory Register Base Address (upper 32-bit)

IDBAR (BAR2) Reserved

BAR3 Reserved BAR4 Reserved BAR5 Reserved

CCPTR CardBus CIS Pointer

SS Subsystem Identifiers

EXPROM Expansion ROM Base Address

CAP Capabilities Pointer

R Reserved

INTR Interrupt Information

MGNT Minimum Grant

MLAT Maximum Latency

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[Table 14] Identifier Register

Bits Type Default Value Description

31:16 RO A808h Device ID

0:15 RO 144Dh Vendor ID

[Table 15] Command Register

Bits Type Default Value Description

15:11 RO 0h Reserved

10 RW 0 Interrupt Disable

9 RO 0 Fast Back-to-Back Enable (N/A) 8 RW 0 SERR# Enable 7 RO 0 IDSEL Stepping/Wait Cycle Control (N/A) 6 RW 0 Parity Error Response Enable 5 RO 0 VGA Palette Snooping Enable (N/A) 4 RO 0 Memory Write and Invalidate Enable (N/A) 3 RO 0 Special Cycle Enable (N/A) 2 RW 0 Bus Master Enable 1 RW 0 Memory Space Enable 0 RW 0 I/O Space Enable

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[Table 16] Status Register

Bits Type Default Value Description

15 RW1C 0 Detected Parity Error 14 RW1C 0 Signaled System Error 13 RW1C 0 Received Master Abort 12 RW1C 0 Received Target Abort 11 RW1C 0 Signaled Target Abort (N/A)

10:9 RO 0h DEVSEL Timing (N/A)

8 RW1C 0 Master Data Parity Error Detected 7 RO 0 Fast Back-to-Back Transaction Capable (N/A) 6RO 0 Reserved 5 RO 0 66MHz Capable (N/A) 4 RO 1 Capabilities List 3 RO 0 Interrupt Status

2:1 RO 0h Reserved

0RO 0 Reserved

[Table 17] Revision ID Register

Bits Type Default Value Description

7:0 RO 00h Controller Hardware Revision ID

[Table 18] Class Code Register

Bits Type Default Value Description

23:16 RO 1h Base Class Code

15:8 RO 8h Sub Class Code

7:0 RO 2h Programming Interface

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[Table 19] Cache Line Size Register

Bits Type Default Value Description

7:0 RW 0h Cache Line Size (N/A)

[Table 20] Master Latency Timer Register

Bits Type Default Value Description

7:0 RO 0h Master Latency Timer (N/A)

[Table 21] Header Type Register

Bits Type Default Value Description

7 RO 0 Multi-Function Device (N/A)

6:0 RO 0h Reserved

[Table 22] Built In Self Test Register

Bits Type Default Value Description

7:0 RO 0h Built In Self Test (N/A)

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[Table 23] Memory Register Base Address Lower 32-bits (BAR0) Register

Bits Type Default Value Description

31:14 RW 0h

13:4 RO 0h Reserved

3 RO 0 Pre-Fetchable

2:1 RO 2h Address Type (64-bit)

0 RO 0 Memory Space Indicator (MEMSI)

[Table 24] Memory Register Base Address Upper 32-bits (BAR1)

Bits Type Default Value Description

31:0 RO 0h Base Address

[Table 25] Index/Data Pair Register Base Address (BAR2) Register

Bits Type Default Value Description

31:0 RO 0h N/A

[Table 26] BAR3 Register

Bits Type Default Value Description

31:0 RO 0h N/A

Base Address

[Table 27] Vendor Specific BAR4 Register

Bits Type Default Value Description

31:0 RO 0h N/A

[Table 28] Vendor Specific BAR5 Register

Bits Type Default Value Description

31:0 RO 0h N/A

[Table 29] Cardbus CIS Pointer Register

Bits Type Default Value Description

31:0 RO 0h N/A

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[Table 30] Subsystem Identifier Register

Bits Type Default Value Description

31:16 RO A801h Subsystem ID

15:0 RO 144Dh Subsystem Vendor ID

[Table 31] Expansion ROM Register

Bits Type Default Value Description

31:17 RW 0h Expansion ROM Base Address

16:1 RO 0h Reserved

0 RW 0 Expansion ROM Enable/Disable

[Table 32] Capabilities Pointer Register

Bits Type Default Value Description

7:0 RO 40h Capability Pointer

[Table 33] Interrupt Information Register

Bits Type Default Value Description

15:8 RO 01h Interrupt Pin

7:0 RW FFh Interrupt Line

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[Table 34] Minimum Grant Register

Bits Type Default Value Description

7:0 RO 0h Minimum Grant

[Table 35] Maximum Latency Register

Bits Type Default Value Description

7:0 RO 0h Maximum Latency

5.1.3 PCI Capability Registers Detail

5.1.3.1 PCI Power Management Capability

[Table 36] PCI Power Management Capability Summary

Start Address End Address Symbol Description

40h 40h PCIPM_ID PCI Power Management Capability ID 41h 41h NEXTCAP Next Capability Pointer 42h 43h PCIPM_CAP PCI Power Management Capabilities 44h 45h PCIPM_CS PCI Power Management Control and Status 46h 46h PCIPM_CSR_BSE PMCSR_BSE Bridge Extensions 47h 47h PCIEPM_DATA Data

[Table 37] PCI Power Management Capability ID Register

Bits Type Default Value Description

15:8 RO 50h Next Capability

7:0 RO 1h Capability ID

IF THERE IS ANY OTHER OPERATION TO IMPLEMENT IN ADDITION TO SPECIFICATION IN THE DATASHEET OR JEDEC STANDARD, PLEASE CONTACT EACH BRANCH OFFICE OR HEADQUARTERS OF SAMSUNG ELECTRONICS.

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