Samsung KP70DM1 Operating Instructions

Chapter 3

IC Description &

3-1 MC68EC000...............................................3-2

3-2 STC 9604 ...................................................3-8

3-3 STL 7053 (TMC).......................................3-15

3-4 STI 9511 (QDMC).....................................3-17

3-5 TP 3404 (QDASL).....................................3-21

3-6 SBS 9401 .................................................3-24

3-7 CODEC (TP3057).....................................3-26

3-8 STL 7065..................................................3-28

3-9 TIMING CHART........................................3-29

Chapter 3. IC Description & Timing

3-1 MC68EC000

3-1-1 General

The MC68EC000 of Motolora is used as processor for DCS COMPACT II(PLUS)main system. MC68E000 is an economic version of MC68EC000. The MC68EC000 has supported by a statically selectabe 8-bit or 16-bit data bus. This architecture provides a fast and efficient processing device that can satisfy the requirements of sophisticated applications based on high-level language.

3-1-2 Pin Map

R/W

DTACK

BR Vcc Vcc

CLK GND GND

MODE

HALT

RESET

NC AVEC BERR

IPL2 IPL1

9 68 61

MC68EC000

D13 D14 D15 GND A23 A22 A21 Vcc A20 A19 A18 A17 A16 A15 A14 A13 A12

4327

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Chapter 3. IC Description & Timing

3-1-3 Circuit Description

Address Bus (A0~A23)

This 24bit, unidirectional, three-state bus is capable of addressing 16Mbytes of data. It provides the address for bus operation during all cycles except interrupt cycles. During interrupt cycles A3, A2, and A1 reflect the level of the interrupt being serviced while A23~A4 and A0 are set to a logic high.

Data Bus (D0~D15)

This 16bit bidirectional, three-state bus is the general-purpose data path. If the controller is operating in the 16bit mode, the data bus transfers and accepts data in either word or byte length. If the controller is operating in the 8 bit mode, the controller drives the entire bus during writes, but only the lower eight bits (D7~D0) contain valid data. In the 8 bit mode, the controller ignores the data on D15~D8 during read cycles. During and interrupt acknowledge cycle the external device supplies the vector number on D7~D0.

Aynchronous Bus control

Aynchronous data transfers are handled using the following control signals : address strobe, read/write, upper and lower data strobes, and data transfer acknowledge.

Address Strobe(AS)

This signal indicates a valid address on the address bus.

Read/Write (R/W)

This signal defines the data bus transfer as a read or write cycle. R/W also works in conjunction with the data strobes as explained in the following paragraph.

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Chapter 3. IC Description & Timing

Upper and Lower Data Strobe (UDS, LDS)

These signals control the flow of data on the data bus as listed in Table. When R/W is high, the controller reads from the data bus as indicated. When R/W is Low, the controller writes to the data bus as shown. During operation in the 8 bit mode, the UDS is always forced high and LDS indicates valid data.

Data Strobe Control of Data Bus for 16 Bit Mode

UDS

1 0 1 0 0 1 0

These condition are result of current implementation and may not appear on future device.

LDS

1 0 0 1 0 0 1

R/W

– 1 1 1 0 0 0

D15 ~ D8

No Valid Data

Valid Data Bits 15 ~ 8

No Valid Data Valid Data Bits 15 ~ 8 Valid Data Bits 15 ~ 8

Valid Data Bits 7 ~ 0

Valid Data Bits 15 ~ 8

D7 ~ D0

No Valid Data Valid Data Bits 7 ~ 0 Valid Data Bits 7 ~ 0

Valid Data Bits 15 ~ 8

Data Transfer Acknowledge(DTACK)

This input indicates that the data transfer is complete. When the controller recognizes DTACK during a read cycle, data is latched and the bus cycle is terminated. When DTACK is recognized during a write cycle the bus cycle is terminated.

Bus Arbitration Control

Bus request and bus grant form a bus arbitration circuit to determine which device will be the bus master.

Bus Request(BR)

This input indicates that an external device requires bus mastership.

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Chapter 3. IC Description & Timing

Bus Grant(BG)

This output indicates to all other potential bus master devices that the controller will release bus control at the end of the current bus cycle.

Interrupt Control

The interrupt priority level signals and autovector signal are used in servicing external interrupts.

Interrupt Priority Level (IPL2, IPL1, IPL0)

These inputs indicate the encoded priority level of the device requesting an interrupt. Level 7 is the highest priority; whereas, level 0 indicates that no interrupts are requested. Level 7 cannot be masked. The least significant bit is given in IPLO, and the most significant bit is contained in IPL2. These lines must remain stable untile the controller signals interrupt acknowledge (FC2~FC0 are all High) to ensure that the interrupt is recognized.

Autovector(AVEC)

This input indicates that the controller should use automatic vectoring for an interrupt during an interrupt acknowledge cycle.

NOTE : AVEC should be asserted only during an interrupt acknowledge cycle, or erratic

controller operation could occur.

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Chapter 3. IC Description & Timing

System Control

The four system control inputs are used to reset or halt the controller, to indicate that the controller state bus errors have occurred, and to switch from 8 bit to 16 bit operating mode.

Reset (RESET)

The bidirectional signal resets (starts a system initialization sequence)the MC68EC000 in response to an external RESET signal. An internally generated reset (result of a RESET instruction) causes all external devices to be reset, and the internal state of the controller is not affected A total system reset (controller and external devices) is the result of external HALT and RESET signals applied simultaneously.

Halt(HALT)

When this bidirectional line is driven by an external device, it causes the controller to stop at the completion of the current bus cycle. When the controller has been halted using this input, all control signals are inactive, and all three-state lines are put in their high-inpedance state. When the controller stop executing instructions, such as in a double bus fault condition, the HALT line is driven by the controller to indicate to external devices that the controller has stopped.

Bus Error (BERR)

This input informs the controller that there is a problem with the bus cycle currently being executed. Problems may be a result of:

°‹Nonresponding devices, °‹Interrupt vector number acquisition failure, °‹Illegal access request as determined by a memory management unit, or °‹Other application-dependent errors.

The bus error signal interacts with the halt signal to determine if the current bus cycle should be reexecuted or if exception processing should be performed.

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Chapter 3. IC Description & Timing

Mode (MODE)

The MODE input selects between the 8 bit and 16 bit operating modes. If this input is grounded at reset, the controller will come out of reset in the 8 bit mode. If this input is tied high or floating at reset, the controller will come out of reset in the 16 bit mode. This input should be changed only at reset and must be stable two clocks after RESET in negated. Changing this input during normal operation may produce unpredictable results.

Processor Status (FC2, FC1, FC0)

These function code outputs indicate the state (user or supervisor) and the cycle type currently being executed. The information indicated by the function code outputs is valid whenever address strobe (AS) is active.

Function Code Outputs

Function Code Output

FC2

0 0 0 0 1 1 1 1

FC1

0 0 1 1 0 0 1 1

FC0

0 1 0 1 0 1 0 1

(Undefined, Reserved) User Data User Program (Undefined, Reserved) (Undefined, Reserved) Supervisor Data Supervisor Program Interrupt Acknowledge

Cycle Time

Clock (CLK)

The clock input is a TTL-compatible signal that is internally buffered for development of the internal clock needed by the controller, The clock input should not be gated off at any time. and the clock signal must conform of minimum and maximum pulse-width times. The clock is a constant-frequency square wave with no stretching or shaping techniques required.

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Chapter 3. IC Description & Timing

3-2 STC-9604

3-2-1 GENERAL

STL-9604 is ASIC which performs various functions. It controls main system. Included are DPLL, Clock Generation, Time Switch, Digital Conference, Multi-Tone/DTMF Detector, QDASL Control, TMC control.

3-2-2 Block Diagram

IC8K IACT

C10M C4M FOIB T1DET

IHWR[7:0]

IDSPIN

IHOS[7:0]

IRING[7:0]

IMETGND[7:0]

DPLL

Clocks

Generation

OFOIB OC4M

ADDRESS

Address

Decode

CPU Interface

DATA IPL

TSW &

CONFERENC

DTMF/TONE

Generation

DTMF/TONE

Detection

8TMC

DTACK

INT

Control

OHWX[7:0]

OPSX[7:0] ODP[7:0] OMUTE[7:0] ORING[7:0]

IRXD

ICI

IDINT[1:0]

3-8

8DMC

OTXD OCD OCS[1:0] OCCLK

CPU

Chapter 3. IC Description & Timing

FOIB from T1

ADR

C16M C4M FOIB T1DET

IHWR[7:0]

IDSPIN

IHOS[7:0] IRING[7:0] IMETGND[7:0] OFSX[7:0] ODP[7:0] OMUTE[7:0]

DATA DS AS IPL

DPLL

IC8K IACT

Clock Gen.

TSW/CONF

DETECTION

DTMF/TONE

Generation

TMC DMC

DTACK

OPOIB

OC4M

OHWX[7:0]

IRXD

ICI

IDINT[1:0]

OTXD

OCO

OCS[1:0]

OCCLK

8 Trunks

C.D.

Generation Purpose

IRXD

PING

Detect

Bypass

SIO

OTXD

OINTSIO

QDASL

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Chapter 3. IC Description & Timing

CPU

NEW ENG

ODSPEN1B

CPU

CPU Borad

NEW ENG

STL

7065

STL

7065

ODSPEN1B

IDSPCEB

AA B0rad

STL

7065

STL

7065

IDSPCEB

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