Datasheet KMM5364003BSW Datasheet (SAMSUNG)

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DRAM MODULE KMM5364003BSW/BSWG

KMM5364003BSW/BSWG Fast Page Mode

4M x 36 DRAM SIMM Using 4Mx16 & Quad CAS 4Mx4, 4K Refresh, 5V

GENERAL DESCRIPTION FEATURES

The Samsung KMM5364003B is a 4Mx36bits Dynamic RAM
high density memory module. The Samsung KMM5364003B
consists of two CMOS 4Mx16bits and one CMOS Quad CAS
4Mx4bits DRAMs in TSOP packages mounted on a 72-pin
glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor
is mounted on the printed circuit board for each DRAM. The
KMM5364003B is a Single In-line Memory Module with edge
connections and is intended for mounting into 72 pin edge
connector sockets.

PERFORMANCE RANGE

Speed

-5 50ns 13ns 90ns 35ns

tRAC tCAC tRC tPC

• Part Identification

- KMM5364003BSW(4K cycles/64ms Ref, TSOP, Solder)

- KMM5364003BSWG(4K cycles/64ms Ref, TSOP, Gold)

• Fast Page Mode Operation

• CAS-before-RAS & Hidden Refresh capability

• RAS-only refresh capability

• TTL compatible inputs and outputs

• Single +5V±10% power supply

• JEDEC standard PDpin & pinout

• PCB : Height(1000mil), single sided component

-6 60ns 15ns 110ns 40ns

PIN CONFIGURATIONS

Pin

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

Symbol

1
2
3
4
5
6
7
8
9

VSS

DQ0

DQ18

DQ1

DQ19

DQ2

DQ20

DQ3

DQ21

Vcc

NC

A0
A1
A2
A3
A4
A5
A6

A10

DQ4

DQ22

DQ5

DQ23

DQ6

DQ24

DQ7

DQ25

A7
A11
Vcc

A8

A9

NC
RAS2
DQ26

DQ8

Pin

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

Symbol

DQ17
DQ35

Vss
CAS0
CAS2
CAS3
CAS1
RAS0

NC
NC

W

NC

DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31

Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16

NC
PD1
PD2
PD3
PD4

NC

Vss

PIN NAMES

Pin Name Function

A0 - A11 Address Inputs
DQ0 - 35 Data In/Out

W Read/Write Enable
RAS0, RAS2 Row Address Strobe
CAS0 - CAS3 Column Address Strobe
PD1 -PD4 Presence Detect
Vcc Power(+5V)
Vss Ground
NC No Connection

PRESENCE DETECT PINS (Optional)

Pin 50NS 60NS

PD1
PD2
PD3
PD4

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

Vss

NC
Vss
Vss

Vss

NC
NC
NC

DRAM MODULE KMM5364003BSW/BSWG

FUNCTIONAL BLOCK DIAGRAM

RAS0/RAS2

CAS0

CAS1

47Ω

47Ω

RAS

LCAS

UCAS

OE

W A0-A11

RAS
CAS0
CAS1
CAS2
CAS3

W A0-A11

U0

U1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ0

DQ1

DQ2

DQ3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16

DQ8
DQ17
DQ26
DQ35

CAS2

CAS3

W

A0-A11

47Ω

47Ω

Vcc

Vss

DQ0

RAS

LCAS

UCAS

OE

U2

W A0-A11

0.1 or 0.22uF Capacitor
for each DRAM

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25

DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34

To all DRAMs

DRAM MODULE KMM5364003BSW/BSWG

ABSOLUTE MAXIMUM RATINGS *

Item Symbol Rating Unit

Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current

* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)

Item Symbol Min Typ Max Unit

Supply Voltage
Ground
Input High Voltage
Input Low Voltage

*1 : VCC+2.0V at pulse width≤20ns, which is measured at VCC.
*2 : -2.0V at pulse width≤20ns, which is measured at VSS.

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)

Symbol Speed

ICC1
ICC2 Don′t care - 6 mA
ICC3
ICC4 -5

ICC5 Don′t care - 3 mA
ICC6

II(L)

IO(L)
VOH

VOL

-5

-6

-5

-6

-6

-5

-6

Don′t care

Don′t care

VIN, VOUT

VCC

Tstg

Pd

IOS

VCC
VSS

VIH
VIL

KMM5364003BSW/BSWG

Min Max

-

-

-

-

-

-

-

-

-10

-5

2.4

-

4.5

2.4

-1.0

0

*2

-1 to +7.0

-1 to +7.0

-55 to +125
3

50

5.0
0

-

-

330
300

330
300

220
190

330
300

10

5

-

0.4

5.5

VCC

0.8

V
V

°C

W

mA

0

*1

V
V
V
V

Unit

mA
mA

mA
mA

mA
mA

mA
mA

uA
uA

V
V

ICC1

: Operating Current * (RAS, CAS, Address cycling @tRC=min)

ICC2

: Standby Current (RAS=CAS=W=VIH)

ICC3

: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)

ICC4

: Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min)

ICC5

: Standby Current (RAS=CAS=W=Vcc-0.2V)

ICC6

: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)

I(IL)

: Input Leakage Current (Any input 0≤VIN≤Vcc+0.5V, all other pins not under test=0 V)

I(OL)

: Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc)

VOH

: Output High Voltage Level (IOH = -5mA)

VOL

: Output Low Voltage Level (IOL = 4.2mA)

* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.

ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one Fast page mode cycle time, tPC.

DRAM MODULE KMM5364003BSW/BSWG

CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)

Item Symbol Min Max Unit

Input capacitance[A0-A11]
Input capacitance[W]
Input capacitance[RAS0/RAS2]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0 - 35]

CIN1
CIN2
CIN3
CIN4
CDQ

-

-

-

-

-

AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)

Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF

25
31
31
24
17

pF
pF
pF
pF
pF

Parameter Symbol

Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
Refresh period
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge

tRC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS
tDH
tREF
tWCS
tCSR
tCHR
tRPC
tCPA

-5 -6

Min Max Min Max

90 110 ns

50 60 ns 3,4,10
13 15 ns 3,4,5

25 30 ns 3,10
0 0 ns 3
0 13 0 15 ns 6
1 50 1 50 ns 2

30 40 ns
50 10K 60 10K ns
13 15 ns
50 60 ns
13 10K 15 10K ns
20 37 20 45 ns 4
15 25 15 30 ns 10

5 5 ns
0 0 ns

10 10 ns

0 0 ns

10 10 ns
25 30 ns

0 0 ns
0 0 ns 8
0 0 ns 8

10 10 ns
10 10 ns
15 15 ns
13 15 ns

0 0 ns 9

10 10 ns 9

64 64 ms
0 0 ns 7
5 5 ns

10 10 ns

5 5 ns

30 35 ns 3

Unit Note

DRAM MODULE KMM5364003BSW/BSWG

AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)

Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF

Parameter Symbol

Fast page mode cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)

tPC
tCP
tRASP
tWRP
tWRH

NOTES

An initial pause of 200us is required after power-up followed

1.
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.

2.

Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref­erence levels for measuring timing of input signals. Transi­tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL loads and 100pF.

3.

Operation within the tRCD(max) limit insures that tRAC(max)

4.
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.

5.

Assumes that tRCD≥tRCD(max).

-5 -6

Min Max Min Max

35 40 ns
10 10 ns
50 200K 60 200K ns
10 10 ns
10 10 ns

This parameter defines the time at which the output achieves

6.
the open circuit condition and is not referenced to VOH or
VOL.

tWCS is non-restrictive operating parameter. It is included in

7.
the data sheet as electrical characteristics only. If

Unit Note

tWCS≥tWCS(min), the cycle is an early write cycle and the

data out pin will remain high impedance for the duration of
the cycle.

Either tRCH or tRRH must be satisfied for a read cycle.

8.

9.

These parameters are referenced to the CAS leading edge in
early write cycles.

Operation within the tRAD(max) limit insures that tRAC(max)

10.

can be met. tRAD(max) is specified as reference point only. If

tRAD is greater than the specified tRAD(max) limit, then

access time is controlled by tAA.

DRAM MODULE KMM5364003BSW/BSWG

READ CYCLE

tRC

RAS

CAS

OE

DQ

A

W

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VOH -
VOL -

tCRP

tASR tRAH

ROW

ADDRESS

tRAD

OPEN

tASC

tRCS

tRAC

tRAS

tCSH

tRSHtRCD
tCAS

tRAL

tCAH

COLUMN

ADDRESS

tAA

tOEA

tCAC

tCLZ

DATA-OUT

tRP

tCRP

tRCH

tRRH

tOFF

tOEZ

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

WRITE CYCLE ( EARLY WRITE )

NOTE : DOUT = OPEN

RAS

CAS

OE

W

A

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

tCRP

tASR tRAH

ROW

ADDRESS

tRAD

tASC

tWCS

tRAS

tCSH

tCAH

COLUMN

ADDRESS

tCWL
tRWL

tWCH
tWP

tRC

tRSHtRCD
tCAS

tRAL

tRP

tCRP

DQ

VIH -
VIL -

tDS

tDH

DATA-IN

Don′t care
Undefined

DRAM MODULE KMM5364003BSW/BSWG

WRITE CYCLE ( OE CONTROLLED WRITE )

NOTE : DOUT = OPEN

RAS

CAS

W

OE

DQ

A

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

tCRP

tASR tRAH

ROW

ADDRESS

tRAD

tASC

tOED

tRAS

tCSH

tCAH

COLUMN

ADDRESS

tDS

tRSHtRCD
tCAS

tWP

tOEH

DATA-IN

tRC

tRP

tCRP

tRAL

tCWL
tRWL

tDH

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

READ - MODIFY - WRTIE CYCLE

tRWC

tRP

RAS

tRAS

VIH -
VIL -

CAS

OE

DQ

A

W

VI/OH -
VI/OL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

tCRP

tRAD

tASR tRAH

ROW

ADDR

tASC

COLUMN

ADDRESS

tCLZ

tAA

tRAC

tCAH

tRWD

tOEA

tCAC

tRSHtRCD
tCAS

tAWD
tCWD

VALID

DATA-OUT

tOED

tOEZ

tCSH

tDS tDH

VALID

DATA-IN

tRWL

tCWL

tWP

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

FAST PAGE READ CYCLE

NOTE : DOUT = OPEN

RAS

CAS

OE

DQ

A

W

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VOH -
VOL -

tCRP

tASR

ROW

ADDR

tRAD

tASC

tRAH

tRCD

tRAC

tCSH

COLUMN

ADDRESS

tAA

tCLZ

tCAS

tCP

tCAH

tRCH

tCAC
tOEA

tOEZ

VALID

DATA-OUT

tPC

tASC

COLUMN

ADDRESS

tAA

tOFF

tCLZ

tRASP

tRHCP

¡ó

tCP

tCAS

¡ó

tCAH tASC tCAH

¡ó

COLUMN

ADDRESS

¡ó

tRCS tRCStRCS

¡ó

tCAC
tOEA

¡ó

¡ó

tAA

tOFF

tOEZ

VALID

DATA-OUT

tCLZ

tRSH

tCAS

tCAC
tOEA

DATA-OUT

tRP

tRRH

tRCH

tOFF

tOEZ

VALID

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

FAST PAGE WRITE CYCLE ( EARLY WRITE )

NOTE : DOUT = OPEN

RAS

CAS

W

OE

DQ

A

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

tCRP

tRAD

tASR tRAH

ROW

ADDR

tRCD

tASC

tWCS

tDS

tRASP

¡ó

tPC

tPC

tCP

tCAS

tCSH

tCAH

COLUMN

ADDRESS

tWCH

tWP

tCWL

tASC

tWCS tWCH

tCAS

¡ó

tCAH tASC tCAH

COLUMN

ADDRESS

¡ó

¡ó

¡ó

tWP

tCWL

¡ó

¡ó

tDH tDS tDH tDS tDH

VALID

DATA-IN

VALID

DATA-IN

¡ó

¡ó

tCP

COLUMN

ADDRESS

tWCS

VALID

DATA-IN

tRP

tRHCP

tRSH

tCAS

tWCH

tWP

tCWL
tRWL

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

FAST PAGE READ - MODIFY - WRITE CYCLE

RAS

CAS

W

OE

DQ

VIH -
VIL -

VIH -
VIL -

VIH -

A

VIL -

VIH -
VIL -

VIH -
VIL -

VI/OH -
VI/OL -

tASR

ROW

ADDR

tRCD

tRAD

tRAH

tRCS

tRAC

tCLZ

COL.

ADDR

tAA

tRWD

tOEA

tCAC

tCSH

tCAH

tAWD

tCAS

tCWD

tOEZ

tCWL

tOED

VALID

DATA-OUT

tDS

tWP

tRASP

tCP

tASCtASC

tDH

VALID

DATA-IN

ADDR

tCLZ

COL.

tCPWD

tOEA

tCAC

tAA

tPRWC

tCAH

tCWD

tAWD

tRSH

tCAS

tRAL

tOED

tOEZ

VALID

DATA-OUT

tCWL

tDS

tRWL

tWP

tDH

VALID

DATA-IN

tRP

tCRP

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

RAS - ONLY REFRESH CYCLE

NOTE : W, OE, DIN = Don′t care

DOUT = OPEN

VIH -

RAS

VIL -

tCRP

VIH -

CAS

VIL -

tASR tRAH

A

VIH -
VIL -

ROW

ADDR

CAS - BEFORE - RAS REFRESH CYCLE

NOTE : OE, A = Don′t care

tRP

tRPC

RAS

VIH -
VIL -

tRAS

tRC

tRAS

tRC

tRPC

tRP

tCRP

tRP

CAS

DQ

W

VIH -
VIL -

VIH -
VIL -

VOH -
VOL -

tCP

tOFF

tCSR

tWRP

tRPC

tCHR

tWRH

OPEN

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

HIDDEN REFRESH CYCLE ( READ )

RAS

CAS

OE

DQ

A

W

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VOH -
VOL -

tCRP

tRAD

tASR tRAH tASC

ROW

ADDRESS

tRCS

OPEN

tRAS

tRAC

tRC

tRSH

tCAH

COLUMN

ADDRESS

tAA

tCLZ

tOEA

tCAC

tRP tRP

tRAS

tCHRtRCD

tWRH

tRRH

tWRP

DATA-OUT

tRC

tOFF

tOEZ

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

HIDDEN REFRESH CYCLE ( WRITE )

NOTE : DOUT = OPEN

RAS

CAS

W

OE

A

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

tCRP

tRCD

tRAD

tASR tRAH tASC

ROW

ADDRESS

tWCS

tDS

tRAS

COLUMN

ADDRESS

tWP

tRC

tRSH

tCAH

tWCH

tDH

tWRH

tWRP

tRAS

tCHR

tRC

tRPtRP

DQ

VIH -
VIL -

DATA-IN

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE

tRP

RAS

CAS

A

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

tCSR

tCHR

tRAS

tCPT

tASC tCAH

COLUMN

ADDRESS

tRSH

tCAS

tRAL

READ CYCLE

VIH -

W

VIL ­VIH -

OE

VIL -

VOH -

DQ

VOL -

WRITE CYCLE

VIH -

W

VIL -

VIH -

OE

VIL -

VIH -

DQ

VIL -

tWRP tWRH

tWRP tWRH

READ-MODIFY-WRITE

tWRP tWRH

VIH -

W

VIL -

VIH -

OE

VIL -

tRCS

tWCS

tDS

tRCS

tCLZ

tAA

tWP

DATA-IN

tAWD

tCAC

tOEA

tAA
tCAC

tOEA

tCWL

tCWD

tRWL

tWCH

tDH

tOED

DATA-OUT

tRWL

tWP

tDH

tCWL

tRCH

tOEZ

tRRH

tOFF

tCLZ tOEZ

VI/OH -

DQ

VI/OL -

VALID

DATA-OUT

NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.

VALID

DATA-IN

tDS

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

CAS - BEFORE - RAS SELF REFRESH CYCLE

NOTE : OE, A = Don′t care

VIH -

RAS

VIL -

VIH -

CAS

VIL -

VOH -

DQ

VOL -

VIH -

W

VIL -

TEST MODE IN CYCLE

NOTE : OE, A = Don′t care

tRPC

tCP

tRP

tOFF

tCSR

tWRP

tRASS tRPS

tRPC

tCHS

OPEN

tWRH

RAS

CAS

DQ

W

VIH -
VIL -

VIH -
VIL -

VIH -
VIL -

VOH -
VOL -

tRPC

tCP

tRP

tOFF

tCSR

tWTS

tWTH

tCHR

tRAS

tRC

tRP

tRPC

OPEN

Don′t care

Undefined

DRAM MODULE KMM5364003BSW/BSWG

PACKAGE DIMENSIONS

Units : Inches (millimeters)

4.250(107.95)

3.984(101.19)

.133(3.38)

1.000(31.75)
.250(6.35)

.125 DIA±.002(3.18±.051)R.062(1.57)

.400(10.16)

.080(2.03)
.250(6.35)

.010(.25)MAX

.250(6.35)

3.750(95.25)

( Front view )

( Back view )

Gold/Solder Plating Lead

R.062±.004(R1.57±.10)

.100(2.54)

MAX

0.125

MIN

.050(1.27)

.041±.004(1.04±.10)

.054(1.37)
.047(1.19)

(3.20MIN)

Tolerances : ±.005(.13) unless otherwise specified

NOTE : The used device is 4Mx16 & Quad CAS 4Mx4 DRAM, TSOPII
DRAM Part No. : KMM5364003BSW/BSWG -- KM416C4100BS & KM44C4003CS(300 mil)