SAMSUNG KM681002B, KM681002BI Technical data

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PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

Document Title

128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Range.

Revision History

Rev No.

Rev. 0.0

Rev.1.0

Rev.2.0

History

Initial release with Design Target.

Release to Preliminary Data Sheet.

1. Replace Design Target to Preliminary.

Release to Final Data Sheet.

2.1. Delete Preliminary

2.2. Delete 32-SOJ-300 package

2.3. Delete L-version.

2.4. Delete Data Retention Characteristics and Waveform.

2.5. Add Capacitive load of the test environment in A.C test load

2.6. Change D.C characteristics Items Icc 160/150/140mA 160/155/150mA

Isb 30mA 50mA

Previous spec.

(8/10/12ns part)

Changed spec.

(8/10/12ns part)

Draft Data

Apr. 1st, 1997

Jun. 1st, 1997

Feb. 25th, 1998

Remark

Design Target

Preliminary

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquart ers.

- 1 -

Rev 2.0

February 1998

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

128K x 8 Bit High-Speed CMOS Static RAM

GENERAL DESCRIPTIONFEATURES

• Fast Access Time 8,10,12ns(Max.)

• Low Power Dissipation Standby (TTL) : 50mA(Max.) (CMOS) : 10mA(Max.) Operating KM681002B - 8 : 160 mA(Max.) KM681002B - 10 : 155 mA(Max.) KM681002B - 12 : 150 mA(Max.)

• Single 5.0V ±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Standard Pin Configuration KM681002BJ : 32-SOJ-400 KM681002BT: 32-TSOP2-400F

The KM681002B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681002B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung ′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681002B is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward.

ORDERING INFORMATION

KM681002B -8/10/12 Commercial Temp. KM681002BI -8/10/12 Industrial Temp.

PIN CONFIGURATION(Top View)

FUNCTIONAL BLOCK DIAGRAM

A0 A1 A2 A3 A4

A5 A6 A7

I/O1~I/O8

CS WE OE

Clk Gen.

Row Select

Data

Cont.

CLK Gen.

Pre-Charge Circuit

Memory Array

256 Rows

512x8 Columns

I/O Circuit

Column Select

A10 A11 A12 A13 A14 A15

A8 A9 A16

I/O1

I/O2

Vcc

Vss I/O3 I/O4

A4 A5 A6 A7

9 10 11 12 13 14 15 16

SOJ/

TSOP2

PIN FUNCTION

Pin Name Pin Function

A0 - A16 Address Inputs

WE Write Enable

CS Chip Select OE Output Enable

I/O1 ~ I/O8 Data Inputs/Outputs

VCC Power(+5.0V) VSS Ground N.C No Connection

A16

A15

A14

A13

I/O8

I/O7

Vss

Vcc

I/O6

I/O5

A12

A11

A10

- 2 -

Rev 2.0

February 1998

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Rating Unit

Voltage on Any Pin Relative to V SS VIN, VOUT -0.5 to 7.0 V Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V Power Dissipation PD 1.0 Storage Temperature TSTG -65 to 150 °C Operating Temperature Commercial TA 0 to 70 °C

Industrial TA -40 to 85 °C

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (TA=0 to 70°C)

Parameter

Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC + 0.5** V Input Low Voltage VIL -0.5* - 0.8 V

NOTE: The above parameters are also guaranteed at industrial temperature range.

* VIL(Min) = -2.0V a.c(Pulse Width≤6ns) for I≤20mA

** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤6ns) for I≤20mA

Symbol

Min

Typ Max Unit

DC AND OPERATING CHARACTERISTICS (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Parameter Symbol Test Conditions

Input Leakage Current ILI VIN = VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL

Operating Current ICC Min. Cycle, 100% Duty

Standby Current ISB Min. Cycle, CS=VIH - 50 mA

ISB1 f=0MHz, CS ≥VCC-0.2V,

Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V

VOH1* IOH1=-0.1mA - 3.95 V

NOTE: The above parameters are also guaranteed at industrial temperature range. * VCC=5.0V, Temp.=25°C

VOUT=VSS to VCC

CS=VIL, VIN=VIH or VIL, IOUT=0mA

VIN≥VCC-0.2V or VIN≤0.2V

8ns - 160 mA 10ns - 155 12ns - 150

Min Max

-2 2 µA

- 10 mA

Unit

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item Symbol Test Conditions MIN Max Unit

Input/Output Capacitance CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 6 pF

* NOTE : Capacitance is sampled and not 100% tested.

- 3 -

Rev 2.0

February 1998

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