SAMSUNG KM681002B, KM681002BI Technical data

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PRELIMINARY

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

Document Title

128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.

Revision History

Rev No.

Rev. 0.0

Rev.1.0

Rev.2.0

History

Initial release with Design Target.

Release to Preliminary Data Sheet.

1. Replace Design Target to Preliminary.

Release to Final Data Sheet.

2.1. Delete Preliminary

2.2. Delete 32-SOJ-300 package

2.3. Delete L-version.

2.4. Delete Data Retention Characteristics and Waveform.

2.5. Add Capacitive load of the test environment in A.C test load

2.6. Change D.C characteristics
Items
Icc 160/150/140mA 160/155/150mA

Isb 30mA 50mA

Previous spec.

(8/10/12ns part)

Changed spec.

(8/10/12ns part)

Draft Data

Apr. 1st, 1997

Jun. 1st, 1997

Feb. 25th, 1998

Remark

Design Target

Preliminary

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquart ers.

- 1 -

Rev 2.0

February 1998

PRELIMINARY

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

128K x 8 Bit High-Speed CMOS Static RAM

GENERAL DESCRIPTIONFEATURES

• Fast Access Time 8,10,12ns(Max.)

• Low Power Dissipation
Standby (TTL) : 50mA(Max.)
(CMOS) : 10mA(Max.)
Operating KM681002B - 8 : 160 mA(Max.)
KM681002B - 10 : 155 mA(Max.)
KM681002B - 12 : 150 mA(Max.)

• Single 5.0V ±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Standard Pin Configuration
KM681002BJ : 32-SOJ-400
KM681002BT: 32-TSOP2-400F

The KM681002B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681002B uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using Samsung ′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681002B is packaged
in a 400mil 32-pin plastic SOJ or TSOP2 forward.

ORDERING INFORMATION

KM681002B -8/10/12 Commercial Temp.
KM681002BI -8/10/12 Industrial Temp.

PIN CONFIGURATION(Top View)

FUNCTIONAL BLOCK DIAGRAM

A0
A1
A2
A3
A4

A5
A6
A7

I/O1~I/O8

CS
WE
OE

Clk Gen.

Row Select

Data

Cont.

CLK
Gen.

Pre-Charge Circuit

Memory Array

256 Rows

512x8 Columns

I/O Circuit

Column Select

A10 A11 A12 A13 A14 A15

A8 A9 A16

1

A0

2

A1

3

A2

4

A3

5

CS

6

I/O1

7

I/O2

8

Vcc

Vss
I/O3
I/O4

WE

A4
A5
A6
A7

9
10
11
12
13
14
15
16

SOJ/

TSOP2

PIN FUNCTION

Pin Name Pin Function

A0 - A16 Address Inputs

WE Write Enable

CS Chip Select
OE Output Enable

I/O1 ~ I/O8 Data Inputs/Outputs

VCC Power(+5.0V)
VSS Ground
N.C No Connection

32

A16

31

A15

30

A14

29

A13

28

OE

27

I/O8

26

I/O7

25

Vss

24

Vcc

23

I/O6

22

I/O5

21

A12

20

A11

19

A10

18

A9

17

A8

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Rev 2.0

February 1998

PRELIMINARY

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Rating Unit

Voltage on Any Pin Relative to V SS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD 1.0
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA 0 to 70 °C

Industrial TA -40 to 85 °C

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (TA=0 to 70°C)

Parameter

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.2 - VCC + 0.5** V
Input Low Voltage VIL -0.5* - 0.8 V

NOTE: The above parameters are also guaranteed at industrial temperature range.

* VIL(Min) = -2.0V a.c(Pulse Width≤6ns) for I≤20mA

** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤6ns) for I≤20mA

Symbol

Min

Typ Max Unit

W

DC AND OPERATING CHARACTERISTICS (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Parameter Symbol Test Conditions

Input Leakage Current ILI VIN = VSS to VCC -2 2 µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL

Operating Current ICC Min. Cycle, 100% Duty

Standby Current ISB Min. Cycle, CS=VIH - 50 mA

ISB1 f=0MHz, CS ≥VCC-0.2V,

Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 - V

VOH1* IOH1=-0.1mA - 3.95 V

NOTE: The above parameters are also guaranteed at industrial temperature range.
* VCC=5.0V, Temp.=25°C

VOUT=VSS to VCC

CS=VIL, VIN=VIH or VIL,
IOUT=0mA

VIN≥VCC-0.2V or VIN≤0.2V

8ns - 160 mA
10ns - 155
12ns - 150

Min Max

-2 2 µA

- 10 mA

Unit

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item Symbol Test Conditions MIN Max Unit

Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN VIN=0V - 6 pF

* NOTE : Capacitance is sampled and not 100% tested.

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Rev 2.0

February 1998

PRELIMINARY

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

TEST CONDITIONS

Parameter Value

Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below

NOTE: The above test conditions are also applied at industrial temperature range.

Output Loads(A)

DOUT

ZO = 50Ω

* Capacitive Load consists of all components of the
test environment.

RL = 50Ω

30pF*

VL = 1.5V

Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

DOUT

255Ω

* Including Scope and Jig Capacitance

+5.0V
480Ω

5pF*

READ CYCLE

Parameter Symbol

Read Cycle Time tRC 8 - 10 - 12 - ns
Address Access Time tAA - 8 - 10 - 12 ns
Chip Select to Output tCO - 8 - 10 - 12 ns
Output Enable to Valid Output tOE - 4 - 5 - 6 ns
Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns
Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns
Chip Disable to High-Z Output tHZ 0 4 0 5 0 6 ns
Output Disable to High-Z Output
Output Hold from Address Change tOH 3 - 3 - 3 - ns
Chip Selection to Power Up Time tPU 0 - 0 - 0 - ns
Chip Selection to Power DownTime tPD - 8 - 10 - 12 ns

NOTE: The above parameters are also guaranteed at industrial temperature range.

tOHZ

KM681002B-8 KM681002B-10 KM681002B-12
Min Max Min Max Min Max

0 4 0 5 0 6 ns

Unit

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Rev 2.0

February 1998

PRELIMINARY

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

WRITE CYCLE

Parameter Symbol

Write Cycle Time tWC 8 - 10 - 12 - ns
Chip Select to End of Write tCW 6 - 7 - 8 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Address Valid to End of Write tAW 6 - 7 - 8 - ns
Write Pulse Width(OE High) tWP 6 - 7 - 8 - ns
Write Pulse Width(OE Low) tWP1 8 - 10 - 12 - ns
Write Recovery Time tWR 0 - 0 - 0 ­Write to Output High-Z
Data to Write Time Overlap tDW 4 - 5 - 6 ­Data Hold from Write Time tDH 0 - 0 - 0 - ns
End Write to Output Low-Z tOW 3 - 3 - 3 - ns

NOTE: The above parameters are also guaranteed at industrial temperature range.

tWHZ

KM681002B-8 KM681002B-10 KM681002B-12

Min Max Min Max Min Max

0 4 0 5 0 6

Unit

ns
ns
ns

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tOH

Data Out Previous Valid Data

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS

OE

tOLZ

Data out

VCC
Current

ICC
ISB

tLZ(4,5)

tPU

50%

tAA

tRC

tAA

tCO

tOE

Valid Data

tHZ(3,4,5)

tOHZ

tOH

Valid Data

tPD

50%

- 5 -

Rev 2.0

February 1998

PRELIMINARY

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

tWC

Address

tAW

OE

tCW(3)

tWR(5)

CS

tAS(4)

WE

Data in

Data out

High-Z

tOHZ(6)

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)

Address

CS

tAS(4)

WE

Data in

Data out

High-Z

tAW

tWHZ(6)

tWC

tCW(3)

tWP1(2)

tWP(2)

High-Z(8)

tDW

Valid Data

tDW tDH

Valid Data

High-Z(8)

tDH

tWR(5)

tOW

(10)

(9)

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Rev 2.0

February 1998

PRELIMINARY

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)

tWC

Address

CS

WE

Data in

Data out

tAW

tCW(3)

tWP(2)tAS(4)

tDW

High-Z

tLZ

tWHZ(6)

Data Valid

High-Z

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.

tWR(5)

tDH

High-Z

High-Z(8)

FUNCTIONAL DESCRIPTION

CS WE OE Mode I/O Pin Supply Current

H X X* Not Select High-Z ISB, ISB1
L H H Output Disable High-Z ICC
L H L Read DOUT ICC
L L X Write DIN ICC

* NOTE : X means Don′t Care.

- 7 -

Rev 2.0

February 1998

PRELIMINARY

PRELIMINARY

Preliminary

PRELIMINARY

KM681002B, KM681002BI CMOS SRAM

PACKAGE DIMENSIONS

32-SOJ-400

11.18 ±0.12

0.440 ±0.005

0.95

( )

0.0375

#32

#1

0.43

0.017

+0.10

-0.05

+0.004

-0.002

21.36

MAX

0.841

20.95 ±0.12

0.825 ±0.005

1.27

0.050

0.71

0.028

+0.10

-0.05

+0.004

-0.002

#17

#16

1.30

( )

0.051

1.30

( )

0.051

Units:millimeters/Inches

0.10

0.004

0.370 ±0.010

10.16

3.76

0.148

0.400

0.027

MAX

0.69

MIN

9.40 ±0.25

0.20

0.008

MAX

+0.10

-0.05

+0.004

-0.002

32-TSOP2-400F

#32

#1

0.95

( )

0.037

0.40 ±0.10

0.016 ±0.004

21.35

MAX

0.841

20.95 ±0.10

0.825 ±0.004

1.27

0.050

#17

#16

11.76 ±0.20

0.463 ±0.008

1.00 ±0.10

0.039 ±0.004

0.05

MIN

0.002

1.20

0.047

( )

10.16

0.15

0.006

MAX

0.25

0.010

0.400

+0.10

-0.05
+0.004

-0.002

0~8°

0.10 MAX

0.004 MAX

0.45 ~0.75

0.018 ~ 0.030

0.50

( )

0.020

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Rev 2.0

February 1998