Samsung KM681002ATI-12, KM681002AT-20, KM681002AT-15, KM681002AT-12, KM681002AJI-12 Datasheet
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KM681002A, KM681002AI
CMOS SRAM
PRELIMINARY
Rev 4.0
- 1 -
Ferruary 1998
Document Title
128Kx8 High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 3.0
Rev. 4.0
Remark
Preliminary
Final
Final
Final
Final
History
Initial release with Preliminary.
Release to final Data Sheet.
1.1. Delete Preliminary
Update D.C parameters.
2.1. Update D.C parameters
Add Industrial Temperature Range parts and 300mil-SOJ PKG.
3.1. Add 32-Pin 300mil-SOJ Package.
3.2. Add Industrial Temperature Range parts with the same parame ters as Commercial Temperature Range parts.
3.2.1. Add KM68002AI parts for Industrial Temperature Range.
3.2.2. Add ordering information.
3.2.3. Add the condition for operating at Industrial Temp. Range.
3.3. Add the test condition for Voh1 with Vcc=5V±5% at 25°C
3.4. Add timing diagram to define tWP as ″(Timing Wave Form of
Write Cycle(CS=Controlled)″
4.1. Delete 17ns Part
Items
Previous spec.
(12/15/17/20ns part)
Updated spec.
(12/15/17/20ns part)
Icc 200/190/180/170mA 170/165/165/160mA
Isb 30mA 25mA
Isb1 10mA 8mA
Draft Data
Apr. 22th, 1995
Feb. 29th, 1996
Jul. 16th, 1996
Jun. 2nd, 1997
Feb. 25th, 1998
KM681002A, KM681002AI
CMOS SRAM
PRELIMINARY
Rev 4.0
- 2 -
Ferruary 1998
128K x 8 Bit High-Speed CMOS Static RAM
GENERAL DESCRIPTIONFEATURES
• Fast Access Time 12, 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL) : 25mA(Max.)
(CMOS) : 8mA(Max.)
Operating KM681002A - 12 : 170mA(Max.)
KM681002A - 15 : 165mA(Max.)
KM681002A - 20 : 160mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM681002AJ : 32-SOJ-400
KM681002AT: 32-TSOP2-400F
KM681002A -12/15/20 Commercial Temp.
KM681002AI -12/15/20 Industrial Temp.
ORDERING INFORMATION
Clk Gen.
I/O1~I/O8
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
Row Select
Data
Cont.
Column Select
A9 A10 A11 A12 A13 A14 A15 A16
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
256x8 Columns
I/O Circuit
PIN FUNCTION
Pin Name Pin Function
A0 - A16 Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
I/O1 ~ I/O8 Data Inputs/Outputs
VCC Power(+5.0V)
VSS Ground
The KM681002A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681002A uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using Samsung′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681002A is packaged
in a 400mil 32-pin plastic SOJ or TSOP2 forward.
PIN CONFIGURATION(Top View)
SOJ/
TSOP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
A8
A0
A1
A2
A3
CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
A8
KM681002A, KM681002AI
CMOS SRAM
PRELIMINARY
Rev 4.0
- 3 -
Ferruary 1998
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD 1.0
W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA 0 to 70 °C
Industrial TA -40 to 85 °C
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
NOTE: The above parameters are also guaranteed at industrial temperature range.
* VIL(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA
** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤10ns) for I≤20mA
Parameter
Symbol
Min
Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.2 - VCC + 0.5** V
Input Low Voltage VIL -0.5* - 0.8 V
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
NOTE: The above parameters are also guaranteed at industrial temperature range.
* VCC=5.0V, Temp.=25°C
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN=VSS to VCC -2 2 µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2 2 µA
Operating Current ICC Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL,
IOUT=0mA
12ns - 170 mA
15ns - 165
20ns - 160
Standby Current ISB Min. Cycle, CS=VIH - 25 mA
ISB1 f=0MHz, CS ≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
- 8 mA
Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 - V
VOH1* IOH1=-0.1mA - 3.95 V
CAPACITANCE*(TA=25°C, f=1.0MHz)
* NOTE : Capacitance is sampled and not 100% tested.
Item Symbol Test Conditions MIN Max Unit
Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN
VIN=0V
- 6 pF
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