Samsung KM681000BLT-7L, KM681000BLT-7, KM681000BLT-5L, KM681000BLT-5, KM681000BLRI-7L Datasheet

PRELIMINARY

V

KM681000B Family CMOS SRAM

128K x8 bit Low Power CMOS Static RAM

GENERAL DESCRIPTIONFEATURES

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Process Technology : 0.6

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Organization : 128Kx8

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Power Supply Voltage : Single 5.0V

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Low Data Retention Voltage : 2V(Min)

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Three state output and TTL Compatible

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Package Type : JEDEC Standard

§-

CMOS

¡¾

10%

32-DIP, 32-SOP, 32-TSOP I R/F

PRODUCT FAMILY

The KM681000B family is fabricated by SAMSUNG's advanced
CMOS process technology. The family can support various
operating temperature ranges and have various package types
for user flexibility of system design. The family also support low
data retention voltage for battery back-up operation with low
data retention current.

Product

Family

KM681000BL
KM681000BL-L
KM681000BLE
KM681000BLE-L
KM681000BLI
KM681000BLI-L

PIN DESCRIPTION

1

2

A16

3

A14

4

A12

5

A7
A6

6

A5

7

32-DIP

A4
A3
A2
A1
A0

SS

32-SOP

8

9

10

11

12

1

13

2

14

3

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Operating

Temperature

Commercial(0~7¡É) 55/70ns

Extended(-25~85¡É) 70/100ns

Industrial(-40~85¡É) 70/100ns

A11

1

A9

2

A8

3

A13

4

WE

5

CS2

CS2

6

A15

7

VCC

8

NC

9

A16

10

A14

11

A12

12

A7

13

A6

14

A5

15

A4

16

16

A4

15

A5

14

A6

13

A7

12

A12

11

A14

10

A16

9

NC

8

VCC

7

A15

6
5

WE

4

A13

3

A8

2

A9

1

A11

32-TSOP

Type I - Forward

32-TSOP

Type I-Reverse

VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4

Speed PKG Type

32-DIP,32-SOP
32-TSOP I R/F

32-SOP
32-TSOP I R/F

32-SOP
32-TSOP I R/F

FUNCTIONAL BLOCK DIAGRAM

32

OE

31

A10
CS1

30

I/O8

29

I/O7

28
27

I/O6

26

I/O5

25

I/O4

24

VSS

23

I/O3

22

I/O2

21

I/O1

20

A0

19

A1

18

A2

17

A3

A3

17
18

A2
A1

19
20

A0

21

I/O1

22

I/O2

23

I/O3

24

VSS

25

I/O4

26

I/O5

27

I/O6

28

I/O7

29

I/O8

30

CS1

31

A10

32

OE

A0~3, A8~11

A4~7,
A12~16

Name Function

A0~A16 Address Inputs

WE Write Enable Input

CS1,CS2

OE Output Enable Input

I/O1~I/O18 Data Inputs/Outputs

Vcc Power
Vss Ground
N.C No Connection

I/O1~8

X-Decoder

Power Dissipation

Standby

(ISB1, Max)

§Ë

100

§Ë

20

§Ë

100

§Ë

50

§Ë

100

§Ë

50

Y-Decoder

Cell
Array

I/O Buffer

Chip Select Inputs

Operating

(ICC2)

70mA

Control Logic

CS1,CS2

WE,OE

Revision 0.3

April 1996

PRELIMINARY

KM681000B Family CMOS SRAM

PRODUCT LIST & ORDERING INFORMATION

PRODUCT LIST

Commercial Temp Product

(0~70¡É)

Extended Temp Products

(-25~85¡É)

Industrial Temp Products

(-40~85¡É)

Part Name Function Part Name Function Part Name Function

KM681000BLP-5
KM681000BLP-5L
KM681000BLP-7
KM681000BLP-7L
KM681000BLG-5
KM681000BLG-5L
KM681000BLG-7
KM681000BLG-7L
KM681000BLT-5
KM681000BLT-5L
KM681000BLT-7
KM681000BLT-7L
KM681000BLR-5
KM681000BLR-5L
KM681000BLR-7
KM681000BLR-7L

32-DIP,55ns,L-pwr
32-DIP,55ns,LL-pwr
32-DIP,70ns,L-pwr
32-DIP,70ns,LL-pwr
32-SOP,55ns,L-pwr
32-SOP,55ns,LL-pwr
32-SOP,70ns,L-pwr
32-SOP,70ns,LL-pwr
32-TSOP F,55ns,L-pwr
32-TSOP F,55ns,LL-pwr
32-TSOP F,70ns,L-pwr
32-TSOP F,70ns,LL-pwr
32-TSOP R,55ns,L-pwr
32-TSOP R,55ns,LL-pwr
32-TSOP R,70ns,L-pwr
32-TSOP R,70ns,LL-pwr

KM681000BLGE-7
KM681000BLGE-7L
KM681000BLGE-10
KM681000BLGE-10L
KM681000BLTE-7
KM681000BLTE-7L
KM681000BLTE-10
KM681000BLTE-10L
KM681000BLRE-7
KM681000BLRE-7L
KM681000BLRE-10
KM681000BLRE-10L

32-SOP,70ns,L-pwr
32-SOP,70ns,LL-pwr
32-SOP,100ns,L-pwr
32-SOP,100ns,LL-pwr
32-TSOP F,70ns,L-pwr
32-TSOP F,70ns,LL-pwr
32-TSOP F,100ns,L-pwr
32-TSOP F,100ns,LL-pwr
32-TSOP R,70ns,L-pwr
32-TSOP R,70ns,LL-pwr
32-TSOP R,100ns,L-pwr
32-TSOP R,100ns,LL-pwr

KM681000BLGI-7
KM681000BLGI-7L
KM681000BLGI-10
KM681000BLGI-10L
KM681000BLTI-7
KM681000BLTI-7L
KM681000BLTI-10
KM681000BLTI-10L
KM681000BLRI-7
KM681000BLRI-7L
KM681000BLRI-10
KM681000BLRI-10L

32-SOP,70ns,L-pwr
32-SOP,70ns,LL-pwr
32-SOP,100ns,L-pwr
32-SOP,100ns,LL-pwr
32-TSOP F,70ns,L-pwr
32-TSOP F,70ns,LL-pwr
32-TSOP F,100ns,L-pwr
32-TSOP F,100ns,LL-pwr
32-TSOP R,70ns,L-pwr
32-TSOP R,70ns,LL-pwr
32-TSOP R,100ns,L-pwr
32-TSOP R,100ns,LL-pwr

ORDERING INFORMATION

KM6 8 X 1000 B X X X - XX X

L-Low Low Power, Blank-Low Power or High Power
Access Time : 5=55ns, 7=70ns, 10=100ns

Operating temperature : Blank=Commerial, I=Industrial, E=Extended,

Package Type : P-DIP, G=SOP, T=TSOP Forward, R=TSOP Reverse

L-Low Power or Low Low Power, Blank-High Power
Die Version : B=3 rd generation

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Density : 1000=1Mbit
Bank=5V, V=3.0~3.6V, U=2.7~3.3V
Organization : 8=x8
SEC Standard SRAM

Revision 0.3

April 1996

PRELIMINARY

KM681000B Family CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V ­Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150

0 to 70

Operating Temperature TA

Soldering temperature and time TSOLDER 260¡É, 10sec (Lead Only) - -

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

-25 to 85

-40 to 85

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¡É
¡É
¡É

-

KM681000BL/L-L

KM681000BLE/LE-L

KM681000BLI/LI-L

RECOMMENDED DC OPERATING CONDITIONS*

Item Symbol Min Typ** Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 - Vcc+0.5 V
Input low voltage VIL -0.5*** - 0.8 V

* 1) Commercial Product : TA=0 to 70¡É, unless otherwise specified

2) Extended Product : TA=-25 to 85¡É, unless otherwise specified

3) Industrial Product : TA=-40 to 85¡É, unless otherwise specified

¡É

** TA=25
*** VIL(min)=-3.0V for ¡Â 50ns pulse width

CAPACITANCE* (f=1MHz, TA=25

Item Symbol Test Condition Min Max Unit

Input capacitance CIN Vin=0V - 6 pF

¡É

)

Input/Output capacitance CIO Vio=0V - 8 pF

* Capacitance is sampled not 100% tested

Revision 0.3

April 1996

PRELIMINARY

KM681000B Family CMOS SRAM

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions* Mi Typ** Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 - 1
Output leakage current ILO CS1=VIH or CS2=VIL or WE=VIL, VIO=Vss to Vcc -1 - 1
Operating power supply current ICC CS1=VIL, CS2=VIH, VIN=VIH or VIL, IIO=0mA - 7 15** mA

ICC1

Average operating current

ICC2

Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS1=VIH, CS2=VIL - - 3 mA

KM681000BL
KM681000BL-L

Standby
Current (CMOS)

* 1) Commercial Product : TA=0 to 70¡É, Vcc=5.0V¡¾10%, unless otherwise specified

2) Extended Product : TA=-25 to 85¡É, Vcc=5.0V¡¾10%, unless otherwise specified

2) Industrial Product : TA=-40 to 85¡É, Vcc=5.0V¡¾10%, unless otherwise specified
** 20mA for Exteneded and Industrial Products

*** 15mA for Extended and Industrial Products

KM681000BLE
KM681000BLE-L

KM681000BLI
KM681000BLI-L

ISB1

Cycle time=1§Á 100% duty
CS1¡Â0.2V, CS2¡ÃVCC-0.2V

IIO=0mA CS1=VIL,CS2=VIH
Min cycle, 100% duty

CS1¡ÃVcc-0.2V
CS2¡ÃVcc-0.2V or
CS2¡Â0.2V
Other input=0~Vcc

L (Low Power)
LL (Low Low Power)--

L (Low Power)
LL (Low Low Power)--

L (Low Power)
LL (Low Low Power)--

- - 10*** mA

- - 70 mA

-

100

-

-

-

-

-

20

100

50

100

50

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§Ë

§Ë

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§Ë

§Ë

§Ë

§Ë

A.C CHARACTERISTICS

TEST CONDITIONS (1.Test Load and Test Input/Output Reference)*

Item Value Remark

Input pulse level 0.8 to 2.4V ­Input rising & falling time 5ns ­input and output reference voltage 1.5V ­Output load (See right) CL=100pF+1TTL -

* See DC Operating conditions

CL*

* Including scope and jig capacitance

Revision 0.3

April 1996