KM681000BLT-5
KM681000B Family |
CMOS SRAM |
|
|
|
|
128K x8 bit Low Power CMOS Static RAM
FEATURES
¡Ü Process Technology : 0.6§- CMOS ¡Ü Organization : 128Kx8
¡Ü Power Supply Voltage : Single 5.0V ¡¾ 10% ¡Ü Low Data Retention Voltage : 2V(Min)
¡Ü Three state output and TTL Compatible ¡Ü Package Type : JEDEC Standard
32-DIP, 32-SOP, 32-TSOP I R/F
GENERAL DESCRIPTION
The KM681000B family is fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Product |
Operating |
|
|
Power Dissipation |
||
Speed |
PKG Type |
|
|
|||
Standby |
Operating |
|||||
Family |
Temperature |
|||||
|
|
|||||
|
|
|
|
(ISB1, Max) |
(ICC2) |
|
|
|
|
|
|
|
|
KM681000BL |
Commercial(0~7¡É) |
55/70ns |
32-DIP,32-SOP |
100§Ë |
|
|
KM681000BL-L |
32-TSOP I R/F |
20§Ë |
|
|||
|
|
|
||||
|
|
|
|
|||
KM681000BLE |
Extended(-25~85¡É) |
70/100ns |
32-SOP |
100§Ë |
70mA |
|
KM681000BLE-L |
32-TSOP I R/F |
50§Ë |
||||
|
|
|
||||
|
|
|
|
|||
|
|
|
|
|
|
|
KM681000BLI |
Industrial(-40~85¡É) |
70/100ns |
32-SOP |
100§Ë |
|
|
KM681000BLI-L |
32-TSOP I R/F |
50§Ë |
|
|||
|
|
|
||||
|
|
|
|
PIN DESCRIPTION
|
|
|
|
|
|
|
|
|
|
|
|
A11 |
|
1 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
A9 |
|
2 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
A8 |
|
3 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
A13 |
|
4 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
WE |
|
|
|
5 |
.C |
|
1 |
|
|
|
32 |
|
VCC |
CS2 |
|
6 |
|||||
A16 |
|
2 |
|
|
|
31 |
|
A15 |
A15 |
|
7 |
|||||
|
|
|
|
|
VCC |
|
8 |
|||||||||
A14 |
|
3 |
|
|
|
30 |
|
CS2 |
NC |
|
9 |
|||||
|
|
|
|
|
A16 |
|
10 |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
A14 |
|
|
|||
A12 |
|
4 |
|
|
|
29 |
|
WE |
|
|
11 |
|||||
A7 |
|
5 |
|
|
|
28 |
|
A13 |
A12 |
|
12 |
|||||
|
|
|
|
|
|
|||||||||||
|
|
|
|
|
A7 |
|
13 |
|||||||||
A6 |
|
6 |
|
|
|
27 |
|
A8 |
A6 |
|
14 |
|||||
A5 |
|
|
32-DIP |
|
|
A9 |
A5 |
|
15 |
|||||||
|
7 |
26 |
|
A4 |
|
16 |
||||||||||
|
||||||||||||||||
A4 |
|
8 |
32-SOP |
25 |
|
A11 |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
||||||||||
A3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
9 |
|
|
|
24 |
|
OE |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
A10 |
|
|
|
|
|
||||
A2 |
|
10 |
|
|
|
23 |
|
A4 |
|
|
16 |
|||||
|
|
|
|
|
|
|
||||||||||
A1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
11 |
|
|
|
22 |
|
CS |
1 |
A5 |
15 |
||||||
A0 |
|
12 |
|
|
|
21 |
|
I/O8 |
A6 |
|
|
14 |
||||
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
A7 |
|
|
13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12 |
||
/O1 |
|
13 |
|
|
|
20 |
|
I/O7 |
A12 |
|
|
|||||
|
|
|
|
|
|
|
11 |
|||||||||
/O2 |
|
14 |
|
|
|
19 |
|
I/O6 |
A14 |
|
|
|||||
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
A16 |
|
|
10 |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
9 |
||
/O3 |
|
15 |
|
|
|
18 |
|
I/O5 |
NC |
|
|
|||||
VSS |
|
|
|
|
|
17 |
|
I/O4 |
VCC |
|
|
8 |
||||
|
16 |
|
|
|
|
A15 |
|
|
7 |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
CS2 |
|
|
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
WE |
|
|
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
A13 |
|
|
4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
A8 |
|
|
3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
A9 |
|
|
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
A11 |
|
|
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
32-TSOP
Type I - Forward
32-TSOP
Type I-Reverse
|
|
FUNCTIONAL BLOCK DIAGRAM |
|
|
||
32 |
OE |
A0~3, A8~11 |
|
Y-Decoder |
|
|
|
|
|
|
|||
31 |
A10 |
|
|
|
|
|
30 |
CS1 |
|
|
|
|
|
29 |
I/O8 |
|
|
|
|
|
28 |
I/O7 |
|
|
|
|
|
27 |
I/O6 |
|
|
|
|
|
26 |
I/O5 |
|
|
|
|
|
25 |
I/O4 |
A4~7, |
Decoder-X |
|
|
|
24 |
VSS |
|
Control |
|
||
23 |
I/O3 |
A12~16 |
Cell |
|
||
|
|
|
||||
22 |
I/O2 |
|
|
|
||
21 |
I/O1 |
|
|
Array |
|
|
20 |
A0 |
|
|
|
|
CS1,CS2 |
19 |
A1 |
|
|
|
|
|
|
|
|
|
WE,OE |
||
18 |
A2 |
|
|
|
Logic |
|
17 |
A3 |
I/O1~8 |
|
|
||
|
|
|
|
I/O Buffer |
|
|
17 |
A3 |
|
|
|
|
|
18 |
A2 |
|
|
|
|
|
19 |
A1 |
|
|
|
|
|
20 |
A0 |
|
|
|
|
|
21 |
I/O1 |
Name |
|
Function |
|
|
22 |
I/O2 |
|
|
|
||
23 |
I/O3 |
A0~A16 |
|
Address Inputs |
|
|
24 |
VSS |
|
|
|
||
25 |
I/O4 |
WE |
|
Write Enable Input |
|
|
26 |
I/O5 |
|
|
|
||
27 |
I/O6 |
CS1,CS2 |
|
Chip Select Inputs |
|
|
28 |
I/O7 |
|
|
|
||
29 |
I/O8 |
|
|
|
||
|
|
|
|
|
||
30 |
CS1 |
OE |
|
Output Enable Input |
|
|
31 |
A10 |
|
|
|
||
|
|
|
|
|
||
32 |
OE |
I/O1~I/O18 |
Data Inputs/Outputs |
|
|
|
|
|
|
|
|||
|
|
Vcc |
|
Power |
|
|
|
|
Vss |
|
Ground |
|
|
|
|
N.C |
|
No Connection |
|
|
Revision 0.3
April 1996
KM681000B Family |
|
|
|
|
CMOS SRAM |
|||
|
|
|
|
|
|
|
|
|
PRODUCT LIST & ORDERING INFORMATION |
|
|
|
|
||||
PRODUCT LIST |
|
|
|
|
|
|
||
|
|
|
|
|
|
|
||
Commercial Temp Product |
Extended Temp Products |
Industrial Temp Products |
|
|||||
|
(0~70¡É) |
(-25~85¡É) |
(-40~85¡É) |
|
||||
Part Name |
|
Function |
Part Name |
|
Function |
Part Name |
Function |
|
KM681000BLP-5 |
|
32-DIP,55ns,L-pwr |
KM681000BLGE-7 |
|
32-SOP,70ns,L-pwr |
KM681000BLGI-7 |
32-SOP,70ns,L-pwr |
|
KM681000BLP-5L |
|
32-DIP,55ns,LL-pwr |
KM681000BLGE-7L |
|
32-SOP,70ns,LL-pwr |
KM681000BLGI-7L |
32-SOP,70ns,LL-pwr |
|
KM681000BLP-7 |
|
32-DIP,70ns,L-pwr |
KM681000BLGE-10 |
|
32-SOP,100ns,L-pwr |
KM681000BLGI-10 |
32-SOP,100ns,L-pwr |
|
KM681000BLP-7L |
|
32-DIP,70ns,LL-pwr |
KM681000BLGE-10L |
|
32-SOP,100ns,LL-pwr |
KM681000BLGI-10L |
32-SOP,100ns,LL-pwr |
|
KM681000BLG-5 |
|
32-SOP,55ns,L-pwr |
KM681000BLTE-7 |
|
32-TSOP F,70ns,L-pwr |
KM681000BLTI-7 |
32-TSOP F,70ns,L-pwr |
|
KM681000BLG-5L |
|
32-SOP,55ns,LL-pwr |
KM681000BLTE-7L |
|
32-TSOP F,70ns,LL-pwr |
KM681000BLTI-7L |
32-TSOP F,70ns,LL-pwr |
|
KM681000BLG-7 |
|
32-SOP,70ns,L-pwr |
KM681000BLTE-10 |
|
32-TSOP F,100ns,L-pwr |
KM681000BLTI-10 |
32-TSOP F,100ns,L-pwr |
|
KM681000BLG-7L |
|
32-SOP,70ns,LL-pwr |
KM681000BLTE-10L |
|
32-TSOP F,100ns,LL-pwr |
KM681000BLTI-10L |
32-TSOP F,100ns,LL-pwr |
|
KM681000BLT-5 |
|
32-TSOP F,55ns,L-pwr |
KM681000BLRE-7 |
|
32-TSOP R,70ns,L-pwr |
KM681000BLRI-7 |
32-TSOP R,70ns,L-pwr |
|
KM681000BLT-5L |
|
32-TSOP F,55ns,LL-pwr |
KM681000BLRE-7L |
|
32-TSOP R,70ns,LL-pwr |
KM681000BLRI-7L |
32-TSOP R,70ns,LL-pwr |
|
KM681000BLT-7 |
|
32-TSOP F,70ns,L-pwr |
KM681000BLRE-10 |
|
32-TSOP R,100ns,L-pwr |
KM681000BLRI-10 |
32-TSOP R,100ns,L-pwr |
|
KM681000BLT-7L |
|
32-TSOP F,70ns,LL-pwr |
KM681000BLRE-10L |
|
32-TSOP R,100ns,LL-pwr |
KM681000BLRI-10L |
32-TSOP R,100ns,LL-pwr |
|
KM681000BLR-5 |
|
32-TSOP R,55ns,L-pwr |
|
|
|
|
|
|
KM681000BLR-5L |
|
32-TSOP R,55ns,LL-pwr |
|
|
|
|
|
|
KM681000BLR-7 |
|
32-TSOP R,70ns,L-pwr |
|
|
|
|
|
|
KM681000BLR-7L |
|
32-TSOP R,70ns,LL-pwr |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ORDERING INFORMATION
KM6 8 X 1000 B X X X - XX X
L-Low Low Power, Blank-Low Power or High Power
Access Time : 5=55ns, 7=70ns, 10=100ns
Operating temperature : Blank=Commerial, I=Industrial, E=Extended,
Package Type : P-DIP, G=SOP, T=TSOP Forward, R=TSOP Reverse
L-Low Power or Low Low Power, Blank-High Power
Die Version : B=3¢rd¥ generation
Density : 1000=1Mbit
Bank=5V, V=3.0~3.6V, U=2.7~3.3V
Organization : 8=x8
SEC Standard SRAM
Revision 0.3
April 1996
KM681000B Family |
|
|
|
|
CMOS SRAM |
||
|
|
|
|
|
|
|
|
ABSOLUTE MAXIMUM RATINGS* |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Item |
|
Symbol |
Ratings |
Unit |
Remark |
|
|
Voltage on any pin relative to Vss |
|
VIN,VOUT |
-0.5 to |
7.0 |
V |
- |
|
|
|
|
|
|
|
|
|
Voltage on Vcc supply relative to Vss |
|
VCC |
-0.5 to |
7.0 |
V |
- |
|
|
|
|
|
|
|
|
|
Power Dissipation |
|
PD |
1.0 |
|
W |
- |
|
|
|
|
|
|
|
|
|
Storage temperature |
|
TSTG |
-65 to 150 |
¡É |
- |
|
|
|
|
|
|
|
|
|
|
|
|
|
0 to 70 |
¡É |
KM681000BL/L-L |
|
|
Operating Temperature |
|
TA |
|
|
|
|
|
|
-25 to |
85 |
¡É |
KM681000BLE/LE-L |
|
||
|
|
|
|
|
|
|
|
|
|
|
-40 to |
85 |
¡É |
KM681000BLI/LI-L |
|
|
|
|
|
|
|
|
|
Soldering temperature and time |
|
TSOLDER |
260¡É, 10sec (Lead Only) |
- |
- |
|
|
|
|
|
|
|
|
|
|
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
Item |
Symbol |
Min |
Typ** |
Max |
Unit |
Supply voltage |
Vcc |
4.5 |
5.0 |
5.5 |
V |
|
|
|
|
|
|
Ground |
Vss |
0 |
0 |
0 |
V |
|
|
|
|
|
|
Input high voltage |
VIH |
2.2 |
- |
Vcc+0.5 |
V |
|
|
|
|
|
|
Input low voltage |
VIL |
-0.5*** |
- |
0.8 |
V |
|
|
|
|
|
|
*1) Commercial Product : TA=0 to 70¡É, unless otherwise specified
2)Extended Product : TA=-25 to 85¡É, unless otherwise specified
3)Industrial Product : TA=-40 to 85¡É, unless otherwise specified
**TA=25¡É
***VIL(min)=-3.0V for ¡Â 50ns pulse width
CAPACITANCE* (f=1MHz, TA=25¡É)
Item |
Symbol |
Test Condition |
Min |
Max |
Unit |
Input capacitance |
CIN |
Vin=0V |
- |
6 |
pF |
|
|
|
|
|
|
Input/Output capacitance |
CIO |
Vio=0V |
- |
8 |
pF |
|
|
|
|
|
|
* Capacitance is sampled not 100% tested
Revision 0.3
April 1996
KM681000B Family |
|
|
|
|
|
|
|
|
|
|
|
CMOS SRAM |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DC AND OPERATING CHARACTERISTICS |
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Item |
Symbol |
|
|
|
|
|
Test Conditions* |
Mi |
Typ** |
Max |
Unit |
|
||||
|
Input leakage current |
ILI |
|
VIN=Vss to Vcc |
|
|
|
-1 |
- |
1 |
§Ë |
|
||||||
|
Output leakage current |
ILO |
|
|
|
1=VIH or CS2=VIL or |
|
|
|
-1 |
- |
1 |
§Ë |
|
||||
|
|
CS |
WE=VIL, VIO=Vss to Vcc |
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
Operating power supply current |
ICC |
|
|
|
1=VIL, CS2=VIH, VIN=VIH or VIL, IIO=0mA |
- |
7 |
15** |
mA |
|
|||||||
|
|
CS |
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
ICC1 |
|
Cycle time=1§Á 100% duty |
- |
- |
10*** |
mA |
|
|||||||
|
Average operating current |
|
|
CS |
1¡Â0.2V, CS2¡ÃVCC-0.2V |
|
|
|
|
|
||||||||
|
|
|
IIO=0mA |
|
1=VIL,CS2=VIH |
|
|
|
|
|
||||||||
|
|
|
|
ICC2 |
|
CS |
- |
- |
70 |
mA |
|
|||||||
|
|
|
|
|
Min cycle, 100% duty |
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
Output low voltage |
VOL |
|
IOL=2.1mA |
|
|
|
- |
- |
0.4 |
V |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
Output high voltage |
VOH |
|
IOH=-1.0mA |
|
|
|
2.4 |
- |
- |
V |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
Standby Current(TTL) |
ISB |
|
|
|
1=VIH, CS2=VIL |
|
|
|
- |
- |
3 |
mA |
|
||||
|
|
CS |
|
|
|
|||||||||||||
|
|
|
KM681000BL |
|
|
|
|
|
|
|
|
L (Low Power) |
- |
- |
100 |
§Ë |
|
|
|
|
|
KM681000BL-L |
|
|
|
1¡ÃVcc-0.2V |
|
LL (Low Low Power) |
- |
- |
20 |
§Ë |
|
||||
|
|
|
|
CS |
|
|||||||||||||
|
Standby |
|
KM681000BLE |
ISB1 |
|
CS2¡ÃVcc-0.2V or |
|
L (Low Power) |
- |
- |
100 |
§Ë |
|
|||||
|
Current (CMOS) |
|
KM681000BLE-L |
|
|
CS2¡Â0.2V |
|
LL (Low Low Power) |
- |
- |
50 |
§Ë |
|
|||||
|
|
|
|
|
|
Other input=0~Vcc |
|
|
|
|
|
|
|
|
||||
|
|
|
KM681000BLI |
|
|
|
L (Low Power) |
- |
- |
100 |
§Ë |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
KM681000BLI-L |
|
|
|
|
|
|
|
|
LL (Low Low Power) |
- |
- |
50 |
§Ë |
|
*1) Commercial Product : TA=0 to 70¡É, Vcc=5.0V¡¾10%, unless otherwise specified
2)Extended Product : TA=-25 to 85¡É, Vcc=5.0V¡¾10%, unless otherwise specified
2)Industrial Product : TA=-40 to 85¡É, Vcc=5.0V¡¾10%, unless otherwise specified
**20mA for Exteneded and Industrial Products
***15mA for Extended and Industrial Products
A.C CHARACTERISTICS
TEST CONDITIONS(1.Test Load and Test Input/Output Reference)* |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
Item |
Value |
Remark |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|||
Input pulse level |
0.8 to 2.4V |
- |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Input rising & falling time |
5ns |
- |
|
|
|
|
|
|
|
|
CL* |
|
|
|
|
|
|||
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
input and output reference voltage |
1.5V |
- |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
Output load (See right) |
CL=100pF+1TTL |
- |
|
|
|
|
|
|
|
* Including scope and jig capacitance
* See DC Operating conditions
Revision 0.3
April 1996