SAMSUNG KM416V4004C, KM416V4104C Technical data

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KM416V4004C,KM416V4104C CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Sam­sungs advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
Part Identification
Active Power Dissipation
Unit : mW
Speed 8K 4K
-45 324 468
-5 288 432
-6 252 396
Refresh Cycles Part
NO.
KM416V4004C* 8K KM416V4104C 4K
* Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Performance Range
Speed
-45 45ns 12ns 74ns 17ns
-5 50ns 15ns 84ns 20ns
-6 60ns 17ns 104ns 25ns
Refresh
cycle
Refresh time
Normal L-ver
64ms 128ms
tRAC tCAC tRC tHPC
RAS UCAS LCAS
W
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• Self-refresh capability (L-ver only)
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) packages
• +3.3V±0.3V power supply
FUNCTIONAL BLOCK DIAGRAM
Control Clocks
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
VBB Generator
Row Decoder
Memory Array
4,194,304 x 16
Cells
Column Decoder
Vcc Vss
Sense Amps & I/O
Lower
Data in
Buffer Lower
Data out
Buffer Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM416V4004C,KM416V4104C CMOS DRAM
PIN CONFIGURATION (Top Views)
•KM416V40(1)04CS
VCC DQ0 DQ1 DQ2 DQ3
VCC DQ4 DQ5 DQ6 DQ7
N.C
VCC RAS
N.C
N.C
N.C
N.C
VCC
1 2 3 4 5 6 7 8 9 10 11 12 13
W
14 15 16 17 18 19
A0
20
A1
21
A2
22
A3
23
A4
24
A5
25
(400mil TSOP(II))
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
26
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
*(N.C) : N.C for 4K Refresh Product
Pin Name Pin function
A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 15 Data In/Out VSS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+3.3V) N.C No Connection
KM416V4004C,KM416V4104C CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Units
Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V Storage Temperature Tstg -55 to +150 °C Power Dissipation PD 1 W Short Circuit Output Current IOS 50 mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
Parameter Symbol Min Typ Max Units
Supply Voltage VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.0 ­Input Low Voltage VIL
*1 : VCC+1.3V at pulse width15ns which is measured at VCC *2 : -1.3 at pulse width15ns which is measured at VSS
-0.3
*2
VCC+0.3
- 0.8 V
*1
V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Symbol Min Max Units
Input Leakage Current (Any input 0≤VIN≤VCC+0.3V, all other pins not under test=0 Volt)
Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC)
Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V
II(L) -5 5 uA
IO(L) -5 5 uA
KM416V4004C,KM416V4104C CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed
-45
ICC1 Dont care
ICC2
ICC3 Dont care
ICC4 Dont care
ICC5
ICC6 Dont care
ICC7 L Dont care 350 350 uA ICCS L Dont care 350 350 uA
Normal
L
Normal
L
-5
-6
Dont care
-45
-5
-6
-45
-5
-6
Dont care
-45
-5
-6
KM416V4004C KM416V4104C
90 80 70
1 1
90 80 70
100
90 80
500 200
130 120 110
Max
130 120 110
1 1
130 120 110
100
90 80
500 200
130 120 110
Units
mA mA mA
mA mA
mA mA mA
mA mA mA
uA uA
mA mA mA
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V W, OE=VIH, Address=Dont care, DQ=Open, TRC=31.25us ICCS : Self Refresh Current RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.
KM416V4004C,KM416V4104C CMOS DRAM
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter Symbol Min Max Units
Input capacitance [A0 ~ A12] CIN1 - 5 pF Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ15] CDQ - 7 pF
AC CHARACTERISTICS (0°CTA70°C, See note 2)
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter Symbol
Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS OE to output in Low-Z Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time
tRC tRWC tRAC tCAC tAA tCLZ tCEZ tOLZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS
-45 -5 -6
Min Max Min Max Min Max
74 84 104 ns
101 113 138 ns
45 50 60 ns 3,4,10 12 13 15 ns 3,4,5
23 25 30 ns 3,10 3 3 3 ns 3 3 13 3 13 3 13 ns 6,20 3 3 3 ns 3 1 50 1 50 1 50 ns 2
25 30 40 ns 45 10K 50 10K 60 10K ns
8 8 10 ns
35 38 40 ns
7 5K 8 10K 10 10K ns
11 33 11 37 14 45 ns 4
9 22 9 25 12 30 ns 10 5 5 5 ns 0 0 0 ns 7 7 10 ns 0 0 0 ns 13 7 7 10 ns 13
23 25 30 ns
0 0 0 ns 0 0 0 ns 8 0 0 0 ns 8 7 7 10 ns 6 7 10 ns 8 8 10 ns 7 7 10 ns 16 0 0 0 ns 9,19
Unit
s
Note
KM416V4004C,KM416V4104C CMOS DRAM
AC CHARACTERISTICS (Continued)
Parameter Symbol
Data hold time Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper Page cycle time Hyper Page read-modify-write cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay CAS precharge to W delay time Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper Page Cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh)
tDH tREF tREF tWCS tCWD tRWD tAWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tCPWD tOEZ tOEH tWTS tWTH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS
-45 -5 -6
Min Max Min Max Min Max
7 7 10 ns 9,19
64 64 64 ms
128 128 128 ms
0 0 0 ns 7 24 27 32 ns 7,15 57 64 77 ns 7 35 39 47 ns 7
5 5 5 ns 17 10 10 10 ns 18
5 5 5 ns
24 28 35 ns 3 17 20 25 ns 21 47 47 56 ns 21
6.5 7 10 ns 14 45 200K 50 200K 60 200K ns 24 30 35 ns
12 13 15 ns 3
8 10 13 ns
36 41 52 ns
3 11 3 13 3 13 ns 6
5 5 5 ns 10 10 10 ns 11 10 10 10 ns 11 10 10 10 ns 10 10 10 ns
4 5 5 ns
3 13 3 13 3 13 ns 6,20
3 13 3 13 3 13 ns 6
8 15 15 ns
5 5 5 ns
5 5 5 ns
5 5 5 ns
5 5 5 ns
100 100 100 us 22,23,24
74 90 110 ns 22,23,24
-50 -50 -50 ns 22,23,24
Units Note
KM416V4004C,KM416V4104C CMOS DRAM
TEST MODE CYCLE
Parameter Symbol
Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Hyper Page cycle time Hyper Page read-modify-write cycle time RAS pulse width (Hyper page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tHPC tHPRWC tRASP tCPA tOEA tOED tOEH
( Note 11 )
-45 -5 -6
Min Max Min Max Min Max
79 89 109 ns
110 121 145 ns
50 55 65 ns 3,4,10,12 17 18 20 ns 3,4,5,12
28 30 35 ns 3,10,12 50 10K 55 10K 65 10K ns 12 10K 13 10K 15 10K ns 18 18 20 ns 39 43 50 ns 28 30 35 ns 29 35 39 ns 7 62 72 84 ns 7 40 47 54 ns 7 22 25 30 ns 21 52 53 61 ns 21 50 200K 55 200K 65 200K ns
29 33 40 ns 3
17 18 20 ns 3 13 18 20 ns 13 18 20 ns
Units Note
KM416V4004C,KM416V4104C CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
1. proper device operation is achieved.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
2. times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. Measured with a load equivalent to 1 TTL load and 100pF.
3.
4.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Assumes that tRCDtRCD(max).
5.
6.
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-
7. teristics only. If tWCStWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.
8.
Either tRCH or tRRH must be satisfied for a read cycle.
9.
This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
10.
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11.
These specifiecations are applied in the test mode. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
12. should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13.
tASC, tCAH are referenced to the earlier CAS falling edge.
14.
tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
15.
tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
KM416V40(1)04C Truth Table
RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE
H X X X X Hi-Z Hi-Z Standby
L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z -
KM416V4004C,KM416V4104C CMOS DRAM
tCWL is specified from W falling edge to the earlier CAS rising edge.
16.
tCSR is referenced to earlier CAS falling before RAS transition low.
17.
18.
tCHR is referenced to the later CAS rising high after RAS transition low.
RAS
LCAS
UCAS
tCSR tCHR
19.
tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle.
LCAS
UCAS
tDS tDH
DQ0 ~ DQ15
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
20.
21.
tASC≥6ns, Assume tT=2.0ns, if tASC≤6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC".
22.
If tRASS100us, then RAS precharge time must use tRPS instead of tRP.
23.
For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification.
24.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
Din
KM416V4004C,KM416V4104C CMOS DRAM
WORD READ CYCLE
VIH -
RAS
VIL -
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VOH - VOL -
DQ8 ~ DQ15
VOH - VOL -
tCRP
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tRCS
OPEN
OPEN
tRAC
tRAC
tRAS
tCSH
tCSH
tCAH
COLUMN
ADDRESS
tAA
tCLZ
tCLZ
tOEA
tCAC
tCAC
tRC
tCAS
tRSHtRCD tCAS
tRAL
tOLZ
tRP
tRSHtRCD
tCRP
tCRP
tRCH
tRRH
tCEZ
tOEZ
DATA-OUT
tCEZ
tOEZ
DATA-OUT
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
LOWER BYTE READ CYCLE
NOTE : DIN = OPEN
VIH -
RAS
VIL -
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VOH - VOL -
DQ8 ~ DQ15
VOH - VOL -
tCRP
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tRCS
OPEN
tRAC
tRAS
tCSH
tCAH
COLUMN
ADDRESS
tAA
tCLZ
tOLZ
tRC
tRP
tRPC
tRSHtRCD tCAS
tRAL
tRCH
tRRH
tCEZ
tOEZ
tOEA
tCAC
DATA-OUT
OPEN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
UPPER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
RAS
UCAS
VIH - VIL -
VIH - VIL -
tCRP
tRAS
tCSH
tRSHtRCD
tCAS
tRP
tCRP
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VOH - VOL -
DQ8 ~ DQ15
VOH - VOL -
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tRCS
OPEN DATA-OUT
tRAC
tCAH
COLUMN
ADDRESS
tAA
tCLZ
tRPC
tRAL
tRCH
tRRH
tCEZ
tOEZ
tOEA
tOLZ
OPEN
tCAC
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
RAS
UCAS
LCAS
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tRAS
tCSH
tRSHtRCD
tCAS
tCSH
tRSHtRCD
tCAS
tRAL
tCAH
COLUMN
ADDRESS
tRP
tCRP
tCRP
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VIH - VIL -
DQ8 ~ DQ15
VIH - VIL -
tWCS
tDS
tDS
tWCH
tWP
tDH
DATA-IN
tDH
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
RAS
UCAS
LCAS
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tRAS
tCSH
tRSHtRCD
tCAS
tRAD
tRP
tCRP
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VIH - VIL -
DQ8 ~ DQ15
VIH - VIL -
tASR tRAH tASC
ROW
ADDRESS
tWCS
tDS
tRAL
tCAH
COLUMN
ADDRESS
tWCH
tWP
tDH
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
RAS
UCAS
LCAS
W
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tWCS
tRAS
tCSH
tCAH
COLUMN
ADDRESS
tWP
tWCH
tRC
tCAS
tRAL
tRP
tRSHtRCD
tCRP
VIH -
OE
VIL -
DQ0 ~ DQ7
VIH - VIL -
DQ8 ~ DQ15
VIH - VIL -
tDS
tDH
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
RAS
UCAS
LCAS
W
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tRAS
tCSH
tRSHtRCD
tCAS
tCSH
tRSHtRCD
tCAS
tRAL
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWP
tRP
tCRP
tCRP
VIH -
OE
VIL -
DQ0 ~ DQ7
VIH - VIL -
DQ8 ~ DQ15
VIH - VIL -
tOED
tDS
tDS
tOEH
tDH
DATA-IN
tDH
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
RAS
VIH -
tRAS
VIL -
tRP
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VIH - VIL -
tCRP
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tOED
tCSH
tCAH
COLUMN
ADDRESS
tDS
DATA-IN
tWP
tOEH
tDH
tCAS
tRAL
tCWL
tRSHtRCD
tRPC
tCRP
tRWL
DQ8 ~ DQ15
VIH - VIL -
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
RAS
UCAS
VIH - VIL -
VIH - VIL -
tCRP
tRAS
tCSH
tRSHtRCD tCAS
tRP
tCRP
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VIH - VIL -
DQ8 ~ DQ15
VIH - VIL -
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tOED
tCRP
tRAL
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWP
tOEH
tDS tDH
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
WORD READ - MODIFY - WRITE CYCLE
tRWC
RAS
tRAS
VIH - VIL -
tRP
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VI/OH - VI/OL -
DQ8 ~ DQ15
VI/OH - VI/OL -
tCRP
tCRP
tRCD
tRCD
tRAD
tASR tRAH tASC tCAH
ROW
ADDR.
COLUMN
ADDRESS
tOLZ
tCLZ
tAA
tRAC
tOLZ
tCLZ
tAA
tRAC
tOEA
tCAC
tCAC
tRWD
tAWD
tCWD
VALID DATA-OUT
VALID DATA-OUT
tRSH
tRSH
tCSH
tOED
tOEZ
tOED
tOEZ
tCAS
tCAS
tWP
tDS tDH
VALID DATA-IN
tDS
tDH
VALID DATA-IN
tRWL
tCWL
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
LOWER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
RAS
UCAS
tRAS
VIH - VIL -
tCRP
VIH - VIL -
tRP
tRPC
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VI/OH - VI/OL -
tCRP
tRAD
tASR tRAH tASC tCAH
ROW
ADDR.
COLUMN
ADDRESS
tOLZ
tCLZ
tAA
tRAC
tOEA
tCAC
tAWD
tRWD
tCSH
tCWD
VALID DATA-OUT
tRSHtRCD
tOED
tOEZ
tCAS
tDS tDH
VALID DATA-IN
tRWL
tCWL
tWP
DQ8 ~ DQ15
VOH - VOL -
OPEN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
UPPER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
RAS
tRAS
VIH - VIL -
tRP
UCAS
LCAS
W
OE
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tRAD
tASR tRAH tASC tCAH
ROW
ADDR
COLUMN
ADDRESS
tRWD
tOEA
tAWD
tCSH
tCWD
tRSHtRCD
tCAS
tRPC
tRWL
tCWL
tWP
DQ0 ~ DQ7
VOH - VOL -
DQ8 ~ DQ15
VI/OH - VI/OL -
tCLZ
tOLZ
tAA
tCAC
OPEN
VALID DATA-OUT
tOED
tOEZtRAC
tDS
VALID DATA-IN
tDH
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE WORD READ CYCLE
tRASP tRP
VIH -
RAS
VIL -
tRHCPtCSH
tHPC tHPC tHPC
tCP tCP tCP
tCAS tCAS tCAS tCAS
UCAS
VIH - VIL -
tCRP
tRCD
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VOH - VOL -
DQ8 ~ DQ15
VOH - VOL -
tCRP
tRCD
tCP tCP tCP
tCAS tCAS tCAS tCAS
tRAD
tASR tRAH tASC tCAH tASC tCAH tCAH tCAHtASC
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
tRCS
tAA
tCPA
tCAC
tOCH
tOEA
tOEA
tCAC
tDOH
VALID DATA-OUT
tOEP
tOEZ
VALID DATA-OUT
tOLZ
tCLZ
tRAC
tCAC
tDOH
VALID DATA-OUT
tOEP
tOEZ
VALID DATA-OUT
tOLZ tCLZ
tASC
COLUMN
ADDR
tCAC tCAC
tAA
tCPA
VALID DATA-OUT
VALID DATA-OUT
COLUMN
ADDRESS
tRAL
tCHO tOEP
tOEZtRAC
VALID DATA-OUT
tOEZ
VALID DATA-OUT
tCPA
tAA
tRCH
tREZ
tRRH
VALID DATA-OUT
VALID DATA-OUT
tOEZ
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE LOWER BYTE READ CYCLE
VIH -
RAS
VIL -
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VOH - VOL -
DQ8 ~ DQ15
VOH - VOL -
tRASP
¡ó
tCRP
tHPC tHPC
tRCD
tCAS tCAS tCAS tCAS
tCP tCP tCP
tRAD
tASR tRAH tASC tCAH tASC tCAH tCAH tASC tCAHtASC
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
tRCS
tAA
tCPA
tAA
tCAC
tOCH
tOEA
tOEA
tRAC
tCAC
tDOH
VALID DATA-OUT
tOEP
tOEZ
VALID DATA-OUT
tOLZ tCLZ
OPEN
COLUMN
ADDR
tCAC tCAC
tAA
tCPA
VALID DATA-OUT
tRHCPtCSH
tHPC
COLUMN
ADDRESS
tRAL
tCHO
tOEP
tOEZ
VALID DATA-OUT
tCPA
tAA
tRCH
tRP
tRPC
tREZ
tRRH
VALID DATA-OUT
tOEZ
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE UPPER BYTE READ CYCLE
tRASP tRP
VIH -
RAS
UCAS
VIL -
VIH - VIL -
tCRP
tRCD
tHPC tHPC tHPC
tCP tCP tCP
tCAS tCAS tCAS tCAS
¡ó
tRHCPtCSH
tRPC
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VOH - VOL -
tCRP
tASR
tRAD
tRAH tASC tCAH tCAH tCAH tASC tCAH
ROW
ADDR.
COLUMN
ADDRESS
tASC
COLUMN
ADDRESS
tASC
COLUMN
ADDR.
tRCS
tAA
tCAC tCAC
tCPA
tCAC
tCPA
tOCH
tOEA
tOEA
OPEN
COLUMN
ADDRESS
tRAL
tCHO
tOEP
tRPC
tREZ
tRRH
tRCH
tCPA
tAAtAA
DQ8 ~ DQ15
VOH - VOL -
tRAC
tOLZ tCLZ
tCAC
tDOH
VALID DATA-OUT
tOEP
tOEZ
VALID DATA-OUT
VALID DATA-OUT
tOEZ
VALID DATA-OUT
VALID DATA-OUT
Dont care
Undefined
tOEZ
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP tRP
RAS
VIH - VIL -
¡ó
tRHCP
UCAS
LCAS
W
OE
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tASR
tHPC
tRCD
tCAS
tHPC tHPC
tRCD
tCAS
tRAD
tCSH
tRAH tCAH tCAH tASC tCAHtASC
ROW
ADDR
tASC
COLUMN
ADDRESS
tWCS tWCH
tWP
tCP
tCAS
¡ó
tCP
tCAS
¡ó
COLUMN
ADDRESS
tWCS tWCH
tWP
tHPC
¡ó
¡ó
¡ó
tCP
tCP
¡ó
¡ó
tWCS tWCH
tRSH
tCRP
tCAS
tRSH
tCAS
tRAL
COLUMN
ADDRESS
tWP
DQ0 ~ DQ7
VIH - VIL -
DQ8 ~ DQ15
VIH - VIL -
tDS
tDH tDS tDH tDS tDH
VALID
DATA-IN
VALID
DATA-IN
¡ó
¡ó
tDH tDH tDHtDStDStDS
VALID
DATA-IN
VALID
DATA-IN
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP tRP
RAS
UCAS
VIH - VIL -
VIH - VIL -
¡ó
tCRP
tRHCP
tRPC
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VIH - VIL -
tCRP
tASR
ROW
ADDR
tRAH
tRCD
tRAD
tCAS
tCSH
tASC
tCAH
COLUMN
ADDRESS
tWCS tWCH
tWP
tDS
tDH tDS tDH tDS tDH
VALID
DATA-IN
tHPC tHPC
tCP
tCAS
¡ó
tASC
tCAH
COLUMN
ADDRESS
¡ó
¡ó
tWCS tWCH
tWP
VALID
DATA-IN
¡ó
¡ó
¡ó
¡ó
¡ó
tCP
tCAS
tRAL
tCAH
tASC
COLUMN
ADDRESS
tWCS tWCH
tWP
VALID
DATA-IN
tRSH
DQ8 ~ DQ15
VIH - VIL -
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP tRP
RAS
VIH - VIL -
¡ó
tRHCP
UCAS
LCAS
W
OE
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tASR
tHPC tHPC
tRCD
tCAS
tRAD
tCSH
tRAH tCAH tCAH tASC tCAHtASC
ROW
ADDR
tASC
tWCS
COLUMN
ADDRESS
tWCH
tWP
tCP
tCAS
COLUMN
ADDRESS
tWCS tWCH
tWP
tRSH
tCP
tCAS
¡ó
tRPC
tRAL
¡ó
¡ó
COLUMN
ADDRESS
tWCS tWCH
¡ó
¡ó
¡ó
tWP
DQ0 ~ DQ7
VIH - VIL -
DQ8 ~ DQ15
VIH - VIL -
tDS
¡ó
¡ó
tDH tDS tDH tDS tDH
VALID
DATA-IN
VALID
DATA-IN
¡ó
¡ó
VALID
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE
VIH -
RAS
VIL -
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VI/OH - VI/OL -
DQ8 ~ DQ15
VI/OH - VI/OL -
tCRP
tCRP
tASR
ROW
ADDR
tRCD
tRCD
tRAD
tASC
tRCS
tRAH
tRAC
tRAC
tCLZ
tCLZ
COL.
ADDR
tRWD
tCAC
tAA
tCAC
tAA
tRASP
tCSH
tCP
tCAS tCAS
tCP
tCAS tCAS
tCAH
tASC
COL.
ADDR
tCWL
tWP
tCWD
tAWD
tOEA
tOED
tCAC
tDH
tOEZ
tDS
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
tOED
tCAC
tDH
tOEZ
tDS
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
tRCS
tAA
tAA
tCAH
tCPWD
tOEA
tHPRWC
tCWD
tAWD
tOEZ
tOEZ
tRSH
tRAL
tRWL tCWL
tOED
VALID
DATA-OUT
tOED
VALID
DATA-OUT
tDS
tDS
tWP
tDH
tDH
tCRP
tCRP
VALID
DATA-IN
VALID
DATA-IN
tRP
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
VIH -
RAS
VIL -
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VI/OH - VI/OL -
DQ8 ~ DQ15
VI/OH - VI/OL -
tCRP
tCRP
tASR
ROW
ADDR
tRCD
tRAD
tASC
tRAH
tRAC
tCLZ
COL.
ADDR
tRCS
tRASP
tCSH
tCP
tCAS tCAS
tCAH
tASC
tCWL
tWP
tCWD
tAWD
tRWD
tOEA
tOEZ
tOED
tCAC
tDH
tDS
tCAC
tAA
tCLZ
tOLZ tOLZ
VALID
DATA-OUT
VALID
DATA-IN
OPEN
COL.
ADDR
tRCS
tOEA
tAA
tHPRWC
tCAH
tAWD
tCPWD
tCWD
tRSH
tRAL
tRWL
tCWL
tOED
tOEZ
VALID
DATA-OUT
tDS
tWP
tDH
tCRP
VALID
DATA-IN
tRP
tRPC
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
RAS
UCAS
LCAS
W
OE
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tASR
ROW
ADDR
tRCD
tRAD
tRAH
tASC
COL.
ADDR
tRCS
tRASP
tCSH
tCP
tCAS tCAS
tCAH
tASC
COL.
ADDR
tCWL
tWP
tCWD
tAWD
tRWD
tOEA
tRCS
tCAH
tCPWD
tOEA
tHPRWC
tCWD tAWD
tRSH
tRAL
tRP
tCRP
tRPC
tRWL tCWL
tWP
DQ0 ~ DQ7
VI/OH - VI/OL -
DQ8 ~ DQ15
VI/OH - VI/OL -
tOLZ
tRAC
tCLZ
tCAC
tAA
tOEZ
tOED
VALID
DATA-OUT
tDS
OPEN
tDH
VALID
DATA-IN
tOLZ
tCAC
tCLZ
tAA
tOED
tOEZ
VALID
DATA-OUT
tDS
tDH
VALID
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HYPER PAGE READ AND WRITE MIXED CYCLE
RAS
UCAS
LCAS
W
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tRAD
tASR
READ(tCAC) READ(tCPA)
tRCD
tCAS
tCAS
tRAH
tASC tCAH tCAH
ROW
ADDR
COLUMN
ADDRESS
tASC
COLUMN
ADDRESS
tRCHtRCS tRCS
tRASP
WRITE
tHPC tHPC tHPC
tCP
tCP
tCAStCAS
tCP
tASC
tHPC
tCAS
tCAH
COL.
ADDR
tHPC
tCP
tCAS
tRCH tWCH
tWCS
tWPE
tRP
READ(tAA)
tRHCP
tCP
tCAS
tHPC
tCP
tCAS
tASC tCAH
COL.
ADDR
tRAL
tRCH
VIH -
OE
VIL -
DQ0 ~ DQ7
VI/OH - VI/OL -
DQ8 ~ DQ15
VI/OH - VI/OL -
tOEA
tRAC
tOEA
tRAC
tAA
tAA
tCAC
tCAC
tWEZ
VALID DATA-OUT
tWEZ
VALID DATA-OUT
tCPA
tCLZ
tWED
tWEZ
VALID
DATA-OUT
tWEZ
VALID
DATA-OUT
tDH
tDS
VALID DATA-IN
tDH
tDS
VALID DATA-IN
tAA
VALID DATA-OUT
VALID DATA-OUT
Dont care
Undefined
tREZtAA
tREZ
KM416V4004C,KM416V4104C CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Dont care
DOUT = OPEN
VIH -
RAS
VIL -
tCRP
VIH -
UCAS
VIL -
tCRP
VIH -
LCAS
VIL -
A
tASR
VIH - VIL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Dont care
tRP
VIH -
RAS
UCAS
VIL -
VIH -
VIL -
tRPC
tCP
tCSR
tCHR
tRAS
tRC
tRAS
tRC
tRP
tRPC
tRP
tRPC
VIH -
LCAS
VIL -
DQ0 ~ DQ7
VOH ­VOL -
DQ8 ~ DQ15
VOH - VOL -
VIH -
W
VIL -
tCEZ
tCP
tCSR
tWRP
tCHR
OPEN
OPEN
tWRH
Dont care Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
VIH -
RAS
VIL -
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ7
VOH - VOL -
tCRP
tCRP
tASR tRAH
ROW
ADDRESS
tRCD
tRAD
tASC
OPEN
tRCS
tRC
tRAS
COLUMN
ADDRESS
tCLZ
tRAC
tCAH
tRAL
tAA
tRSH
tRSHtRCD
tCAC
tOEA
tOLZ
tRP
tRC
tRAS
tCHR
tCHR
tWRH
tOEZ
DATA-OUT
tRP
tCEZ
tREZ
tWEZ
DQ8 ~ DQ15
VOH - VOL -
* In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
OPEN
DATA-IN
DATA-OUT
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
RAS
UCAS
LCAS
W
OE
A
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
VIH - VIL -
tCRP
tCRP
tRAD
tASR tRAH tASC
ROW
ADDRESS
tWCS
tRC
tRAS
COLUMN
ADDRESS
tWP
tRSHtRCD
tCAH
tWCH
tRP
tWRP
tCHRtRCD tRSH
tCHR
tRC
tRAS
tWRH
tRP
DQ0 ~ DQ7
VIH - VIL -
DQ8 ~ DQ15
VIH - VIL -
tDS
tDS
tDH
DATA-IN
tDH
DATA-IN
Dont care
Undefined
KM416V4004C,KM416V4104C CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Dont care
VIH -
RAS
VIL -
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
DQ0 ~ DQ7
VOH ­VOL -
DQ8 ~ DQ15
VOH - VOL -
VIH -
W
VIL -
tCEZ
tRPC
tCP
tCP
tRP
tCSR
tCSR
tWRP
tWRH
tRASS
tRPS
tRPC
tCHS
tCHS
OPEN
OPEN
TEST MODE IN CYCLE
NOTE : OE , A = Dont care
VIH -
RAS
VIL -
VIH -
UCAS
VIL -
VIH -
LCAS
VIL -
VIL -
W
VIH -
DQ0 ~ DQ15
VOH - VOL -
tRPC
tCP
tCP
tRP
tCEZ
tCSR
tCSR
tWTS
tWTH
tCHR
tCHR
tRAS
tRC
tRP
tRPC
OPEN
Dont care Undefined
KM416V4004C,KM416V4104C CMOS DRAM
PACKAGE DIMENSION
50 TSOP(II) 400mil
0.841 (21.35) MAX
0.821 (20.85)
0.829 (21.05)
0.0315 (0.80)0.034 (0.875)
0.455 (11.56)
0.002 (0.05) MIN
0.010 (0.25)
0.018 (0.45)
0.471 (11.96)
0.047 (1.20) MAX
0.018 (0.45)
0.030 (0.75)
Units : Inches (millimeters)
0.400 (10.16)
0.004 (0.10)
0.010 (0.25)
0.010 (0.25) TYP
0~8
O
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