Samsung KM416V254DTL-7, KM416V254DTL-6, KM416V254DT-6, KM416V254DT-5, KM416V254DJL-5 Datasheet

KM416C254D, KM416V254D CMOS DRAM

This is a family of 262,144 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access
of memory cells within the same row. Power supply voltage(+5.0V or +3.3V), Access time (-5,-6 or -7), power consumption(Normal or
Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS­only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 EDO Mode
DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reli­ability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

• Part Identification

- KM416C254D/DL (5V, 512 Ref.)

- KM416V254D/DL (3.3V, 512 Ref.)

• Extended Data Out Mode operation

• 2 CAS Byte/Wrod Read/Write operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in 40-pin SOJ 400mil and 44(40)-pin
packages

• Triple +5V±10% power supply (5V product)

• Triple +3.3V±0.3V power supply (3.3V product)

Control
Clocks

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Row Decoder

Column Decoder

Lower

Data out

Buffer

RAS
UCAS
LCAS

W

Vcc
Vss

DQ0

to

DQ7

Memory Array

262,144 x16

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

256K x 16Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• Refresh Cycles
Part

NO.

VCC

Refresh

cycle

Refresh period

Normal L-ver

C254D 5V

512 8ms 128ms

V254D 3.3V

• Performance Range
Speed

tRAC tCAC tRC tHPC

Remark

-5 50ns 15ns 84ns 20ns 5V only

-6 60ns 15ns 104ns 25ns 5V/3.3V

-7 70ns 20ns 124ns 30ns 5V/3.3V

• Active Power Dissipation

Speed 3.3V(512 Ref.) 5V(512 Ref.)

-5 - 605

-6 255 495

-7 235 440

Unit : mW

Sense Amps & I/O

Upper

Data in

Buffer

Upper

Data out

Buffer

Lower

Data in

Buffer

DQ8

to

DQ15

OE

A0~A8

KM416C254D, KM416V254D CMOS DRAM

PIN CONFIGURATION (Top Views)

Pin Name Pin Function

A0 - A8 Address Inputs

DQ0 - 15 Data In/Out

VSS Ground

RAS Row Address Strobe

UCAS Upper Column Address Strobe

LCAS Lower Column Address Strobe

W Read/Write Input

OE Data Output Enable

VCC

Power(+5V)
Power(+3.3V)

N.C No Connection

•KM416C/V254DJ

•KM416C/V254DT

VCC
DQ0
DQ1
DQ2
DQ3

VCC
DQ4
DQ5
DQ6
DQ7

N.C
N.C

W

RAS

N.C

A0
A1
A2
A3

VCC

VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8

N.C
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31

30
29
28
27
26
25
24
23
22
21

VCC
DQ0
DQ1
DQ2
DQ3

VCC
DQ4
DQ5
DQ6
DQ7

N.C

N.C

W

RAS

N.C

A0
A1
A2
A3

VCC

VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8

N.C
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31

30
29
28
27
26
25
24
23
22
21

(SOJ) (TSOP-II)

KM416C254D, KM416V254D CMOS DRAM

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted

to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Parameter Symbol

Rating

Units

3.3V 5V

Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 -55 to +150 °C
Power Dissipation PD 1 1 W
Short Circuit Output Current IOS 50 50 mA

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS

Parameter Symbol

3.3V 5V
Units

Min Typ Max Min Typ Max

Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V
Ground VSS 0 0 0 0 0 0 V
Input High Voltage VIH 2.0 -

VCC+0.3

*1

2.4 -

VCC+1.0

*1

V

Input Low Voltage VIL

-0.3

*2

- 0.8

-1.0

*2

- 0.8 V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Max Parameter Symbol Min Max Units

3.3V

Input Leakage Current (Any input 0≤VIN≤VIN+0.3V,
all other input pins not under test=0 Volt)

II(L) -5 5 uA

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

IO(L) -5 5 uA

Output High Voltage Level(IOH=-2mA) VOH 2.4 - V
Output Low Voltage Level(IOL=2mA) VOL - 0.4 V

5V

Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,
all other input pins not under test=0 Volt)

II(L) -5 5 uA

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

IO(L) -5 5 uA

Output High Voltage Level(IOH=-5mA) VOH 2.4 - V
Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V

KM416C254D, KM416V254D CMOS DRAM

*Note :

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3, ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In
ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC.

DC AND OPERATING CHARACTERISTICS (Continued)

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(V IL)=0.2V, UCAS, LCAS=0.2V,
DQ=Don′t care, TRC=125us, TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A8=VCC-0.2V or 0.2V,
DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open

Symbol Power Speed

Max

Units

KM416V254D KM416C254D

ICC1 Don′t care

-5

-6

-7

­70
65

110

90
80

mA
mA
mA

ICC2 Don′t care Don′t care 1 2 mA

ICC3 Don′t care

-5

-6

-7

­70
65

110

90
80

mA
mA
mA

ICC4 Don′t care

-5

-6

-7

­60
55

90
80
70

mA
mA
mA

ICC5

Normal

L

Don′t care

0.5

100

1

150

mA

uA

ICC6 Don′t care

-5

-6

-7

­70
65

110

90
80

mA
mA

mA
ICC7 L Don′t care 200 300 uA
ICCS L Don′t care 100 200 uA

KM416C254D, KM416V254D CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A8] CIN1 - 5 pF
Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ15] CDQ - 7 pF

Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V

Note) *1 : 5V only

Parameter Symbol

-5

*1

-6 -7
Units Notes

Min Max Min Max Min Max

Random read or write cycle time

tRC

84 104 124 ns

Read-modify-write cycle time

tRWC

116 138 163 ns

Access time from RAS

tRAC

50 60 70 ns 3,4,10

Access time from CAS

tCAC

15 15 20 ns 3,4,5

Access time from column address

tAA

25 30 35 ns 3,10

CAS to output in Low-Z

tCLZ

3 3 3 ns 3

Output buffer turn-off delay from CAS

tCEZ

3 13 3 13 3 18 ns 6,12

Transition time (rise and fall)

tT

2 50 2 50 2 50 ns 2

RAS precharge time

tRP

30 40 50 ns

RAS pulse width

tRAS

50 10K 60 10K 70 10K ns

RAS hold time

tRSH

15 15 20 ns

CAS hold time

tCSH

40 50 60 ns

CAS pulse width

tCAS

8 10K 10 10K 15 10K ns

RAS to CAS delay time

tRCD

20 35 20 45 20 50 ns 4

RAS to column address delay time

tRAD

15 25 15 30 15 35 ns 10

CAS to RAS precharge time

tCRP

5 5 5 ns

Row address set-up time

tASR

0 0 0 ns

Row address hold time

tRAH

10 10 10 ns

Column address set-up time

tASC

0 0 0 ns 13

Column address hold time

tCAH

8 10 15 ns 13

Column address to RAS lead time

tRAL

25 30 35 ns

Read command set-up time

tRCS

0 0 0 ns

Read command hold time referenced to CAS

tRCH

0 0 0 ns 8

Read command hold time referenced to RAS

tRRH

0 0 0 ns 8

Write command set-up time

tWCS

0 0 0 ns 7

Write command hold time

tWCH

10 10 10 ns

Write command pulse width

tWP

10 10 10 ns

Write command to RAS lead time

tRWL

13 15 15 ns

Write command to CAS lead time

tCWL

8 10 15 ns 16

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

KM416C254D, KM416V254D CMOS DRAM

AC CHARACTERISTICS (Continued)

Note) *1 : 5V only

Parameter Symbol

-5

*1

-6 -7
Units Notes

Min Max Min Max Min Max

Data set-up time

tDS

0 0 0 ns 9,19

Data hold time

tDH

8 10 15 ns 9,19

Refresh period (Normal)

tREF

8 8 8 ms

Refresh period (L-ver)

tREF

128 128 128 ms

CAS to W delay time

tCWD

32 32 42 ns 7,15

RAS to W delay time

tRWD

67 77 92 ns 7

Column address to W delay time

tAWD

42 47 57 ns 7

CAS precharge to W delay time

tCPWD

45 52 62 ns 7

CAS set-up time (CAS -before-RAS refresh)

tCSR

5 5 5 ns 17

CAS hold time (CAS -before-RAS refresh)

tCHR

10 10 10 ns 18

RAS to CAS precharge time

tRPC

5 5 5 ns

CAS precharge time (C-B-R counter test cycle)

tCPT

20 20 25 ns

Access time from CAS precharge

tCPA

28 35 40 ns 3

Hyper Page mode cycle time

tHPC

20 25 30 ns 11

Hyper Page read-modify-write cycle time

tHPRWC

57 66 81 ns 11

CAS precharge time (Hyper Page cycle)

tCP

8 10 10 ns 14

RAS pulse width (Hyper Page cycle)

tRASP

50 100K 60 100K 70 100K ns

RAS hold time from CAS precharge

tRHCP

30 35 40 ns

OE access time

tOEA

15 15 20 ns 3

OE to data delay

tOED

13 13 18 ns

Output buffer turn off delay time from OE

tOEZ

3 13 3 13 3 18 ns 6

OE command hold time

tOEH

15 15 20 ns

Output data hold time

tDOH

5 5 5 ns

Output buffer turn off delay from RAS

tREZ

3 15 3 15 3 20 ns 6,12

Output buffer turn off delay from W

tWEZ

3 13 3 13 3 18 ns 6

W to data delay

tWED

13 13 18 ns

OE to CAS hold time

tOCH

5 5 5 ns

CAS hold time to OE

tCHO

5 5 5 ns

OE precharge time

tOEP

5 5 5 ns

W pulse width (Hyper Page Cycle)

tWPE

5 5 5 ns

RAS pulse width (C-B-R self refresh)

tRASS

100 100 100 us 20,21,22

RAS precharge time (C-B-R self refresh)

tRPS

90 110 130 ns 20,21,22

CAS hold time (C-B-R self refresh)

tCHS

-50 -50 -50 ns 20,21,22

KM416C254D, KM416V254D CMOS DRAM

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 50pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical

characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con­ditions is satisfied, the condition of the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled
write cycle and read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

tASC≥6ns, Assume tT = 2.0ns

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before RAS high going, the open circuit condition of the output is achieved by RAS going.

KM416C/V254D/DL Truth Table

RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE

H H H H H Hi-Z Hi-Z Standby

L H H H H Hi-Z Hi-Z Refresh
L L H H L DQ-OUT Hi-Z Byte Read
L H L H L Hi-Z DQ-OUT Byte Read
L L L H L DQ-OUT DQ-OUT Word Read
L L H L H DQ-IN - Byte Write
L H L L H - DQ-IN Byte Write
L L L L H DQ-IN DQ-IN Word Write
L L L H H Hi-Z Hi-Z -

7.

6.

5.

10.

9.

8.

12.

11.

3.

2.

1.

4.

NOTES

KM416C254D, KM416V254D CMOS DRAM

tASC, tCAH are referenced to the earlier CAS rising edge.
tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
tCWD is referenced to the later CAS falling edge at word red-modify-write cycle.
tCWL is specified from W falling edge to the earlier CAS rising edge.
tCSR is referenced to earlier CAS falling low before RAS transition low.
tCHR is referenced to the later CAS rising high after RAS transition low.

tCSR tCHR

RAS

LCAS

UCAS

tDS tDH

LCAS

DQ0 ~ DQ15

Din

20.

18.

17.

16.

13.

15.

14.

19.

UCAS

W

tDS, tDH are specified for the earlier CAS falling low.

f tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 512(512K) cycle of burst refresh must be executed within 8ms
before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.

21.

22.

KM416C254D, KM416V254D CMOS DRAM

tCRP

RAS

VIH -
VIL -

UCAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VOH -
VOL -

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tASR tRAH tASC

tCAH

tCRP

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

tCEZ

tRCH

Don′t care

Undefined

LCAS

VIH -
VIL -

tCRP

tCSH

tRSHtRCD
tCAS

tRAD

tRRH

VOH -
VOL -

DQ8 ~ DQ15

tCAC

tCLZ

tRAC

OPEN DATA-OUT

DATA-OUT

tCEZ

tOEZ

tOEZ

tRCS

WORD READ CYCLE

tOLZ

KM416C254D, KM416V254D CMOS DRAM

NOTE : DIN = OPEN

LOWER BYTE READ CYCLE

RAS

VIH -
VIL -

LCAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VOH -
VOL -

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tRP

tCSH

tRSHtRCD
tCAS

tRAL

tRAD

tASR tRAH tASC

tCAH

tCRP

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

DATA-OUT

tOEZ

tCEZ

tRRH

tRCH

Don′t care

Undefined

tCRP

tRPC

UCAS

VIH -
VIL -

OPEN

VOH -
VOL -

DQ8 ~ DQ15

tRCS

tOLZ

KM416C254D, KM416V254D CMOS DRAM

NOTE : DIN = OPEN

UPPER BYTE READ CYCLE

RAS

VIH -
VIL -

LCAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VOH -
VOL -

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tRAD

tASR tRAH tASC

tCAH

tCRP

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

DATA-OUT

tOEZ

tCEZ

tRRH

tRCH

Don′t care

Undefined

UCAS

VIH -
VIL -

OPEN

VOH -
VOL -

DQ8 ~ DQ15

tCRP

tRPC

tRCS

tOLZ