Samsung KM416RD8AS-SM80, KM416RD8AS-RM80 Datasheet

KM416RD8AS Direct RDRAM

™

Target

Rev. 0.9 July 1999

128Mbit RDRAM

256K x 16 bit x 2*16 Dependent Banks

Direct RDRAM

Revision 0.9

July 1999

for Consumer Package

KM416RD8AS Direct RDRAM

™

Target

Rev. 0.9 July 1999

Revision History

Version 0.9 (July 1999) -Target

- Based on the Rambus Datasheet ver. 0.9.

- For Consumer Package.

KM416RD8AS Direct RDRAM

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Target

Rev. 0.9 July 1999

KM 4 XX XX XX X X - X X XX

1 2 3 4 5 6 7 8

SAMSUNG Memory

Device

Organization Product

Speed

Package Type

Revision

Density

1. SAMSUNG Memory

2. Device

3. Organization

4. Product

6. Revision

7. Package Type

10. Speed

5. Density

9. tRAC(Row Access Time)

tRAC(Row Access Time)

8. Power & Refresh

Power & Refresh

ORDERING INFORMATION

- 4 : DRAM

- 16 : x16 bit

- 18 : x18 bit

- RD : Direct RAMBUS DRAM

- 2 : 2M

- 4 : 4M

- 8 : 8M

- 16 : 16M

- Blank : 1st Gen.

- A : 2nd Gen.

- C : u - BGA(CSP-Forward)

- D : u - BGA(CSP-Reverse)

- W : WL - CSP

- S : u-BGA For Consumer Package

- Blank : Normal Power Self Refesh(32m/8K, 3.9us)

- L : Low Power Self Refesh(32m/8K, 3.9us)

- R : Normal Power Self Refesh(32m/16K, 1.9us)

- S : Low Power Self Refesh(32m/16K, 1.9us)

- DS : for Daisy Chain Sample

- 80 : 800Mbps (400MHz)

- 70 : 711Mbps (356MHz)

- 60 : 600Mbps (300MHz)

- Blank : for Daisy Chain Sample

- M : 40ns

- K : 45ns

- G : 53.3ns

- B~D, F, J, L, N~ : Reserved

Rev. 0.9 July 1999

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KM416RD8AS Direct RDRAM

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Overview

The Rambus Direct RDRAM™ is a general purpose highperformance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.

The 128Mbit Direct Rambus DRAMs (RDRAM) ar extremely high-speed CMOS DRAMs organized as 8M words by 16 bits. The use of Rambus Signaling Level (RSL) technology permits 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at

1.25 ns per two bytes (10ns per sixteen bytes). The architecture of the Direct RDRAMs allows the highest

sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's thirty-two banks support up to four simultaneous transactions.

System oriented features for mobile, graphics and large memory systems include power management, byte masking.

Features

♦ Highest sustained bandwidth per DRAM device

- 1.6GB/s sustained data transfer rate

- Separate control and data buses for maximized efficiency

- Separate row and column control buses for easy scheduling and highest performance

- 32 banks: four transactions can take place simultaneously at full bandwidth data rates

♦ Low latency features

- Write buffer to reduce read latency

- 3 precharge mechanisms for controller flexibility

- Interleaved transactions

♦ Advanced power management:

- Multiple low power states allows flexibility in power-

consumption versus time to transition to active state

- Power-down self-refresh

♦ Organization: 1Kbyte pages and 32 banks, x 16 ♦ Uses Rambus Signaling Level (RSL) for up to 800MHz

operation

The 128Mbit Direct RDRAMs are offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and mobile applications.

Direct RDRAMs operate from a 2.5 volt supply.

Key Timing Parameters/Part Numbers

a.The “32s"designation indicates that this RDRAM core is composed of 32 banks which use a "split" bank architecture.

b.The “R"designation indicates that this RDRAM core uses Normal Power Self Refresh.

c.The “S"designation indicates that this RDRAM core uses Low Power Self Refresh.

Figure 1: Direct RDRAM Consumer CSP Package

Organization

Speed

Part Number

Binning

I/O

Freq.

MHz

rac

(Row

Access

Time) ns

256Kx16x32sa-RM80 800 40 KM416RD8AS-RbM80

-SM80 800 40 KM416RD8AS-ScM80

SEC KOREA

KM4xxRD8AC

SEC KOREA

KM416RD8AS-RK80

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Pinouts and Definitions

This table shows the pin assignments of the center-bondedforward RDRAM package from the top-side of the package

(the view looking down on the package as it is mounted on the circuit board).

Table 1 : Pin Assignment (Top View)

DQA7 DQA4 CFM CFMN RQ5 RQ3 DQB0 DQB4 DQB7

VSS DQA5 DQA2 VDDA RQ6 RQ2 DQB1 DQB5 VSS

CMD VDD VSS VSSA VDD VSS VDD VDD SIO0

4 3

SCK VSS VDD VSS VSS VDD VSS VSS SIO1

VCMOS DQA6 DQA1 VREF RQ7 RQ1 DQB2 DQB6 VCMOS

NC DQA3 DQA0 CTMN CTM RQ4 RQ0 DQB3 NC

A B C D E F G H J

Chip

Top View

Top marking example of Consumer package

For Consumer package, pin #1(ROW 1, COL A) is located at the A1 postion on the top side and the A1 position is marked by the marker “•"

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Table 2: Pin Description

Signal I/O Type # of Pins Description

SIO1,SIO0 I/O CMOS

2 Serial input/output. Pins for reading from and writing to the control

registers using a serial access protocol. Also used for power management.

CMD I CMOS

1 Command input. Pins used in conjunction with SIO0 and SIO1 for

reading from and writing to the control registers. Also used for power management.

SCK I CMOS

1 Serial clock input. Clock source used for reading from and writing to

the control registers

6 Supply voltage for the RDRAM core and interface logic.

DDa

1 Supply voltage for the RDRAM analog circuitry.

CMOS

2 Supply voltage for CMOS input/output pins. GND 9 Ground reference for RDRAM core and interface. GNDa 1 Ground reference for RDRAM analog circuitry. DQA7..DQA0 I/O RSL

8 Data byte A. Eight pins which carry a byte of read or write data

between the Channel and the RDRAM.

CFM I RSL

1 Clock from master. Interface clock used for receiving RSL signals

from the Channel. Positive polarity.

CFMN I RSL

1 Clock from master. Interface clock used for receiving RSL signals

from the Channel. Negative polarity

REF

1 Logic threshold reference voltage for RSL signals CTMN I RSL

1 Clock to master. Interface clock used for transmitting RSL signals

to the Channel. Negative polarity.

CTM I RSL

1 Clock to master. Interface clock used for transmitting RSL signals

to the Channel. Positive polarity.

RQ7..RQ5 or ROW2..ROW0

I RSL

3 Row access control. Three pins containing control and address

information for row accesses.

RQ4..RQ0 or COL4..COL0

I RSL

5 Column access control. Five pins containing control and address

information for column accesses.

DQB7.. DQB0

I/O RSL

8 Data byte B. Eight pins which carry a byte of read or write data

between the Channel and the RDRAM. NC 2 No Connection Total pin count per package 54

a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.

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Figure 2: 128 Mbit Direct RDRAM Block Diagram

Bank 31

DQA7..DQA0

1:8 Demux8:1 Mux

Write Buffer

1:8 Demux

Write Buffer

8:1 Mux

Bank 30

Bank 29

Bank 18

Bank 17

Bank 16

Bank 15

Bank 14

Bank 13

Bank 1

Bank 0

SAmp

1/2

DQB7..DQB0

1:8 Demux

Packet Decode

ROW2..ROW0 COL4..COL0CTM CTMN CFM CFMN

SCK,CMD

RCLKTCLK

Control Registers

DCCOP CBC MAMBDXXOP BXDR RROP BR

886555556

95511

AV M S

Write

Buffer

MatchMatch

Mux

Match

DEVID

512x64x128

Internal DQB Data Path

Column Decode & Mask

REFR

Row Decode

Mux

ACT

RD, WR

Power Modes

DRAM Core

Mux

XOP Decode

PREX

PREC

8 88

8 8

PRER

COLX COLC COLM

SIO0,SIO1

Sense Amp

Internal DQA Data Path

Packet Decode

ROWA

ROWR

RCLK RCLK

RCLKTCLK

RCLK TCLK

RQ7..RQ5 or

RQ4..RQ0 or

SAmp

0/1

SAmp

14/15

SAmp

13/14

SAmp

16/17

SAmp

17/18

SAmp

29/30

SAmp

30/31

SAmp

32x64

SAmp

1/2

SAmp

0/1

SAmp

14/15

SAmp

13/14

SAmp

16/17

SAmp

17/18

SAmp

29/30

SAmp

30/31

SAmp

32x64

Bank 2

•••

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KM416RD8AS Direct RDRAM

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General Description

Figure2 is a block diagram of the 128 Mbit Direct RDRAM. It consists of two major blocks: a “core” block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to

1.6GB/s.

Control Registers: The CMD, SCK, SIO0, and SIO1

pins appear in the upper center of Figure2. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM on the Channel.

Clocking: The CTM and CTMN pins (Clock-To-Master)

generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-FromMaster) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins.

DQA,DQB Pins: These 16 pins carry read (Q) and write

(D) data across the Channel. They are multiplexed/de-multiplexed from/to two 64-bit data paths (running at one-eighth the data frequency) inside the RDRAM.

Banks: The 16Mbyte core of the RDRAM is divided into

sixteen 0.5Mbyte banks, each organized as 512 rows, with each row containing 64 dualocts, and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed.

Sense Amps: The RDRAM contains two sets of 17 sense

amps. Each sense amp consists of 512 bytes of fast storage (256 for DQA and 256 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM (except for numbers 0, 15, 16, and

31). This introduces the restriction that adjacent banks may not be simultaneously accessed.

RQ Pins: These pins carry control and address informa-

tion. They are broken into two groups. RQ7..RQ5 are also called ROW2..ROW0, and are used primarily for controlling row accesses. RQ4..RQ0 are also called COL4..COL0, and are used primarily for controlling column accesses.

ROW Pins: The principle use of these three pins is to

manage the transfer of data between the banks and the sense amps of the RDRAM. These pins are de-multiplexed into a

24-bit ROWA (row-activate) or ROWR (row-operation) packet.

COL Pins: The principle use of these five pins is to

manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet.

ACT Command: An ACT (activate) command from an

ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 256 byte sense amps for DQA and two for DQB).

PRER Command: A PRER (precharge) command from

an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated.

RD Command: The RD (read) command causes one of

the 64 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel.

WR Command: The WR (write) command causes a

dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turnaround.

PREC Precharge: The NOP, RDA and WRA

commands are similar to PREC, RD and WR, except that a precharge operation is scheduled at the end of the data transfer. These commands provide a second mechanism for performing precharge.

PREX Precharge: After a RD command, or after a WR

command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge.

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Packet Format

Figure3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table4 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM.

The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a five bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the “RsvX” notation to reserve bits for future address field extension.

Figure3 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table5 describes the fields which comprise these packets.

The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit.

The 23 bit COLC packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands.

The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from a time t

RTR

earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit device address, a five bit bank address, and a five bit opcode. The COLX packet may also be used to specify some housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet.

Table 4: Field Description for ROWA Packet and ROWR Packet

Field Description

DR4T,DR4F Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit. DR3..DR0 Device address for ROWA or ROWR packet. BR4..BR0 Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM. AV Selects between ROWA packet (AV=1) and ROWR packet (AV=0). R7..R0 Row address for ROWA packet. RsvR denotes bits reserved for future row address extension. ROP10..ROP0 Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.

Table 5: Field Description for COLC Packet, COLM Packet, and COLX Packet

Field Description

S Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. DC4..DC0 Device address for COLC packet. BC4..BC0 Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0’s). C5..C0 Column address for COLC packet. RsvC denotes bits ignored by the RDRAM. COP3..COP0 Opcode field for COLC packet. Specifies read, write, precharge, and power management functions. M Selects between COLM packet (M=1) and COLX packet (M=0). MA7..MA0 Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA7..0. MB7..MB0 Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB7..0. DX4..DX0 Device address for COLX packet. BX4..BX0 Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’s). XOP4..XOP0 Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions.

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Figure 3: Packet Formats

CTM/CFM

COL4

COL3

COL2

COL1

COL0

S=1aMA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

MB6 MB3 MB0

MB5 MB2

CTM/CFM

ROW2 DR4T

DR2 BR0 BR3 RsvR R8 R5

ROW1

DR4F

DR1 BR1 BR4 RsvR R7 R4 R1

ROW0 DR3

DR0 BR2 RsvB AV=1 R6 R3 R0

ACT a0

PREX d0MSK (b1)

PRER c0

WR b1

CTM/CFM

COL4

DC4 S=1 RsvC

COL3

DC3

C5 C3

COL2

DC2

COP1 RsvB BC2 C2

DC1

COP0 BC4 BC1 C1

DC0

COP2 COP3 BC3 BC0 C0

COL1

COL0

CTM/CFM

ROW2

ROW1

ROW0

CTM/CFM

COL4

COL3

COL2

COL1

COL0

ROP2

DR4T

DR2 BR0 BR3 ROP10 ROP8 ROP5

DR4F

DR1 BR1 BR4 ROP9ROP7ROP4 ROP1

DR3

DR0 BR2 RsvB AV=0 ROP6 ROP3ROP0

S=1bDX4 XOP4 RsvB BX1

M=0 DX3 XOP3 BX4 BX0

DX2 XOP2 BX3

DX1 XOP1 BX2

DX0 XOP0

ROWA Packet

COLM Packet

COLC Packet

COLX Packet

ROWR Packet

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

PACKET

The COLM is associated with a

previous COLC, and is aligned with the present COLC, indicated by the Start bit (S=1) position.

The COLX is aligned with the present COLC, indicated by the Start bit (S=1) position.

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Field Encoding Summary

Table6 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a

broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed.

Table7 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps.

An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the

row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command.

The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in “ Power state management ” on page 38. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in “Current and Temperature Control” on page 43.

Table 6: Device Field Encodings for ROWA Packet and ROWR Packet

DR4T DR4F Device Selection Device Match signal (DM)

1 1 All devices (broadcast) DM is set to 1 0 1 One device selected DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0 1 0 One device selected DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0 0 0 No packet present DM is set to 0

Table 7: ROWA Packet and ROWR Packet Field Encodings

DMaAV

ROP10..ROP0 Field

Name

Command Description

10 9 8 7 6 5 4 3 2:0

0 - - - - - - - - - --- - No operation. 1 1 Row address ACT Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb. 1 0 1 1 0 0 0 xcx x 000 PRER Precharge bank BR4..BR0 of this device. 1 0 0 0 0 1 1 0 0 x 000 REFA Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device.

Increment REFR if BR4..BR0 = 1111 (see Figure50). 1 0 1 0 1 0 1 0 0 x 000 REFP Precharge bank BR4..BR0 of this device after REFA (see Figure50). 1 0 x x 0 0 0 0 1 x 000 PDNR Move this device into the powerdown (PDN) power state (see Figure47). 1 0 x x 0 0 0 1 0 x 000 NAPR Move this device into the nap (NAP) power state (see Figure47). 1 0 x x 0 0 0 1 1 x 000 NAPRC Move this device into the nap (NAP) power state conditionally 1 0 x x x x x x x 0 000 ATTNbMove this device into the attention (ATTN) power state (see Figure45). 1 0 x x x x x x x 1 000 RLXR Move this device into the standby (STBY) power state (see Figure46). 1 0 0 0 0 0 0 0 0 x 001 TCAL Temperature calibrate this device (see Figure52). 1 0 0 0 0 0 0 0 0 x 010 TCEN Temperature calibrate/enable this device (see Figure52). 1 0 0 0 0 0 0 0 0 0 000 NOROP No operation.

a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table6. b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1). c. An “ x ” entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).

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Table8 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure17 for a more detailed description.

The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See “ Power State Management ” on page 38.

Table9 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be

specified without consuming control bandwidth on the ROW pins. It is also used for the CAL(calibrate) and SAM (sample) current control commands (see “Current and Temperature Control” on page 43), and for the RLXX power mode command (see “Power State Management” on page

38).

Table 8: COLC Packet Field Encodings

S DC4.. DC0

(select device)

COP3..0 Name Command Description

0 ---- ----- - No operation. 1 /= (DEVID4 ..0) ----- - Retire write buffer of this device. 1 == (DEVID4 ..0) x000bNOCOP Retire write buffer of this device. 1 == (DEVID4 ..0) x001 WR Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer. 1 == (DEVID4 ..0) x010 RSRV Reserved, no operation. 1 == (DEVID4 ..0) x011 RD Read column C5..C0 of bank BC4..BC0 of this device. 1 == (DEVID4 ..0) x100 PREC Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure14). 1 == (DEVID4 ..0) x101 WRA Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired. 1 == (DEVID4 ..0) x110 RSRV Reserved, no operation. 1 == (DEVID4 ..0) x111 RDA Same as RD, but precharge bank BC4..BC0 afterward. 1 == (DEVID4 ..0) 1xxx RLXC Move this device into the standby (STBY) power state (see Figure46).

a. “ /= ” means not equal, “ == ” means equal. b. An “ x ” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).

Table 9: COLM Packet and COLX Packet Field Encodings

DX4 .. DX0 (selects device)

XOP4..0 Name Command Description

1 ---- - MSK MB/MA bytemasks used by WR/WRA. 0 /= (DEVID4 ..0) - - No operation. 0 == (DEVID4 ..0) 00000 NOXOP No operation. 0 == (DEVID4 ..0) 1xxx0

PREX Precharge bank BX4..BX0 of this device (see Figure14). 0 == (DEVID4 ..0) x10x0 CAL Calibrate (drive) IOL current for this device (see Figure51). 0 == (DEVID4 ..0) x11x0 CAL/SAM Calibrate (drive) and Sample ( update) IOL current for this device (see Figure51). 0 == (DEVID4 ..0) xxx10 RLXX Move this device into the standby (STBY) power state (see Figure46). 0 == (DEVID4 ..0) xxxx1 RSRV Reserved, no operation.

a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).

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DQ Packet Timing

Figure4 shows the timing relationship of COLC packets with D and Q data packets. This document uses a specific convention for measuring time intervals between packets: all packets on the ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as a reference point, and all packets on the DQA/DQB pins (D and Q) use the leading edge of the packet as a reference point.

An RD or RDA command will transmit a dualoct of read data Q a time t

CAC

later. This time includes one to five cycles of round-trip propagation delay on the Channel. The t

CAC

parameter may be programmed to a one of a range of

values ( 8, 9, 10, 11, or 12 t

CYCLE

). The value chosen depends upon the number of RDRAM devices on the Channel and the RDRAM timing bin. See Figure39 for more information.

A WR or WRA command will receive a dualoct of write data D a time t

CWD

later. This time does not need to include the round-trip propagation time of the Channel since the COLC and D packets are traveling in the same direction.

When a Q packet follows a D packet (shown in the left half of the figure), a gap (t

CAC

-t

CWD

) will automatically appear

between them because the t

CWD

value is always less than the

CAC

value. There will be no gap between the two COLC packets with the WR and RD commands which schedule the D and Q packets.

When a D packet follows a Q packet (shown in the right half of the figure), no gap is needed between them because the t

CWD

value is less than the t

CAC

value. However, , a gap of

CAC

-t

CWD

or greater must be inserted between the COLC packets with the RD WR commands by the controller so the Q and D packets do not overlap.

COLM Packet to D Packet Mapping

Figure5 shows a write operation initiated by a WR command in a COLC packet. If a subset of the 16 bytes of write data are to be written, then a COLM packet is transmitted on the COL pins a time t

RTR

after the COLC packet containing the WR command. The M bit of the COLM packet is set to indicate that it contains the MA and MB mask fields. Note that this COLM packet is aligned with the COLC packet which causes the write buffer to be retired. See Figure17 for more details.

If all 16 bytes of the D data packet are to be written, then no further control information is required. The packet slot that would have been used by the COLM packet (t

RTR

after the COLC packet) is available to be used as an COLX packet. This could be used for a PREX precharge command or for a

housekeeping command (this case is not shown). The M bit is not asserted in an COLX packet and causes all 16 bytes of the previous WR to be written unconditionally. Note that a RD command will never need a COLM packet, and will always be able to use the COLX packet option (a read operation has no need for the byte-write-enable control bits).

Figure5 also shows the mapping between the MA and MB fields of the COLM packet and bytes of the D packet on the DQA and DQB pins. Each mask bit controls whether a byte of data is written (=1) or not written (=0).

Figure 4: Read (Q) and Write (D) Data Packet - Timing for t

CAC

= 8, 9, 10, 11, or 12 t

CYCLE

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

RD b1

Q (a1)

WR a1

D (a1)

CWD

RD c1

Q (a1)

CAC

-t

CWD

This gap on the DQA/DQB pins appears automatically This gap on the COL pins must be inserted by the controller

CAC

WR d1

D (d1)

CAC-tCWD

CWD

WR d1

Q (c1)

• • •

WR d1

• • •

D (d1)Q (c1)

• • •

Q (a1)

Q (b1)

WR d1

D (d1)

Q (c1)

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Figure 5: Mapping Between COLM Packet and D Packet for WR Command

CTM/CFM

COL4

COL3

COL2

COL1

COL0

MA7 MA5 MA3 MA1

M=1 MA6 MA4 MA2 MA0

MB7 MB4 MB1

MB6 MB3 MB0

MB5 MB2

CTM/CFM

DQA7..0 DQB7..0

COL4

..COL0

ROW2

..ROW0

MSK (a1)

retire (a1)WR a1

D (a1)

ACT b0ACT a0

Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a3 = {Da,Ba}

RTR

CTM/CFM

DQB7

DQB6

DQB1

DQB0

DB63DB7 DB15 DB23 DB31 DB39 DB47 DB55

DB6 DB14 DB22 DB30 DB38 DB46 DB54 DB62

DB1

DB9 DB17 DB25 DB33 DB41 DB49 DB57

DB0

DB8 DB16 DB24 DB32 DB40 DB48 DB56

COLM Packet

PRER a2

DQA7

DQA6

DQA1

DQA0

D Packet

MB0

DA63DA7 DA15 DA23 DA31 DA49 DA47 DA55

DA6 DA14 DA22 DA30 DA38 DA46 DA54 DA62

DA1

DA9 DA17 DA25 DA33 DA41 DA49 DA56

DA0

DA8 DA16 DA24 DA32 DA40 DA48 DA56

MA0

MB1

MA1

MB2

MA2

MB3

MA3

MB4

MA4

MB5

MA5

MB6

MA6

MB7

MA7

•••

CWD

Each bit of the MB7..MB0 field controls writing (=1) or no writing (=0) of the indicated DB bits when

the M bit of the COLM packet is one.

Each bit of the MA7..MA0 field controls writing (=1) or no writing (=0) of the indicated DA bits when

the M bit of the COLM packet is one.

When M=1, the MA and MB

fields control writing of

individual data bytes.

When M=0, all data bytes are

written unconditionally.

•••

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ROW-to-ROW Packet Interaction

Figure6 shows two packets on the ROW pins separated by an interval t

RRDELAY

which depends upon the packet

contents. No other ROW packets are sent to banks {Ba,Ba+1,Ba-1} between packet “a” and packet “b” unless noted otherwise. Table10 summarizes the t

RRDELAY

values

for all possible cases.

Cases RR1 through RR4 show two successive ACT commands. In case RR1, there is no restriction since the ACT commands are to different devices. In case RR2, the tRR restriction applies to the same device with non-adjacent banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1 is inserted, t

RRDELAY

is tRC (t

RAS

to the PRER command,

and tRP to the next ACT). Cases RR5 through RR8 show an ACT command followed

by a PRER command. In cases RR5 and RR6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. In cases RR7 and RR8, the t

RAS

restriction means the activated bank must wait

before it can be precharged. Cases RR9 through RR12 show a PRER command followed

by an ACT command. In cases RR9 and RR10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. RR10a and RR10b depend upon whether a bracketed bank (Ba+-1) is precharged or activated. In cases RR11 and RR12, the same and adjacent banks must all wait tRP for the sense amp and bank to precharge before being activated.

Figure 6: ROW-to-ROW Packet Interaction- Timing

CTM/CFM

DQA7..0 DQB7..0

COL4

..COL0

ROW2

..ROW0

17T18T19

Transaction a: ROPa

Transaction b: ROPb

a0 = {Da,Ba,Ra} b0= {Db,Bb,Rb}

RRDELAY

ROPa a0 ROPb b0

Table 10: ROW-to-ROW Packet Interaction - Rules

Case # ROPa Da Ba Ra ROPb Db Bb Rb t

RRDELAY

Example

RR1 ACT Da Ba Ra ACT /= Da xxxx x..x t

PACKET

Figure11

RR2 ACT Da Ba Ra ACT == Da /= {Ba,Ba+1,Ba-1} x..x t

Figure11

RR3 ACT Da Ba Ra ACT == Da == {Ba+1,Ba-1} x..x t

- illegal unless PRER to Ba/Ba+1/Ba-1 Figure10

RR4 ACT Da Ba Ra ACT == Da == {Ba} x..x t

- illegal unless PRER to Ba/Ba+1/Ba-1 Figure10

RR5 ACT Da Ba Ra PRER /= Da xxxx x..x t

PACKET

Figure11

RR6 ACT Da Ba Ra PRER == Da /= {Ba,Ba+1,Ba-1} x..x t

PACKET

Figure11

RR7 ACT Da Ba Ra PRER == Da == { Ba+1,Ba-1} x..x t

RAS

Figure10

RR8 ACT Da Ba Ra PRER == Da == {Ba} x..x t

RAS

Figure15

RR9 PRER Da Ba Ra ACT /= Da xxxx x..x t

PACKET

Figure12

RR10 PRER Da Ba Ra ACT == Da /= {Ba,Ba+-1,Ba+-2} x..x t

PACKET

Figure12

RR10a PRER Da Ba Ra ACT == Da == {Ba+2} x..x t

PACKET/tRP

if Ba+1 is precharged/activated.

RR10b PRER Da Ba Ra ACT == Da == {Ba-2} x..x t

PACKET/tRP

if Ba-1 is precharged/activated.

RR11 PRER Da Ba Ra ACT == Da == {Ba+1,Ba-1} x..x t

Figure10

RR12 PRER Da Ba Ra ACT == Da == {Ba} x..x t

Figure10

RR13 PRER Da Ba Ra PRER /= Da xxxx x..x t

PACKET

Figure12

RR14 PRER Da Ba Ra PRER == Da /= {Ba,Ba+1,Ba-1} x..x t

Figure12

RR15 PRER Da Ba Ra PRER == Da == {Ba+1,Ba-1} x..x t

Figure12

RR16 PRER Da Ba Ra PRER == Da == Ba x..x t

Figure12

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ROW-to-ROW Interaction - continued

Cases RR13 through RR16 summarize the combinations of two successive PRER commands. In case RR13 there is no restriction since two devices are addressed. In RR14, t

applies, since the same device is addressed. In RR15 and RR16, the same bank or an adjacent bank may be given repeated PRER commands with only the tPP restriction.

Two adjacent banks can’t be activate simultaneously. A precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). If bank Ba is activate and a PRER is directed to Ba, then bank Ba will be precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If bank Ba+1 is activate and a PRER is directed to Ba, then bank Ba+1 will be precharged along with sense amps Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a PRER is directed to Ba, then bank Ba-1 will be precharged along with sense amps Ba/Ba-1 and Ba-1/Ba-2.

A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, NAPRC, PDNR, RLXR, ATTN, TCAL, and TCEN commands are discussed in later sections (see Table7 for cross-ref).

ROW-to-COL Packet Interaction

Figure7 shows two packets on the ROW and COL pins. They must be separated by an interval t

RCDELAY

which depends upon the packet contents. Table11 summarizes the t

RCDELAY

values for all possible cases. Note that if the COL packet is earlier than the ROW packet, it is considered a COL-to-ROW packet interaction.

Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command. Figure15 and Figure16 show examples of RC5 - an activation followed by a read or write. RC4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). In cases RC1, RC2, and RC3, there is no interaction of the ROW and COL packets.

Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There is either no interaction (RC6 through RC9) or an illegal situation with a read or write of a precharged bank (RC9).

The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in a COLC packet or a PREX command in a COLX packet. The constraints of these precharge operations may be converted to equivalent PRER command constraints using the rules summarized in Figure14.

Figure 7: ROW-to-COL Packet Interaction- Timing

CTM/CFM

DQA7..0 DQB7..0

COL4

..COL0

ROW2

..ROW0

17T18T19

Transaction a: ROPa Transaction b: COPb

a0 = {Da,Ba,Ra}

b1= {Db,Bb,Cb1}

RCDELAY

ROPa a0

COPb b1

Table 11: ROW-to-COL Packet Interaction - Rules

Case # ROPa Da Ba Ra COPb Db Bb Cb1 t

RCDELAY

Example

RC1 ACT Da Ba Ra NOCOP,RD,retire /= Da xxxx x..x 0 RC2 ACT Da Ba Ra NOCOP == Da xxxx x..x 0 RC3 ACT Da Ba Ra RD,retire == Da /= {Ba,Ba+1,Ba-1} x..x 0 RC4 ACT Da Ba Ra RD,retire == Da == {Ba+1,Ba-1} x..x Illegal RC5 ACT Da Ba Ra RD,retire == Da == Ba x..x t

RCD

Figure15 RC6 PRER Da Ba Ra NOCOP,RD,retire /= Da xxxx x..x 0 RC7 PRER Da Ba Ra NOCOP == Da xxxx x..x 0 RC8 PRER Da Ba Ra RD,retire == Da /= {Ba,Ba+1,Ba-1} x..x 0 RC9 PRER Da Ba Ra RD,retire == Da == {Ba+1,Ba-1} x..x Illegal

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COL-to-COL Packet Interaction

Figure8 shows three arbitrary packets on the COL pins. Packets “b” and “c” must be separated by an interval t

CCDELAY

which depends upon the command and address values in all three packets. Table12 summarizes the t

CCDELAY

values for all possible cases. Cases CC1 through CC5 summarize the rules for every situ-

ation other than the case when COPb is a WR command and COPc is a RD command. In CC3, when a RD command is followed by a WR command, a gap of t

CAC

-t

CWD

must be inserted between the two COL packets. See Figure4 for more explanation of why this gap is needed. For cases CC1,

CC2, CC4, and CC5, there is no restriction (t

CCDELAY

tCC). In cases CC6 through CC10, COPb is a WR command and

COPc is a RD command. The t

CCDELAY

value needed between these two packets depends upon the command and address in the packet with COPa. In particular, in case CC6 when there is WR-WR-RD command sequence directed to the same device, a gap will be needed between the packets with COPb and COPc. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Figure18 (right) provides a more detailed explanation of this case.

In case CC10, there is a RD-WR-RD sequence directed to the same device. If a prior write to the same device is unretired when COPa is issued, then a gap will be needed between the packets with COPb and COPc as in case CC6. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place.

Cases CC7, CC8, and CC9 have no restriction (t

CCDELAY

tCC). For the purposes of analyzing COL-to-ROW interactions,

the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation PREC to take place. This precharge may be converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure14.

Figure 8: COL-to-COL Packet Interaction- Timing

CTM/CFM

DQA7..0 DQB7..0

COL4

..COL0

ROW2

..ROW0

17T18T19

COPa a1

Transaction a: COPa

COPc c1

Transaction b: COPb Transaction c: COPc

a1 = {Da,Ba,Ca1} b1 = {Db,Bb,Cb1}

c1 = {Dc,Bc,Cc1}

CCDELAY

COPb b1

Table 12: COL-to-COL Packet Interaction - Rules

Case # COPa Da Ba Ca1 COPb Db Bb Cb1 COPc Dc Bc Cc1 t

CCDELAY

Example

CC1 xxxx xxxxx x..x x..x NOCOP Db Bb Cb1 xxxx xxxxx x..x x..x t

CC2 xxxx xxxxx x..x x..x RD,WR Db Bb Cb1 NOCOP xxxxx x..x x..x t

CC3 xxxx xxxxx x..x x..x RD Db Bb Cb1 WR xxxxx x..x x..x tCC+t

CAC

-t

CWD

Figure4

CC4 xxxx xxxxx x..x x..x RD Db Bb Cb1 RD xxxxx x..x x..x t

Figure15

CC5 xxxx xxxxx x..x x..x WR Db Bb Cb1 WR xxxxx x..x x..x t

Figure16

CC6 WR == Db x x..x WR Db Bb Cb1 RD == Db x..x x..x t

RTR

Figure18

CC7 WR == Db x x..x WR Db Bb Cb1 RD /= Db x..x x..x t

CC8 WR /= Db x x..x WR Db Bb Cb1 RD == Db x..x x..x t

CC9 NOCOP == Db x x..x WR Db Bb Cb1 RD == Db x..x x..x t

CC10 RD == Db x x..x WR Db Bb Cb1 RD == Db x..x x..x tCC

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COL-to-ROW Packet Interaction

Figure9 shows arbitrary packets on the COL and ROW pins. They must be separated by an interval t

CRDELAY

which depends upon the command and address values in the packets. Table13 summarizes the t

CRDELAY

value for all

possible cases. Cases CR1, CR2, CR3, and CR9 show no interaction

between the COL and ROW packets, either because one of the commands is a NOP or because the packets are directed to different devices or to non-adjacent banks.

Case CR4 is illegal because an already-activated bank is to be re-activated without being precharged Case CR5 is illegal because an adjacent bank can’t be activated or precharged until bank Ba is precharged first.

In case CR6, the COLC packet contains a RD command, and the ROW packet contains a PRER command for the same bank. The t

RDP

parameter specifies the required spacing.

Likewise, in case CR7, the COLC packet causes an automatic retire to take place, and the ROW packet contains a PRER command for the same bank. The t

RTP

parameter

specifies the required spacing. Case CR8 is labeled “Hazardous” because a WR command

should always be followed by an automatic retire before a precharge is scheduled. Figure19 shows an example of what can happen when the retire is not able to happen before the precharge.

For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation to take place. This precharge may converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure14.

A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, PDNR, and RLXR commands are discussed in a later section.

Figure 9: COL-to-ROW Packet Interaction- Timing

CTM/CFM

DQA7..0 DQB7..0

COL4

..COL0

ROW2

..ROW0

T17T18T

Transaction a: COPa Transaction b: ROPb

a1= {Da,Ba,Ca1}

b0= {Db,Bb,Rb}

CRDELAY

ROPb b0

COPa a1

Table 13: COL-to-ROW Packet Interaction - Rules

Case # COPa Da Ba Ca1 ROPb

Bb Rb t

CRDELAY

Example

CR1 NOCOP Da Ba Ca1 x..x xxxxx xxxx x..x 0 CR2 RD/WR Da Ba Ca1 x..x /= Da xxxx x..x 0 CR3 RD/WR Da Ba Ca1 x..x == Da /= {Ba,Ba+1,Ba-1} x..x 0 CR4 RD/WR Da Ba Ca1 ACT == Da == {Ba} x..x Illegal CR5 RD/WR Da Ba Ca1 ACT == Da == {Ba+1,Ba-1} x..x Illegal CR6 RD Da Ba Ca1 PRER == Da == {Ba,Ba+1,Ba-1} x..x t

RDP

Figure15

CR7 retire

Da Ba Ca1 PRER == Da == {Ba,Ba+1,Ba-1} x..x t

RTP

Figure16

CR8 WR

Da Ba Ca1 PRER == Da == {Ba,Ba+1,Ba-1} x..x 0 Figure19

CR9 xxxx Da Ba Ca1 NOROP xxxxx xxxx x..x 0

a. This is any command which permits the write buffer of device Da to retire (see Table8). “Ba” is the bank address in the write buffer. b. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure19.

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ROW-to-ROW Examples

Figure10 shows examples of some of the ROW-to-ROW packet spacings from Table10. A complete sequence of activate and precharge commands is directed to a bank. The RR8 and RR12 rules apply to this sequence. In addition to satisfying the t

RAS

and tRP timing parameters, the separation

between ACT commands to the same bank must also satisfy the tRC timing parameter (RR4).

When a bank is activated, it is necessary for adjacent banks to remain precharged. As a result, the adjacent banks will also satisfy parallel timing constraints; in the example, the RR11 and RR3 rules are analogous to the RR12 and RR4 rules.

Figure11 shows examples of the ACT-to-ACT (RR1, RR2) and ACT-to-PRER (RR5, RR6) command spacings from Table10. In general, the commands in ROW packets may be spaced an interval t

PACKET

apart unless they are directed to

the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device.

Figure 10: Row Packet Example

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

ACT a0 PRER a1

RAS

a0 = {Da,Ba,Ra}

a1 = {Da,Ba+1}

b0 = {Da,Ba+1,Rb}

Same Device Adjacent Bank RR7

Same Device Adjacent Bank RR11

ACT b0

b0 = {Da,Ba,Rb}Same Device Same Bank RR12

b0 = {Da,Ba+1,Rb}Same Device Adjacent Bank RR3

b0 = {Da,Ba,Rb}Same Device Same Bank RR4

Figure 11: Row Packet Example

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

ACT a0 PRER b0

PACKET

ACT c0

a0 = {Da,Ba,Ra}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device Any Bank

Same Device Non-adjacent Bank

RR1 RR2

ACT a0ACT a0ACT b0 PRER c0

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device Any Bank

Same Device Non-adjacent Bank

RR5 RR6

ACT a0

PACKET

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Figure12 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command spacings from Table10. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown, but are similar to RR14. In general, the commands in ROW packets may be

spaced an interval t

PACKET

apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device.

Row and Column Cycle Description

Activate: A row cycle begins with the activate (ACT) operation. The activation process is destructive; the act of sensing the value of a bit in a bank’s storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value.

Restore: Because the activation process is destructive, a hidden operation called restore is automatically performed. The restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank.

Read/Write: While the restore operation takes place, the sense amp may be read (RD) and written (WR) using column operations. If new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical.

Precharge: When both the restore operation and the column operations are completed, the sense amp and bank are precharged (PRE). This leaves them in the proper state to begin another activate operation.

Intervals: The activate operation requires the interval t

RCD,MIN

to complete. The hidden restore operation requires

the interval t

RAS,MIN

- t

RCD,MIN

to complete. Column read

and write operations are also performed during the t

RAS,MIN

- t

RCD,MIN

interval (if more than about four column operations are performed, this interval must be increased). The precharge operation requires the interval t

RP,MIN

complete. Adjacent Banks: An RDRAM with an “s” designation

(256Kx32sx16) indicates it contains “split banks”. This means the sense amps are shared between two adjacent banks. The only exception is that sense amp 0 and sense amp 0, 15, 16, and 31are not shared. When a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. These two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations.

For example (referring to the block diagram of Figure2), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 512 bytes loaded into each sense amp from the 1Kbyte row - 256 bytes to the DQA side and 256 bytes to the DQB side). While this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing.

Figure 12: Row Packet Examples

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

PRER a0 ACT b0

PACKET

PRER c0

a0 = {Da,Ba,Ra}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device Any Bank

Same Device Non-adjacent Bank

RR13 RR14

PRER a0PRER a0PRER b0 ACT c0

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device Any Bank

Same Device Non-adjacent Bank

RR9

RR10

PRER a0

c0 = {Da,Ba+1Rc}Same Device Same Bank RR16

c0 = {Da,Ba,Rc}Same Device Adjacent Bank RR15

PACKET

+ 44 hidden pages