SAMSUNG KM416C4000C, KM416C4100C Technical data

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KM416C4000C, KM416C4100C CMOS DRAM

4M x 16bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -5 or -6) are optional features of this family. All of this family
have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 Fast Page Mode DRAM family is fabri­cated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

• Part Identification

- KM416C4000C(5.0V, 8K Ref.)

- KM416C4100C(5.0V, 4K Ref.)

• Active Power Dissipation

Speed 8K 4K

-5 495 660

-6 440 605

• Refresh Cycles
Part

NO.

KM416C4000C* 8K
KM416C4100C 4K

* Access mode & RAS only refresh mode
: 8K cycle/64ms

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms

• Performance Range

Speed

tRAC tCAC tRC tPC

-5 50ns 13ns 90ns 35ns

-6 60ns 15ns 110ns 40ns

Refresh

cycle

Refresh time

Normal

64ms

Unit : mW

RAS
UCAS
LCAS

W

A0~A12

(A0~A11)*1

A0~A8

(A0~A9)*1

• Fast Page Mode operation

• 2CAS Byte/Word Read/Write operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Fast parallel test mode capability

• TTL(5.0V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic TSOP(II) package

• +5.0V±10% power supply

FUNCTIONAL BLOCK DIAGRAM

Control
Clocks

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Note) *1 : 4K Refresh

VBB Generator

Row Decoder

Memory Array

4,194,304 x 16

Cells

Column Decoder

Vcc
Vss

Sense Amps & I/O

Lower

Data in

Buffer
Lower

Data out

Buffer
Upper

Data in

Buffer

Upper

Data out

Buffer

DQ0

to

DQ7

OE

DQ8

to

DQ15

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

KM416C4000C, KM416C4100C CMOS DRAM

PIN CONFIGURATION (Top Views)

• KM416C40(1)00CS

VCC
DQ0
DQ1
DQ2
DQ3

VCC
DQ4
DQ5
DQ6
DQ7

N.C

VCC
RAS

N.C

N.C

N.C

N.C

VCC

*(N.C) : N.C for 4K Refresh Product

1
2
3
4
5
6
7
8
9
10
11
12
13

W

14
15
16
17
18
19

A0

20

A1

21

A2

22

A3

23

A4

24

A5

25

(400mil TSOP(II))

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

27
26

VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
VSS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS

Pin Name Pin function

A0 - A12 Address Inputs(8K Product)
A0 - A11 Address Inputs(4K Product)
DQ0 - 15 Data In/Out
VSS Ground
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC Power(+5.0V)
N.C No Connection

KM416C4000C, KM416C4100C CMOS DRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Units

Voltage on any pin relative to VSS VIN,VOUT -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 °C
Power Dissipation PD 1 W
Short Circuit Output Current IOS Address 50 mA

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

Parameter Symbol Min Typ Max Units

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.6 ­Input Low Voltage VIL -1.0 - 0.7 V

*2

VCC+1.0

*1

V

*1 : VCC+2.0V at pulse width≤20ns which is measured at VCC
*2 : -2.0 at pulse width≤20ns which is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter Symbol Min Max Units

Input Leakage Current (Any input 0≤VIN≤VCC+0.5V,
all other pins not under test=0 Volt)

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

Output High Voltage Level(IOH=-5mA) VOH 2.4 - V
Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V

II(L) -5 5 uA

IO(L) -5 5 uA

KM416C4000C, KM416C4100C CMOS DRAM

DC AND OPERATING CHARACTERISTICS (Continued)

Symbol Power Speed

ICC1 Don′t care

ICC2 Normal Don′t care 2 2 mA

ICC3 Don′t care

ICC4 Don′t care

ICC5 Normal Don′t care 1 1 mA

ICC6 Don′t care

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)

-5

-6

-5

-6

-5

-6

-5

-6

KM416C4000C KM416C4100C

90
80

90
80

60
50

120
110

Max

120
110

120
110

70
60

120
110

Units

mA
mA

mA
mA

mA
mA

mA
mA

*Note :

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.

KM416C4000C, KM416C4100C CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A12] CIN1 - 5 pF
Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ15] CDQ - 7 pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition : VCC=5.0V±10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.4/0.6V

Parameter Symbol

Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time

tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS
tDH

-5 -6

Min Max Min Max

90 110

133 153 ns

50 60 ns 3,4,10
13 15 ns 3,4,5

25 30 ns 3,10
0 0 ns 3
0 13 0 13 ns 6
1 50 1 50 ns 2

30 40 ns
50 10K 60 10K ns
13 15 ns
50 60 ns
13 10K 15 10K ns
20 37 20 45 ns 4
15 25 15 30 ns 10

5 5 ns
0 0 ns

10 10 ns

0 0 ns 13

10 10 ns 13
25 30 ns

0 0 ns
0 0 ns 8
0 0 ns 8

10 10 ns
10 10 ns
15 15 ns
13 15 ns 16

0 0 ns 9,19

10 10 ns 9,19

Units Note

ns

KM416C4000C, KM416C4100C CMOS DRAM

AC CHARACTERISTICS (Continued)

Parameter Symbol

Refresh period (4K, Normal)
Refresh period (8K, Normal)
Write command set-up time
CAS to W delay time
RAS to W delay time
Column address to W delay time
CAS precharge W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Fast Page mode cycle time
Fast Page mode read-modify-write cycle time
CAS precharge time (Fast Page cycle)
RAS pulse width (Fast Page cycle)
RAS hold time from CAS precharge
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
RAS pulse width (C-B-R self refresh)

RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)

tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tPC
tPRWC
tCP
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tRASS

tRPS
tCHS

-5 -6

Min Max Min Max

64 64 ms
64 64 ms

0 0 ns 7
36 38 ns 7,15
73 83 ns 7
48 53 ns 7
53 60 ns

5 5 ns 17
10 10 ns 18

5 5 ns

30 35 ns 3
35 40 ns
76 85 ns
10 10 ns 14
50 200K 60 200K ns
30 35 ns

13 15 ns

13 13 ns

0 13 0 13 ns 6
13 15 ns
10 10 ns 11
15 15 ns 11
10 10 ns
10 10 ns

100 100 us 20,21,22

90 110 ns 20,21,22

-50 -50 ns 20,21,22

Units Note

KM416C4000C, KM416C4100C CMOS DRAM

TEST MODE CYCLE

Parameter Symbol

Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
RAS pulse width
CAS pulse width
RAS hold time
CAS hold time
Column Address to RAS lead time
CAS to W delay time
RAS to W delay time
Column Address to W delay time
Fast Page mode cycle time
Fast Page mode read-modify-write cycle time
RAS pulse width (Fast Page cycle)
Access time from CAS precharge
OE access time
OE to data delay
OE command hold time

tRC
tRWC
tRAC
tCAC
tAA
tRAS
tCAS
tRSH
tCSH
tRAL
tCWD
tRWD
tAWD
tPC
tPRWC
tRASP
tCPA
tOEA
tOED
tOEH

( Note 11 )

-5 -6

Min Max Min Max

95 115 ns

138 160 ns

55 65 ns 3,4,10,12
18 20 ns 3,4,5,12

30 35 ns 3,10,12
55 10K 65 10K ns
18 10K 20 10K ns
18 20 ns
55 65 ns
30 35 ns
41 43 ns 7
78 88 ns 7
53 58 ns 7
40 45 ns
81 90 ns
55 200K 65 200K ns

35 40 ns 3

18 20 ns
18 18 ns
18 20 ns

Units Note

KM416C4000C, KM416C4100C CMOS DRAM

NOTES

1.

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.

2.

VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.

3.

Measured with a load equivalent to 2 TTL load and 100pF.

4.

Operation within the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

5.

Assumes that tRCD≥tRCD(max).

6.

tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh

or Vol.

tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char-

7.

acteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.

8.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.

9.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.

10.

If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.

11.

In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

12.

KM416C40(1)00C Truth Table

RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE

H X X X X Hi-Z Hi-Z Standby

L H H X X Hi-Z Hi-Z Refresh
L L H H L DQ-OUT Hi-Z Byte Read
L H L H L Hi-Z DQ-OUT Byte Read
L L L H L DQ-OUT DQ-OUT Word Read
L L H L H DQ-IN - Byte Write
L H L L H - DQ-IN Byte Write
L L L L H DQ-IN DQ-IN Word Write
L L L H H Hi-Z Hi-Z -

KM416C4000C, KM416C4100C CMOS DRAM

tASC, tCAH are referenced to the earlier CAS falling edge.

13.

14.

tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.

15.

tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.

16.

tCWL is specified from W falling edge to the earlier CAS rising edge.

17.

tCSR is referenced to the earlier CAS falling edge before RAS transition low.

18.

tCHR is referenced to the later CAS rising edge after RAS transition low.

RAS

LCAS

UCAS

tCSR tCHR

tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge.

19.

LCAS

UCAS

tDS tDH

DQ0 ~ DQ15

If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.

20.

21.

For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately

22.
before and after self refresh in order to meet refresh specification.

Din

KM416C4000C, KM416C4100C CMOS DRAM

WORD READ CYCLE

VIH -

RAS

VIL -

VIH -

UCAS

VIL -

VIH -

LCAS

VIL -

VIH -

A

VIL -

VIH -

W

VIL -

VIH -

OE

VIL -

DQ0 ~ DQ7

VOH -
VOL -

DQ8 ~ DQ15

VOH -
VOL -

tCRP

tCRP

tASR tRAH

ROW

ADDRESS

tRAD

OPEN

OPEN

tASC

tRCS

tCSH

tCSH

COLUMN

ADDRESS

tRAC

tRAC

tRAS

tCAH

tAA

tCLZ

tCLZ

tOEA

CAC

t

tCAC

tRC

tCAS

tCAS

tRAL

tRP

tRSHtRCD

tRSHtRCD

tCRP

tCRP

tRCH

tRRH

tOFF

tOEZ

DATA-OUT

tOFF

tOEZ

DATA-OUT

Don′t care

Undefined

KM416C4000C, KM416C4100C CMOS DRAM

LOWER BYTE READ CYCLE

NOTE : DIN = OPEN

VIH -

RAS

VIL -

VIH -

UCAS

VIL -

VIH -

LCAS

VIL -

VIH -

A

VIL -

VIH -

W

VIL -

VIH -

OE

VIL -

DQ0 ~ DQ7

VOH -
VOL -

tCRP

tCRP

tASR tRAH

ROW

ADDRESS

tRAD

OPEN

tASC

tRCS

tRAC

tRAS

tCSH

tCAH

COLUMN

ADDRESS

tAA

tCLZ

tRC

tRP

tRPC

tRSHtRCD

tCAS

tRAL

tRCH

tRRH

tOFF

tOEZ

tOEA

tCAC

DATA-OUT

DQ8 ~ DQ15

VOH -
VOL -

OPEN

Don′t care

Undefined