Samsung KM416C4100BS-5, KM416C4100BS-45, KM416C4000BS-6, KM416C4000BS-5, KM416C4000BS-45 Datasheet

KM416C4000B, KM416C4100B CMOS DRAM

This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6) are optional features of this family. All of this fam­ily have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 Fast Page Mode DRAM family is fabri­cated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Part Identification

- KM416C4000B(5.0V, 8K Ref.)

- KM416C4100B(5.0V, 4K Ref.)

• Fast Page Mode operation

• 2CAS Byte/Word Read/Write operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Fast parallel test mode capability

• TTL(5.0V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic TSOP(II) package

• +5.0V±10% power supply

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

4M x 16bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

FEATURES

• Refresh Cycles
Part

NO.

Refresh

cycle

Refresh time

Normal

KM416C4000B* 8K

64ms

KM416C4100B 4K

• Performance Range
Speed

tRAC tCAC tRC tPC

-45 45ns 12ns 80ns 31ns

-5 50ns 13ns 90ns 35ns

-6 60ns 15ns 110ns 40ns

• Active Power Dissipation

Speed 8K 4K

-45 550 715

-5 495 660

-6 440 605

Unit : mW

Control
Clocks

Lower

Data out

Buffer

RAS

UCAS

LCAS

W

Vcc
Vss

DQ0

to

DQ7

A0~A12

(A0~A11)*1

A0~A8

(A0~A9)*1

Memory Array

4,194,304 x 16

Cells

FUNCTIONAL BLOCK DIAGRAM

Note) *1 : 4K Refresh

Sense Amps & I/O

Upper

Data in

Buffer

Upper

Data out

Buffer

Lower

Data in

Buffer

DQ8

to

DQ15

OE

* Access mode & RAS only refresh mode
: 8K cycle/64ms

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms

Row Decoder

Column Decoder

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

KM416C4000B, KM416C4100B CMOS DRAM

PIN CONFIGURATION (Top Views)

VCC
DQ0
DQ1
DQ2
DQ3

VCC
DQ4
DQ5
DQ6
DQ7

N.C

VCC

W

RAS

N.C
N.C
N.C
N.C

A0
A1
A2
A3
A4
A5

VCC

VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
VSS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

Pin Name Pin function

A0 - A12 Address Inputs(8K Product)
A0 - A11 Address Inputs(4K Product)
DQ0 - 15 Data In/Out
VSS Ground
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC Power(+5.0V)
N.C No Connection

(400mil TSOP(II))

*(N.C) : N.C for 4K Refresh Product

• KM416C40(1)00BS

KM416C4000B, KM416C4100B CMOS DRAM

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Parameter Symbol Rating Units

Voltage on any pin relative to VSS VIN,VOUT -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 °C
Power Dissipation PD 1 W
Short Circuit Output Current IOS Address 50 mA

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

*1 : VCC+2.0V at pulse width≤20ns which is measured at VCC
*2 : -2.0 at pulse width≤20ns which is measured at VSS

Parameter Symbol Min Typ Max Units

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.4 -

VCC+1.0

*1

V

Input Low Voltage VIL -1.0 - 0.8 V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter Symbol Min Max Units

Input Leakage Current (Any input 0≤VIN≤VCC+0.5V,
all other pins not under test=0 Volt)

II(L) -5 5 uA

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

IO(L) -5 5 uA

Output High Voltage Level(IOH=-5mA) VOH 2.4 - V
Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V

*2

KM416C4000B, KM416C4100B CMOS DRAM

*Note :

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.

DC AND OPERATING CHARACTERISTICS (Continued)

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)

Symbol Power Speed

Max

Units

KM416C4000B KM416C4100B

ICC1 Don′t care

-45

-5

-6

100

90
80

130
120
110

mA
mA
mA

ICC2 Normal Don′t care 2 2 mA

ICC3 Don′t care

-45

-5

-6

100

90
80

130
120
110

mA
mA
mA

ICC4 Don′t care

-45

-5

-6

70
60
50

80
70
60

mA
mA
mA

ICC5 Normal Don′t care 1 1 mA

ICC6 Don′t care

-45

-5

-6

100

90
80

130
120
110

mA
mA
mA

KM416C4000B, KM416C4100B CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A12] CIN1 - 5 pF
Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ15] CDQ - 7 pF

Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V

Parameter Symbol

-45 -5 -6
Units Note

Min Max Min Max Min Max

Random read or write cycle time

tRC

80 90 110

ns

Read-modify-write cycle time

tRWC

115 133 153 ns

Access time from RAS

tRAC

45 50 60 ns 3,4,10

Access time from CAS

tCAC

12 13 15 ns 3,4,5

Access time from column address

tAA

23 25 30 ns 3,10

CAS to output in Low-Z

tCLZ

0 0 0 ns 3

Output buffer turn-off delay

tOFF

0 13 0 13 0 13 ns 6

Transition time (rise and fall)

tT

1 50 1 50 1 50 ns 2

RAS precharge time

tRP

25 30 40 ns

RAS pulse width

tRAS

45 10K 50 10K 60 10K ns

RAS hold time

tRSH

12 13 15 ns

CAS hold time

tCSH

45 50 60 ns

CAS pulse width

tCAS

12 10K 13 10K 15 10K ns

RAS to CAS delay time

tRCD

18 33 20 37 20 45 ns 4

RAS to column address delay time

tRAD

13 22 15 25 15 30 ns 10

CAS to RAS precharge time

tCRP

5 5 5 ns

Row address set-up time

tASR

0 0 0 ns

Row address hold time

tRAH

8 10 10 ns

Column address set-up time

tASC

0 0 0 ns 13

Column address hold time

tCAH

8 10 10 ns 13

Column address to RAS lead time

tRAL

23 25 30 ns

Read command set-up time

tRCS

0 0 0 ns

Read command hold time referenced to CAS

tRCH

0 0 0 ns 8

Read command hold time referenced to RAS

tRRH

0 0 0 ns 8

Write command hold time

tWCH

8 10 10 ns

Write command pulse width

tWP

8 10 10 ns

Write command to RAS lead time

tRWL

13 15 15 ns

Write command to CAS lead time

tCWL

12 13 15 ns 16

Data set-up time

tDS

0 0 0 ns 9,19

Data hold time

tDH

10 10 10 ns 9,19

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

KM416C4000B, KM416C4100B CMOS DRAM

AC CHARACTERISTICS (Continued)

Parameter Symbol

-45 -5 -6
Units Note

Min Max Min Max Min Max

Refresh period (4K, Normal)

tREF

64 64 64 ms

Refresh period (8K, Normal)

tREF

64 64 64 ms

Write command set-up time

tWCS

0 0 0 ns 7

CAS to W delay time

tCWD

32 36 38 ns 7,15

RAS to W delay time

tRWD

67 73 83 ns 7

Column address to W delay time

tAWD

43 48 53 ns 7

CAS precharge W delay time

tCPWD

48 53 60 ns

CAS set-up time (CAS -before-RAS refresh)

tCSR

5 5 5 ns 17

CAS hold time (CAS -before-RAS refresh)

tCHR

10 10 10 ns 18

RAS to CAS precharge time

tRPC

5 5 5 ns

Access time from CAS precharge

tCPA

26 30 35 ns 3

Fast Page mode cycle time

tPC

31 35 40 ns

Fast Page mode read-modify-write cycle time

tPRWC

70 76 85 ns

CAS precharge time (Fast Page cycle)

tCP

9 10 10 ns 14

RAS pulse width (Fast Page cycle)

tRASP

45 200K 50 200K 60 200K ns

RAS hold time from CAS precharge

tRHCP

28 30 35 ns

OE access time

tOEA

12 13 15 ns

OE to data delay

tOED

12 13 13 ns

Output buffer turn off delay time from OE

tOEZ

0 13 0 13 0 13 ns 6

OE command hold time

tOEH

12 13 15 ns

Write command set-up time (Test mode in)

tWTS

10 10 10 ns 11

Write command hold time (Test mode in)

tWTH

15 15 15 ns 11

W to RAS precharge time (C-B-R refresh)

tWRP

10 10 10 ns

W to RAS hold time (C-B-R refresh)

tWRH

10 10 10 ns

RAS pulse width (C-B-R self refresh)

tRASS

100 100 100 us 20,21,22

RAS precharge time (C-B-R self refresh)

tRPS

80 90 110 ns 20,21,22

CAS hold time (C-B-R self refresh)

tCHS

-50 -50 -50 ns 20,21,22

KM416C4000B, KM416C4100B CMOS DRAM

TEST MODE CYCLE

Parameter Symbol

-45 -5 -6
Units Note

Min Max Min Max Min Max

Random read or write cycle time

tRC

85 95 115 ns

Read-modify-write cycle time

tRWC

120 138 160 ns

Access time from RAS

tRAC

50 55 65 ns 3,4,10,12

Access time from CAS

tCAC

17 18 20 ns 3,4,5,12

Access time from column address

tAA

28 30 35 ns 3,10,12

RAS pulse width

tRAS

50 10K 55 10K 65 10K ns

CAS pulse width

tCAS

17 10K 18 10K 20 10K ns

RAS hold time

tRSH

17 18 20 ns

CAS hold time

tCSH

50 55 65 ns

Column Address to RAS lead time

tRAL

28 30 35 ns

CAS to W delay time

tCWD

37 41 43 ns 7

RAS to W delay time

tRWD

72 78 88 ns 7

Column Address to W delay time

tAWD

48 53 58 ns 7

Fast Page mode cycle time

tPC

36 40 45 ns

Fast Page mode read-modify-write cycle time

tPRWC

75 81 90 ns

RAS pulse width (Fast Page cycle)

tRASP

50 200K 55 200K 65 200K ns

Access time from CAS precharge

tCPA

31 35 40 ns 3

OE access time

tOEA

17 18 20 ns

OE to data delay

tOED

17 18 18 ns

OE command hold time

tOEH

17 18 20 ns

( Note 11 )

KM416C4000B, KM416C4100B CMOS DRAM

KM416C40(1)00B Truth Table

RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE

H X X X X Hi-Z Hi-Z Standby

L H H X X Hi-Z Hi-Z Refresh
L L H H L DQ-OUT Hi-Z Byte Read
L H L H L Hi-Z DQ-OUT Byte Read
L L L H L DQ-OUT DQ-OUT Word Read
L L H L H DQ-IN - Byte Write
L H L L H - DQ-IN Byte Write
L L L L H DQ-IN DQ-IN Word Write
L L L H H Hi-Z Hi-Z -

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL load and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).

tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh

or Vol.

tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char-

acteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

5.

6.

7.

8.

9.

10.

11.

12.

1.

2.

3.

4.

KM416C4000B, KM416C4100B CMOS DRAM

tASC, tCAH are referenced to the earlier CAS falling edge.
tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
tCWL is specified from W falling edge to the earlier CAS rising edge.

tCSR is referenced to the earlier CAS falling edge before RAS transition low.
tCHR is referenced to the later CAS rising edge after RAS transition low.

tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge.

If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.

tCSR tCHR

RAS

LCAS

UCAS

tDS tDH

LCAS

UCAS

DQ0 ~ DQ15

Din

21.

20.

19.

15.

14.

13.

18.

17.

16.

22.

KM416C4000B, KM416C4100B CMOS DRAM

RAS

VIH -
VIL -

UCAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VOH -
VOL -

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tASR tRAH

tASC

tCAH

tCRP

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

tOFF

tRCH

Don′t care

Undefined

LCAS

VIH -
VIL -

tCRP

tCSH

tRSHtRCD

tCAS

tRAD

tCRP

tRRH

VOH -
VOL -

DQ8 ~ DQ15

tCAC

tCLZ

tRAC

OPEN

DATA-OUT

DATA-OUT

tOFF

tOEZ

tOEZ

tRCS

WORD READ CYCLE

KM416C4000B, KM416C4100B CMOS DRAM

tCRP

NOTE : DIN = OPEN

LOWER BYTE READ CYCLE

RAS

VIH -
VIL -

LCAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VOH -
VOL -

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tRAD

tASR tRAH

tASC

tCAH

tCRP

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN DATA-OUT

tOEZ

tOFF

tRCH

Don′t care

Undefined

tRPC

UCAS

VIH -
VIL -

OPEN

VOH -
VOL -

DQ8 ~ DQ15

tRCS

tRRH