Samsung KM416C4104CS-6, KM416C4104CS-5, KM416C4004CS-6, KM416C4004CS-5 Datasheet

KM416C4004C, KM416C4104C CMOS DRAM

This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-5 or -6) are optional features of this family.
All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 EDO Mode DRAM family
is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Part Identification

- KM416C4004C(5.0V, 8K Ref.)

- KM416C4104C(5.0V, 4K Ref.)

• Extended Data Out Mode operation

• 2 CAS Byte/Word Read/Write operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Fast parallel test mode capability

• TTL(5.0V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic TSOP(II) package

• +5.0V±10% power supply

Control
Clocks

Lower

Data out

Buffer

RAS
UCAS
LCAS

W

Vcc
Vss

DQ0

to

DQ7

A0~A12

(A0~A11)*1

A0~A8

(A0~A9)*1

Memory Array

4,194,304 x 16

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

4M x 16bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Note) *1 : 4K Refresh

• Refresh Cycles
Part

NO.

Refresh

cycle

Refresh time

Normal

KM416C4004C* 8K

64ms

KM416C4104C 4K

• Performance Range

Speed

tRAC tCAC tRC tHPC

-5 50ns 13ns 84ns 20ns

-6 60ns 15ns 104ns 25ns

• Active Power Dissipation

Speed 8K 4K

-5 495 660

-6 440 605

Unit : mW

Sense Amps & I/O

Upper

Data in

Buffer

Upper

Data out

Buffer

Lower

Data in

Buffer

DQ8

to

DQ15

OE

* Access mode & RAS only refresh mode
: 8K cycle/64ms

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms

Row Decoder

Column Decoder

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

KM416C4004C, KM416C4104C CMOS DRAM

VCC
DQ0
DQ1
DQ2
DQ3

VCC
DQ4
DQ5
DQ6
DQ7

N.C

VCC

W

RAS

N.C

N.C

N.C

N.C

A0
A1
A2
A3
A4
A5

VCC

VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
VSS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

PIN CONFIGURATION (Top Views)

Pin Name Pin function

A0 - A12 Address Inputs(8K Product)
A0 - A11 Address Inputs(4K Product)
DQ0 - 15 Data In/Out
VSS Ground
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC Power(+5.0V)
N.C No Connection

(400mil TSOP(II))

*(N.C) : N.C for 4K Refresh Product

• KM416C40(1)04CS

KM416C4004C, KM416C4104C CMOS DRAM

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Parameter Symbol Rating Units

Voltage on any pin relative to VSS VIN,VOUT -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 °C
Power Dissipation PD 1 W
Short Circuit Output Current IOS Address 50 mA

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

*1 : VCC+2.0V at pulse width≤20ns which is measured at VCC
*2 : -2.0 at pulse width≤20ns which is measured at VSS

Parameter Symbol Min Typ Max Units

Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.6 -

VCC+1.0

*1

V

Input Low Voltage VIL

-1.0

*2

- 0.7 V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter Symbol Min Max Units

Input Leakage Current (Any input 0≤VIN≤VCC+0.5V,
all other pins not under test=0 Volt)

II(L) -5 5 uA

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

IO(L) -5 5 uA

Output High Voltage Level(IOH=-5mA) VOH 2.4 - V
Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V

KM416C4004C, KM416C4104C CMOS DRAM

*Note :

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time tHPC.

DC AND OPERATING CHARACTERISTICS (Continued)

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)

Symbol Power Speed

Max

Units

KM416C4004C KM416C4104C

ICC1 Don′t care

-5

-6

90
80

120
110

mA
mA

ICC2 Normal Don′t care 2 2 mA

ICC3 Don′t care

-5

-6

90
80

120
110

mA
mA

ICC4 Don′t care

-5

-6

100

90

110
100

mA
mA

ICC5 Normal Don′t care 1 1 mA

ICC6 Don′t care

-5

-6

120
110

120
110

mA
mA

KM416C4004C, KM416C4104C CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A12] CIN1 - 5 pF
Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ15] CDQ - 7 pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition : VCC=5.0V±10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.0/0.8V

Parameter Symbol

-5 -6
Units Note

Min Max Min Max

Random read or write cycle time

tRC

84 104 ns

Read-modify-write cycle time

tRWC

116 138 ns

Access time from RAS

tRAC

50 60 ns 3,4,10

Access time from CAS

tCAC

13 15 ns 3,4,5

Access time from column address

tAA

25 30 ns 3,10

CAS to output in Low-Z

tCLZ

3 3 ns 3

Output buffer turn-off delay from CAS

tCEZ

3 13 3 13 ns 6,21

OE to output in Low-Z

tOLZ

3 3 ns 3

Transition time (rise and fall)

tT

1 50 1 50 ns 2

RAS precharge time

tRP

30 40 ns

RAS pulse width

tRAS

50 10K 60 10K ns

RAS hold time

tRSH

13 15 ns

CAS hold time

tCSH

38 45 ns

CAS pulse width

tCAS

8 10K 10 10K ns

RAS to CAS delay time

tRCD

20 37 20 45 ns 4

RAS to column address delay time

tRAD

15 25 15 30 ns 10

CAS to RAS precharge time

tCRP

5 5 ns

Row address set-up time

tASR

0 0 ns

Row address hold time

tRAH

10 10 ns

Column address set-up time

tASC

0 0 ns

Column address hold time

tCAH

8 10 ns 13

Column address to RAS lead time

tRAL

25 30 ns 13

Read command set-up time

tRCS

0 0 ns

Read command hold time referenced to CAS

tRCH

0 0 ns 8

Read command hold time referenced to RAS

tRRH

0 0 ns 8

Write command hold time

tWCH

10 10 ns

Write command pulse width

tWP

10 10 ns

Write command to RAS lead time

tRWL

13 15 ns

Write command to CAS lead time

tCWL

8 10 ns 16

Data set-up time

tDS

0 0 ns 9,19

KM416C4004C, KM416C4104C CMOS DRAM

AC CHARACTERISTICS (Continued)

Parameter Symbol

-5 -6
Units Note

Min Max Min Max

Data hold time

tDH

8 10 ns 9,19

Refresh period (4K, Normal)

tREF

64 64 ms

Refresh period (8K, Normal)

tREF

64 64 ms

Write command set-up time

tWCS

0 0 ns 7

CAS to W delay time

tCWD

30 32 ns 7,15

RAS to W delay time

tRWD

67 77 ns 7

Column address W delay time

tAWD

42 47 ns 7

CAS set-up time (CAS -before-RAS refresh)

tCSR

5 5 ns 17

CAS hold time (CAS -before-RAS refresh)

tCHR

10 10 ns 18

RAS to CAS precharge time

tRPC

5 5 ns

Access time from CAS precharge

tCPA

28 35 ns 3

Hyper Page cycle time

tHPC

20 25 ns 20

Hyper Page read-modify-write cycle time

tHPRWC

47 56 ns 20

CAS precharge time (Hyper page cycle)

tCP

8 10 ns 14

RAS pulse width (Hyper page cycle)

tRASP

50 200K 60 200K ns

RAS hold time from CAS precharge

tRHCP

30 35 ns

OE access time

tOEA

13 15 ns

OE to data delay

tOED

13 13 ns

CAS precharge to W delay time

tCPWD

45 54 ns

Output buffer turn off delay time from OE

tOEZ

3 13 3 13 ns 6

OE command hold time

tOEH

13 15 ns

Write command set-up time (Test mode in)

tWTS

10 10 ns 11

Write command hold time (Test mode in)

tWTH

10 10 ns 11

W to RAS precharge time (C-B-R refresh)

tWRP

10 10 ns

W to RAS hold time (C-B-R refresh)

tWRH

10 10 ns

Output data hold time

tDOH

5 5 ns

Output buffer turn off delay from RAS

tREZ

3 13 3 13 ns 6,21

Output buffer turn off delay from W

tWEZ

3 13 3 13 ns 6

W to data delay

tWED

15 15 ns

OE to CAS hold time

tOCH

5 5 ns

CAS hold time to OE

tCHO

5 5 ns

OE precharge time

tOEP

5 5 ns

W pulse width (Hyper page cycle)

tWPE

5 5 ns

RAS pulse width (C-B-R self refresh)

tRASS

100 100 us 22,23,24

RAS precharge time (C-B-R self refresh)

tRPS

90 110 ns 22,23,24

CAS hold time (C-B-R self refresh)

tCHS

-50 -50 ns 22,23,24

KM416C4004C, KM416C4104C CMOS DRAM

TEST MODE CYCLE

Parameter Symbol

-5 -6
Units Note

Min Max Min Max

Random read or write cycle time

tRC

89 109 ns

Read-modify-write cycle time

tRWC

121 145 ns

Access time from RAS

tRAC

55 65 ns 3,4,10,12

Access time from CAS

tCAC

18 20 ns 3,4,5,12

Access time from column address

tAA

30 35 ns 3,10,12

RAS pulse width

tRAS

55 10K 65 10K ns

CAS pulse width

tCAS

13 10K 15 10K ns

RAS hold time

tRSH

18 20 ns

CAS hold time

tCSH

43 50 ns

Column Address to RAS lead time

tRAL

30 35 ns

CAS to W delay time

tCWD

35 39 ns 7

RAS to W delay time

tRWD

72 84 ns 7

Column Address to W delay time

tAWD

47 54 ns 7

Hyper Page cycle time

tHPC

25 30 ns 20

Hyper Page read-modify-write cycle time

tHPRWC

53 61 ns 20

RAS pulse width (Hyper page cycle)

tRASP

55 200K 65 200K ns

Access time from CAS precharge

tCPA

33 40 ns 3

OE access time

tOEA

18 20 ns

OE to data delay

tOED

18 20 ns

OE command hold time

tOEH

18 20 ns

( Note 11 )

KM416C4004C, KM416C4104C CMOS DRAM

KM416C40(1)04C Truth Table

RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE

H X X X X Hi-Z Hi-Z Standby

L H H X X Hi-Z Hi-Z Refresh
L L H H L DQ-OUT Hi-Z Byte Read
L H L H L Hi-Z DQ-OUT Byte Read
L L L H L DQ-OUT DQ-OUT Word Read
L L H L H DQ-IN - Byte Write
L H L L H - DQ-IN Byte Write
L L L L H DQ-IN DQ-IN Word Write
L L L H H Hi-Z Hi-Z -

NOTES

An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL load and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
These parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical charac-

teristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the dura­tion of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle and the
data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of
the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

tASC, tCAH are referenced to the earlier CAS falling edge.
tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.

7.

6.

5.

10.

9.

8.

13.

12.

11.

15.

14.

3.

2.

1.

4.

KM416C4004C, KM416C4104C CMOS DRAM

tCWL is specified from W falling edge to the earlier CAS rising edge.
tCSR is referenced to the earlier CAS falling edge before RAS transition low.
tCHR is referenced to the later CAS rising edge after RAS transition low.

tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle.

tASC≥6ns, Assume tT = 2.0ns

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.

tCSR tCHR

RAS

LCAS

UCAS

tDS tDH

LCAS

UCAS

DQ0 ~ DQ15

Din

22.

21.

20.

19.

18.

17.

16.

23.

24.

KM416C4004C, KM416C4104C CMOS DRAM

tCRP

RAS

VIH -
VIL -

UCAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

V

IH -

VIL -

VOH -
VOL -

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tCRP

tRP

tCSH

tRSHtRCD

tCAS

tRAL

tASR tRAH tASC

tCAH

tCRP

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

tCEZ

tRCH

Don′t care

Undefined

LCAS

VIH -
VIL -

tCRP

tCSH

tRSHtRCD

tCAS

tRAD

tRRH

VOH -
VOL -

DQ8 ~ DQ15

tCAC

tCLZ

tRAC

OPEN

DATA-OUT

DATA-OUT

tCEZ

tOEZ

tOEZ

tRCS

WORD READ CYCLE

tOLZ

KM416C4004C, KM416C4104C CMOS DRAM

NOTE : DIN = OPEN

LOWER BYTE READ CYCLE

RAS

VIH -
VIL -

LCAS

VIH -
VIL -

A

VIH -
VIL -

W

VIH -
VIL -

OE

VIH -
VIL -

VOH -
VOL -

DQ0 ~ DQ7

COLUMN

ADDRESS

ROW

ADDRESS

tRAS

tRC

tRP

tCSH

tRSHtRCD
tCAS

tRAL

tRAD

tASR tRAH tASC

tCAH

tCRP

tAA

tOEA

tCAC

tCLZ

tRAC

OPEN

DATA-OUT

tOEZ

tCEZ

tRRH

tRCH

Don′t care

Undefined

tCRP

tRPC

UCAS

VIH -
VIL -

OPEN

VOH -
VOL -

DQ8 ~ DQ15

tRCS

tOLZ