SAMSUNG K9F5608X0D Technical data

查询K9F5608X0D-FCB0供应商

K9F5608R0D K9F5608U0D

K9F5608D0D

FLASH MEMORY

K9F5608X0D

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* Samsung Electronics reserves the right to change products or specification without notice.

K9F5608R0D K9F5608U0D

K9F5608D0D

Document Title

32M x 8 Bit NAND Flash Memory

Revision History

Revision No.

0.0

History

Initial issue

FLASH MEMORY

Draft Date

May 16th. 2005

Remark

Advance

0.1

0.2

1.0

1.1

1. Leaded package devices are eliminated

1. LOCKPRE pin mode is eliminated

Aug. 11th. 2005

Oct. 17th. 2005

Oct. 30th. 2005

Dec. 30th 2005

Advance

Preliminary

Final

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

K9F5608R0D K9F5608U0D

K9F5608D0D

FLASH MEMORY

32M x 8 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F5608R0D-J 1.65 ~ 1.95V

K9F5608D0D-P

K9F5608D0D-J FBGA

K9F5608U0D-P

K9F5608U0D-J FBGA

K9F5608U0D-F WSOP1

FEATURES

• Voltage Supply

- 1.8V device(K9F5608R0D) : 1.65~1.95V

- 2.65V device(K9F5608D0D) : 2.4~2.9V

- 3.3V device(K9F5608U0D) : 2.7 ~ 3.6 V

• Organization

- Memory Cell Array

-(32M + 1024K)bit x 8 bit

- Data Register

- (512 + 16)bit x 8bit

• Automatic Program and Erase

- Page Program

-(512 + 16)Byte

- Block Erase :

- (16K + 512)Byte

• Page Read Operation

- Page Size

- (512 + 16)Byte

- Random Access : 15µs(Max.)

- Serial Page Access : 50ns(Min.)

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

2.4 ~ 2.9V

2.7 ~ 3.6V

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Intelligent Copy-Back

• Unique ID for Copyright Protection

• Package

- K9F5608D(U)0D-PCB0/PIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F5608X0D-JCB0/JIB0 63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)

- Pb-free Package

- K9F5608U0D-FCB0/FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F5608U0D-F(WSOPI ) is the same device as K9F5608U0D-P(TSOP1) except package type.

FBGA

TSOP1

GENERAL DESCRIPTION

Offered in 32Mx8bit , the K9F5608X0D is 256M bit with spare 8M bit capacity. The device is offered in 1.8V, 2.65V, 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs on a 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F5608X0D′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F5608X0D is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

K9F5608R0D K9F5608U0D

PIN CONFIGURATION (TSOP1)

K9F5608D0D

FLASH MEMORY

K9F5608D(U)0D-PCB0/PIB0

N.C N.C N.C N.C N.C N.C R/B RE

CE N.C N.C Vcc Vss N.C N.C

CLE ALE

WE WP N.C N.C N.C N.C N.C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

20.00±0.20

0.787±0.008

+0.07

-0.03

0.20

#48

N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C

Unit :mm/Inch

MAX

0.10

0.004

0.25 ()

0.010

+0.003

-0.001

+0.07

-0.03

0.16

0.008

0.50

0.0197

0~8°

0.45~0.75

0.018~0.030

#24

0.25

TYP

0.010

18.40±0.10

0.724±0.004

#25

+0.075

0.035 +0.003

-0.001

0.125

0.005

0.50

()

0.020

MAX

0.488

12.40

1.00±0.05

0.039±0.002

1.20 MAX

0.047

12.00

0.472

0.05 MIN

0.002

K9F5608R0D K9F5608U0D

K9F5608D0D

FLASH MEMORY

PIN CONFIGURATION (FBGA)

PACKAGE DIMENSIONS

63-Ball FBGA (measured in millimeters)

Top View

9.00±0.10

K9F5608X0D-JCB0/JIB0

Top View

3456 1 2

N.C N.C

N.C

NC NC

N.C N.C

N.C

(Datum A)

NC NC NC

/RE CLE

NC NC

NCNCNC

NC NC

NCNC I/O0

I/O1NC NC VccQ I/O5 I/O7

N.C

R/B/WE/CEVssALE/WP

NCNC

Vcc

VssI/O6I/O4I/O3I/O2Vss

N.C N.C

N.C

N.CN.C

Bottom View

9.00±0.10

0.80 x 9= 7.20

0.80 x 5= 4.00

0.80

4321

#A1

(Datum B)

11. 00±0.10

63-∅0.45±0.05

∅

0.20 M A B

0.10MAX

2.80

0.80

11. 00±0.10

0.80 x7= 5.60

0.80 x11= 8.80

2.00

Side View

9.00±0.10

0.45±0.05

0.25(Min.)

1.00(Max.)

K9F5608R0D K9F5608U0D

PIN CONFIGURATION (WSOP1)

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

K9F5608D0D

N.C

N.C N.C N.C R/B RE

N.C Vcc Vss N.C

CLE ALE

WE WP N.C N.C

N.C N.C

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

DNU

K9F5608U0D-FCB0/FIB0

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

FLASH MEMORY

N.C N.C DNU N.C I/O7 I/O6 I/O5 I/O4 N.C DNU N.C Vcc Vss N.C DNU N.C I/O3 I/O2 I/O1 I/O0 N.C DNU N.C N.C

48 - WSOP1 - 1217F

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP (0.50±0.06)

#24

15.40±0.10

#48

#25

0.70 MAX

0.58±0.04

(0.01Min)

Unit :mm

12.00±0.10

12.40MAX

17.00±0.20

+0.075

-0.035

0.10

0.45~0.75

K9F5608R0D K9F5608U0D

PIN DESCRIPTION

Pin NAME Pin Function

0 ~ I/O7

I/O

CLE

ALE

R/B

K9F5608D0D

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE

CHIP ENABLE

The CE

input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE read operation, refer to ’Page read’ section of Device operation.

READ ENABLE

The RE

input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE

WRITE ENABLE

The WE

input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE

pulse.

WRITE PROTECT

The WP

pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage

generator is reset when the WP

READY/BUSY OUTPUT

The R/B

output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

with ALE high.

which also increments the internal column address counter by one.

pin is active low.

FLASH MEMORY

signal.

control during

OUTPUT BUFFER POWER

Vcc

Vss GROUND

N.C

DNU

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave V

Vcc

Q is the power supply for Output Buffer.

Vcc

Q is internally connected to Vcc, thus should be biased to Vcc.

POWER

CC is the power supply for device.

NO CONNECTION

Lead is not internally connected.

DO NOT USE

Leave it disconnected

CC or VSS disconnected.

K9F5608R0D K9F5608U0D

Figure 1-1. K9F5608X0D FUNCTIONAL BLOCK DIAGRAM

VCC

K9F5608D0D

FLASH MEMORY

A9 - A24

A0 - A7

X-Buffers Latches & Decoders

Y-Buffers Latches & Decoders

Command

CE RE WE

Control Logic

& High Voltage

Generator

CLE ALE

Figure 2-1. K9F5608X0D ARRAY ORGANIZATION

256M + 8M Bit

NAND Flash

ARRAY

(512 + 16)Byte x 65536

Page Register & S/A

Y-Gat ing

I/O Buffers & Latches

Global Buffers

1 Block =32 Pages = (16K + 512) Byte

Output

Driver

VCC/VCCQ VSS

I/0 0

I/0 7

64K Pages (=2,048 Blocks)

1st half Page Register

(=256 Bytes)

512Byte 16 Byte

2nd half Page Register

(=256 Bytes)

Page Register

512 Byte

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

8 is set to "Low" or "High" by the 00h or 01h Command.

* A

* The device ignores any additional input of address cycles than required.

0 A1 A2 A3 A4 A5 A6 A7

1 Page = 528 Byte 1 Block = 528 Byte x 32 Pages = (16K + 512) Byte 1 Device = 528Bytes x 32Pages x 2048 Blocks = 264 Mbits

8 bit

I/O 0 ~ I/O 7

16 Byte

Column Address Row Address

(Page Address)

K9F5608R0D K9F5608U0D

K9F5608D0D

PRODUCT INTRODUCTION

The K9F5608X0D is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations.The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figure 2-1. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F5608X0D. The K9F5608X0D has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O′s by bringing WE Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution. The 32M-byte physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F5608X0D.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.

to low while CE is low. Data is latched on the rising edge of WE. Command Latch

FLASH MEMORY

Table 1. COMMAND SETS

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 2 50h -

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Copy-Back Program 00h 8Ah

Block Erase 60h D0h

Read Status 70h - O

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

00h/01h

K9F5608R0D K9F5608U0D

K9F5608D0D

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

VIN/OUT -0.6 to + 4.6

Voltage on any pin relative to V

Temperature Under Bias

Storage Temperature

Short Circuit Current Ios 5 mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

K9F5608X0D-XCB0

K9F5608X0D-XIB0 -40 to +125

K9F5608X0D-XCB0

K9F5608X0D-XIB0

CC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

CC -0.6 to + 4.6

CCQ -0.6 to + 4.6

BIAS

STG -65 to +150 °C

-10 to +125

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C)

Parameter Symbol

Supply Voltage V

K9F5608R0D(1.8V)

Min Ty p. Max Min Typ. Max Min Typ. Max

CC 1.65 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 V

CCQ 1.65 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 V

SS 0000 0 0000 V

K9F5608D0D(2.65V) K9F5608U0D(3.3V)

FLASH MEMORY

°C

Unit

K9F5608R0D K9F5608U0D

K9F5608D0D

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions

Min Typ Max Min Typ Max Min Typ Max

Operat-

Current

Sequential Read

ing

Program I

Erase I

Stand-by Current(TTL) I

Stand-by Current(CMOS)

Input Leakage Current I

Output Leakage Current I

Input High Voltage V

Input Low Voltage, All inputs

Output High Voltage

Level

Output Low Voltage

Level

Output Low Current(R/B

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

)IOL(R/B)

tRC=50ns, CE

CC1

IOUT=0mA

CC2 - - 8 20 - 10 20 - 10 25

CC3 - - 8 20 - 10 20 - 10 25

SB1CE=VIH, WP=0V/VCC --1--1--1

SB2CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50 - 10 50

LI VIN=0 to Vcc(max) - - ±10 - - ±10 - - ±10

LO VOUT=0 to Vcc(max) - - ±10 - - ±10 - - ±10

I/O pins

IH*

Except I/O pins

IL* - -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8

K9F5608R0D :IOH=-100µA

VOH

K9F5608D0D :I

K9F5608U0D :I

=VIL

OH=-100µA

OH=-400µA

- 8 20 - 10 20 - 10 20

+0.3

CCQ

Vcc

-0.4

CCQ

-0.1

K9F5608R0D :IOL=100uA

K9F5608D0D :I

K9F5608U0D :I

K9F5608R0D :V

K9F5608D0D :V

K9F5608U0D :V

OL=100µA

OL=2.1mA

OL=0.1V

OL=0.4V

- - 0.1 - - 0.4 - - 0.4

34- 34 - 810-mA

FLASH MEMORY

K9F5608X0D

-0.4

CCQ

+0.3

2.0 -

--2.4--

CCQ

+0.3

Unit1.8V 2.65V 3.3V

µA

+ 25 hidden pages