SAMSUNG K9F5608X0D Technical data

K9F5608X0D-FCB0
K9F5608R0D	FLASH MEMORY
K9F5608U0D K9F5608D0D

K9F5608X0D

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*Samsung Electronics reserves the right to change products or specification without notice.

1

K9F5608R0D	FLASH MEMORY
K9F5608U0D K9F5608D0D

Document Title

32M x 8 Bit NAND Flash Memory

Revision History

Revision No. History			Draft Date		Remark
0.0	Initial issue		May 16th. 2005		Advance
0.1	1.	Leaded package devices are eliminated	Aug. 11th.	2005	Advance
0.2			Oct. 17th.	2005	Preliminary
1.0			Oct. 30th.	2005	Final
1.1	1.	LOCKPRE pin mode is eliminated	Dec. 30th 2005

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

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	K9F5608R0D				FLASH MEMORY
	K9F5608U0D K9F5608D0D
	32M x 8 Bit NAND Flash Memory
	PRODUCT LIST
	Part Number	Vcc Range		Organization	PKG Type
	K9F5608R0D-J	1.65 ~ 1.95V			FBGA
	K9F5608D0D-P	2.4	~ 2.9V		TSOP1
	K9F5608D0D-J			X8	FBGA
	K9F5608U0D-P				TSOP1
		2.7	~ 3.6V
	K9F5608U0D-J				FBGA
	K9F5608U0D-F				WSOP1

FEATURES

• Voltage Supply
- 1.8V device(K9F5608R0D) : 1.65~1.95V	• Command/Address/Data Multiplexed I/O Port
- 2.65V device(K9F5608D0D) : 2.4~2.9V	• Hardware Data Protection
- 3.3V device(K9F5608U0D) : 2.7 ~ 3.6 V	- Program/Erase Lockout During Power Transitions
• Organization	• Reliable CMOS Floating-Gate Technology
- Memory Cell Array	- Endurance	: 100K Program/Erase Cycles
-(32M + 1024K)bit x 8 bit	- Data Retention : 10 Years
- Data Register	• Command Register Operation
- (512 + 16)bit x 8bit	• Intelligent Copy-Back
• Automatic Program and Erase	• Unique ID for Copyright Protection
- Page Program	• Package
-(512 + 16)Byte	- K9F5608D(U)0D-PCB0/PIB0
- Block Erase :	48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- (16K + 512)Byte	- K9F5608X0D-JCB0/JIB0
• Page Read Operation	63Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- Page Size	- Pb-free Package
- (512 + 16)Byte	- K9F5608U0D-FCB0/FIB0
- Random Access : 15µs(Max.)	48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
- Serial Page Access : 50ns(Min.)	* K9F5608U0D-F(WSOPI ) is the same device as
• Fast Write Cycle Time	K9F5608U0D-P(TSOP1) except package type.
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)

GENERAL DESCRIPTION

Offered in 32Mx8bit , the K9F5608X0D is 256M bit with spare 8M bit capacity. The device is offered in 1.8V, 2.65V, 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs on a 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F5608X0D′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.

The K9F5608X0D is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

3

K9F5608R0D									FLASH MEMORY
K9F5608U0D K9F5608D0D
PIN CONFIGURATION (TSOP1)
					K9F5608D(U)0D-PCB0/PIB0
		N.C							N.C
				1			48
		N.C		2			47		N.C
		N.C		3			46		N.C
		N.C		4			45		N.C
		N.C		5			44		I/O7
		N.C		6			43		I/O6
		R/B		7			42		I/O5
		RE		8			41		I/O4
		CE		9			40		N.C
		N.C		10			39		N.C
		N.C		11			38		N.C
		Vcc		12			37		Vcc
		Vss		13			36		Vss
		N.C		14			35		N.C
		N.C		15			34		N.C
		CLE		16			33		N.C
		ALE		17			32		I/O3
		WE		18			31		I/O2
		WP		19			30		I/O1
		N.C		20			29		I/O0
		N.C		21			28		N.C
		N.C		22			27		N.C
		N.C		23			26		N.C
		N.C		24			25		N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F									Unit :mm/Inch
				20.00±0.20						MAX
										0.10	0.004
					0.787±0.008

	+0.07 -0.03		#1			#48
		0.20
											)
											0.25	0.010
											(
+0.07 -0.03	+0.003 -0.001							MAX
0.16	0.008							12.40	0.488	12.00 0.472
0.50		0.0197	#24			#25
									1.00±0.05		0.05
								0.039±0.002			0.002 MIN
			TYP			+0.075 0.035			1.20
					18.40±0.10		+0.003	0.001-	0.047MAX
					0.724±0.004
			0.25	0.010		0.125
0~8°							0.005

		0.45~0.75		(						0.50	)
	0.018~0.030
										0.020

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K9F5608R0D								FLASH MEMORY
K9F5608U0D K9F5608D0D
PIN CONFIGURATION (FBGA)		K9F5608X0D-JCB0/JIB0
			Top View
		1					6
			2	3	4	5
	N.C	N.C					N.C N.C
A	N.C						N.C N.C
		/WP	ALE	Vss	/CE	/WE	R/B
B
		NC	/RE	CLE NC		NC	NC
C
		NC	NC	NC	NC	NC	NC
D
		NC	NC	NC	NC	NC	NC
E
		NC	NC	NC	NC	NC	NC
F
		NC	I/O0	NC	NC	NC Vcc
G
		NC	I/O1	NC	VccQ	I/O5	I/O7
H
		Vss	I/O2	I/O3	I/O4	I/O6	Vss
	N.C	N.C					N.C N.C
	N.C	N.C					N.C N.C

PACKAGE DIMENSIONS

63-Ball FBGA (measured in millimeters)

Top View		Bottom View

9.00±0.10

(Datum A)

#A1

(Datum B)

11.00±0.10 2.80

63- 0.45±0.05

0.20 M A

9.00±0.10 A

0.80 x 9= 7.20 0.80 x 5= 4.00

													0.80																												B
6										5			4					3	2		1
A																															0.80
B
C
																																		x7=0.805.60			x11=0.808.80			0.10±11.00
D
E
F
G

H
B	2.00

Side View

9.00±0.10

0.10MAX 0.45±0.05

	0.25(Min.)			1.00(Max.)

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K9F5608R0D					FLASH MEMORY
K9F5608U0D K9F5608D0D
PIN CONFIGURATION (WSOP1)
			K9F5608U0D-FCB0/FIB0
N.C					N.C
		1	48
N.C		2	47		N.C
DNU		3	46		DNU
N.C		4	45		N.C
N.C		5	44		I/O7
N.C		6	43		I/O6
R/B		7	42		I/O5
RE		8	41		I/O4
CE		9	40		N.C
DNU		10	39		DNU
N.C		11	38		N.C
Vcc		12	37		Vcc
Vss		13	36		Vss
N.C		14	35		N.C
DNU		15	34		DNU
CLE		16	33		N.C
ALE		17	32		I/O3
WE		18	31		I/O2
WP		19	30		I/O1
N.C		20	29		I/O0
N.C		21	28		N.C
DNU		22	27		DNU
N.C		23	26		N.C
N.C		24	25		N.C

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48 - WSOP1 - 1217F			Unit :mm
	0.70 MAX

0.58±0.04

#1

15.40±0.10

#48

+0.07 +0.07 0.20 -0.03 0.16 -0.03

0.50TYP (0.50±0.06)

#24

#25

10.0±00.12	40MAX.12

(0.01Min)

0.10-+00..035075

17.00±0.20

0

°

~

8

°

0.45~0.75

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K9F5608R0D

FLASH MEMORY

K9F5608U0D K9F5608D0D

PIN DESCRIPTION

Pin NAME

Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/

O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

CLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

ALE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state,

CE

high is ignored, and

CE

the device does not return to standby mode in program or erase operation. Regarding CE control during

read operation, refer to ’Page read’ section of Device operation.

READ ENABLE

RE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

WE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the

WE

pulse.

WRITE PROTECT

WP

The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage

generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

R/B

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

OUTPUT BUFFER POWER

VccQ

VccQ is the power supply for

Output Buffer.

VccQ is internally connected to Vcc, thus should be biased to Vcc.

Vcc

POWER

VCC is the power supply for device.

Vss

GROUND

N.C

NO CONNECTION

Lead is not internally connected.

DNU

DO NOT USE

Leave it disconnected

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

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K9F5608R0D	FLASH MEMORY
K9F5608U0D K9F5608D0D

	Figure 1-1. K9F5608X0D FUNCTIONAL BLOCK DIAGRAM
	VCC
	VSS
	A9 - A24	X-Buffers	256M + 8M Bit
		Latches
		& Decoders	NAND Flash
		Y-Buffers	ARRAY
	A0 - A7
		Latches
		& Decoders	(512 + 16)Byte x 65536
		A8	Page Register & S/A
	Command		Y-Gating
		Command
		Register	I/O Buffers & Latches		VCC/VCCQ
					VSS
	CE	Control Logic
	RE	& High Voltage		Output	I/0 0
	WE	Generator	Global Buffers
				Driver	I/0 7
		CLE ALE WP
	Figure 2-1. K9F5608X0D ARRAY ORGANIZATION
			1 Block =32 Pages
			= (16K + 512) Byte

64K Pages

(=2,048 Blocks)

			1	Page = 528 Byte
			1	Block = 528 Byte x 32 Pages
	1st half Page Register	2nd half Page Register		= (16K + 512) Byte
			1	Device = 528Bytes x 32Pages x 2048 Blocks
	(=256 Bytes)	(=256 Bytes)
				= 264 Mbits
			8 bit
	512Byte		16 Byte

								I/O 0 ~ I/O 7
		Page Register
		512 Byte				16 Byte

	I/O 0	I/O 1	I/O 2	I/O 3	I/O 4	I/O 5	I/O 6	I/O 7
1st Cycle	A0	A1	A2	A3	A4	A5	A6	A7
2nd Cycle	A9	A10	A11	A12	A13	A14	A15	A16
3rd Cycle	A17	A18	A19	A20	A21	A22	A23	A24

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register.

*A8 is set to "Low" or "High" by the 00h or 01h Command.

*The device ignores any additional input of address cycles than required.

Column Address

Row Address

(Page Address)

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K9F5608R0D	FLASH MEMORY
K9F5608U0D K9F5608D0D

PRODUCT INTRODUCTION

The K9F5608X0D is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations.The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figure 2-1. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F5608X0D.

The K9F5608X0D has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution. The 32M-byte physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F5608X0D.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.

Table 1. COMMAND SETS

Function	1st. Cycle	2nd. Cycle	Acceptable Command during Busy
Read 1	00h/01h	-
Read 2	50h	-
Read ID	90h	-
Reset	FFh	-	O
Page Program	80h	10h
Copy-Back Program	00h	8Ah
Block Erase	60h	D0h
Read Status	70h	-	O

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

9

K9F5608R0D				FLASH MEMORY
K9F5608U0D K9F5608D0D
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol	Rating		Unit
		VIN/OUT	-0.6 to + 4.6
Voltage on any pin relative to VSS					V
		VCC	-0.6 to + 4.6
		VCCQ	-0.6 to + 4.6
Temperature Under Bias	K9F5608X0D-XCB0	TBIAS	-10 to +125		°C
	K9F5608X0D-XIB0		-40 to +125
Storage Temperature	K9F5608X0D-XCB0	TSTG	-65 to +150		°C
	K9F5608X0D-XIB0
Short Circuit Current		Ios	5		mA

NOTE :

1.Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C)

	Parameter	Symbol	K9F5608R0D(1.8V)			K9F5608D0D(2.65V)			K9F5608U0D(3.3V)			Unit
			Min	Typ.	Max	Min	Typ.	Max	Min	Typ.	Max
	Supply Voltage	VCC	1.65	1.8	1.95	2.4	2.65	2.9	2.7	3.3	3.6	V
	Supply Voltage	VCCQ	1.65	1.8	1.95	2.4	2.65	2.9	2.7	3.3	3.6	V
	Supply Voltage	VSS	0	0	0	0	0	0	0	0	0	V

10

K9F5608R0D	FLASH MEMORY
K9F5608U0D K9F5608D0D

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

																			K9F5608X0D
Parameter				Symbol						Test Conditions							1.8V			2.65V				3.3V		Unit
																Min	Typ	Max	Min	Typ		Max	Min	Typ	Max
	Sequential							tRC=50ns,
Operat-				ICC1							CE=VIL					-	8	20	-	10		20	-	10	20
ing	Read							IOUT=0mA
Current	Program			ICC2				-								-	8	20	-	10		20	-	10	25	mA
	Erase			ICC3				-								-	8	20	-	10		20	-	10	25
Stand-by Current(TTL)				ISB1												-	-	1	-	-		1	-	-	1
								CE=VIH, WP=0V/VCC
Stand-by Cur-				ISB2
								CE=VCC-0.2, WP=0V/VCC								-	10	50	-	10		50	-	10	50
rent(CMOS)
																										µA
Input Leakage Current				ILI				VIN=0 to Vcc(max)								-	-	±10	-	-		±10	-	-	±10
Output Leakage Current				ILO				VOUT=0 to Vcc(max)								-	-	±10	-	-		±10	-	-	±10
								I/O pins								VccQ	-	VCCQ	VCCQ	-		VCCQ	2.0	-	VCCQ
Input High Voltage				VIH*												-0.4		+0.3	-0.4			+0.3			+0.3
								Except I/O pins								VCC	-	VCC	VCC	-		VCC	2.0	-	VCC
																-0.4		+0.3	-0.4			+0.3			+0.3
Input Low Voltage, All				VIL*				-								-0.3	-	0.4	-0.3	-		0.5	-0.3	-	0.8
inputs
																										V
Output High Voltage								K9F5608R0D :IOH=-100µA								VCCQ			VCCQ
				VOH				K9F5608D0D :IOH=-100µA									-	-		-		-	2.4	-	-
Level																-0.1			-0.4
								K9F5608U0D :IOH=-400µA
Output Low Voltage								K9F5608R0D :IOL=100uA
				VOL				K9F5608D0D :IOL=100µA								-	-	0.1	-	-		0.4	-	-	0.4
Level
								K9F5608U0D :IOL=2.1mA
								K9F5608R0D :VOL=0.1V
Output Low Current(R/B)							K9F5608D0D :VOL=0.1V									3	4	-	3	4		-	8	10	-	mA
				IOL(R/B)
								K9F5608U0D :VOL=0.4V

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

11