SAMSUNG K9F5608X0D Technical data

查询K9F5608X0D-FCB0供应商

K9F5608R0D
K9F5608U0D

K9F5608D0D

FLASH MEMORY

K9F5608X0D

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1

K9F5608R0D
K9F5608U0D

K9F5608D0D

Document Title

32M x 8 Bit NAND Flash Memory

Revision History

Revision No.

0.0

History

Initial issue

FLASH MEMORY

Draft Date

May 16th. 2005

Remark

Advance

0.1

0.2

1.0

1.1

1. Leaded package devices are eliminated

1. LOCKPRE pin mode is eliminated

Aug. 11th. 2005

Oct. 17th. 2005

Oct. 30th. 2005

Dec. 30th 2005

Advance

Preliminary

Final

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.

2

K9F5608R0D
K9F5608U0D

K9F5608D0D

FLASH MEMORY

32M x 8 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F5608R0D-J 1.65 ~ 1.95V

K9F5608D0D-P

K9F5608D0D-J FBGA

K9F5608U0D-P

K9F5608U0D-J FBGA

K9F5608U0D-F WSOP1

FEATURES

• Voltage Supply

- 1.8V device(K9F5608R0D) : 1.65~1.95V

- 2.65V device(K9F5608D0D) : 2.4~2.9V

- 3.3V device(K9F5608U0D) : 2.7 ~ 3.6 V

• Organization

- Memory Cell Array

-(32M + 1024K)bit x 8 bit

- Data Register

- (512 + 16)bit x 8bit

• Automatic Program and Erase

- Page Program

-(512 + 16)Byte

- Block Erase :

- (16K + 512)Byte

• Page Read Operation

- Page Size

- (512 + 16)Byte

- Random Access : 15µs(Max.)

- Serial Page Access : 50ns(Min.)

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

2.4 ~ 2.9V

X8

2.7 ~ 3.6V

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Intelligent Copy-Back

• Unique ID for Copyright Protection

• Package

- K9F5608D(U)0D-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F5608X0D-JCB0/JIB0
63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)

- Pb-free Package

- K9F5608U0D-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F5608U0D-F(WSOPI ) is the same device as
K9F5608U0D-P(TSOP1) except package type.

FBGA

TSOP1

TSOP1

GENERAL DESCRIPTION

Offered in 32Mx8bit , the K9F5608X0D is 256M bit with spare 8M bit capacity. The device is offered in 1.8V, 2.65V, 3.3V Vcc. Its
NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed
in typical 200µs on a 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page
can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command
input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal
verification and margining of data. Even the write-intensive systems can take advantage of the K9F5608X0D′s extended reliability of
100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F5608X0D is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.

3

K9F5608R0D
K9F5608U0D

PIN CONFIGURATION (TSOP1)

K9F5608D0D

FLASH MEMORY

K9F5608D(U)0D-PCB0/PIB0

N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE

CE
N.C
N.C
Vcc
Vss
N.C
N.C

CLE
ALE

WE
WP
N.C
N.C
N.C
N.C
N.C

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

20.00±0.20

0.787±0.008

+0.07

-0.03

#1

0.20

#48

N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C

Unit :mm/Inch

MAX

0.10

0.004

0.25
()

0.010

+0.003

-0.001

+0.07

-0.03

0.16

0.008

0.50

0.0197

0~8°

0.45~0.75

0.018~0.030

#24

0.25

TYP

0.010

18.40±0.10

0.724±0.004

#25

+0.075

0.035
+0.003

-0.001

0.125

0.005

0.50

()

0.020

MAX

0.488

12.40

1.00±0.05

0.039±0.002

1.20
MAX

0.047

12.00

0.472

0.05
MIN

0.002

4

K9F5608R0D
K9F5608U0D

K9F5608D0D

FLASH MEMORY

PIN CONFIGURATION (FBGA)

A

B

C

D

E

F

G

H

PACKAGE DIMENSIONS

63-Ball FBGA (measured in millimeters)

Top View

9.00±0.10

K9F5608X0D-JCB0/JIB0

Top View

3456 1 2

N.C N.C

N.C

NC

NC

NC

NC NC

N.C N.C

N.C

(Datum A)

NC NC NC

/RE CLE

NC NC

NC

NC

NCNCNC

NC NC

NCNC I/O0

I/O1NC NC VccQ I/O5 I/O7

N.C

N.C

N.C

N.C

R/B/WE/CEVssALE/WP

NC

NC

NC

NC

NC

NCNC

Vcc

VssI/O6I/O4I/O3I/O2Vss

N.C N.C

N.C

N.CN.C

Bottom View

9.00±0.10

0.80 x 9= 7.20

0.80 x 5= 4.00

0.80

65

4321

A

B

#A1

(Datum B)

11. 00±0.10

63-∅0.45±0.05

∅

0.20 M A B

0.10MAX

2.80

A

0.80

B

C

D

E

F

11. 00±0.10

0.80 x7= 5.60

0.80 x11= 8.80

G

H

2.00

2.00

Side View

9.00±0.10

0.45±0.05

0.25(Min.)

1.00(Max.)

5

K9F5608R0D
K9F5608U0D

PIN CONFIGURATION (WSOP1)

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

K9F5608D0D

N.C

1

N.C

N.C
N.C
N.C
R/B
RE

CE

N.C
Vcc
Vss
N.C

CLE
ALE

WE
WP
N.C
N.C

N.C
N.C

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

DNU

DNU

DNU

DNU

K9F5608U0D-FCB0/FIB0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

FLASH MEMORY

N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C

48 - WSOP1 - 1217F

#1

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP
(0.50±0.06)

#24

15.40±0.10

#48

#25

0.70 MAX

0.58±0.04

(0.01Min)

Unit :mm

12.00±0.10

12.40MAX

17.00±0.20

+0.075

-0.035

0.10

0

°

~

8

°

0.45~0.75

6

K9F5608R0D
K9F5608U0D

PIN DESCRIPTION

Pin NAME Pin Function

0 ~ I/O7

I/O

CLE

ALE

CE

RE

WE

WP

R/B

K9F5608D0D

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE

CHIP ENABLE

The CE

input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE
read operation, refer to ’Page read’ section of Device operation.

READ ENABLE

The RE

input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE

WRITE ENABLE

The WE

input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE

pulse.

WRITE PROTECT

The WP

pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage

generator is reset when the WP

READY/BUSY OUTPUT

The R/B

output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.

with ALE high.

which also increments the internal column address counter by one.

pin is active low.

FLASH MEMORY

signal.

control during

OUTPUT BUFFER POWER

Vcc

Q

Vcc

Vss GROUND

N.C

DNU

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave V

Vcc

Q is the power supply for Output Buffer.

Vcc

Q is internally connected to Vcc, thus should be biased to Vcc.

POWER

V

CC is the power supply for device.

NO CONNECTION

Lead is not internally connected.

DO NOT USE

Leave it disconnected

CC or VSS disconnected.

7

K9F5608R0D
K9F5608U0D

Figure 1-1. K9F5608X0D FUNCTIONAL BLOCK DIAGRAM

VCC

SS

V

K9F5608D0D

FLASH MEMORY

A9 - A24

A0 - A7

X-Buffers
Latches
& Decoders

Y-Buffers
Latches
& Decoders

A8

Command

Command

Register

CE
RE
WE

Control Logic

& High Voltage

Generator

CLE ALE

WP

Figure 2-1. K9F5608X0D ARRAY ORGANIZATION

256M + 8M Bit

NAND Flash

ARRAY

(512 + 16)Byte x 65536

Page Register & S/A

Y-Gat ing

I/O Buffers & Latches

Global Buffers

1 Block =32 Pages
= (16K + 512) Byte

Output

Driver

VCC/VCCQ
VSS

I/0 0

I/0 7

64K Pages
(=2,048 Blocks)

1st half Page Register

(=256 Bytes)

512Byte 16 Byte

2nd half Page Register

(=256 Bytes)

Page Register

512 Byte

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

8 is set to "Low" or "High" by the 00h or 01h Command.

* A

* The device ignores any additional input of address cycles than required.

0 A1 A2 A3 A4 A5 A6 A7

1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits

8 bit

I/O 0 ~ I/O 7

16 Byte

Column Address
Row Address

(Page Address)

8

K9F5608R0D
K9F5608U0D

K9F5608D0D

PRODUCT INTRODUCTION

The K9F5608X0D is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are
located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations.The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND struc­tured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in
Figure 2-1. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis.
The memory array consists of 2048 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited
on the K9F5608X0D.
The K9F5608X0D has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts while providing high perfor­mance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O′s by bringing WE
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com­mands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus.
Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the
other cycle for execution. The 32M-byte physical space requires 24 addresses, thereby requiring three cycles for word-level address­ing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three
address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F5608X0D.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.

to low while CE is low. Data is latched on the rising edge of WE. Command Latch

FLASH MEMORY

Table 1. COMMAND SETS

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 1

Read 2 50h -

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Copy-Back Program 00h 8Ah

Block Erase 60h D0h

Read Status 70h - O

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

00h/01h

-

9

K9F5608R0D
K9F5608U0D

K9F5608D0D

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

VIN/OUT -0.6 to + 4.6

Voltage on any pin relative to V

Temperature Under Bias

Storage Temperature

Short Circuit Current Ios 5 mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

SS

K9F5608X0D-XCB0

K9F5608X0D-XIB0 -40 to +125

K9F5608X0D-XCB0

K9F5608X0D-XIB0

CC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

V

CC -0.6 to + 4.6

V

CCQ -0.6 to + 4.6

T

BIAS

T

STG -65 to +150 °C

-10 to +125

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C)

Parameter Symbol

Supply Voltage V

Supply Voltage V

Supply Voltage V

K9F5608R0D(1.8V)

Min Ty p. Max Min Typ. Max Min Typ. Max

CC 1.65 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 V

CCQ 1.65 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 V

SS 0000 0 0000 V

K9F5608D0D(2.65V) K9F5608U0D(3.3V)

FLASH MEMORY

V

°C

Unit

10

K9F5608R0D
K9F5608U0D

K9F5608D0D

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions

Min Typ Max Min Typ Max Min Typ Max

Operat-

Current

Sequential
Read

ing

Program I

Erase I

Stand-by Current(TTL) I

Stand-by Cur­rent(CMOS)

Input Leakage Current I

Output Leakage Current I

Input High Voltage V

Input Low Voltage, All
inputs

Output High Voltage

Level

Output Low Voltage

Level

Output Low Current(R/B

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

)IOL(R/B)

tRC=50ns, CE

I

CC1

IOUT=0mA

CC2 - - 8 20 - 10 20 - 10 25

CC3 - - 8 20 - 10 20 - 10 25

SB1CE=VIH, WP=0V/VCC --1--1--1

I

SB2CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50 - 10 50

LI VIN=0 to Vcc(max) - - ±10 - - ±10 - - ±10

LO VOUT=0 to Vcc(max) - - ±10 - - ±10 - - ±10

I/O pins

IH*

Except I/O pins

V

IL* - -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8

K9F5608R0D :IOH=-100µA

VOH

K9F5608D0D :I

K9F5608U0D :I

=VIL

OH=-100µA

OH=-400µA

- 8 20 - 10 20 - 10 20

Q

-

-

--

V

+0.3

V

+0.3

CCQ

CC

Vcc

-0.4

V

-0.4

CCQ

V

-0.1

CC

K9F5608R0D :IOL=100uA

V

OL

K9F5608D0D :I

K9F5608U0D :I

K9F5608R0D :V

K9F5608D0D :V

K9F5608U0D :V

OL=100µA

OL=2.1mA

OL=0.1V

OL=0.1V

OL=0.4V

- - 0.1 - - 0.4 - - 0.4

34- 34 - 810-mA

FLASH MEMORY

K9F5608X0D

V

-0.4

V

-0.4

V

-0.4

CCQ

CC

CCQ

V

CCQ

-

-

+0.3

V

CC

+0.3

2.0 -

2.0 -

--2.4--

V

CCQ

+0.3

V

+0.3

Unit1.8V 2.65V 3.3V

mA

µA

CC

V

11

K9F5608R0D
K9F5608U0D

K9F5608D0D

VALID BLOCK

Parameter Symbol Min Ty p. Max Unit

Valid Block Number N

NOTE :

device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-

1. The
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase

cycles.

Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.

3.

VB 2013 - 2048 Blocks

AC TEST CONDITION

(K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C
K9F5608R0D : Vcc=1.65V~1.95V , K9F5608D0D : Vcc=2.4V~2.9V , K9F5608U0D : Vcc=2.7V~3.6V unless otherwise noted)

Parameter K9F5608R0D K9F5608D0D K9F5608U0D

Input Pulse Levels 0V to Vcc

Input Rise and Fall Times 5ns 5ns 5ns

Input and Output Timing Levels Vcc

K9F5608R0D:Output Load (Vcc
K9F5608D0D:Output Load (Vcc
K9F5608U0D:Output Load (Vcc

K9F5608U0D:Output Load (Vcc

Q:1.8V +/-10%)
Q:2.65V +/-10%)
Q:3.0V +/-10%)

Q:3.3V +/-10%) - - 1 TTL GATE and CL=100pF

1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

Q 0V to VccQ 0.4V to 2.4V

Q/2 VccQ/2 1.5V

FLASH MEMORY

. Do not erase or program

CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance C

Input Capacitance C

NOTE : Capacitance is periodically sampled and not 100% tested.

I/O VIL=0V - 10 pF

IN VIN=0V - 10 pF

MODE SELECTION

CLE ALE CE WE RE WP Mode

HL L H X

Read Mode

L H L H X Address Input(3clock)

HL L H H

Write Mode

L H L H H Address Input(3clock)

L L L H H Data Input

L L L H X Data Output

L L L H H X During Read(Busy)

XX X X H X

During Read(Busy) on the devices except

K9F5608D0D_Y,P

X X X X X H During Program(Busy)

X X X X X H During Erase(Busy)

X

(1)

X

XX H X X

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

X X X L Write Protect

(2)

CC

Stand-by

0V/V

Command Input

Command Input

On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P

On K9F5608U0D_Y,P,V,F or

12

K9F5608R0D
K9F5608U0D

K9F5608D0D

PROGRAM/ERASE CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Program Time t

Number of Partial Program Cycles
in the Same Page

Block Erase Time t

Main Array

Spare Array - - 3 cycles

PROG - 200 500 µs

Nop

BERS -23ms

--2cycles

AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT

Parameter Symbol Min Max Unit

CLE setup Time t

CLE Hold Time t

setup Time tCS 0-ns

CE

CE

Hold Time tCH 10 - ns

WE

Pulse Width tWP

ALE setup Time t

ALE Hold Time t

Data setup Time t

Data Hold Time t

Write Cycle Time t

High Hold Time tWH 15 - ns

WE

Address to Data Loading Time t

NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

CLS 0-ns

CLH 10 - ns

(1)

25

ALS 0-ns

ALH 10 - ns

DS 20 - ns

DH 10 - ns

WC 50 - ns

ADL 100 - ns

FLASH MEMORY

-ns

13

K9F5608R0D
K9F5608U0D

K9F5608D0D

AC CHARACTERISTICS FOR OPERATION

Parameter Symbol Min Max Unit

Data Transfer from Cell to Register t

ALE to RE

CLE to RE

Ready to RE

Delay tAR 10 - ns

Delay tCLR 10 - ns

Low tRR 20 - ns

RE Pulse Width t

WE High to Busy t

Read Cycle Time t

Access Time tREA -

RE

CE

Access Time tCEA -45ns

RE

High to Output Hi-Z tRHZ -30ns

CE

High to Output Hi-Z tCHZ -20ns

or CE High to Output hold tOH 15 - ns

RE

RE

High Hold Time tREH 15 - ns

Output Hi-Z to RE

WE

High to RE Low tWHR 60 - ns

Device Resetting Time

Low tIR 0-ns

(Read/Program/Erase) tRST -

R -15µs

RP 25 - ns

WB - 100 ns

RC 50 - ns

FLASH MEMORY

30/35

5/10/500

(1)

(2)

ns

µs

Symbol Min Max Uni

K9F5608U0D­P, F o r
K9F5608D0D-­P only

NOTE: 1. K9F5608R0D tREA = 35ns.

2. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

3. The time to Ready depends on the value of the pull-up resistor tied R/B

4. To break the sequential read cycle, CE

Last RE High to Busy(at sequential read) t

CE

High to Ready(in case of interception by CE at tCRY -

CE

High Hold Time(at the last serial read)

must be held high for longer time than tCEH.

(4)

pin.

RB - 100 ns

tCEH 100 - ns

50 +tr(R/B

(3)

)

ns

14

K9F5608R0D
K9F5608U0D

K9F5608D0D

NAND Flash Technical Notes

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction

Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial
invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.

Start

FLASH MEMORY

up to 1K Program/Erase cycles.

Increment Block Address

Create (or update)

Initial

Invalid Block(s) Table

Figure 3. Flow chart to create initial invalid block table.

Set Block Address = 0

No

No

Check "FFh" ?

Yes

Last Block ?

Yes

End

Check "FFh" at the column address
517of the 1st and 2nd page in the block

*

15

K9F5608R0D
K9F5608U0D

K9F5608D0D

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail­ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be
reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode Detection and Countermeasure sequence

Write

Read Single Bit Failure Verify ECC -> ECC Correction

Erase Failure Status Read after Erase --> Block Replacement

Program Failure Status Read after Program --> Block Replacement

FLASH MEMORY

ECC

Program Flow Chart

: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection

Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

No

*

Program Error

No

I/O 0 = 0 ?

Program Completed

Yes

Yes

: If program operation results in an error, map out

*

the block including the page in error and copy the
target data to another block.

16

K9F5608R0D
K9F5608U0D

NAND Flash Technical Notes (Continued)

K9F5608D0D

FLASH MEMORY

Erase Flow Chart

*

Erase Error

No

Start

Write 60h

Write Block Address

Write D0h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

Yes

I/O 0 = 0 ?

Yes

No

Read Flow Chart

Reclaim the Error

Start

Write 00h

Write Address

Read Data

ECC Generation

No

Verify ECC

Yes

Page Read Completed

Erase Completed

: If erase operation results in an error, map out

*

the failing block and replace it with another block.

Block Replacement

Block A

1st

∼

{

(n-1)th

nth

(page)

1st

∼

(n-1)th

nth

(page)

* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

an error occurs.

Block B

{

2

Buffer memory of the controller.

1

17

K9F5608R0D
K9F5608U0D

K9F5608D0D

Pointer Operation of K9F5608X0D(X8)

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.

Table 2. Destination of the pointer

Command Pointer position Area

00h
01h
50h

0 ~ 255 byte

256 ~ 511 byte

512 ~ 527 byte

1st half array(A)

2nd half array(B)

spare array(C)

"A" area

(00h plane)

256 Byte

"A" "B" "C"

FLASH MEMORY

"B" area

(01h plane)

256 Byte

"C" area

(50h plane)

16 Byte

Internal

Page Register

(1) Command input sequence for programming ’A’ area

The address pointer is set to ’A’ area(0~255), and sustained

Address / Data input

00h

’A’,’B’,’C’ area can be programmed.
It depends on how many data are inputted.

80h 10h 00h 80h 10h

(2) Command input sequence for programming ’B’ area

The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.

Address / Data input

01h

’B’, ’C’ area can be programmed.
It depends on how many data are inputted.

80h 10h 01h 80h 10h

(3) Command input sequence for programming ’C’ area

Pointer select
commnad
(00h, 01h, 50h)

Pointer

Figure 4. Block Diagram of Pointer Operation

Address / Data input

’00h’ command can be omitted.

Address / Data input

’01h’ command must be rewritten before
every program operation

The address pointer is set to ’C’ area(512~527), and sustained

Address / Data input

50h

Only ’C’ area can be programmed.

80h 10h 50h 80h 10h

Address / Data input

’50h’ command can be omitted.

18

K9F5608R0D
K9F5608U0D

K9F5608D0D

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE
ing would provide significant savings in power consumption.

Figure 6. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

FLASH MEMORY

during the data-loading and read-

WE

ALE

I/Ox

tCS

CE

WE

Start Add.(3Cycle)80h Data Input

tWP

Figure 7. Read Operation with CE

CLE

CE

On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR

tCH

don’t-care.

≈

CE

RE

I/O0~7

tCEA

don’t-care

CE

tREA

≈

Data Input

out

10h

tOH

RE

ALE

R/B

WE

I/Ox

≈

tR

Start Add.(3Cycle)00h

19

Data Output(sequential)

K9F5608R0D
K9F5608U0D

K9F5608D0D

FLASH MEMORY

Device

K9F5608X0D(X8 device) I/O 0 ~ I/O 7 ~528byte

NOTE: 1. I/O8~15 must be set to "0" during command or address input.

I/O8~15 are used only for data bus.

I/O DATA

I/Ox Data In/Out

Command Latch Cycle

CLE

tCLS

tCS

CE

tWP

WE

tALS

ALE

tCLH

tCH

tALH

I/Ox

Address Latch Cycle

CLE

CE

WE

ALE

tCLS

tCS

tALS

tWP

tWC

tDS

tDS

Command

tWH

tALH

tDH

tALS

tDH

tWP

tDS

tWC

tALH

tDH

tWH

tALS

tWP

tDS

tCH

tALH

tDH

I/Ox

AO~A7

A17~A24A9~A16

20

K9F5608R0D
K9F5608U0D

Input Data Latch Cycle

CLE

CE

K9F5608D0D

FLASH MEMORY

tCLH

tCH

tWP

tWC

tDS

DIN 0

tDH

tWH

tWP

tDS

DIN 1

≈

tDH

tALS

ALE

WE

I/Ox

Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)

tREA

tRC

tREH

tREA

tRP

CE

RE

tWP

tDH

tDS

≈

DIN n

≈

≈≈≈≈

tREA

tCHZ*

tOH

I/Ox

R/B

tRHZ*

Dout

tRR

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

Dout

21

tRHZ*

tOH

Dout

K9F5608R0D
K9F5608U0D

Status Read Cycle

CLE

CE

WE

RE

K9F5608D0D

tCLS

tCS

tWP

tDS

tCLH

tCH

tDH

tCLR

tWHR1

tIR

tCEA

tREA

FLASH MEMORY

tCHZ

tOH

tRHZ

tOH

I/Ox

Read1 Operation (Read One Page)

CLE

CE

tWC

WE

ALE

RE

I/Ox

R/B

N Address

Read
CMD

A0~A7

Column
Address

m = 528 , Read CMD = 00h or 01h

A9~A16 A17~A24

Page(Row)
Address

70h

tWB

On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR

tAR

tR

tRC

tRR

Dout N Dout N+1

Busy

NOTES : 1) is only valid On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P

Dout N+2

Status Output

Dout N+3

1)
tCEH

tCHZ
tOH

tCRY

tRHZ

tOH

≈

≈≈

Dout m

tRB

1)

22

K9F5608R0D
K9F5608U0D

Read1 Operation (Intercepted by CE)

CLE

CE

WE

ALE

K9F5608D0D

tWB

On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P

must be held

CE
low during tR

tAR

FLASH MEMORY

tCHZ
tOH

RE

I/Ox

Read

CMD

N Address

Col. Add

Column
Address

Row Add1

Page(Row)
Address

R/B

Read2 Operation (Read One Page)

CLE

CE

WE

ALE

RE

Row Add2

tWB

tR

tRR

Busy

tRC

Dout N Dout N+1

On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR

tR

tAR

tRR

Dout N+2

Dout N+3

≈

I/Ox

R/B

50h

Col. Add

Row Add1 Row Add2

M Address

0~A3 are Valid Address & A4~A7 are Don′t care

A

23

Dout

n+M

Selected
Row

n = 512, m = 16

Dout

n+M+1

n

Dout n+m

≈

m

Start
address M

K9F5608R0D
K9F5608U0D

Sequential Row Read Operation (only for On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)

CLE

CE

WE

ALE

K9F5608D0D

FLASH MEMORY

RE

I/Ox

00h

Row Add1

Col. Add

R/B

M

Page Program Operation

CLE

CE

tWC

Row Add2

≈

Dout

Dout

N

Ready

Busy Busy

N

tWC

N+1

Dout
N+2

M+1

Output

tWC

≈≈

Dout

≈

527

≈

Dout1Dout2Dout

Dout

0

527

≈

Output

WE

ALE

RE

I/Ox

R/B

tADL

tWB

tPROG

N Address

≈≈

80h 70h I/O0

Sequential Data
Input Command

Col. Add

Column
Address

Row Add1

Row Add2

Page(Row)

Address

DinNDin

1 up to m Data
Serial Input

N+1

Din

m

m = 528 byte

10h

Program
Command

Read Status
Command

≈

I/O

0=0 Successful Program
0=1 Error in Program

I/O

24

K9F5608R0D
K9F5608U0D

Copy-Back Program Operation

CLE

CE

K9F5608D0D

tWC

FLASH MEMORY

WE

tWB

ALE

RE

I/Ox

00h 70h I/O0

Col. Add

Column

Address

Row Add1 Row Add2

Page(Row)

Address

R/B

Block Erase Operation (Erase One Block)

CLE

CE

tWC

tR

Busy

≈

8Ah

Program

Command

A0~A7 A17~A24A9~A16

Column
Address

Page(Row)

Address

tWB

tPROG

≈

Busy

Read Status
Command

I/O

0=0 Successful Program

I/O

0=1 Error in Program

WE

ALE

RE

I/Ox

R/B

A9~A16 A17~A24

60h

Auto Block Erase
Setup Command

Page(Row)

Address

tWB

D0h 70h I/O 0

tBERS

Busy

≈

Erase Command Read Status

25

Command

0=0 Successful Erase

I/O
I/O

0=1 Error in Erase

K9F5608R0D
K9F5608U0D

Manufacture & Device ID Read Operation

CLE

CE

WE

ALE

RE

I/Ox

K9F5608D0D

90h

Read ID Command Maker Code Device Code

00h

Address. 1cycle

tAR

tREA

ECh

FLASH MEMORY

Device
Code*

Device Device Code*

K9F5608R0D 35h

K9F5608D0D 75h

K9F5608U0D 75h

26

K9F5608R0D
K9F5608U0D

K9F5608D0D

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis­ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera­tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 byte of data within the selected page are transferred
to the data registers in less than 15µs(t
output of R/B
RE

. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Addresses A
the starting address of the spare area while addresses A
to the main area. Figures 8,9 show typical sequence and timings for each read operation.

pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing

R). The system controller can detect the completion of this data transfer(tR) by analyzing the

4~A7 are ignored . The Read1 command is needed to move the pointer back

FLASH MEMORY

0~A3 set

Sequential Row Read is available only on

After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 15µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operations are allowed only within a block and after the last page
of a block being readout, the sequential read operation must be terminated by bringing CE
the next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row
read operation.

K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P :

high. Unless the operation

high. When the page address moves onto

Figure8. Read1 Operation

CLE

On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held

CE

WE

ALE

tR

R/B

low during tR

RE

I/Ox

NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.

Start Add.(3Cycle)

00h

A0 ~ A7 & A9 ~ A24

(00h Command)

Main array

Data Field Spare Field

Data Output(Sequential)

1)

(01h Command)

1st half array 2st half array

Data Field Spare Field

27

K9F5608R0D
K9F5608U0D

Figure 9. Read2 Operation

CLE

CE

WE

ALE

K9F5608D0D

On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR

FLASH MEMORY

R/B

tR

RE

I/Ox

A4 ~ A7 Don’t care

50h

Start Add.(3Cycle)

Data Output(Sequential)

Spare Field

Main array

Data Field Spare Field

Figure 8-1. Sequential Row Read1 Operation (only for K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)

R/B

tR

tR

≈

tR

I/Ox

00h

01h

Start Add.(3Cycle)

0 ~ A7 & A9 ~ A24

A

Block

(00h Command)

1st half array 2nd half array

Data Field Spare Field

Data Output Data Output Data Output

1st 2nd Nth

1st half array 2nd half array

1st
2nd
Nth

(528 Byte) (528 Byte)

(01h Command)

1st
2nd
Nth

Data Field Spare Field

28

K9F5608R0D
K9F5608U0D

K9F5608D0D

Figure 9-1. Sequential Row Read2 Operation (only for K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)

FLASH MEMORY

R/B

I/Ox

50h

(A4 ~ A7 :
Don

Start Add.(3Cycle)

A0 ~ A3 & A9 ~ A24

′t Care)

tR

Data Output

1st

Data Field Spare Field

tR

1st
Block

Nth

≈

Data Output

2nd Nth

(16Byte) (16Byte)

tR

Data Output

29

K9F5608R0D
K9F5608U0D

K9F5608D0D

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the
same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be
done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data
may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm com­mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro­gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE
itoring the R/B
while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read
Status command mode until another valid command is written to the command register.

and CE low, to read the status register. The system controller can detect the completion of a program cycle by mon-

output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid

Figure 10. Program Operation

FLASH MEMORY

R/B

tPROG

I/Ox

80h

Address & Data Input

10h 70h

I/O0

Fail

Pass

COPY-BACK PROGRAM

The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution
of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with
"00h" command with the address of the source page moves the whole 528bytes data into the internal buffer. As soon as the Flash
returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed. The
data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back Pro­gram is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory array is
internally partitioned into two different planes, copy-back program is allowed only within the same memory plane. Thus, A14, the
plane address, of source and destination page address must be the same."When there is a program-failure at Copy-Back opera-

tion, error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back
operations could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation."

Figure 11. Copy-Back Program Operation

R/B

I/Ox

00h

Add.(3Cycles)

Source Address

tR

8Ah 70h

Add.(3Cycles)

Destination Address

tPROG

I/O0

Fail

Pass

30

K9F5608R0D
K9F5608U0D

K9F5608D0D

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com­mand(60h). Only address A
loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory
contents are not accidentally erased due to external noise conditions.
At the rising edge of WE
erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.

14 to A24 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address

after the erase confirm command input, the internal write controller handles erase and erase-verify. When the

Figure 12. Block Erase Operation

FLASH MEMORY

R/B

tBERS

I/Ox

60h

Address Input(2Cycle)

Block Add. : A9 ~ A24

D0h

70h

I/O0

Fail

Pass

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE
the system to poll the progress of each device in multiple memory connections even when R/B
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.

or RE, whichever occurs last. This two line control allows

pins are common-wired. RE or CE

Table4. Read Status Register Definition

I/O # Status Definition

I/O 0 Program / Erase

I/O 1

I/O 2 "0"

I/O 3 "0"

I/O 4 "0"

I/O 5 "0"

I/O 6 Device Operation "0" : Busy "1" : Ready

I/O 7 Write Protect "0" : Protected "1" : Not Protected

Reserved for Future

Use

"0" : Successful Program / Erase

"1" : Error in Program / Erase

"0"

31

K9F5608R0D
K9F5608U0D

K9F5608D0D

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.

Figure 13. Read ID Operation

CLE

tCEA

CE

WE

tAR

ALE

RE

FLASH MEMORY

I/Ox

90h

00h

Address. 1cycle Maker code Device code

tWHR1

tREA

ECh

Device Device Code*

K9F5608R0D 35h

K9F5608D0D 75h

K9F5608U0D 75h

Device
Code*

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP
already in reset state a new reset command will not be accepted by the command register. The R/B
after the Reset command is written. Refer to Figure 14 below.

is high. Refer to table 5 for device status after reset operation. If the device is

pin transitions to low for tRST

Figure 14. RESET Operation

R/B

tRST

I/Ox

FFh

Table5. Device Status

Operation Mode Read 1 Waiting for next command

After Power-up After Reset

32

K9F5608R0D
K9F5608U0D

K9F5608D0D

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 15). Its value can
be determined by the following guidance.

VCC

pin is normally high but transitions to low after program or erase command is written to the command reg-

outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)

Rp

R/B

open drain output

ibusy

Ready Vcc

1.8V device - VOL : 0.1V, VOH : VccQ-0.1V

2.65V device - V

3.3V device - V

OL : 0.4V, VOH : VccQ-0.4V

OL : 0.4V, VOH : 2.4V

FLASH MEMORY

VOH

GND

Device

CL

VOL

Busy

tf

Figure 15. Rp vs tr ,tf & Rp vs ibusy

tr

33

K9F5608R0D
K9F5608U0D

K9F5608D0D

FLASH MEMORY

@ Vcc = 1.8V, Ta = 25°C , C

1.7

30

1.7

Ibusy

tr

tf

0.85

60

1.7

300n 3m

tr,tf [s]

200n

100n

1K 2K 3K

90

1.7

L

0.57

= 30pF

120

0.43

1.7

4K

Rp(ohm)

@ Vcc = 2.65V, Ta = 25°C , C

300n 3m

tr,tf [s]

200n

100n

2.3

30

2.3

Ibusy

tr

tf

1.1

60

0.75

2.3

90

2.3

= 30pF

L

120

2.3

0.55

2m

1m

2m

1m

Ibusy [A]

Ibusy [A]

Rp value guidance

Rp(min, 1.8V part) =

Rp(min, 2.65V part) =

Rp(min, 3.3V part) =

1K 2K 3K

4K

Rp(ohm)

@ Vcc = 3.3V, Ta = 25°C , C

2.4

300n 3m

tr,tf [s]

200n

Ibusy

1.2

200

300

0.8

= 100pF

L

400

tr

100n

100

3.6

3.6

tf

3.6

1K 2K 3K

0.6

3.6

4K

Rp(ohm)

V

CC(Max.) - VOL(Max.)

IOL + ΣIL

V

CC(Max.) - VOL(Max.)

IOL + ΣIL

CC(Max.) - VOL(Max.)

V

IOL + ΣIL

=

=

=

1.85V

3mA

3mA

8mA

+ ΣIL

2.5V

+ ΣIL

3.2V

+ ΣIL

2m

1m

Ibusy [A]

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

34

K9F5608R0D
K9F5608U0D

K9F5608D0D

Data Protection & Power up sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP
ware protection and is recommended to be kept at V
required before internal circuit gets ready for any command sequences as shown in Figure 16. The two step command sequence for
program/erase provides additional software protection.

IL during power-up and power-down and recovery time of minimum 10µs is

Figure 16. AC Waveforms for Power Transition

FLASH MEMORY

pin provides hard-

VCC

WP

WE

1.8V device : ~ 1.5V

2.65V device : ~ 2.0V

3.3V device : ~ 2.5V

10µs

High

1.8V device : ~ 1.5V

≈

2.65V device : ~ 2.0V

3.3V device : ~ 2.5V

≈

≈≈

35

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