Samsung K9F5608U0M-YIB0, K9F5608U0M-YCB0 Datasheet

K9F5608U0M-YCB0,K9F5608U0M-YIB0

Document Title

32M x 8 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No.

0.0

0.1

0.2

0.3

0.4

0.5

History

Initial issue.

Revised real-time map-out algorithm(refer to technical notes)

1. Changed device name i. KM29U256T -> K9F5608U0M-YCB0 ii. KM29U256IT -> K9F5608U0M-YIB0

1. Changed tWP AC Timing

- If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise tWP may be minimum 25ns.

2. Changed Sequential Row Read operation

- The Sequential Read 1 and 2 operation is allowed only within a block

3. Changed invalid block(s) marking method prior to shipping

- The invalid block(s) information is written the 1st or 2nd page of the invalid block(s) with 00h data

--->The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has 00h data at the column address of 517.

4. Added a new card-type package : K9S5608U0M-MCB0

1. Changed Endurance : 1million -> 100K Program/Erase Cycles

1. Changed package name : K9S5608U0M-MCB0 ->K9F5608U0M-MCB0(Micro Flash Card)

2. Changed invalid block(s) marking method prior to shipping

- The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has 00h data at the column address of 517.

--->The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh data at the column address of 517.

Draft Date

April. 10th 1999

July. 23th 1999

Sep. 15th 1999

Mar. 21th 2000

Apr. 7th 2000

Apr. 29th 2000

Remark

Advanced Information Advanced Information Preliminary

Preliminary

0.6

0.7

1. Removed Micro Flash Card

2. Changed SE pin description

- SE is recommended to coupled to GND or Vcc and should not be toggled during reading or programming.

1. Explain how pointer operation works in detail.

2. Renamed GND input (pin # 6) on behalf of SE (pin # 6)

- The SE input controls the access of the spare area. When SE is high, the spare area is not accessible for reading or programming. SE is rec ommended to be coupled to GND or Vcc and should not be toggled during reading or programming. => Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.

3. Updated operation for tRST timing

- If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

July 17th 2000

Nov. 20th 2000

Final

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

K9F5608U0M-YCB0,K9F5608U0M-YIB0

32M x 8 Bit NAND Flash Memory

GENERAL DESCRIPTIONFEATURES

• Voltage Supply : 2.7V~3.6V

• Organization

- Memory Cell Array : (32M + 1024K)bit x 8bit

- Data Register : (512 + 16)bit x8bit

• Automatic Program and Erase

- Page Program : (512 + 16)Byte

- Block Erase : (16K + 512)Byte

• 528-Byte Page Read Operation

- Random Access : 10µs(Max.)

- Serial Page Access : 50ns(Min.)

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Package :

- K9F5608U0M-YCB0/YIB0 : 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

The K9F5608U0M are a 32M(33,554,432)x8bit NAND Flash Memory with a spare 1,024K(1,048,576)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 528byte page in typically 200µs and an erase operation can be performed in typically 2ms on a 16K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9F5608U0M′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F5608U0M-YCB0/YIB0 is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

FLASH MEMORY

PIN CONFIGURATION

PIN DESCRIPTION

K9F5608U0M-YCB0/YIB0

N.C

GND

R/B RE

CE N.C N.C Vcc Vss N.C N.C

CLE

ALE

WP N.C N.C N.C N.C

5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

N.C

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

N.C

I/O7

I/O6

I/O5

I/O4

N.C

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

Pin Name Pin Function

I/O0 ~ I/O7 Data Input/Outputs

CLE Command Latch Enable ALE Address Latch Enable

CE Chip Enable

RE Read Enable WE Write Enable WP Write Protect

GND GND input for enabling spare area

R/B Ready/Busy output VCC Power VSS Ground N.C No Connection

K9F5608U0M-YCB0,K9F5608U0M-YIB0

Figure 1. FUNCTIONAL BLOCK DIAGRAM

VCC VSS

FLASH MEMORY

A9 - A24

A0 - A7

X-Buffers Latches & Decoders

Y-Buffers Latches & Decoders

Command

CE RE WE

Control Logic

& High Voltage

Generator

CLE ALE

Figure 2. ARRAY ORGANIZATION

256M + 8M Bit

NAND Flash

ARRAY

(512 + 16)Byte x 65536

Page Register & S/A

Y-Gating

I/O Buffers & Latches

Global Buffers

1 Block =32 Pages = (16K + 512) Byte

Output

Driver

VCC VSS

I/0 0 I/0 7

64K Pages (=2,048 Blocks)

1st half Page Register (=256 Bytes)

512Byte 16 Byte

2nd half Page Register (=256 Bytes)

Page Register

512 Byte

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command.

1 Page = 528 Byte 1 Block = 528 Bytes x 32 Pages = (16K + 512) Byte 1 Device = 528Bytes x 32Pages x 2048 Blocks = 264 Mbits

8 bit

I/O 0 ~ I/O 7

16 Byte

Column Address Row Address

(Page Address)

K9F5608U0M-YCB0,K9F5608U0M-YIB0

FLASH MEMORY

PRODUCT INTRODUCTION

The K9F5608U0M is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2,048 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F5608U0M.

The K9F5608U0M has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address loading. The 32M byte physical space requires 25 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F5608U0M.

Table 1. COMMAND SETS

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 1 Read 2 Read ID 90h Reset FFh - O Page Program 80h 10h Block Erase 60h D0h Read Status 70h - O

NOTE : 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle.

2. The 50h command is valid only when the GND inout (pin # 6) is low level.

00h/01h

50h

(1)

(2)

K9F5608U0M-YCB0,K9F5608U0M-YIB0

FLASH MEMORY

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the Busy state during program or erase, CE high is ignored, and does not return the device to standby mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.

GND (Pin # 6)

Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

K9F5608U0M-YCB0,K9F5608U0M-YIB0

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

Voltage on any pin relative to VSS

Temperature Under Bias

Storage Temperature

NOTE :

1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

K9F5608U0M-YCB0

K9F5608U0M-YIB0 -40 to +125

K9F5608U0M-YCB0

K9F5608U0M-YIB0

VIN -0.6 to + 4.6

VCC -0.6 to + 4.6

TBIAS

TSTG -65 to +150 °C

-10 to +125

°C

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F5608U0M-YCB0 :TA=0 to 70°C, K9F5608U0M-YIB0:TA=-40 to 85°C)

Parameter Symbol Min Typ. Max Unit

Supply Voltage VCC 2.7 3.3 3.6 V Supply Voltage VSS 0 0 0 V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions Min Typ Max Unit

Operating

Current

Stand-by Current(TTL) ISB1

Stand-by Current(CMOS) ISB2

Input Leakage Current ILI VIN=0 to 3.6V - - ±10 Output Leakage Current ILO VOUT=0 to 3.6V - - ±10 Input High Voltage VIH - 2.0 - VCC+0.3 Input Low Voltage, All inputs VIL - -0.3 - 0.8 Output High Voltage Level VOH IOH=-400µA 2.4 - - Output Low Voltage Level Output Low Current(R/B) IOL(R/B) VOL=0.4V 8 10 - mA

Sequential Read ICC1 tRC=50ns, CE=VIL, IOUT=0mA - 10 20 Program ICC2 - - 10 20 Erase ICC3 - - 10 20

CE=VIH, WP=GND input (Pin #6) = 0V/VCC

CE=VCC-0.2, WP=GND input (Pin #6) = 0V/VCC

VOL IOL=2.1mA - - 0.4

- - 1

- 10 50

µA

K9F5608U0M-YCB0,K9F5608U0M-YIB0

FLASH MEMORY

VALID BLOCK

Parameter Symbol Min Typ. Max Unit

Valid Block Number NVB 2013 - 2048 Blocks

NOTE :

1. The K9F5608U0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try

to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block

AC TEST CONDITION

(K9F5608U0M-YCB0 :TA=0 to 70°C, K9F5608U0M-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise)

Parameter Value

Input Pulse Levels 0.4V to 2.4V Input Rise and Fall Times

5ns Input and Output Timing Levels 1.5V Output Load (3.0V +/-10%) 1 TTL GATE and CL=50pF Output Load (3.3V +/-10%) 1 TTL GATE and CL=100pF

CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE ALE CE WE RE GND WP Mode

H L L H X X

Read Mode

Command Input L H L H X X Address Input(3clock) H L L H X H

Write Mode

Command Input L H L H X H Address Input(3clock) L L L H L L L H L L L H H X X X X X

L/H L/H L/H L/H

(3)

H Data Input X Sequential Read & Data Output X During Read(Busy)

H During Program(Busy) X X X X X X H During Erase(Busy) X X X H X X

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

3. When GND input is high, spare area is deselected.

(1)

X X X X L Write Protect

0V/VCC

(2)

0V/VCC

(2)

Stand-by

Program/Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time tPROG - 200 500 µs Number of Partial Program Cycles

in the Same Page

Main Array

Spare Array - - 3 cycles

Nop

Block Erase Time tBERS - 2 3 ms

- - 2 cycles

K9F5608U0M-YCB0,K9F5608U0M-YIB0

FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

Parameter Symbol Min Max Unit

CLE Set-up Time tCLS 0 - ns CLE Hold Time tCLH 10 - ns CE Setup Time tCS 0 - ns CE Hold Time tCH 10 - ns WE Pulse Width tWP ALE Setup Time tALS 0 - ns ALE Hold Time tALH 10 - ns Data Setup Time tDS 20 - ns Data Hold Time Write Cycle Time tWC 50 - ns WE High Hold Time tWH 15 - ns

NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

tDH 10 - ns

(1)

- ns

AC Characteristics for Operation

Parameter Symbol Min Max Unit

Data Transfer from Cell to Register tR - 10 µs ALE to RE Delay( ID read ) tAR1 100 - ns ALE to RE Delay(Read cycle) tAR2 50 - ns CE to RE Delay( ID read) tCR 100 - ns Ready to RE Low tRR 20 - ns RE Pulse Width tRP 30 - ns WE High to Busy tWB - 100 ns Read Cycle Time tRC 50 - ns RE Access Time tREA - 35 ns RE High to Output Hi-Z tRHZ 15 30 ns CE High to Output Hi-Z tCHZ - 20 ns RE High Hold Time tREH 15 - ns Output Hi-Z to RE Low tIR 0 - ns Last RE High to Busy(at sequential read) tRB - 100 ns CE High to Ready(in case of interception by CE at read) tCRY CE High Hold Time(at the last serial read) RE Low to Status Output tRSTO - 35 CE Low to Status Output tCSTO - 45 ns WE High to RE Low tWHR 60 - ns RE access time(Read ID) tREADID - 35 ns Device Resetting Time(Read/Program/Erase) tRST - 5/10/500 µs

NOTE :

1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

2. To break the sequential read cycle, CE must be held high for longer time than tCEH.

3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

(2)

tCEH 100 - ns

50 +tr(R/B)

(1)

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