Samsung K9F3208W0A-TIB0, K9F3208W0A-TCB0 Datasheet

K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

≈

Document Title

4M x 8 Bit NAND Flash Memory

Revision History

Revision No.

0.0

0.1

0.2

0.3

0.4

0.5

History

Initial issue.

Data Sheet, 1999

1. Added CE don’t care mode during the data-loading and reading

1. Revised real-time map-out algorithm(refer to technical notes)

2. Removed erase suspend/resume mode

1. Changed device name

- KM29W32000AT -> K9F3208W0A-TCB0

- KM29W32000AIT -> K9F3208W0A-TIB0

1. Changed invalid block(s) marking method prior to shipping

- The invalid block(s) information is written the 1st or 2nd page of the
invalid block(s) with 00h data

--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has non-FFh data at the column address of 517.

2. Changed SE pin description

- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.

1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences

~ 2.5V

V

CC

High

WP

≈

≈

~ 2.5V

Draft Date

April 10th 1998

April 10th 1999

July 23th 1999

Sep. 15th 1999

July 17th 2000

July 23th 2001

Remark

Advance

WE

1µ

2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.

3. AC parameter tAR1 value : 150ns --> 20ns

4. #40 Pin Name : nSE --> GND

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html.

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.

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K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

4M x 8 Bit NAND Flash Memory

GENERAL DESCRIPTIONFEATURES

• Voltage Supply : 2.7V ~ 5.5V

• Organization

- Memory Cell Array : (4M + 128K)bit x 8bit

- Data Register : (512 + 16)bit x8bit

• Automatic Program and Erase

- Page Program : (512 + 16)Byte

- Block Erase : (8K + 256)Byte

- Status Register

• 528-Byte Page Read Operation

- Random Access : 10µs(Max.)

- Serial Page Access : 50ns(Min.)

• Fast Write Cycle Time

- Program Time : 250µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 1Million Program/Erase Cycles

- Data Retention : 10 years

• Command Register Operation

• 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)

- Forward Type

The K9F3208W0A is a 4M(4,194,304)x8bit NAND Flash Mem­ory with a spare 128K(131,072)x8bit. Its NAND cell provides
the most cost-effective solution for the solid state mass storage
market. A program operation programs the 528-byte page in
typical 250µs and an erase operation can be performed in typi­cal 2ms on an 8K-byte block.
Data in the page can be read out at 50ns cycle time per byte.
The I/O pins serve as the ports for address and data input/out­put as well as command inputs. The on-chip write controller
automates all program and erase system functions, including
pulse repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take
advantage of the K9F3208W0A extended reliability of
1,000,000 program/erase cycles by providing ECC(Error Cor­rection Code) with real time mapping-out algorithm. The
K9F3208W0A is an optimum solution for large nonvolatile stor­age application such as solid state storage, digital voice
recorder, digital still camera and other portable applications
requiring nonvolatility.

PIN CONFIGURATION

VSS

1

CLE

2

ALE

3

WE

4

WP

5

N.C

6

N.C

7

N.C

8

N.C

9

N.C

10
11
12

N.C

13

N.C

14

N.C

15

N.C

16

N.C

17

I/O0

18

I/O1

19

I/O2

20

I/O3

21

VSS

22 VCCQ

VCC

44

CE

43

RE

42

R/B

41

GND

40

N.C

39

N.C

38

N.C

37

N.C

36

N.C

35
34
33

N.C

32

N.C

31

N.C

30

N.C

29

N.C

28

I/O7

27

I/O6

26

I/O5

25

I/O4

24
23

PIN DESCRIPTION

44(40) TSOP (II)

STANDARD TYPE

NOTE : Connect all VCC, VCCQ and VSS pins of each device to power supply outputs.

Do not leave VCC or VSS disconnected.

Pin Name Pin Function

I/O0 ~ I/O7 Data Inputs/Outputs

CLE Command Latch Enable
ALE Address Latch Enable

CE Chip Enable

RE Read Enable
WE Write Enable
WP Write Protect

SE Spare area Enable
R/B Ready/Busy output

GND Ground Input

VCC Power(2.7V ~ 5.5V)

VCCQ Output Butter Power(2.7V ~ 5.5V)

VSS Ground
N.C No Connection

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K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

Figure 1. FUNCTIONAL BLOCK DIAGRAM

VCC

VSS

A9 - A21

A0 - A7

Command

CE
RE
WE

X-Buffers
Latches
& Decoders

Y-Buffers
Latches
& Decoders

A8

Command

Register

Control Logic

& High Voltage

Generator

CLE ALE WP

2nd half Page Register & S/A

1st half Page Register & S/A

Y-Gating

32M + 1M Bit

NAND Flash

ARRAY

(512 + 16)Byte x 8192

Y-Gating

I/O Buffers & Latches

Global Buffers

Output

Driver

VCCQ
VSS

I/0 0
I/0 7

Figure 2. ARRAY ORGANIZATION

32M : 8K Pages
(= 512 Blocks)

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 *X *X *X

NOTE : Column Address : Starting Address of the Register.

1st half Page Register
(=256 Bytes)

2nd half Page Register
(=256 Bytes)

512Bytes 16Bytes

Page Register

512Bytes

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

00h Command(Read) : Defines the starting Address of the 1st half of the Register.
01h Command(Read) : Defines the sarting Address of the 2nd half of the Register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* X can be High or Low.
* The device ignores any additional input of address cycles than reguired.

1 Block =16 Pages
= (8K + 256) Byte

1 Page = 528 Bytes
1 Block = 528 B x 16 Pages
= (8K + 256) Bytes
1 Device = 528Bytes x 16Pages x 512 Blocks
= 33 Mbits

8 bit

I/O 0 ~ I/O 7

16Bytes

Column Address
Row Address
(Page Address)

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K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

PRODUCT INTRODUCTION

The K9F3208W0A is a 33Mbit(34,603,008 bit) memory organized as 8192 rows(pages) by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans­fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16
pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 512 separately or grouped erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F3208W0A.

The K9F3208W0A has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 4M byte physical space requires 22 addresses, thereby requiring three cycles for byte-level addressing: col­umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.

Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F3208W0A.

Table 1. COMMAND SETS

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 1
Read 2
Read ID 90h ­Reset FFh - O
Page Program 80h 10h
Block Erase 60h D0h
Read Status 70h - O

NOTE : 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved
to the 1st half register(00h) on the next cycle.

2. The 50h command is valid only when the SE(pin 40) is low level.

00h/01h

50h

(1)

(2)

-

-

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

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K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby
mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.

Spare Area Enable(SE)

The SE input controls the access of the spare area. When SE is high, the spare area is not accessible for reading or programming.
SE is recommended to be coupled to GND or Vcc and should not be toggled during reading or programming.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.

Power Line(VCC & VCCQ)

The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V
tolerant I/O with 5V power supply at VCCQ.

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K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

Voltage on any pin relative to VSS VIN -0.6 to +7.0 V

Temperature Under Bias

Storage Temperature TSTG -65 to +150 °C

NOTE :

1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

K9F3208W0A-TCB0

K9F3208W0A-TIB0 -40 to +125

TBIAS

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F3208W0A-TCB0:TA=0 to 70°C, K9F3208W0A-TIB0:TA=-40 to 85°C)

Parameter Symbol Min Typ. Max Unit

Supply Voltage VCC 2.7 - 5.5 V
Supply Voltage VCCQ 2.7 - 5.5 V
Supply Voltage VSS 0 0 0 V

NOTE : 1. Vcc and VccQ pins are separated each other.

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions

Operating

Current

Stand-by Current(TTL) ISB1 CE=VIH, WP=SE=0V/VCC - - 1 - - 1
Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=SE=0V/VCC - 10 50 - 10 50

Output Leakage Current ILO VOUT=0 to 5.5V - - ±10 - - ±10

Input High Voltage VIH

Input Low Voltage, All inputs VIL - -0.3 - 0.6 -0.3 - 0.8
Output High Voltage Level VOH IOH=-400µA 2.4 - - 2.4 - ­Output Low Voltage Level
Output Low Current(R/B) IOL(R/B) VOL=0.4V 8 10 - 8 10 - mA

Sequential Read ICC1 tRC=80ns, CE=VIL, IOUT=0mA - 10 20 - 15 30
Program ICC2 - - 10 20 - 15 30
Erase ICC3 - - 10 20 - 25 40

I/O pins 2.0 - VCCQ+0.3 3.0 - VCCQ+0.5
Except I/O pins 2.0 - VCC+0.3 3.0 - VCC+0.5

VOL IOL=2.1mA - - 0.4 - - 0.4

Min Typ Max Min Typ Max

-10 to +125

Vcc=2.7V ~ 3.6V Vcc=3.6V ~ 5.5V

°C

Unit

mA

µAInput Leakage Current ILI VIN=0 to 5.5V - - ±10 - - ±10

V

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K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

VALID BLOCK

Parameter Symbol Min Typ. Max Unit

Valid Block Number NVB 502 508 512 Blocks

NOTE :

1. The K9F3208W0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not

erase or program factory-market bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

AC TEST CONDITION

(K9F3208W0A-TCB0:TA=0 to 70°C, K9F3208W0A-TIB0:TA=-40 to 85°C, VCC=2.7V ~ 5.5V unless otherwise noted)

Parameter

Vcc=2.7V ~ 3.6V Vcc=3.6V ~ 5.5V

Input Pulse Levels 0.4V to 2.4V 0.4V to 3.4V
Input Rise and Fall Times 5ns
Input and Output Timing Levels

Output Load

CL=50pF(3.0V+/-10%),100pF(3.0V~3.6V)

1 TTL GATE and

CAPACITANCE(TA=25°C, Vcc=5.0V f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance CI/O VIL=0V - 10 pF
Input Capacitance CIN VIN=0V - 10 pF

NOTE : Capacitance is periodically sampled and not 100% tested.

Value

0.8V and 2.0V

1 TTL GATE and CL=100pF

MODE SELECTION

CLE ALE CE WE RE SE WP Mode

H L L H X X

L H L H X X Address Input(3clock)

H L L H X H

L H L H X H Address Input(3clock)
L L L H
L L L H
L L L H H

X X X X X

L/H
L/H
L/H
L/H

(3)

(3)

(3)

(3)

H

X Sequential Read & Data Output
X During Read(Busy)

H During Program(Busy)

Read Mode

Write Mode

Data Input

Command Input

Command Input

X X X X X X H During Erase(Busy)
X
X X H X X

NOTE : 1. X can be VIL or VIH

2. WP should be biased to CMOS high or CMOS low for standby.

3. When SE is high, spare area is deselected.

(1)

X

X X X X L Write Protect

0V/VCC

(2)

0V/VCC

(2)

Stand-by

Program/Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time tPROG - 0.25 1.5 ms
Number of Partial Program Cycles in the Same Page Nop - - 10 cycles
Block Erase Time tBERS - 2 10 ms

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K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

Parameter Symbol Min Max Unit

CLE Set-up Time tCLS 0 - ns
CLE Hold Time tCLH 10 - ns
CE Setup Time tCS 0 - ns
CE Hold Time
WE Pulse Width tWP 25 - ns
ALE Setup Time tALS 0 - ns
ALE Hold Time
Data Setup Time tDS 20 - ns
Data Hold Time tDH 10 - ns
Write Cycle Time tWC 50 - ns
WE High Hold Time

AC Characteristics for Operation

Parameter Symbol Min Max Unit

Data Transfer from Cell to Register tR - 10 µs
ALE to RE Delay(read ID) tAR1 20 - ns
ALE to RE Delay(Read cycle) tAR2 50 - ns
CLE to RE Delay tCLR 50 - ns
CE to RE Delay(ID read) tCR 100 - ns
Ready to RE Low tRR 20 - ns
RE Pulse Width tRP 30 - ns
WE High to Busy tWB - 100
Read Cycle Time tRC 50 - ns
RE Access Time tREA - 35 ns
RE High to Output Hi-Z tRHZ 15 30 ns
CE High to Output Hi-Z
RE High Hold Time tREH 15 - ns
Output Hi-Z to RE Low tIR 0 - ns
Last RE High to Busy(at sequential read) tRB - 100 ns
CE High to Ready(in case of interception by CE at read) tCRY ­CE High Hold Time(at the last serial read)
RE Low to Status Output tRSTO - 35
CE Low to Status Output tCSTO - 45 ns
RE High to WE Low tRHW 0 - ns
WE High to RE Low tWHR 60 - ns
RE access time(Read ID) tREADID - 35 ns
Device Resetting Time(Read/Program/Erase) tRST - 5/10/500 µs

NOTE :

1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.

2. To break the sequential read cycle, CE must be held high for longer time than tCEH.

(2)

tCH 10 - ns

tALH 10 -

tWH 15 - ns

tCHZ - 20 ns

50 +tr(R/B)

tCEH 100 - ns

(1)

ns

ns

ns

ns

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K9F3208W0A-TCB0, K9F3208W0A-TIB0 FLASH MEMORY

NAND Flash Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor­mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor­mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar­anteed to be a valid block, does not require Error Correction.

Identifying Invalid Block(s)

All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid

block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impos­sible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any inten­tional erasure of the original invalid block information is prohibited.

Start

Increment Block Address

Create (or update)

Invalid Block(s) Table

Set Block Address = 0

Check "FFh" at the column address 517

Yes

Yes

*

of the 1st and 2nd page in the block

No

No

Figure 1. Flow chart to create invalid block table.

Check "FFh" ?

Last Block ?

End

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