SAMSUNG K9F1216U0A Technical data

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

K9F1216U0A
K9F1208U0A

Document Title

64M x 8 Bit , 32M x 16 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

History

Initial issue.

TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed.
(before) 9 x 11 /0.8mm pitch , Width 1.0 mm
(after ) To Be Decided.

TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed.
(before) 9 x 11 /0.8mm pitch , Width 1.0 mm, to
(after) 8.5 x 15 /0.8mm pitch, Width 1.0mm

Pin numbering includes TBGA Dummy ball . (Page5)

Pin numbering excludes TBGA Dummy ball . (Page5)
Pin assignment of TBGA dummy ball is changed.
(before) DNU --> (after) N.C

1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 43)

2. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 44)

The min. Vcc value 1.8V devices is changed.
K9F1208Q0A : Vcc 1.65V~1.95V --> 1.70V~1.95V

Pb-free Package is added.
K9F1208U0A-FCB0,FIB0
K9F1208Q0A-HCB0,HIB0
K9F1216U0A-HCB0,HIB0
K9F1216U0A-PCB0,PIB0
K9F1216Q0A-HCB0,HIB0
K9F1208U0A-HCB0,HIB0
K9F1208U0A-PCB0,PIB0

Draft Date

Apr. 25th 2002

May. 9th 2002

July, 10th 2002

Aug, 10th 2002

Oct, 21th 2002

Nov, 21th 2002

Mar. 5th 2003

Mar. 13rd 2003

Remark

Preliminary

0.8

0.9

1.0

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

Errata is added.(Front Page)-K9F1208Q0A

tWC tWH tWP tRC tREH tRP tREA tCEA
Specification 45 15 25 50 15 25 30 45

Relaxed value 60 20 40 60 20 40 40 55

New definition of the number of invalid blocks is added.
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)

1. 2.65V device is added.

2. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)

Mar. 17th 2003

Apr. 4th 2003

Jul. 4th 2003

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.

1

K9F1216U0A
K9F1208U0A

Document Title

64M x 8 Bit , 32M x 16 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No.

1.1

1.2

1.3

1.4

1.5

Errata is deleted.
AC parameters are changed.-K9F1208Q0A

tWC tWH tWP tRC tREH tRP tREA tCEA
Before 45 15 25 50 15 25 30 45

After 60 20 40 60 20 40 40 55

1. K9F1208Q0A-DC(I)B0,K9F1216Q0A-DC(I)B0, K9F1208D0A-DC(I)B0,
K9F1216D0A-DC(I)B0,K9F1208U0A-DC(I)B0, K9F1216U0A-DC(I)B0 are
deleted.

1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.

1. PKG(TSOP1, WSOP1) Dimension Change

1. NAND Flash Technical Notes is changed.

-Invalid block -> initial invalid block ( page 16 )

-Error in write or read operation ( page 17 )

-Program Flow Chart ( page 17 )

Draft Date

Aug. 1st 2003

Oct. 14th 2003

Apr. 24th 2004

May. 24th 2004

Oct. 25th. 2004

RemarkHistory

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.

2

K9F1216U0A
K9F1208U0A

FLASH MEMORY

64M x 8 Bit / 32M x 16 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F1208U0A-Y,P

K9F1208U0A-V,F WSOP1

K9F1216U0A-Y,P X16 TSOP1

2.7 ~ 3.6V

FEATURES

• Voltage Supply

-2.7 ~ 3.6 V

• Organization

- Memory Cell Array

- X8 device(K9F1208U0A) : (64M + 2048K)bit x 8 bit

- X16 device(K9F1216U0A) : (32M + 1024K)bit x 16bit

- Data Register

- X8 device(K9F1208U0A) : (512 + 16)bit x 8bit

- X16 device(K9F1216U0A) : (256 + 8)bit x16bit

• Automatic Program and Erase

- Page Program

- X8 device(K9F1208U0A) : (512 + 16)Byte

- X16 device(K9F1216U0A) : (256 + 8)Word

- Block Erase :

- X8 device(K9F1208U0A) : (16K + 512)Byte

- X16 device(K9F1216U0A) : ( 8K + 256)Word

• Page Read Operation

- Page Size

- X8 device(K9F1208U0A) : (512 + 16)Byte

- X16 device(K9F1216U0A) : (256 + 8)Word

- Random Access : 12µs(Max.)

- Serial Page Access : 50ns(Min.)

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Intelligent Copy-Back

• Unique ID for Copyright Protection

• Package

- K9F12XXU0A-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F1208U0A-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)

- K9F12XXU0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F1208U0A-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F1208U0A-V,F(WSOPI ) is the same device as
K9F1208U0A-Y,P(TSOP1) except package type.

X8

TSOP1

GENERAL DESCRIPTION

Offered in 64Mx8bit or 32Mx16bit, the K9F12XXU0A is 512M bit with spare 16M bit capacity. The device is offered in 3.3V Vcc. Its
NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed
in typical 200µs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in typical 2ms
on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per byte(X8 device) or
word(X16 device). The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write con­trol automates all program and erase functions including pulse repetition, where required, and internal verification and margining of
data. Even the write-intensive systems can take advantage of the K9F12XXU0A′s extended reliability of 100K program/erase cycles
by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F12XXU0A is an optimum solution for large
nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

3

K9F1216U0A
K9F1208U0A

PIN CONFIGURATION (TSOP1)

K9F12XXU0A-YCB0,PCB0/YIB0,PIB0

X8X16 X16X8

N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE

CE
N.C
N.C
Vcc
Vss
N.C
N.C

CLE
ALE

WE
WP
N.C
N.C
N.C
N.C
N.C

N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE

CE
N.C
N.C
Vcc
Vss
N.C
N.C

CLE
ALE

WE
WP
N.C
N.C
N.C
N.C
N.C

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

FLASH MEMORY

Vss

N.C

I/O15

N.C

I/O7

N.C

I/O14

N.C

I/O6

I/O7

I/O13

I/O6

I/O5

I/O5

I/O12

I/O4

I/O4

N.C

N.C

N.C

N.C

N.C

Vcc

Vcc

N.C

Vss

N.C

N.C

N.C

N.C

I/O11

N.C

I/O3

I/O3

I/O10

I/O2

I/O2

I/O1

I/O9

I/O0

I/O1

N.C

I/O8

N.C

I/O0

N.C

Vss

N.C

48 - TSOP1 - 1220F

+0.07

-0.03

#1

0.20

+0.003

-0.001

+0.07

-0.03

0.16

0.008

0.50

0.0197
#24

TYP

0.25

0.010

0~8°

20.00±0.20

0.787±0.008

18.40±0.10

0.724±0.004

#48

#25

+0.075

0.035

0.125

Unit :mm/Inch

MAX

0.10

0.004

0.25

0.010

()

MAX

12.00

0.472

0.488

12.40

1.00±0.05

0.039±0.002

1.20
MAX

0.047

+0.003

-0.001

0.005

0.05

0.002

MIN

0.45~0.75

0.018~0.030

0.50

()

0.020

4

K9F1216U0A
K9F1208U0A

PIN CONFIGURATION (WSOP1)

K9F1208U0A-VCB0,FCB0/VIB0,FIB0

N.C

N.C

1

N.C

N.C
N.C
N.C
R/B
RE

CE

N.C
Vcc
Vss
N.C

CLE
ALE

WE
WP
N.C
N.C

N.C
N.C

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

DNU

DNU

DNU

DNU

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48

N.C

47

DNU

46

N.C

45

I/O7

44

I/O6

43

I/O5

42

I/O4

41

N.C

40

DNU

39

N.C

38

Vcc

37

Vss

36

N.C

35

DNU

34

N.C

33

I/O3

32

I/O2

31

I/O1

30

I/O0

29

N.C

28

DNU

27

N.C

26

N.C

25

FLASH MEMORY

48 - WSOP1 - 1217F

#1

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP
(0.50±0.06)

#24

15.40±0.10

#48

#25

0.70 MAX

0.58±0.04

(0.01Min)

Unit :mm

12.00±0.10

12.40MAX

17.00±0.20

+0.075

-0.035

0.10

0

°

~

8

°

0.45~0.75

5

K9F1216U0A
K9F1208U0A

PIN DESCRIPTION

Pin Name Pin Function

DATA INPUTS/OUTPUTS

0 ~ I/O7

I/O

(K9F1208X0A)

I/O

0 ~ I/O15

(K9F1216X0A)

The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper­ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.

FLASH MEMORY

CLE

ALE

CE

RE

WE

WP

R/B

Vcc

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE

CHIP ENABLE

The CE

input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE
read operation, refer to ’Page read’ section of Device operation .

READ ENABLE

The RE

input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE

WRITE ENABLE

The WE

input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE

pulse.

WRITE PROTECT

The WP

pin provides inadvertent write/erase protection during power transitions. The internal high voltage

generator is reset when the WP

READY/BUSY OUTPUT

The R/B

output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.

OUTPUT BUFFER POWER

Q

Vcc

Q is the power supply for Output Buffer.

Vcc

Q is internally connected to Vcc, thus should be biased to Vcc.

with ALE high.

control during

which also increments the internal column address counter by one.

pin is active low.

signal.

Vcc

Vss GROUND

N.C

DNU

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

POWER

V

CC is the power supply for device.

NO CONNECTION

Lead is not internally connected.

DO NOT USE

Leave it disconnected.

Do not leave VCC or VSS disconnected.

6

K9F1216U0A
K9F1208U0A

Figure 1-1. K9F1208X0A (X8) FUNCTIONAL BLOCK DIAGRAM

VCC

SS

V

FLASH MEMORY

A9 - A25

X-Buffers
Latches
& Decoders

A0 - A7

Y-Buffers
Latches
& Decoders

(512 + 16)Byte x 131072

Page Register & S/A

A8

Command

Command

CE
RE
WE

Register

Control Logic

& High Voltage

Generator

CLE ALE

WP

I/O Buffers & Latches

Global Buffers

Figure 2-1. K9F1208X0A (X8) ARRAY ORGANIZATION

512M + 16M Bit

NAND Flash

ARRAY

Y-Gatin g

1 Block =32 Pages
= (16K + 512) Byte

Output

Driver

VCC/VCCQ
VSS

I/0 0

I/0 7

128K Pages
(=4,096 Blocks)

1st half Page Register

(=256 Bytes)

2nd half Page Register

(=256 Bytes)

8 bit

512Byte 16 Byte

Page Register

512 Byte

16 Byte

I/O 0 ~ I/O 7

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A

0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

4th Cycle A25 *L *L *L *L *L *L *L

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

* A

8 is set to "Low" or "High" by the 00h or 01h Command.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 4096 Blocks
= 528 Mbits

Column Address
Row Address

(Page Address)

7

K9F1216U0A
K9F1208U0A

Figure 1-2. K9F1216X0A (X16) FUNCTIONAL BLOCK DIAGRAM

VCC

SS

V

FLASH MEMORY

A9 - A25

A0 - A7

Command

CE
RE
WE

X-Buffers
Latches
& Decoders

Y-Buffers
Latches
& Decoders

Command

Register

Control Logic

& High Voltage

Generator

CLE ALE

WP

5126M + 16M Bit

(256 + 8)Word x 131072

Page Register & S/A

I/O Buffers & Latches

Global Buffers

Figure 2-2. K9F1216X0A (X16) ARRAY ORGANIZATION

NAND Flash

ARRAY

Y-Gatin g

1 Block =32 Pages
= (8K + 256) Word

Output

Driver

VCC/VCCQ
VSS

I/0 0

I/0 15

1 Page = 264 Word

128K Pages
(=4,096 Blocks)

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O8 to 15

1st Cycle A

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

4th Cycle A25

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

0 A1 A2 A3 A4 A5 A6 A7

Page Register

(=256 Words)

256Word 8 Word

Page Register

256 Word

8 Word

I/O 0 ~ I/O 15

L* L* L* L* L* L* L* L*

1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 4096 Blocks
= 528 Mbits

16 bit

L*

L*

L*

Column Address

Row Address
(Page Address)

8

K9F1216U0A
K9F1208U0A

Product Introduction

The K9F1208X0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns
are located from column address of 512 to 527. A 528-byte(x8 device), 264word(x16 device) data register is connected to memory
cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The
memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different
page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a
block. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase
operation is executed on a block basis. The memory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the
bit by bit erase operation is prohibited on the K9F1208X0A.

The K9F1208X0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires 26
addresses(X8 device) or 25 addresses(X16 device), thereby requiring four cycles for byte-level addressing: column address, low row
address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required
command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by
writing specific commands into the command register. Table 1 defines the specific commands of the K9F1208X0A.

The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into four 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte(X8 device) or 256 word(X16 device) structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.

to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

FLASH MEMORY

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burst­reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.

Table 1. Command Sets

Function 1st. Cycle 2nd. Cycle 3rd. Cycle

Read 1

00h/01h

(1)

--

Read 2 50h - -

Read ID 90h - -

Reset FFh - - O

Page Program (True)

Page Program (Dummy)

Copy-Back Program(True)

(2)

(2)

(2)

Copy-Back Program(Dummy)

(2)

80h 10h -

80h 11h -

00h 8Ah 10h

03h 8Ah 11h

Block Erase 60h D0h -

Multi-Plane Block Erase 60h----60h D0h -

Read Status 70h - - O

Read Multi-Plane Status

71h

(3)

-- O

Acceptable Command

during Busy

NOTE : 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer is

automatically moved to the 1st half register(00h) on the next cycle.

2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.

Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation.

3. The 71h command should be used for read status of Multi Plane operation.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

9

K9F1216U0A
K9F1208U0A

Memory Map

The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte(X8 device) or 264 word(X16
device) page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from
each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four
sequential blocks.

Figure 3. Memory Array Map

FLASH MEMORY

Plane 0
(1024 Block)

Block 0

Page 0

Page 1

Page 30

Page 31

Block 4

Page 0

Page 1

Page 30

Page 31

Block 4088

Page 0

Page 1

Plane 1
(1024 Block)

Block 1

Page 0

Page 1

Page 30

Page 31

Block 5

Page 0

Page 1

Page 30

Page 31

Block 4089

Page 0

Page 1

Plane 2
(1024 Block)

Block 2

Page 0

Page 1

Page 30

Page 31

Block 6

Page 0

Page 1

Page 30

Page 31

Block 4090

Page 0

Page 1

Plane 3
(1024 Block)

Block 3

Page 0

Page 1

Page 30

Page 31

Block 7

Page 0

Page 1

Page 30

Page 31

Block 4091

Page 0

Page 1

Page 30

Page 31

Block 4092

Page 0

Page 1

Page 30

Page 31

528byte Page Registers

Page 30

Page 31

Block 4093

Page 0

Page 1

Page 30

Page 31

528byte Page Registers 528byte Page Registers 528byte Page Registers

Page 30

Page 31

Block 4094

Page 0

Page 1

Page 30

Page 31

Page 30

Page 31

Block 4095

Page 0

Page 1

Page 30

Page 31

10

K9F1216U0A
K9F1208U0A

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

VIN/OUT -0.6 to + 4.6

Voltage on any pin relative to V

Temperature Under Bias

Storage Temperature

Short Circuit Current Ios 5 mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F12XXU0A-XCB0 :TA=0 to 70°C, K9F12XXU0A-XIB0:TA=-40 to 85°C)

Parameter Symbol Min Typ . Max Unit

Supply Voltage V

Supply Voltage V

Supply Voltage V

SS

K9F12XXU0A-XCB0

K9F12XXU0A-XIB0 -40 to +125

K9F12XXU0A-XCB0

K9F12XXU0A-XIB0

CC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

CC 2.7 3.3 3.6 V

CCQ 2.7 3.3 3.6 V

SS 000V

V

CC -0.6 to + 4.6

V

CCQ -0.6 to + 4.6

T

BIAS

T

STG -65 to +150 °C

FLASH MEMORY

-10 to +125

V

°C

11

K9F1216U0A
K9F1208U0A

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions Min Ty p Max Min Typ Max Unit

Operating

Current

Sequential Read I

Program I

Erase I

Stand-by Current(TTL) I

Stand-by Current(CMOS) I

Input Leakage Current I

Output Leakage Current I

tRC=50ns, CE

CC1

IOUT=0mA

CC2 - - 10 20 - 10 20

CC3 - - 10 20 - 10 20

SB1CE=VIH, WP=0V/VCC --1--1

SB2CE=VCC-0.2, WP=0V/VCC - 10 50 - 10 50

LI VIN=0 to Vcc(max) - - ±10 - - ±10

LO VOUT=0 to Vcc(max) - - ±10 - - ±10

I/O pins

Input High Voltage V

IH*

Except I/O pins

Input Low Voltage, All inputs V

Output High Voltage Level V

Output Low Voltage Level V

Output Low Current(R/B

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

)IOL(R/B)VOL=0.4V 3 4 - 8 10 - mA

IL* - -0.3 - 0.5 -0.3 - 0.8

OH IOH=-400µA

OL IOL=2.1mA - - 0.4 - - 0.4

=VIL

- 10 20 - 10 20

V

-0.4

V

-0.4

V

-0.4

CCQ

CCQ

-

CC

-

--2.4--

FLASH MEMORY

V

CCQ

CC

2.0 -

2.0 -

+0.3

V

+0.3

V

CCQ

+0.3

V

+0.3

CC

mA

µA

V

12

K9F1216U0A
K9F1208U0A

VALID BLOCK

Parameter Symbol Min Typ . Max Unit

Valid Block Number N

NOTE :

1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-

sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase
cycles.

3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.

AC TEST CONDITION

(K9F12XXU0A-XCB0 :TA=0 to 70°C, K9F12XXU0A-XIB0:TA=-40 to 85°C, K9F12XXU0A : Vcc=2.7V~3.6V unless otherwise noted)

Input Pulse Levels 0.4V to 2.4V

Input Rise and Fall Times 5ns

Input and Output Timing Levels 1.5V

K9F12XXU0A:Output Load (Vcc

K9F12XXU0A:Output Load (Vcc

Q:3.0V +/-10%) 1 TTL GATE and CL=50pF

Q:3.3V +/-10%) 1 TTL GATE and CL=100pF

VB 4,026 - 4,096 Blocks

Parameter K9F12XXU0A

FLASH MEMORY

. Do not erase or program

CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance C

Input Capacitance C

NOTE : Capacitance is periodically sampled and not 100% tested.

I/O VIL=0V - 10 pF

IN VIN=0V - 10 pF

MODE SELECTION

CLE ALE CE WE RE WP Mode

HLL HX

Read Mode

L H L H X Address Input(4clock)

HLL HH

Write Mode

L H L H H Address Input(4clock)

L L L H H Data Input

L L L H X Data Output

L L L H H X During Read(Busy) on K9F1208U0A-Y,P,V,F

X X X X H X During Read(Busy) on the devices except K9F1208U0A-Y,P,V,F

X X X X X H During Program(Busy)

X X X X X H During Erase(Busy)

X

XXHXX

NOTE : 1. X can be VIL or VIH.

(1)

X

2. WP should be biased to CMOS high or CMOS low for standby.

X X X L Write Protect

(2)

CC

Stand-by

0V/V

Command Input

Command Input

13

K9F1216U0A
K9F1208U0A

PROGRAM / ERASE CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Program Time t

Dummy Busy Time for Multi Plane Program t

Number of Partial Program Cycles
in the Same Page

Main Array

Spare Array - - 2 cycles

Block Erase Time t

NOTE : 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and temperature

°C.

of 25

AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT

Parameter Symbol Min Max Unit

CLE setup Time t

CLE Hold Time t

CE

setup Time tCS 0-ns

Hold Time tCH 10 - ns

CE

WE

Pulse Width tWP

ALE setup Time t

ALE Hold Time t

Data setup Time t

Data Hold Time t

Write Cycle Time t

WE

High Hold Time tWH 15 - ns

NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

CLS 0-ns

CLH 10 - ns

ALS 0-ns

ALH 10 - ns

DS 20 - ns

DH 10 - ns

WC 50 - ns

PROG - 200 500 µs

DBSY 110

Nop

BERS -23ms

25

- - 1 cycle

(1)

FLASH MEMORY

µs

-ns

14