Samsung K6R1008C1B-TI8, K6R1008C1B-TI12, K6R1008C1B-TI10, K6R1008C1B-TC8, K6R1008C1B-TC12 Datasheet
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K6R1008C1B-C, K6R1008C1B-I
CMOS SRAM
PRELIMINARY
Rev 2.0
- 1 -
February 1998
PRELIMINARY
PRELIMINARY
Preliminary
Document Title
128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev No.
Rev. 0.0
Rev.1.0
Rev.2.0
Remark
Design Target
Preliminary
Final
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Delete 32-SOJ-300 package.
2.3. Delete L-version.
2.4. Delete Data Retention Characteristics and Waveform.
2.5. Add Capacitive load of the test environment in A.C test load.
2.6. Change D.C characteristics.
Items
Previous spec.
(8/10/12ns part)
Changed spec.
(8/10/12ns part)
ICC 160/150/140mA 160/155/150mA
ISB 30mA 50mA
Draft Data
Apr. 1st, 1997
Jun. 1st, 1997
Feb. 25th, 1998
K6R1008C1B-C, K6R1008C1B-I
CMOS SRAM
PRELIMINARY
Rev 2.0
- 2 -
February 1998
PRELIMINARY
PRELIMINARY
Preliminary
128K x 8 Bit High-Speed CMOS Static RAM
GENERAL DESCRIPTIONFEATURES
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL) : 50mA(Max.)
(CMOS) : 10mA(Max.)
Operating K6R1008C1B-8 : 160mA(Max.)
K6R1008C1B-10 : 155mA(Max.)
K6R1008C1B-12 : 150mA(Max.)
• Single 5.0V ±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R1008C1B-J : 32-SOJ-400
K6R1008C1B-T: 32-TSOP2-400CF
K6R1008C1B-C8/C10/C12 Commercial Temp.
K6R1008C1B-I8/I10/I12 Industrial Temp.
ORDERING INFORMATION
Clk Gen.
I/O1~I/O8
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
Row Select
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
256 Rows
512x8 Columns
I/O Circuit
PIN FUNCTION
Pin Name Pin Function
A0 - A16 Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
I/O1 ~ I/O8 Data Inputs/Outputs
VCC Power(+5.0V)
VSS Ground
N.C No Connection
The K6R1008C1B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
K6R1008C1B uses 8 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in
high-density high-speed system applications. The
K6R1008C1B is packaged in a 400mil 32-pin plastic SOJ or
TSOP2 forward.
PIN CONFIGURATION(Top View)
SOJ/
TSOP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
A8
A0
A1
A2
A3
CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE
A4
A5
A6
A7
A10 A11 A12 A13 A14 A15
A0
A1
A2
A3
A4
A5
A6
A7
A8 A9 A16
K6R1008C1B-C, K6R1008C1B-I
CMOS SRAM
PRELIMINARY
Rev 2.0
- 3 -
February 1998
PRELIMINARY
PRELIMINARY
Preliminary
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD 1.0 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA 0 to 70 °C
Industrial TA -40 to 85 °C
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
* The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 6ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 6ns) for I ≤ 20mA.
Parameter
Symbol
Min
Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.2 - VCC + 0.5***
V
Input Low Voltage VIL -0.5** - 0.8
V
CAPACITANCE*(TA=25°C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item Symbol Test Conditions MIN Max Unit
Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN
VIN=0V
- 6 pF
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN = VSS to VCC -2 2 µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2 2 µA
Operating Current ICC Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL,
IOUT=0mA
8ns - 160 mA
10ns - 155
12ns - 150
Standby Current ISB Min. Cycle, CS=VIH - 50 mA
ISB1 f=0MHz, CS ≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
- 10 mA
Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 - V
VOH1** IOH1=-0.1mA - 3.95 V
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