SAMSUNG K4S640832K Technical data
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K4S640832K
Synchronous DRAM
Rev. 1.1 February 2006
1 of 14
K4S641632K
* Samsung Electronics reserves the right to change products or specification without notice.
64Mb K-die SDRAM Specification
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
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K4S640832K
Synchronous DRAM
Rev. 1.1 February 2006
2 of 14
K4S641632K
Revision History
Revision Month Year History
0.0 January 2005 - Target spec release
0.1 March 2005 - Change DC current
0.2 April 2005 - Delete bit organization for x4
0.3 July 2005 - Delete 7ns speed bin
1.0 September 2005 - Final spec release
1.1 February 2006 - Added 5ns speed bin for x16
K4S640832K
Synchronous DRAM
Rev. 1.1 February 2006
3 of 14
K4S641632K
Part No. Orgainization Max Freq. Interface Package
K4S640832K-T(U)C/L75 8Mb x 8 133MHz(CL=3)
LVTT L
54pin TSOP(II)
Pb (Pb-free)
K4S641632K-T(U)C/L50
4Mb x 16
200MHz(CL=3)
K4S641632K-T(U)C/L60 166MHz(CL=3)
K4S641632K-T(U)C/L75 133MHz(CL=3)
The K4S640832K / K4S641632K is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8
bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows
precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies,
programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
• Pb/Pb-free Package
• RoHS compliant for Pb-free Package
GENERAL DESCRIPTION
FEATURES
Ordering Information
2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM
Row & Column address configuration
Organization Row Address Column Address
8Mx8 A0~A11 A0-A8
4Mx16 A0~A11 A0-A7
K4S640832K
Synchronous DRAM
Rev. 1.1 February 2006
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K4S641632K
11. 76±0.20
0.463±0.008
0.002
0.05
MIN
0.008
0.21
± 0.002
± 0.05
0.020
0.50
(
)
0.005
-0.001
+0.003
0.125
-0.035
+0.075
0.400
10.16
0.45~0.75
0.018~0.030
0.010
0.25
TYP
0~8°C
#54
#28
#1
#27
0.004
0.10
MAX
0.028
0.71
( )
0.012
0.30
0.0315
0.80
0.047
1.20
MAX
0.039
1.00
± 0.004
± 0.10
0.891
22.62
MAX
0.875
22.22
± 0.004
± 0.10
+0.10
-0.05
+0.004
-0.002
54Pin TSOP(II) Package Dimension
Package Physical Dimension
K4S640832K
Synchronous DRAM
Rev. 1.1 February 2006
5 of 14
K4S641632K
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Data Input Register
2M x 8 / 1M x 16
2M x 8 / 1M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS
RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
2M x 8 / 1M x 16
2M x 8 / 1M x 16
Timing Register
Samsung Electronics reserves the right to change products or specification without notice.
*
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