Samsung K4S640832F-TL75, K4S640832F-TC75 Datasheet
K4S640832F
CMOS SDRAM
64Mbit SDRAM
2M x 8Bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 1.1
May. 2003
* Samsung Electronics reserves the right to change products or specification without notice.
Rev.1.1 May. 2003
K4S640832F
Revision History
CMOS SDRAM
Revision 0.0 (June, 2001)
Revision 0.1 (Sep., 2001)
• Changed the Notes in Operating AC Parameter.
< Before >
5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .
< After >
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Revision 1.0 (May, 2003)
• Revision Changed (Confirmed revision will be 1.0)
Revision 1.1 (May, 2003)
Delete 100MHz speed
Rev.1.1 May. 2003
K4S640832F
2M x 8Bit x 4 Banks Synchronous DRAM
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
•
DQM for masking
•
• Auto & self refresh
64ms refresh period (4K Cycle)
•
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
GENERAL DESCRIPTIONFEATURES
The K4S640832F is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits,
fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4S640832F-TC/L75 133MHz(CL=3) LVTTL 54
CLK
ADD
Address Register
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS
Bank Select
Refresh Counter
Row Buffer
LRAS
LCBR
Data Input Register
Row Decoder Col. Buffer
LCAS LWCBR
Timing Register
RAS CAS WE DQM
2M x 8
2M x 8
2M x 8
2M x 8
Column Decoder
Latency & Burst Length
Programming Register
Sense AMP
LWE
LDQM
Output BufferI/O Control
DQi
Samsung Electronics reserves the right to change products or specification without notice.
*
Rev.1.1 May. 2003
K4S640832F
PIN CONFIGURATION (Top view)
VDD
DQ0
DDQ
V
N.C
DQ1
SSQ
V
N.C
DQ2
DDQ
V
N.C
DQ3
SSQ
V
N.C
DD
V
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
DD
V
PIN FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
SSQ
V
N.C
DQ6
DDQ
V
N.C
DQ5
SSQ
V
N.C
DQ4
DDQ
V
N.C
SS
V
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
SS
V
CMOS SDRAM
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE Clock enable
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby .
A
0 ~ A11 Address
BA0 ~ BA1 Bank select address
RAS
CAS
WE
Row address strobe
Column address strobe
Write enable
DQM Data input/output mask
DQ
0 ~ 7 Data input/output Data inputs/outputs are multiplexed on the same pins.
DD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
V
V
DDQ/VSSQ Data output power/ground
N.C/RFU
No connection
/reserved for future use
Row/column addresses are multiplexed on the same pins.
Row address : RA
0 ~ RA11, Column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS
Makes data output Hi-Z, t
, WE active.
SHZ after the clock and masks the output.
Blocks data input when DQM active.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
low.
low.
Rev.1.1 May. 2003
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