Samsung K4S281632D-NL7C, K4S281632D-NL75, K4S281632D-NL60, K4S281632D-NL1H, K4S281632D-NC7C Datasheet
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K4S281632D
Rev. 0.1 Sept. 2001
CMOS SDRAM
128Mbit SDRAM
2M x 16Bit x 4 Banks
Synchronous DRAM
LVTTL
Rev. 0.1
Sept. 2001
* Samsung Electronics reserves the right to change products or specification without notice.
K4S281632D
Rev. 0.1 Sept. 2001
CMOS SDRAM
Revision History
Revision 0.0 (July, 2001)
Revision 0.1 (Sep., 2001)
• Redefined IDD1 & IDD4 in DC Characteristics
• Changed the Notes in Operating AC Parameter.
< Before >
5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
< After >
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
K4S281632D
Rev. 0.1 Sept. 2001
2M x 16Bit x 4 Banks Synchronous DRAM
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
CMOS SDRAM
GENERAL DESCRIPTIONFEATURES
The K4S281632D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4S281632D-NC60/NL60 166MHz(CL=3)
K4S281632D-NC7C/NL7C 133MHz(CL=2)
K4S281632D-NC75/NL75 133MHz(CL=3)
K4S281632D-NC1H/NL1H 100MHz(CL=2)
LVTTL
54
sTSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Refresh Counter
Row Buffer
Address Register
CLK
ADD
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
Data Input Register
Row Decoder Col. Buffer
LCAS LWCBR
2M x 16
2M x 16
2M x 16
2M x 16
Column Decoder
Latency & Burst Length
Programming Register
LWE
LDQM
Sense AMP
Output BufferI/O Control
DQi
CLK CKE CS RAS CAS WE LDQM
* Samsung Electronics reserves the right to change products or specification without notice.
Timing Register
UDQM
K4S281632D
Rev. 0.1 Sept. 2001
PIN CONFIGURATION (Top view)
VDD
VDD
WE
CS
BA0
BA1
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
LDQM
CAS
RAS
A10/AP
54Pin sTSOP (II)
(400mil x 441mil)
(0.4 mm Pin pitch)
CMOS SDRAM
VSS
54
DQ15
53
VSSQ
52
DQ14
51
DQ13
50
VDDQ
49
DQ12
48
DQ11
47
VSSQ
46
DQ10
45
DQ9
44
VDDQ
43
DQ8
42
VSS
41
N.C/RFU
40
UDQM
39
CLK
38
CKE
37
N.C
36
A11
35
A9
34
A8
33
A7
32
A6
31
A5
30
A4
29
VSS
28
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select
CKE Clock enable
A0 ~ A11 Address
BA0 ~ BA1 Bank select address
RAS Row address strobe
CAS Column address strobe
WE Write enable
L(U)DQM Data input/output mask
DQ0 ~ 15 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground
N.C/RFU
No connection
/reserved for future use
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
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