Samsung K4S281632C-TP75, K4S281632C-TP1L, K4S281632C-TI75, K4S281632C-TI1L, K4S281632C-TI1H Datasheet
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K4S281632C-TI(P)
CMOS SDRAM
128Mbit SDRAM
2M x 16Bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.1
June 2001
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 Jun. 2001
K4S281632C-TI(P)
Revision History
Revision 0.0 (November 18, 2000)
• First generation.
Revision 0.1 (June 20, 2001)
• Final Specification.
CMOS SDRAM
Rev. 0.1 Jun. 2001
K4S281632C-TI(P)
2M x 16Bit x 4 Banks Synchronous DRAM
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
• Industrial Temperature Operation (- 40 to 85 °C)
CMOS SDRAM
GENERAL DESCRIPTIONFEATURES
The K4S281632C is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4S281632C-TI/P75 133MHz(CL=3)
K4S281632C-TI/P1H 100MHz(CL=2)
K4S281632C-TI/P1L 100MHz(CL=3)
LVTTL
54
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Refresh Counter
Row Buffer
Address Register
CLK
ADD
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
Data Input Register
Row Decoder Col. Buffer
LCAS LWCBR
2M x 16
2M x 16
2M x 16
2M x 16
Column Decoder
Latency & Burst Length
Programming Register
LWE
LDQM
Sense AMP
Output BufferI/O Control
DQi
Timing Register
CLK CKE CS RAS CAS WE LDQM
* Samsung Electronics reserves the right to change products or specification without notice.
UDQM
Rev. 0.1 Jun. 2001
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