Samsung K4E660812B-TCL-6, K4E660812B-TCL-5, K4E660812B-TC-5, K4E660812B-TC-45, K4E660812B-JCL-6 Datasheet

CMOS DRAMK4E660812B, K4E640812B

This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor­mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using
Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

• Extended Data Out Mode operation

• CAS -before-RAS refresh capability

• RAS -only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• Fast parallel test mode capability

• LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic SOJ and TSOP(II) packages

• +3.3V±0.3V power supply

Control

Clocks

RAS
CAS

W

Vcc
Vss

A0~A12

(A0~A11)*1

A0~A9

(A0~A10)*1

Memory Array
8,388,608 x 8

Cells

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

8M x 8bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Note) *1 : 4K Refresh

Sense Amps & I/O

DQ0

to

DQ7

Data out

Buffer

Data in

Buffer

Row Decoder

Column Decoder

VBB Generator

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

OE

• Part Identification

- K4E660812B-JC/L(3.3V, 8K Ref., SOJ)

- K4E640812B-JC/L(3.3V, 4K Ref., SOJ)

- K4E660812B-TC/L(3.3V, 8K Ref., TSOP)

- K4E640812B-TC/L(3.3V, 4K Ref., TSOP)

FEATURES

• Refresh Cycles
Part

NO.

Refresh

cycle

Refresh time

Normal L-ver

K4E660812B* 8K

64ms 128ms

K4E640812B 4K

Unit : mW

* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

• Active Power Dissipation

Speed 8K 4K

-45 360 468

-50 324 432

-60 288 396

¡Ü Performance Range

Speed

tRAC tCAC tRC tHPC

-45 45ns 12ns 74ns 17ns

-50 50ns 13ns 84ns 20ns

-60 60ns 15ns 104ns 25ns

CMOS DRAMK4E660812B, K4E640812B

VCC
DQ0
DQ1
DQ2
DQ3

N.C

VCC

W

RAS

A0
A1
A2
A3
A4
A5

VCC

VSS
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

PIN CONFIGURATION (Top Views)

* (N.C) : N.C for 4K Refresh product

Pin Name Pin Function

A0 - A12 Address Inputs(8K Product)
A0 - A11 Address Inputs(4K Product)
DQ0 - 7 Data In/Out
VSS Ground
RAS Row Address Strobe
CAS Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC Power(+3.3V)
N.C No Connection

VCC
DQ0
DQ1
DQ2
DQ3

N.C

VCC

W

RAS

A0
A1
A2
A3
A4
A5

VCC

VSS
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

¡Û

¡Û

(T : 400mil TSOP(II))(J : 400mil SOJ)

• K4E660812B-J

• K4E640812B-J

• K4E660812B-T

• K4E640812B-T

CMOS DRAMK4E660812B, K4E640812B

ABSOLUTE MAXIMUM RATINGS

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Parameter Symbol Rating Units

Voltage on any pin relative to VSS VIN,VOUT -0.5 to +6.5 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V
Storage Temperature Tstg -55 to +150 °C
Power Dissipation PD 1 W
Short Circuit Output Current IOS Address 50 mA

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

*1 : 6.5V at pulse width≤15ns which is measured at VCC
*2 : -1.3 at pulse width≤15ns which is measured at VSS

Parameter Symbol Min Typ Max Units

Supply Voltage VCC 3.0 3.3 3.6 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.0 -

+5.5

*1

V

Input Low Voltage VIL

-0.3

*2

- 0.8 V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter Symbol Min Max Units

Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,
all other pins not under test=0 Volt)

II(L) -5 5 uA

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

IO(L) -5 5 uA

Output High Voltage Level(IOH=-2mA) VOH 2.4 - V
Output Low Voltage Level(IOL=2mA) VOL - 0.4 V

CMOS DRAMK4E660812B, K4E640812B

*Note :

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.

DC AND OPERATING CHARACTERISTICS (Continued)

ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)
ICC4* : Extended Data Out Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V
W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open

Symbol Power Speed

Max

Units

K4E660812B K4E640812B

ICC1 Don′t care

-45

-50

-60

100

90
80

130
120
110

mA
mA
mA

ICC2

Normal

L

Don′t care

2
2

2
2

mA
mA

ICC3 Don′t care

-45

-50

-60

100

90
80

130
120
110

mA
mA
mA

ICC4 Don′t care

-45

-50

-60

110
100

90

120
110
100

mA
mA
mA

ICC5

Normal

L

Don′t care

500
300

500
300

uA
uA

ICC6 Don′t care

-45

-50

-60

100

90
80

130
120
110

mA
mA

mA
ICC7 L Don′t care 400 400 uA
ICCS L Don′t care 400 400 uA

CMOS DRAMK4E660812B, K4E640812B

CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A12] CIN1 - 5 pF
Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ7] CDQ - 7 pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

Parameter Symbol

-45 -50 -60
Units Note

Min Max Min Max Min Max

Random read or write cycle time

tRC

74 84 104 ns

Read-modify-write cycle time

tRWC

101 113 138 ns

Access time from RAS

tRAC

45 50 60 ns 3,4,10

Access time from CAS

tCAC

12 13 15 ns 3,4,5

Access time from column address

tAA

23 25 30 ns 3,10

CAS to output in Low-Z

tCLZ

3 3 3 ns 3

Output buffer turn-off delay from CAS

tCEZ

3 13 3 13 3 13 ns 6,14

OE to output in Low-Z

tOLZ

3 3 3 ns 3

Transition time (rise and fall)

tT

1 50 1 50 1 50 ns 2

RAS precharge time

tRP

25 30 40 ns

RAS pulse width

tRAS

45 10K 50 10K 60 10K ns

RAS hold time

tRSH

8 8 10 ns

CAS hold time

tCSH

35 38 40 ns

CAS pulse width

tCAS

7 5K 8 10K 10 10K ns

RAS to CAS delay time

tRCD

11 33 11 37 14 45 ns 4

RAS to column address delay time

tRAD

9 22 9 25 12 30 ns 10

CAS to RAS precharge time

tCRP

5 5 5 ns

Row address set-up time

tASR

0 0 0 ns

Row address hold time

tRAH

7 7 10 ns

Column address set-up time

tASC

0 0 0 ns

Column address hold time

tCAH

7 7 10 ns

Column address to RAS lead time

tRAL

23 25 30 ns

Read command set-up time

tRCS

0 0 0 ns

Read command hold time referenced to CAS

tRCH

0 0 0 ns 8

Read command hold time referenced to RAS

tRRH

0 0 0 ns 8

Write command hold time

tWCH

7 7 10 ns

Write command pulse width

tWP

6 7 10 ns

Write command to RAS lead time

tRWL

8 8 10 ns

Write command to CAS lead time

tCWL

7 7 10 ns

Data set-up time

tDS

0 0 0 ns 9

CMOS DRAMK4E660812B, K4E640812B

AC CHARACTERISTICS (Continued)

Parameter Symbol

-45 -50 -60
Units Note

Min Max Min Max Min Max

Data hold time

tDH

7 7 10 ns 9

Refresh period (Normal)

tREF

64 64 64 ms

Refresh period (L-ver)

tREF

128 128 128 ms

Write command set-up time

tWCS

0 0 0 ns 7

CAS to W delay time

tCWD

24 27 32 ns 7

RAS to W delay time

tRWD

57 64 77 ns 7

Column address to W delay time

tAWD

35 39 47 ns 7

CAS set-up time (CAS -before-RAS refresh)

tCSR

5 5 5 ns

CAS hold time (CAS -before-RAS refresh)

tCHR

10 10 10 ns

RAS to CAS precharge time

tRPC

5 5 5 ns

Access time from CAS precharge

tCPA

24 28 35 ns 3

Hyper Page cycle time

tHPC

17 20 25 ns 13

Hyper Page read-modify-write cycle time

tHPRWC

47 47 56 ns 13

CAS precharge time (Hyper page cycle)

tCP

6.5 7 10 ns

RAS pulse width (Hyper page cycle)

tRASP

45 200K 50 200K 60 200K ns

RAS hold time from CAS precharge

tRHCP

24 30 35 ns

OE access time

tOEA

12 13 15 ns

OE to data delay

tOED

8 10 13 ns

CAS precharge to W delay time

tCPWD

36 41 52 ns

Output buffer turn off delay time from OE

tOEZ

3 11 3 13 3 13 ns 6

OE command hold time

tOEH

5 5 5 ns

Write command set-up time (Test mode in)

tWTS

10 10 10 ns 11

Write command hold time (Test mode in)

tWTH

10 10 10 ns 11

W to RAS precharge time (C-B-R refresh)

tWRP

10 10 10 ns

W to RAS hold time (C-B-R refresh)

tWRH

10 10 10 ns

Output data hold time

tDOH

4 5 5 ns

Output buffer turn off delay from RAS

tREZ

3 13 3 13 3 13 ns 6,14

Output buffer turn off delay from W

tWEZ

3 13 3 13 3 13 ns 6

W to data delay

tWED

8 15 15 ns

OE to CAS hold time

tOCH

5 5 5 ns

CAS hold time to OE

tCHO

5 5 5 ns

OE precharge time

tOEP

5 5 5 ns

W pulse width (Hyper Page Cycle)

tWPE

5 5 5 ns

RAS pulse width (C-B-R self refresh)

tRASS

100 100 100 us 15,16,17

RAS precharge time (C-B-R self refresh)

tRPS

74 90 110 ns 15,16,17

CAS hold time (C-B-R self refresh)

tCHS

-50 -50 -50 ns 15,16,17

CMOS DRAMK4E660812B, K4E640812B

TEST MODE CYCLE

Parameter Symbol

-45 -50 -60
Units Note

Min Max Min Max Min Max

Random read or write cycle time

tRC

79 89 109 ns

Read-modify-write cycle time

tRWC

110 121 145 ns

Access time from RAS

tRAC

50 55 65 ns 3,4,10,12

Access time from CAS

tCAC

17 18 20 ns 3,4,5,12

Access time from column address

tAA

28 30 35 ns 3,10,12

RAS pulse width

tRAS

50 10K 55 10K 65 10K ns

CAS pulse width

tCAS

12 10K 13 10K 15 10K ns

RAS hold time

tRSH

18 18 20 ns

CAS hold time

tCSH

39 43 50 ns

Column Address to RAS lead time

tRAL

28 30 35 ns

CAS to W delay time

tCWD

29 35 39 ns 7

RAS to W delay time

tRWD

62 72 84 ns 7

Column Address to W delay time

tAWD

40 47 54 ns 7

Hyper Page cycle time

tHPC

22 25 30 ns 13

Hyper Page read-modify-write cycle time

tHPRWC

52 53 61 ns 13

RAS pulse width (Hyper page cycle)

tRASP

50 200K 55 200K 65 200K ns

Access time from CAS precharge

tCPA

29 33 40 ns 3

OE access time

tOEA

17 18 20 ns

OE to data delay

tOED

13 18 20 ns

OE command hold time

tOEH

13 18 20 ns

( Note 11 )