Samsung K4E171611D-T, K4E171611D-J, K4E171612D-T, K4E171612D-J, K4E151612D-J Datasheet

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K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self­refresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsungs advanced CMOS pro­cess to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
Part Identification
- K4E171611D-J(T) (5V, 4K Ref.)
- K4E151611D-J(T) (5V, 1K Ref.)
- K4E171612D-J(T) (3.3V, 4K Ref.)
- K4E151612D-J(T) (3.3V, 1K Ref.)
• Extended Data Out Mode operation (Fast Page Mode with Extended Data Out)
• 2 CAS Byte/Word Read/Write operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
• JEDEC Standard pinout
Available in plastic SOJ 400mil and TSOP(II) packages
Single +5V±10% power supply (5V product)
Single +3.3V±0.3V power supply (3.3V product)
Control Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Column Decoder
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc Vss
DQ0
to
DQ7
A0-A11
(A0 - A9)*1
A0 - A7
(A0 - A9)*1
Memory Array
1,048,576 x16
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
1M x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles Part
NO.
VCC
Refresh
cycle
Refresh period
Nor- L-ver
K4E171611D 5V
4K 64ms
128ms
K4E171612D 3.3V K4E151611D 5V
1K 16ms
K4E151612D 3.3V
Performance Range
Speed
tRAC tCAC tRC tHPC
Remark
-45 45ns 13ns 69ns 16ns 5V/3.3V
-50 50ns 15ns 84ns 20ns 5V/3.3V
-60 60ns 17ns 104ns 25ns 5V/3.3V
Active Power Dissipation
Speed
3.3V 5V
4K 1K 4K 1K
-45 360 540 550 825
-50 324 504 495 770
-60 288 468 440 715
Unit : mW
Sense Amps & I/O
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE
Note) *1 : 1K Refresh
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
VCC DQ0 DQ1 DQ2 DQ3
VCC DQ4 DQ5 DQ6 DQ7
N.C N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0 A1 A2 A3
VCC
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C
N.C LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23
PIN CONFIGURATION (Top Views)
Pin Name Pin Function
A0 - A11 Address Inputs (4K Product)
A0 - A9 Address Inputs (1K Product)
DQ0 - 15 Data In/Out
VSS Ground
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC
Power(+5V) Power(+3.3V)
N.C No Connection
VCC DQ0 DQ1 DQ2 DQ3
VCC DQ4 DQ5 DQ6 DQ7
N.C N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0 A1 A2 A3
VCC
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
*A10 and A11 are N.C for K4E151611(2)D(5V/3.3V, 1K Ref. product) J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
• K4E17(5)1611(2)D-J
• K4E17(5)1611(2)D-T
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter Symbol
Rating
Units
3.3V 5V
Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 °C Power Dissipation PD 1 1 W Short Circuit Output Current IOS Address 50 50 mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
Parameter Symbol
3.3V 5V Units
Min Typ Max Min Typ Max
Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V Ground VSS 0 0 0 0 0 0 V Input High Voltage VIH 2.0 -
VCC+0.3
*1
2.4 -
VCC+1.0
*1
V
Input Low Voltage VIL
-0.3
*2
- 0.8
-1.0
*2
- 0.8 V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max Parameter Symbol Min Max Units
3.3V
Input Leakage Current (Any input 0≤VIN≤VIN+0.3V, all other input pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V
5V
Input Leakage Current (Any input 0≤VIN≤VIN+0.5V, all other input pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC.
DC AND OPERATING CHARACTERISTICS (Continued)
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Hyper Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V, DQ=Dont care, TRC=31.25us(4K/L-ver), 125us(1K/L-ver) TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
Symbol Power Speed
Max
Units
K4E171612D K4E151612D K4E171611D K4E151611D
ICC1 Dont care
-45
-50
-60
100
90 80
150 140 130
100
90 80
150 140 130
mA mA mA
ICC2
Normal
L
Dont care
1 1
1 1
2 1
2 1
mA mA
ICC3 Dont care
-45
-50
-60
100
90 80
150 140 130
100
90 80
150 140 130
mA mA mA
ICC4 Dont care
-45
-50
-60
110 100
90
110 100
90
110 100
90
110 100
90
mA mA mA
ICC5
Normal
L
Dont care
0.5
200
0.5
200
1
200
1
200
mA
uA
ICC6 Dont care
-45
-50
-60
100
90 80
150 140 130
110
90 80
150 140 130
mA mA
mA ICC7 L Dont care 300 200 350 250 uA ICCS L Dont care 150 150 200 200 uA
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter Symbol Min Max Units
Input capacitance [A0 ~ A11] CIN1 - 5 pF Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ15] CDQ - 7 pF
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Parameter Symbol
-45 -50 -60 Units Notes
Min Max Min Max Min Max
Random read or write cycle time
tRC
79 84 104 ns
Read-modify-write cycle time
tRWC
105 115 140 ns
Access time from RAS
tRAC
45 50 60 ns 3,4,10
Access time from CAS
tCAC
14 15 17 ns 3,4,5
Access time from column address
tAA
23/*20 25 30 ns 3,10
CAS to output in Low-Z
tCLZ
3 3 3 ns 3
Output buffer turn-off delay from CAS
tCEZ
3 13 3 13 3 15 ns 6,19
OE to output in Low-Z
tOLZ
3 3 3 ns 3
Transition time (rise and fall)
tT
2 50 2 50 2 50 ns 2
RAS precharge time
tRP
30 30 40 ns
RAS pulse width
tRAS
45 10K 50 10K 60 10K ns
RAS hold time
tRSH
13 13 17 ns
CAS hold time
tCSH
36 40 50 ns
CAS pulse width
tCAS
7 / *6.5 10K 8 10K 10 10K ns 18
RAS to CAS delay time
tRCD
19 31 20 35 20 43 ns 4
RAS to column address delay time
tRAD
14 22 15 25 15 30 ns 10
CAS to RAS precharge time
tCRP
5 5 5 ns
Row address set-up time
tASR
0 0 0 ns
Row address hold time
tRAH
9 10 10 ns
Column address set-up time
tASC
0 0 0 ns 11
Column address hold time
tCAH
7 8 10 ns 11
Column address to RAS lead time
tRAL
23 25 30 ns
Read command set-up time
tRCS
0 0 0 ns
Read command hold time referenced to CAS
tRCH
0 0 0 ns 8
Read command hold time referenced to RAS
tRRH
0 0 0 ns 8
Write command hold time
tWCH
8 10 10 ns
Write command pulse width
tWP
8 10 10 ns
Write command to RAS lead time
tRWL
10 13 15 ns
Write command to CAS lead time
tCWL
7 8 10 ns 14
AC CHARACTERISTICS (0°CTA≤70°C, See note 1,2)
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
* KM416C1204DT-45 (5V, 1K Refresh) only
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
AC CHARACTERISTICS (Continued)
* KM416C1204DT-45 (5V, 1K Refresh) only
Parameter Symbol
-45 -50 -60 Units Notes
Min Max Min Max Min Max
Data set-up time
tDS
0 0 0 ns 9,17
Data hold time
tDH
7 8 10 ns 9,17
Refresh period (1K, Normal)
tREF
16 16 16 ms
Refresh period (4K, Normal)
tREF
64 64 64 ms
Refresh period (L-ver)
tREF
128 128 128 ms
Write command set-up time
tWCS
0 0 0 ns 7
CAS to W delay time
tCWD
28 32 36 ns 7,13
RAS to W delay time
tRWD
59 67 79 ns 7
Column address W delay time
tAWD
37 42 49 ns 7
CAS precharge to W delay time
tCPWD
39 47 54 ns 7
CAS set-up time (CAS -before-RAS refresh)
tCSR
5 5 5 ns 15
CAS hold time (CAS -before-RAS refresh)
tCHR
10 10 10 ns 16
RAS to CAS precharge time
tRPC
5 5 5 ns
Access time from CAS precharge
tCPA
25 28 35 ns 3
Hyper Page mode cycle time
tHPC
18 20 25 ns 18
Hyper Page read-modify-write cycle time
tHPRWC
39 47 56 ns 18
CAS precharge time (Hyper Page cycle)
tCP
7 / *6.5 8 10 ns 12
RAS pulse width (Hyper Page cycle)
tRASP
45 200K 50 200K 60 200K ns
RAS hold time from CAS precharge
tRHCP
27 30 35 ns
OE access time
tOEA
13 13 15 ns 3
OE to data delay
tOED
10 13 15 ns
Output buffer turn off delay time from OE
tOEZ
3 13 3 13 3 15 ns 6
OE command hold time
tOEH
10 13 15 ns
Output data hold time
tDOH
4 5 5 ns
Output buffer turn off delay from RAS
tREZ
3 13 3 13 3 15 ns 6,19
Output buffer turn off delay from W
tWEZ
3 13 3 13 3 15 ns 6
W to data delay
tWED
15 15 15 ns
OE to CAS hold time
tOCH
5 5 5 ns
CAS hold time to OE
tCHO
5 5 5 ns
OE precharge time
tOEP
5 5 5 ns
W pulse width (Hyper Page Cycle)
tWPE
5 5 5 ns
RAS pulse width (C-B-R self refresh)
tRASS
100 100 100 us 20,21,22
RAS precharge time (C-B-R self refresh)
tRPS
79 90 110 ns 20,21,22
CAS hold time (C-B-R self refresh)
tCHS
-50 -50 -50 ns 20,21,22
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Assumes that tRCDtRCD(max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min), tAWDtAWD(min) and tCPWDtCPWD(min), then the cycle is a read­modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
K4E17(5)1611(2)D Truth Table
RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE
H X X X X Hi-Z Hi-Z Standby
L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z -
8.
6.
5.
10.
9.
3.
2.
1.
4.
7.
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
tASC, tCAH are referenced to the earlier CAS falling edge. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. tCWL is specified from W falling edge to the earlier CAS rising edge. tCSR is referenced to the earlier CAS falling edge before RAS transition low. tCHR is referenced to the later CAS rising edge after RAS transition low.
tCSR tCHR
RAS
LCAS
UCAS
22.
13.
19.
12.
11.
tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
tASC6ns, assume tT=2.0ns. If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed within 64ms/16ms before and after self refresh, in order to meet refresh specification. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
18.
16.
15.
14.
21.
20.
17.
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
tCRP
RAS
VIH - VIL -
UCAS
VIH - VIL -
A
VIH - VIL -
W
VIH - VIL -
OE
VIH - VIL -
VOH - VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tASR tRAH tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
tCEZ
tRCH
Dont care
Undefined
LCAS
VIH - VIL -
tCRP
tCSH
tRSHtRCD
tCAS
tRAD
tRRH
VOH - VOL -
DQ8 ~ DQ15
tCAC
tCLZ
tRAC
OPEN
DATA-OUT
DATA-OUT
tCEZ
tOEZ
tOEZ
tRCS
WORD READ CYCLE
tOLZ
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
NOTE : DIN = OPEN
LOWER BYTE READ CYCLE
RAS
VIH - VIL -
LCAS
VIH - VIL -
A
VIH - VIL -
W
VIH - VIL -
OE
VIH - VIL -
VOH - VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN DATA-OUT
tOEZ
tCEZ
tRRH
tRCH
Dont care
Undefined
tCRP
tRPC
UCAS
VIH - VIL -
OPEN
VOH - VOL -
DQ8 ~ DQ15
tRCS
tOLZ
K4E171611D, K4E151611D
CMOS DRAMK4E171612D, K4E151612D
NOTE : DIN = OPEN
UPPER BYTE READ CYCLE
RAS
VIH - VIL -
LCAS
VIH - VIL -
A
VIH - VIL -
W
VIH - VIL -
OE
VIH - VIL -
VOH - VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tRAD
tASR tRAH tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
DATA-OUT
tOEZ
tCEZ
tRRH
tRCH
Dont care
Undefined
UCAS
VIH - VIL -
OPEN
VOH - VOL -
DQ8 ~ DQ15
tCRP
tRPC
tRCS
tOLZ
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