SAMSUNG K4D64163HF Technical data
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K4D64163HF
64Mbit DDR SDRAM
Double Data Rate Synchronous DRAM
64M DDR SDRAM
1M x 16Bit x 4 Banks
Revision 1.1
August 2002
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.1(Aug. 2002)
K4D64163HF
Revision History
Revision 1.1 (August 6, 2002)
• Typo corrected
Revision 1.0 (June 17, 2002)
• Defined DC spec
Revision 0.1 (May 20, 2002) - Target Spec
• Typo corrected
Revision 0.0 (April 30, 2002) - Target Spec
• Defined Target Specification
64M DDR SDRAM
- 2 -
Rev. 1.1(Aug. 2002)
K4D64163HF
1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
64M DDR SDRAM
• 3.3V +
• 2.5V +
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read l a te ncy 3 (c lock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
• Differential clock input
• No Wrtie-Interrupted by Read Function
5% power supply for device operation
5% power supply for I/O interface
going edge of the system clock
ORDERING INFORMATION
• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 64ms refresh period (4K cycle)
• 66pin TSOP-II
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin
Part NO. Max Freq. Max Data Rate Interface Package
K4D64163HF-TC33 300MHz 600Mbps/pin
K4D64163HF-TC36 275MHz 550Mbps/pin
K4D64163HF-TC40 250MHz 500Mbps/pin
K4D64163HF-TC50 200MHz 400Mbps/pin
K4D64163HF-TC60 166MHz 333Mbps/pin
SSTL_2 66 pin TSOP-II
GENERAL DESCRIPTION
FOR 1M x 16Bit x 4 Bank DDR SDRAM
The K4D64163H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 16
bits, fabricated with SAMSUNG
extremely high performance up to 1. 2GB/s/chip. I/O transactions are po ssible on bo th edges of the clock cycle. Range o f
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of
high performance memory system applications.
’s high performance CMOS technology. Synchronous features with Data Strobe allow
- 3 -
Rev. 1.1(Aug. 2002)
K4D64163HF
PIN CONFIGURATION (Top View)
64M DDR SDRAM
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
VDD
1
2
3
4
5
6
7
8
9
10
66 PIN TSOP(II)
11
(400mil x 875mil)
12
(0.65 mm Pin Pitch)
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A0
A1
A2
A3
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
CK,CK Differential Clock Input BA0, BA1 Bank Select Address
CKE Clock Enable A
CS
RAS
CAS
Chip Select DQ0 ~ DQ15 Data Input/Output
Row Address Strobe VDD Power
Column Address Strobe VSS Ground
WE Write Enable V
LDQS,UDQS Data Strobe V
LDM,UDM Data Mask NC No Connection
0 ~A11 Address Input
DDQ Power for DQ’s
SSQ Ground for DQ’s
- 4 -
Rev. 1.1(Aug. 2002)
K4D64163HF
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol Type Function
The differential system clock Input.
CK, CK
*1 Input
All of the inputs are sampled on the rising edge of the clock except
DQ
’s and DM’s that are sampled on both edges of the DQS.
64M DDR SDRAM
CKE Input
CS
RAS
CAS
WE
Input
Input
Input
Input
LDQS,(U)DQS Input/Output
LDM,UDM Input
Activates the CK signal when high and deactivates the CK
signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
enables the command decoder when low and disabled the com-
CS
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS
low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS
low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS
, WE active.
Data Strobe : Output with read data, input with write data. Edgealigned with read data, centered in write data. Used to capture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ;
UDQS corresponds to the data on DQ8-DQ15.
Input Data Mask : DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS. DM
pins include dummy loading internally, to matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ;
UDM correspons to the data on DQ8-DQ15.
DQ
0 ~ DQ15 Input/Output Data inputs/Outputs are multiplexed on the same pins.
0, BA1 Input S el ec ts which bank is to be active.
BA
0 ~ A11 Input
A
DD/VSS Power Supply Power and ground for the input buffers and core logic.
V
DDQ/VSSQ Power Supply
V
REF Power Supply Reference voltage for inputs, used for SSTL interface.
V
NC/RFU No connection/
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0 ~ RA11, Column addresses : CA0 ~ CA7.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left "No connection" on the device
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF to CK pin.
- 5 -
Rev. 1.1(Aug. 2002)
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