Samsung K4D26323RA-GC36, K4D26323RA-GC33, K4D26323RA-GC2A Datasheet

K4D26323RA-GC

128Mbit DDR SDRAM

Double Data Rate Synchronous RAM

with Bi-directional Data Strobe and DLL

* VDD / VDDQ=2.8V *

128M DDR SDRAM

1M x 32Bit x 4 Banks

(144-Ball FBGA)

Revision 2.0

January 2003

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev. 2.0 (Jan. 2003)

* VDD / VDDQ=2.8V *

K4D26323RA-GC

Revision History

Revision 2.0 (January 16, 2003)

• Changed package ball height from 0.25mm to 0.35mm

Revision 1.9 (August 12, 2002)

• Changed tRC of K4D26323RA-GC2A from 20tCK to 15tCK

• Changed tRFC of K4D26323RA-GC2A from 22tCK to 17tCK

• Changed tRAS of K4D26323RA-GC2A from 14tCK to 10tCK

• Changed tRCDRD of K4D26323RA-GC2A from 7tCK to 5tCK

• Changed tRCDWR of K4D26323RA-GC2A from 5tCK to 3tCK

• Changed tRP of K4D26323RA-GC2A from 6tCK to 5tCK

• Changed tDAL of K4D26323RA-GC2A from 9tCK to 8tCK

• Changed tRC of K4D26323RA-GC33 from 17tCK to 13tCK

• Changed tRFC of K4D26323RA-GC33 from 19tCK to 15tCK

• Changed tRAS of K4D26323RA-GC33 from 12tCK to 9tCK

• Changed tRCDRD of K4D26323RA-GC33 from 6tCK to 4tCK

• Changed tRCDWR of K4D26323RA-GC33 from 4tCK to 2tCK

• Changed tRP of K4D26323RA-GC33 from 5tCK to 4tCK

• Changed tWR of K4D26323RA-GC33 from 3tCK to 2tCK

• Changed tDAL of K4D26323RA-GC33 from 8tCK to 7tCK

128M DDR SDRAM

Revision 1.8 (July 18, 2002)

• Changed power dissipation from 2,0W to 3.3W

Revision 1.7 (May 7, 2002)

• Typo corrected

Revision 1.6 (Janaury 29, 2002)

• Changed CL of K4D26323RA-GC33/36 from 5tCK to 4tCK

• Changed tCK(max) of K4D26323RA-GC2A from 5ns to 4ns. For all the CL5 operation, guaranteed tCK(max) is 4ns .

Revision 1.5 (December 10, 2001)

• Removed K4D263238A-GC33/40/45/5 0/55/60(VDD/VDDQ=2.5V) from the spec

Revision 1.4 (November 14, 2001)

• Added K4D26323RA-GC36(VDD/VDDQ=2.8V)

Revision 1.3 (October 22, 2001)

• Corrected part number of K4D263238A-GC2A to K4D26323RA-GC2A

• Changed tCDLR of -GC2A and GC33 from 3tCK to 2tCK and applied since Sept 15, 2001.

• Defined x32 DDR for mobile PC graphics separately - K4D26323AA-GL** featured with VDDQ=1.8V,ICC6=1mA with reduced operating current. Refer to the K4D26323AA-GL** spec for more detail information.

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Rev. 2.0 (Jan. 2003)

* VDD / VDDQ=2.8V *

K4D26323RA-GC

Revision 1.2 (September 13, 2001)

• Define DC spec value of K4D26323RA-GC33 and K4D263238A-GC2A

• Changed tCK(max) of -2A and -33 from 7ns to 5ns

Revision 1.1 (September 3, 2001)

• Added K4D26323RA-GC33(VDD/VDDQ=2.8V)

• Added K4D263238A-GC2A(350MHz)

Revision 1.0 (August 16, 2001)

• Changed tCDLR of K4D263238A-GC33 from 2tCK to 3tCK

• Removed VDDQ=1.8V from the spec.

• Added K4D263238A-GL as a low power part

• Defined DC spec.

Revision 0.1 (August 2, 2001) - Target Spec

• Changed tCK(max) of K4D263238A-GC45/-50/-55/-60 from 7ns to 10ns.

Revision 0.0 (June, 2001) - Target Spec

• Defined Target Specification

128M DDR SDRAM

- 3 -

Rev. 2.0 (Jan. 2003)

* VDD / VDDQ=2.8V *

K4D26323RA-GC

1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL

FEATURES

• 2.8V + 5% power supply for device operation

• 2.8V + 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• MRS cycle with address key programs

-. Read latency 3,4 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

• Full page burst length for sequential burst type only

• Start address of the full page burst should be even

• All inputs except data & DM are sampled at the positive going edge of the system clock

• Differential clock input

• No Wrtie-Interrupted by Read Function

• 4 DQS’s ( 1DQS / Byte )

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• Auto & Self refresh

• 32ms refresh period (4K cycle)

• 144-Ball FBGA

• Maximum clock frequency up to 350MHz

• Maximum data rate up to 700Mbps/pin

128M DDR SDRAM

ORDERING INFORMATION

Part NO. Max Freq. Max Data Rate Interface Package

K4D26323RA-GC2A 350MHz 700Mbps/pin

K4D26323RA-GC36 275MHz 550Mbps/pin

SSTL_2

(VDD/VDDQ=2.8V)

144-Ball FBGA K4D26323RA-GC33 300MHz 600Mbps/pin

GENERAL DESCRIPTION

FOR 1M x 32Bit x 4 Bank DDR SDRAM

The K4D26323RA is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and pro grammable latencies allow the d evice to be useful for a variety of high performance memory system applications.

- 4 -

Rev. 2.0 (Jan. 2003)

* VDD / VDDQ=2.8V *

K4D26323RA-GC

PIN CONFIGURATION (Top View)

2345678910111213

DQS0

DM0

VSSQ

DQ3

DQ2

DQ0

DQ31

DQ29

128M DDR SDRAM

DQ28

VSSQ

DM3

DQS3

DQ4

DQ6

DQ7

DQ17

DQ19

DQS2

DQ21

DQ22

CAS

RAS

VDDQ

DQ5

VDDQ

DQ16

DQ18

DM2

DQ20

DQ23

VSSQ VSSQ VSSQ

VDD

VDDQ

VDD

NOTE:

1. RFU1 is reserved for A12

2. RFU2 is reserved for BA2

3. VSS Thermal balls are optional

BA0

VDDQ

VDD

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VDD VDD

A11

VDDQ

VSS VSS VSS VSS

VSSQ

VSS

BA1

DQ1

VSSQ

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

A10

VDDQ

VDD

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

DQ30

VSSQ

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSSVSSVSSVSS

RFU

VDDQ NC

VSSQ VSSQ

VSSQ

VSS

RFU

VDDQ

DQ26

VDD

VDDQ

VDD

2A5

A8/AP

VDDQ

DQ15

DQ13

DM1

DQ11

DQ9

CKE

DQ27

DQ25

DQ24

DQ14

DQ12

DQS1

DQ10

DQ8

MCL

VREF

PIN DESCRIPTION

CK,CK Differential Clock Input BA0, BA1 Bank Select Address CKE Clock Enable A0 ~A11 Address Input CS Chip Select DQ0 ~ DQ31 Data Input/Output RAS CAS WE Write Enable VDDQ Power for DQ’s DQS Data Strobe VSSQ Ground for DQ’s DM Data Mask NC No Connection RFU Reserved for Future Use MCL Must Connect Low

Row Address Strobe VDD Power Column Address Strobe VSS Ground

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Rev. 2.0 (Jan. 2003)

* VDD / VDDQ=2.8V *

K4D26323RA-GC

128M DDR SDRAM

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol Type Function

The differential system clock Input.

CK, CK*1 Input

CKE Input

CS Input

RAS

CAS Input

WE Input

DQS0 ~ DQS3 Input/Output

DM0 ~ DM3 Input

DQ0 ~ DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins.

BA0, BA1 Input Selects which bank is to be active.

A0 ~ A11 Input

DD/VSS Power Supply Power and ground for the input buffers and core logic.

VDDQ/VSSQ Power Supply

VREF Power Supply Reference voltage for inputs, used for SSTL interface.

NC/RFU No connection/

MCL Must Connect Low Must connect low

*1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply V

Input

Reserved for future use

All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are sampled on both edges of the DQS.

Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode.

CS enables the command decoder when low an d di sa bl e d th e command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue.

Latches row addresses on the positive going edge of the CK with RAS

low. Enables row access & precharge.

Latches column addresses on the positive going edge of the CK with CAS low. Enables column access.

Enables write operation and row precharge. Latches data in starting from CAS, WE active.

Data input and output are synchronized with both edge of DQS. DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23, DQS3 for DQ24 ~ DQ31.

Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.

Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. Column address CA

Isolated power supply and ground for the output buffers to provide improved noise immunity.

This pin is recommended to be left "No connection" on the device

REF to CK pin.

8 is used for auto precharge.

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Rev. 2.0 (Jan. 2003)

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