SAMSUNG K4B2G0846C Technical data

2Gb C-die DDR3 SDRAM

http://www.BDTIC.com/SAMSUNG

78FBGA with Lead-Free & Halogen-Free (RoHS compliant)

Rev. 1.31, Nov. 2010

K4B2G0446C K4B2G0846C

datasheet

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datasheet DDR3 SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First Release Dec. 2009 - S.H.Kim

1.01 - Corrected Current Data Dec. 2009 - S.H.Kim

1.1 - Deleted operation frequency of DDR3 800 (6-6-6) Jan. 2010 - S.H.Kim

1.2 - Added "CL5" to supported CL setting Feb. 2010 - S.H.Kim

1.21 - Corrected Typo. Feb. 2010 - S.H.Kim

1.22 - Corrected Typo. Apr. 2010 - S.H.Kim

1.3 - Updated JESD79-3E Jun. 2010 - S.H.Kim

1.31 - Corrected Typo. Nov. 2010 - S.H.Kim

Rev. 1.31

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datasheet DDR3 SDRAM

Table Of Contents

2Gb C-die DDR3 SDRAM

1. Ordering Information .....................................................................................................................................................5

2. Key Features................................................................................................................................................................. 5

3. Package pinout/Mechanical Dimension & Addressing................................................................................................. 6

3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6

3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7

3.3 FBGA Package Dimension (x4/x8).......................................................................................................................... 8

4. Input/Output Functional Description..............................................................................................................................9

5. DDR3 SDRAM Addressing ...........................................................................................................................................10

6. Absolute Maximum Ratings ..........................................................................................................................................11

6.1 Absolute Maximum DC Ratings............................................................................................................................... 11

6.2 DRAM Component Operating Temperature Range ................................................................................................ 11

7. AC & DC Operating Conditions..................................................................................................................................... 11

7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 11

8. AC & DC Input Measurement Levels ............................................................................................................................12

8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12

8.2 V

8.3 AC & DC Logic Input Levels for Differential Signals...............................................................................................14

8.4 Differential Input Cross Point Voltage...................................................................................................................... 16

8.5 Slew rate definition for Differential Input Signals .....................................................................................................16

8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 16

9. AC & DC Output Measurement Levels ......................................................................................................................... 17

9.1 Single-ended AC & DC Output Levels..................................................................................................................... 17

9.2 Differential AC & DC Output Levels......................................................................................................................... 17

9.3 Single-ended Output Slew Rate .............................................................................................................................. 17

9.4 Differential Output Slew Rate .................................................................................................................................. 18

9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 18

9.6 Overshoot/Undershoot Specification ....................................................................................................................... 19

9.7 34ohm Output Driver DC Electrical Characteristics.................................................................................................20

9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 21

9.9 ODT Timing Definitions ........................................................................................................................................... 24

10. IDD Current Measure Method..................................................................................................................................... 27

10.1 IDD Measurement Conditions ...............................................................................................................................27

11. 2Gb DDR3 SDRAM C-die IDD Specification Table ....................................................................................................36

12. Input/Output Capacitance ...........................................................................................................................................37

13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 ...................................................................... 38

13.1 Clock Specification ................................................................................................................................................ 38

13.2 Refresh Parameters by Device Density................................................................................................................. 39

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 39

Tolerances...................................................................................................................................................... 13

REF

8.3.1. Differential signals definition ............................................................................................................................ 14

8.3.2. Differential swing requirement for clock (CK - CK

8.3.3. Single-ended requirements for differential signals ...........................................................................................15

9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19

9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 19

9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 21

9.8.1. ODT DC Electrical Characteristics...................................................................................................................22

9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 23

9.9.1. Test Load for ODT Timings..............................................................................................................................24

9.9.2. ODT Timing Definitions.................................................................................................................................... 24

13.1.1. Definition for tCK(avg).................................................................................................................................... 38

13.1.2. Definition for tCK(abs).................................................................................................................................... 38

13.1.3. Definition for tCH(avg) and tCL(avg).............................................................................................................. 38

13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) .................................................................................................38

13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 38

13.1.6. Definition for tERR(nper)................................................................................................................................ 38

13.3.1. Speed Bin Table Notes .................................................................................................................................. 42

) and strobe (DQS - DQS) .................................................. 14

Rev. 1.31

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14. Timing Parameters by Speed Grade ..........................................................................................................................43

14.1 Jitter Notes ............................................................................................................................................................46

14.2 Timing Parameter Notes........................................................................................................................................ 47

14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 48

14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 54

datasheet DDR3 SDRAM

Rev. 1.31

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datasheet DDR3 SDRAM

1. Ordering Information

[ Table 1 ] Samsung 2Gb DDR3 C-die ordering information table

Organization

512Mx4 K4B2G0446C-HCF8 K4B2G0446C-HCH9 K4B2G0446C-HCK0 78 FBGA

256Mx8 K4B2G0846C-HCF8 K4B2G0846C-HCH9 K4B2G0846C-HCK0 78 FBGA

NOTE :

1. Speed bin is in order of CL-tRCD-tRP.

2. Backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

3. Backward compatible to DDR3-1066(7-7-7)

DDR3-1066 (7-7-7)

DDR3-1333 (9-9-9)

DDR3-1600 (11-11-11)

2. Key Features

[ Table 2 ] 2Gb DDR3 C-die Speed bins

Speed

tCK(min) 2.5 1.875 1.5 1.25 ns

CAS Latency 6 7 9 11 n CK

tRCD(min) 15 13.125 13.5 13.75 ns

tRP(min) 15 13.125 13.5 13.75 ns

tRAS(min) 37.5 37.5 36 35 ns

tRC(min) 52.5 50.625 49.5 48.75 ns

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

6-6-6 7-7-7 9-9-9 11-11- 11

Rev. 1.31

Package

Unit

• JEDEC standard 1.5V ± 0.075V Power Supply

•V

• 400 MHz f

• 8 Banks

• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11

• Programmable Additive Latency: 0, CL-2 or CL-1 clock

• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6

• 8-bit pre-fetch

• Burst Length: 8 (Interleave without any limit, sequential with starting

• Bi-directional Differential Data-Strobe

• Internal(self) calibration : Internal self calibration through ZQ pin

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower than T

• Asynchronous Reset

• Package : 78 balls FBGA - x4/x8

• All of Lead-Free products are compliant for RoHS

• All of products are Halogen-free

= 1.5V ± 0.075V

DDQ

for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,

667MHz f

(DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)

address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

(RZQ : 240 ohm ± 1%)

85°C < T

for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin

85°C, 3.9us at

CASE

< 95 °C

The 2Gb DDR3 SDRAM C-die is organized as a 64Mbit x 4 I/Os x 8banks

or 32Mbit x 8 I/Os x 8banks device. This synchronous device achieves high

speed double-data-rate transfer rates of up to 1600Mb/sec/pin (DDR3-

1600) for general applications.

The chip is designed to comply with the following key DDR3 SDRAM fea-

tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,

On Die Termination using ODT pin and Asynchronous Reset .

All of the control and address inputs are synchronized with a pair of exter-

nally supplied differential clocks. Inputs are latched at the crosspoint of dif-

ferential clocks (CK rising and CK

pair of bidirectional strobes (DQS and DQS

ion. The address bus is used to convey row, column, and bank address

information in a RAS

with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V

The 2Gb DDR3 C-die device is available in 78ball FBGAs(x4/x8).

/CAS multiplexing style. The DDR3 device operates

falling). All I/Os are synchronized with a

) in a source synchronous fash-

DDQ

NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing

Diagram”.

2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.

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datasheet DDR3 SDRAM

3. Package pinout/Mechanical Dimension & Addressing

3.1 x4 Package Pinout (Top view) : 78ball FBGA Package

1 2 3 4 5 6 7 8 9

Rev. 1.31

REFDQ

DDQ

SSQ

F NC

G ODT

SSQ

NC NC

DQ0 DM

SSQ

DQ2 DQS DQ1 DQ3

NC DQS

DDQ

RAS CK

CAS CK

NC NC NC

H NC CS WE A10/AP ZQ NC H

BA0 BA2 NC

A3 A0 A12/BC BA1

A5 A2 A1 A4

A7 A9 A11 A6

RESET A13 A14 A8

Ball Locations (x4)

Populated ball Ball not populated

Top view

(See the balls through the package)

REFCA

1234 89567

DDQ

SSQ

DDQ

NC F

CKE G

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datasheet DDR3 SDRAM

3.2 x8 Package Pinout (Top view) : 78ball FBGA Package

1 2 3 4 5 6 7 8 9

Rev. 1.31

REFDQ

DDQ

SSQ

F NC

G ODT

SSQ

NC NU/TDQS

DQ0 DM/TDQS

SSQ

DQ2 DQS DQ1 DQ3

DQ6 DQS

DDQ

DQ4 DQ7 DQ5

RAS CK

CAS CK

H NC CS WE A10/AP ZQ NC H

BA0 BA2 NC

A3 A0 A12/BC BA1

A5 A2 A1 A4

A7 A9 A11 A6

RESET A13 A14 A8

Ball Locations (x8)

Populated ball Ball not populated

Top view

(See the balls through the package)

REFCA

1234 89567

DDQ

SSQ

DDQ

NC F

CKE G

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3.3 FBGA Package Dimension (x4/x8)

Rev. 1.31

datasheet DDR3 SDRAM

(Datum A)

(Datum B)

78 - ∅0.45 Solder ball

(Post Reflow ∅0.50 ± 0.05)

0.2 ABM

0.80

A B C D E F G H J K L M N

7.50 ± 0.10

1.60

876543219

3.20

(0.95)

(1.90)

BOTTOM VIEW

#A1 INDEX MARK

4.80

0.80

MOLDING AREA

Units : Millimeters

11.00 ± 0.10

0.80 x 12 = 9.60

#A1

7.50 ± 0.10

TOP VIEW

0.10MAX

11.00 ± 0.10

0.35 ± 0.05

1.10 ± 0.10

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datasheet DDR3 SDRAM

4. Input/Output Functional Description

[ Table 3 ] Input/Output function description

Symbol Typ e Function

CK, CK

CKE Input

ODT Input

, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

RAS

(DMU), (DML)

BA0 - BA2 Input

A0 - A14 Input

A10 / AP Input

A12 / BC

RESET

DQ Input/Output Data Input/ Output: Bi-directional data bus.

DQS, (DQS

TDQS, (TDQS

) Input/Output

NC No Connect: No internal electrical connection is present.

DDQ

SSQ

REFDQ

REFCA

ZQ Supply Reference Pin for ZQ calibration

Input

)Output

Supply DQ Power Supply: 1.5V +/- 0.075V

Supply DQ Ground

Supply Power Supply: 1.5V +/- 0.075V

Supply Ground

Supply Reference voltage for DQ

Supply Reference voltage for CA

NOTE : Input only pins (BA0-BA2, A0-A14, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.

Clock: CK and CK

the positive edge of CK and negative edge of CK

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After V

stable during the power on and initialization sequence, it must be maintained during all operations (including SelfRefresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.

Chip Select: All commands are masked when CS systems with multiple Ranks. CS

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle.

Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC see below) The address inputs also provide the op-code during Mode Register Set commands.

Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge) A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details

Active Low Asynchronous Reset: Reset is active when RESET

must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and

RESET 20% of V

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended.

Termination Data Strobe: TDQS/TDQS MR1, DRAM will enable the same termination resistance function on TDQS/TDQS disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.

are differential clock inputs. All address and control input signals are sampled on the crossing of

. Output (read) data is referenced to the crossings of CK and CK

is registered HIGH. CS provides for external Rank selection on

is considered part of the command code.

and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode

is enabled by Mode Register A11 setting in MR1.

is LOW, and inactive when RESET is HIGH.

, i.e. 1.20V for DC high and 0.30V for DC low.

is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in

Rev. 1.31

has become

REFCA

, ODT

have additional functions,

that is applied to DQS/DQS. When

is not used. x4/

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5. DDR3 SDRAM Addressing

1Gb

Configuration 256Mb x 4 128Mb x 8 64Mb x 16

# of Bank 8 8 8

Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2

Auto precharge A

Row Address A

Column Address A0 - A9,A11 A0 - A9 A0 - A9

BC switch on the fly A12/BC A12/BC A12/BC

Page size

2Gb

Configuration 512Mb x 4 256Mb x 8 128Mb x 16

# of Bank 8 8 8

Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2

Auto precharge A

Row Address A

Column Address A0 - A9,A11 A0 - A9 A0 - A9

BC switch on the fly A12/BC A12/BC A12/BC

Page size

Rev. 1.31

datasheet DDR3 SDRAM

10/AP A10/AP A10/AP

0 - A13 A0 - A13 A0 - A12

1 KB 1 KB 2 KB

10/AP A10/AP A10/AP

0 - A14 A0 - A14 A0 - A13

1 KB 1 KB 2 KB

4Gb

Configuration 1Gb x 4 512Mb x 8 256Mb x 16

# of Bank 8 8 8

Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2

Auto precharge A

Row Address A

Column Address A0 - A9,A11 A0 - A9 A0 - A9

BC switch on the fly A12/BC A12/BC A12/BC

Page size

10/AP A10/AP A10/AP

0 - A15 A0 - A15 A0 - A14

1 KB 1 KB 2 KB

8Gb

Configuration 2Gb x 4 1Gb x 8 512Mb x 16

# of Bank 8 8 8

Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2

Auto precharge A

Row Address A

Column Address A0 - A9,A11 ,A13 A0 - A9,A11 A0 - A9

BC switch on the fly A12/BC A12/BC A12/BC

Page size

NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calcula

where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

ted as follows: page size = 2

10/AP A10/AP A10/AP

0 - A15 A0 - A15 A0 - A15

2 KB 2 KB 2 KB

COLBITS

* ORG÷8

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datasheet DDR3 SDRAM

6. Absolute Maximum Ratings

6.1 Absolute Maximum DC Ratings

[ Table 4 ] Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

Voltage on V

DDQ

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the cente

3. V

equal to or less than 300mV.

Voltage on any pin relative to Vss -0.4 V ~ 1.975 V V 1

IN, VOUT

Storage Temperature -55 to +100 °C 1, 2

STG

and V

DDQ

Voltage on VDD pin relative to Vss -0.4 V ~ 1.975 V V 1,3

pin relative to Vss -0.4 V ~ 1.975 V V 1,3

DDQ

cause permanent damage to the device. This is a stress rating only and functional operation of the

must be within 300mV of each other at all times; and V

r/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

must be not greater than 0.6 x V

REF

, When VDD and V

DDQ

are less than 500mV; V

DDQ

REF

may be

6.2 DRAM Component Operating Temperature Range

[ Table 5 ] Temperature Range

Symbol Parameter rating Unit NOTE

OPER

NOTE :

1. Operating Temperature T

JESD51-2.

2. The Normal Temperature Range specifies the temperatures where a tained between 0-85°C u

3. Some applications require operation of the Extended Temperature Range between 85°C an following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefo b) If Self-Refresh operation is required in the Extended Temperature

Range capability (MR2 A6 = 0

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

nder all operating conditions

Operating Temperature Range 0 to 95 °C 1, 2, 3

ll DRAM specifications will be supported. During operation, the DRAM case temperature must be main-

d 95°C case temperature. Full specifications are guaranteed in this range, but the

re reducing the refresh interval tREFI to 3.9us.

and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

7. AC & DC Operating Conditions

7.1 Recommended DC operating Conditions (SSTL_1.5)

[ Table 6 ] Recommended DC Operating Conditions

Symbol Parameter

DDQ

NOTE :

1. Under all conditions V

2. V

tracks with VDD. AC parameters are measured with VDD and V

DDQ

Supply Voltage 1.425 1.5 1.575 V 1,2

Supply Voltage for Output 1.425 1.5 1.575 V 1,2

must be less than or equal to VDD.

DDQ

tied together.

DDQ

Min. Typ . Max.

Rating

Units NOTE

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datasheet DDR3 SDRAM

8. AC & DC Input Measurement Levels

8.1 AC & DC Logic input levels for single-ended signals

[ Table 7 ] Single-ended AC & DC input levels for Command and Address

Symbol Parameter

(DC100)

IH.CA

(DC100)

IL.CA

(AC175)

IH.CA

(AC175)

IL.CA

(AC150)

IH.CA

(AC150)

IL.CA

REFCA

NOTE :

1. For input only pins except RESET

2. See ’Overshoot/Undershoot Specification’ on page 19.

3. The AC peak noise on V

4. For reference : approx. V

(dc) is used as a simplified symbol for V

5. V

(dc) is used as a simplified symbol for V

6. V

7. V

(ac) is used as a simplified symbol for V

used when VREF + 150mV is referenced.

(ac) is used as a simplified symbol for V

8. V

when V

REF

DC input logic high

DC input logic low

AC input logic high

AC input logic low -

AC input logic high

AC input logic low -

Reference Voltage for ADD,

(DC)

CMD inputs

, V

may not allow V

REF

/2 ± 15mV

- 150mV is referenced.

REF

= V

(DC)

REFCA

to deviate from V

REF

(DC100)

IH.CA

(DC100)

IL.CA

(AC175) and V

IH.CA

(AC175) and V

IL.CA

Min. Max.

REF

0.49*V

(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

REF

(AC150); V

IH.CA

(AC150); V

IL.CA

DDR3-800/1066/1333/1600

+ 100 V

+ 175

+150

(AC175) value is used when V

IH.CA

(AC175) value is used when V

IL.CA

- 100

REF

- mV 1,2,7

- 175

REF

- mV 1,2,7

-150

REF

0.51*V

+ 175mV is referenced and V

REF

- 175mV is referenced and V

REF

Rev. 1.31

Unit NOTE

mV 1,5

mV 1,6

mV 1,2,8

V3,4

(AC150) value is

IH.CA

(AC150) value is used

IL.CA

[ Table 8 ] Single-ended AC & DC input levels for DQ and DM

Symbol Parameter

(DC100)

IH.DQ

(DC100)

IL.DQ

(AC175)

IH.DQ

(AC175)

IL.DQ

(AC150)

IH.DQ

(AC150)

IL.DQ

REF

NOTE :

1. For input only pins except RESET

2. See ’Overshoot/Undershoot Specification’ on page 19.

3. The AC peak noise on V

4. For reference : approx. V

5. V

(dc) is used as a simplified symbol for V

6. V

7. V

(ac) is used as a simplified symbol for V

when V

(ac) is used as a simplified symbol for V

8. V

- 150mV is referenced.

REF

DC input logic high

DC input logic low

AC input logic high

AC input logic low -

AC input logic high

AC input logic low NOTE 2

Reference Voltage for DQ,

(DC)

DM inputs

, V

= V

REF

REFDQ

may not allow V

REF

+ 150mV is referenced.

REF

/2 ± 15mV

REF

IH.DQ

IL.DQ

IH.DQ

IL.DQ

(DC)

to deviate from V

(DC100)

(AC175), V

DDR3-800/1066 DDR3-1333/1600

Min. Max. Min. Max.

+ 100 V

REF

+ 175

REF

+ 150

REF

0.49*V

REF

(AC150) ; V

IH.DQ

(AC150) ; V

IL.DQ

- 100 V

REF

+ 100 V

REF

- - - mV 1,2,7

- 175

REF

NOTE 2

- 150

REF

0.51*V

(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

(AC175) value is used when V

IH.DQ

(AC175) value is used when V

IL.DQ

- - mV 1,2,8

+ 150

REF

NOTE 2

0.49*V

+ 175mV is referenced, V

REF

- 175mV is referenced, V

REF

Unit NOTE

- 100

REF

mV 1,5

mV 1,6

NOTE 2 mV 1,2,7

- 150

REF

0.51*V

IL.DQ

mV 1,2,8

V3,4

(AC150) value is used

IH.DQ

(AC150) value is used when

- 12 -

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K4B2G0846C

Rev. 1.31

datasheet DDR3 SDRAM

8.2 V

The dc-tolerance limits and ac-noise limits for the reference voltages V

REF

page 12. Furthermore V

Tolerances

REF

(t) as a function of time. (V

(DC) is the linear average of V

REF

(t) may temporarily deviate from V

REF

voltage

stands for V

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on

REF

REFCA

and V

likewise).

REFDQ

(DC) by no more than ± 1% VDD.

REF

REFCA

and V

are illustrate in Figure 1. It shows a valid reference voltage

REFDQ

time

Figure 1. Illustration of V

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

" shall be understood as V

REF

This clarifies, that dc-variations of V

which setup and hold is measured. System timing and voltage budgets need to account for V

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

and voltage effects due to ac-noise on V

(DC), as defined in Figure 1.

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

REF

(DC) tolerance and VREF ac-noise limits

REF

(DC) deviations from the optimum position within the

REF

ac-noise. Timing

REF

- 13 -

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datasheet DDR3 SDRAM

8.3 AC & DC Logic Input Levels for Differential Signals

8.3.1 Differential signals definition

tDVAC

VIH.DIFF.AC.MIN

.DIFF.MIN

0.0 half cycle

.DIFF.MAX

.DIFF.AC.MAX

Rev. 1.31

Differential Input Voltage (i.e. DQS-DQS, CK-CK)

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

tDVAC

time

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

[ Table 9 ] Differential AC & DC Input Levels

Symbol Parameter

IHdiff

ILdiff

(AC)

IHdiff

(AC)

ILdiff

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK - CK

level is used for a signal group, then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK

[ Table 10 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

use VIH/VIL(AC) of ADD/CMD and V

(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"

Slew Rate [V/ns]

differential input high +0.2 NOTE 3 V 1

differential input low NOTE 3 -0.2 V 1

differential input high ac

differential input low ac NOTE 3

; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and V

REFCA

> 4.0 75 - 175 -

4.0 57 - 170 -

3.0 50 - 167 -

2.0 38 - 163 -

1.8 34 - 162 -

1.6 29 - 161 -

1.4 22 - 159 -

1.2 13 - 155 -

1.0 0 - 150 -

< 1.0 0 - 150 -

2 x (VIH(AC) - V

tDVAC [ps] @ |V

min max min max

DDR3-800/1066/1333/1600

min max

)

REF

, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,

(AC)| = 350mV tDVAC [ps] @ |V

IH/Ldiff

NOTE 3 V 2

2 x (VIL(AC) - V

REF

)

unit NOTE

; if a reduced ac-high or ac-low

REFDQ

(AC)| = 300mV

IH/Ldiff

- 14 -

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K4B2G0446C K4B2G0846C

8.3.3 Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK

half-cycle. DQS, DQSL, DQSU, DQS

proceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V

nals, then these ac-levels apply also for the single-ended signals CK and CK

have to approximately reach V

, DQSL have to reach V

SEH

min / V

SEH

datasheet DDR3 SDRAM

max [approximately equal to the ac-levels { VIH(AC) / VIL(AC)} for ADD/CMD signals] in every

SEL

min / V

max [approximately the ac-levels { VIH(AC) / VIL(AC)} for DQ signals] in every half-cycle

SEL

150(AC)/VIL150(AC) is used for ADD/CMD sig-

VDD or V

/2 or V

VSS or V

Note that while ADD/CMD and DQ signal requirements are with respect to V

with respect to V

ended components of differential signals the requirement to reach V

mode characteristics of these signals.

/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

DDQ

min

SEH

DDQ

max

SEL

SSQ

Figure 3. Single-ended requirement for differential signals

max, V

SEL

CK or DQS

SEL

time

, the single-ended components of differential signals have a requirement

REF

min has no bearing on timing, but adds a restriction on the common

SEH

[ Table 11 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK

Symbol Parameter

SEH

SEL

NOTE :

1. For CK, CK

2. V

reduced level applies also here

3. These values are not defined, however the single-ended signals CK, CK limits (V

Specification"

use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.

(AC)/VIL(AC) for DQs is based on V

(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes NOTE3

Single-ended low-level for CK, CK

; VIH(AC)/VIL(AC) for ADD/CMD is based on V

REFDQ

, DQS, DQSL, or DQSU

DDR3-800/1066/1333/1600

Min Max

/2)+0.175

(VDD/2)+0.175

NOTE3

; if a reduced ac-high or ac-low level is used for a signal group, then the

REFCA

, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective

- 15 -

NOTE3 V 1, 2

/2)-0.175

Unit NOTE

V1, 2

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datasheet DDR3 SDRAM

8.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK

cross point of true and complement signal to the mid level between of V

[ Table 12 ] Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter

NOTE :

1. Extended range for V ±250 mV, and the differential slew rate of CK-CK

and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual

and VSS.

CK, DQS

VDD/2

CK, DQS

Figure 4. VIX Definition

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing V

is larger than 3 V/ ns. Refer to Table 11 on page 15 for V

DDR3-800/1066/1333/1600

Min Max

-150 150 mV

-175 175 mV 1

-150 150 mV

SEL

and V

standard values.

SEH

SEL

/ V

Unit NOTE

of at least VDD/2

SEH

8.5 Slew rate definition for Differential Input Signals

See 14.3 “Address/Command Setup, Hold and Derating :” on page 48 for single-ended slew rate definitions for address and command signals. See 14.4 “Data Setup, Hold and Slew Rate Derating :” on page 54 for single-ended slew rate definitions for data signals.

8.6 Slew rate definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5.

[ Table 13 ] Differential input slew rate definition

Description

Differential input slew rate for rising edge (CK-CK

Differential input slew rate for falling edge (CK-CK

NOTE : The differential signal (i.e. CK - CK

and DQS - DQS) must be linear between these thresholds.

and DQS-DQS)

Measured

From To

ILdiffmax

IHdiffmin

ILdiffmax

IHdiffmin

ILdiffmax

Defined by

IHdiffmin

Delta TRdiff

IHdiffmin

Delta TFdiff

- V

ILdiffmax

delta TFdiff

Figure 5. Differential Input Slew Rate definition for DQS, DQS, and CK, CK

delta TRdiff

- 16 -

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K4B2G0846C

datasheet DDR3 SDRAM

9. AC & DC Output Measurement Levels

9.1 Single-ended AC & DC Output Levels

[ Table 14 ] Single-ended AC & DC output levels

Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE

(DC) DC output high measurement level (for IV curve linearity) 0.8 x V

(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V

(DC) DC output low measurement level (for IV curve linearity) 0.2 x V

(AC) AC output high measurement level (for output SR) VTT + 0.1 x V

(AC) AC output low measurement level (for output SR) VTT - 0.1 x V

NOTE : 1. The swing of +/-0.1 x V

load of 25Ω to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

DDQ

/2.

DDQ

9.2 Differential AC & DC Output Levels

[ Table 15 ] Differential AC & DC output levels

Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE

(AC) AC differential output high measurement level (for output SR) +0.2 x V

OHdiff

(AC) AC differential output low measurement level (for output SR) -0.2 x V

OLdiff

NOTE : 1. The swing of +/-0.2xV

load of 25Ω to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

DDQ

/2 at each of the differential outputs.

DDQ

Rev. 1.31

9.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 16 and Figure 6.

[ Table 16 ] Single-ended output slew rate definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 17 ] Single-ended output slew rate

Parameter Symbol

Single ended output slew rate SRQse 2.5 5 2.5 5 2.5 5 2.5 5 V/ns

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

se : Single-ended Signals For Ron = RZQ/7 setting

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Min Max Min Max Min Max Min Max

Measured

From To

(AC) VOH(AC)

(AC) VOL(AC)

OH(AC)

Defined by

(AC)-VOL(AC)

Delta TRse

(AC)-VOL(AC)

Delta TFse

Units

Figure 6. Single-ended Output Slew Rate Definition

- 17 -

VTT

OL(AC)

delta TRsedelta TFse

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datasheet DDR3 SDRAM

9.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

(AC) for differential signals as shown in Table 18 and Figure 7.

diff

[ Table 18 ] Differential output slew rate definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 19 ] Differential output slew rate

Parameter Symbol

Differential output slew rate SRQdiff 5 10 5 10 5 10 5 10 V/ns

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals For Ron = RZQ/7 setting

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Min Max Min Max Min Max Min Max

Measured

From To

(AC) V

OLdiff

(AC) V

OHdiff

OLdiff

(AC)

OHdiff

Defined by

(AC)-V

OLdiff

Delta TRdiff

(AC)-V

OLdiff

Delta TFdiff

(AC)

OLdiff

(AC) and V

Units

OH-

(AC)

OHdiff

VTT

(AC)

OLdiff

delta TRdiffdelta TFdiff

Figure 7. Differential Output Slew Rate Definition

9.5 Reference Load for AC Timing and Output Slew Rate

Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

DDQ

CK/CK

DUT

Reference Point

Figure 8. Reference Load for AC Timing and Output Slew Rate

DQ DQS DQS

- 18 -

Ω

VTT = V

DDQ

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