Samsung F8275X, F8274X, C8278X, F8278X, S3C8275X User Manual

S3C8275X/F8275X/C8278X

/F8278X/C8274X/F8274X

8-BIT CMOS

MICROCONTROLLERS

USER'S MANUAL

Revision 1.4

Important Notice

The information in this publication has been carefully
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.

Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.

This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-Bit CMOS Microcontrollers
User's Manual, Revision 1.4
Publication Number: 21.4-S3-C8275X/F8275X/C8278X/F8278X/C8274X/F8274X-042007

© 2007 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.

"Typical" parameters can and do vary in different
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"Typicals" must be validated for each customer
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Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are
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objectives.

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San #24 Nongseo-Dong, Giheung-Gu
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TEL: (82)-(31)-209-5238
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Printed in the Republic of Korea

NOTIFICATION OF REVISIONS

ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea

PRODUCT NAME: S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-bit

CMOS Microcontroller

DOCUMENT NAME: S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X User's Manual,

Revision1.4

DOCUMENT NUMBER: 21.4-S3-C8275X/F8275X/C8278X/F8278X/C8274X/F8274X-042007

EFFECTIVE DATE: April, 2007

SUMMARY: As a result of additional product testing and evaluation, some specifications

published in the S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X User's
Manual, Revision 1, have been changed. These changes for
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X microcontroller,
which are described in detail in the Revision Descriptions section below,
are related to the followings:
— Chapter 16. Embedded flash memory interface
— Chapter 17. Electrical Data
— Chapter 7. Clock Circuit
— Chapter 2. Address Spaces

DIRECTIONS:

Please note the changes in your copy (copies) of the
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X User's Manual, Revision 1.
Or, simply attach the Revision Descriptions of the next page to
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X User's Manual, Revision 1.

REVISION HISTORY

Revision Date Remark

0 February, 2005 Preliminary spec for internal release only.
1 April, 2005 First edition. Reviewed by Finechips.

1.1 July, 2005 Second edition. Reviewed by Finechips.

1.2 August, 2005 Third edition. Reviewed by Finechips.

1.3 May, 2006 Fourth edition. Reviewed by Finechips

1.4 April, 2007 Fifth edition. Reviewed by Finechips

REVISION DESCRIPTIONS

1. Electrical Data

Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM

= − 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)

(T

A

Parameter Symbol Conditions Min Typ Max Unit

(2)

(1)

(3)

Programming time
Chip erasing time
Sector erasing time
Data access time

Number of writing/erasing FNwe

NOTES:

1. The programming time is the time during which one byte (8-bit) is programmed.

2. The chip erasing time is the time during which all 16K byte block is erased.

3. The sector erasing time is the time during which all 128 byte block is erased.

4. Maximum number of writing/erasing is 10,000 times for full-flash(S3F8275) and 100 times for half-flash
(S3F8278X/F8274X).

5. The chip erasing is available in Tool Program Mode only.

Ftp
Ftp1
Ftp2
Ft

RS

−

−

−

− −

− − −

30

50

10

− − µs

− −

− −

25

−

10,000

(4)

ms
ms

ns

Times

2. Condition of Operating Voltage

Condition of operating voltage is modified “fx = 0 − 4.2MHz” to “fx = 0.4 − 4.2MHz” at 2.0V – 3.6V and
“fx = 0 − 8MHz” to “fx = 0.4 − 8MHz” at 2.5V − 3.6V in the page 17-2.

3. CHAPTHER 16. Embedded Flash Memory Interface

This chapter is modified for only S3F8275X.

4. CHAPTHER 7. Clock Circuit

The contents of OSCCON.7 should be changed “ 0 = Select normal circuit for sub oscillator” into “ 0 = Initial state”
in the page 4-21 and Figure 7-10.

It is added “NOTE: The OSCCON.7 should be maintained to “1”, during the sub oscillator operation.” In the page
4-21 and Figure 7-10.

The figure 7-7 is modified partly.

Descriptions of Revision 1.4

1. Smart Option Area

The Figures are modified about smart option area. Those are “Figure 2-1. Program Memory Address Space” and
“Figure 5-3. ROM Vector Address Area”.

2. CHAPTHER 17. Electrical Data

It is changed “VDD = 2.0 V to 3.6 V” into “VDD = 2.2 V to 3.6 V” in the Table 17-12.

3. DEVICE NAME

The device name is changed S3C8275/F8275/C8278/F8278/C8274/F8274 to
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X. The ‘X’ means ‘Commercial type’.

Preface

The S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Microcontroller User's Manual is designed for
application designers and programmers who are using the S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
microcontroller for application development. It is organized in two main parts:

Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming

model, instruction set, and interrupt structure. It has six chapters:
Chapter 1 Product Overview

Chapter 2 Address Spaces
Chapter 3 Addressing Modes

Chapter 1, "Product Overview," is a high-level introduction to
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X with general product descriptions, as well as detailed
information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined
stack operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
S3C8-series CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.

Chapter 5, "Interrupt Structure," describes the S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X interrupt
structure in detail and further prepares you for additional information presented in the individual hardware module
descriptions in Part II.

Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of
each instruction are presented in a standard format. Each instruction description includes one or more practical
examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the
first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed
information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.

Chapter 4 Control Registers
Chapter 5 Interrupt Structure
Chapter 6 Instruction Set

Part II "hardware Descriptions," has detailed information about specific hardware components of the
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X microcontroller. Also included in Part II are electrical,
mechanical, Flash MCU, and development tools data. It has 14 chapters:

Chapter 7 Clock Circuit
Chapter 8 RESET and Power-Down
Chapter 9 I/O Ports
Chapter 10 Basic Timer
Chapter 11 Timer 1
Chapter 12 Watch Timer
Chapter 13 LCD Controller/Driver
Chapter 14 Serial I/O Interface

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER iii

Chapter 15 Battery Level Detector
Chapter 16 Embedded Flash Memory Interface
Chapter 17 Electrical Data
Chapter 18 Mechanical Data
Chapter 19 S3F8275X/F8278X/F8274X

Flash MCU

Chapter 20 Development Tools

Table of Contents

Part I — Programming Model

Chapter 1 Product Overview

S3C8-Series Microcontrollers .......................................................................................................................1-1

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Microcontroller.......................................................1-1

Flash..............................................................................................................................................................1-1

Features ........................................................................................................................................................1-2

Block Diagram...............................................................................................................................................1-3

Pin Assignment .............................................................................................................................................1-4

Pin Descriptions ............................................................................................................................................1-6

Pin Circuits ....................................................................................................................................................1-8

Chapter 2 Address Spaces

Overview........................................................................................................................................................2-1

Program Memory (ROM)...............................................................................................................................2-2

Smart Option.........................................................................................................................................2-3

Register Architecture.....................................................................................................................................2-5

Register Page Pointer (PP)..................................................................................................................2-8

Register Set 1.......................................................................................................................................2-10

Register Set 2.......................................................................................................................................2-10

Prime Register Space...........................................................................................................................2-11

Working Registers ................................................................................................................................2-12

Using the Register Points.....................................................................................................................2-13

Register Addressing......................................................................................................................................2-15

Common Working Register Area (C0H–CFH) .....................................................................................2-17

4-Bit Working Register Addressing ......................................................................................................2-18

8-Bit Working Register Addressing ......................................................................................................2-20

System and User Stack.................................................................................................................................2-22

Chapter 3 Addressing Modes

Overview........................................................................................................................................................3-1

Register Addressing Mode (R)......................................................................................................................3-2

Indirect Register Addressing Mode (IR)........................................................................................................3-3

Indexed Addressing Mode (X).......................................................................................................................3-7

Direct Address Mode (DA) ............................................................................................................................3-10

Indirect Address Mode (IA) ...........................................................................................................................3-12

Relative Address Mode (RA).........................................................................................................................3-13

Immediate Mode (IM)....................................................................................................................................3-14

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER v

Table of Contents (Continued)

Chapter 4 Control Registers

Overview....................................................................................................................................................... 4-1

Chapter 5 Interrupt Structure

Overview....................................................................................................................................................... 5-1

Interrupt Types..................................................................................................................................... 5-2

S3C8275X/C8278X/C8274X Interrupt Structure................................................................................. 5-3

Interrupt Vector Addresses.................................................................................................................. 5-4

Enable/Disable Interrupt Instructions (EI, DI) ...................................................................................... 5-6

System-Level Interrupt Control Registers............................................................................................ 5-6

Interrupt Processing Control Points..................................................................................................... 5-7

Peripheral Interrupt Control Registers................................................................................................. 5-8

System Mode Register (SYM) ............................................................................................................. 5-9

Interrupt Mask Register (IMR) ............................................................................................................. 5-10

Interrupt Priority Register (IPR)............................................................................................................ 5-11

Interrupt Request Register (IRQ)......................................................................................................... 5-13

Interrupt Pending Function Types........................................................................................................ 5-14

Interrupt Source Polling Sequence...................................................................................................... 5-15

Interrupt Service Routines ................................................................................................................... 5-15

Generating Interrupt Vector Addresses............................................................................................... 5-16

Nesting of Vectored Interrupts............................................................................................................. 5-16

Instruction Pointer (IP)......................................................................................................................... 5-16

Fast Interrupt Processing..................................................................................................................... 5-16

Chapter 6 Instruction Set

Overview....................................................................................................................................................... 6-1

Data Types........................................................................................................................................... 6-1

Register Addressing............................................................................................................................. 6-1

Addressing Modes............................................................................................................................... 6-1

Flags Register (FLAGS)....................................................................................................................... 6-6

Flag Descriptions ................................................................................................................................. 6-7

Instruction Set Notation........................................................................................................................ 6-8

Condition Codes .................................................................................................................................. 6-12

Instruction Descriptions........................................................................................................................ 6-13

vi S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER

Table of Contents (Continued)

Part II Hardware Descriptions

Chapter 7 Clock Circuit

Overview........................................................................................................................................................7-1

System Clock Circuit ............................................................................................................................7-1

Main Oscillator Circuits.........................................................................................................................7-2

Sub Oscillator Circuits ..........................................................................................................................7-2

Clock Status During Power-Down Modes............................................................................................7-3

System Clock Control Register (CLKCON)..........................................................................................7-4

Clock Output Control Register (CLOCON)...........................................................................................7-5

Oscillator Control Register (OSCCON)................................................................................................7-6

Switching the CPU Clock......................................................................................................................7-7

Chapter 8 RESET and Power-Down

System Reset................................................................................................................................................8-1

Overview...............................................................................................................................................8-1

Normal Mode Reset Operation.............................................................................................................8-1

Hardware Reset Values........................................................................................................................8-2

Power-Down Modes......................................................................................................................................8-5

Stop Mode ............................................................................................................................................8-5

Idle Mode..............................................................................................................................................8-6

Chapter 9 I/O Ports

Overview........................................................................................................................................................9-1

Port Data Registers ..............................................................................................................................9-2

port 0.....................................................................................................................................................9-3

port 1.....................................................................................................................................................9-7

port 2.....................................................................................................................................................9-11

port 3.....................................................................................................................................................9-13

Port 4 ....................................................................................................................................................9-15

Port 5 ....................................................................................................................................................9-17

Port 6 ....................................................................................................................................................9-19

Chapter 10 Basic Timer

Overview........................................................................................................................................................10-1

Basic Timer Control Register (BTCON) ...............................................................................................10-2

Basic Timer Function Description.........................................................................................................10-3

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER vii

Table of Contents (Continued)

Chapter 11 Timer 1

One 16-bit Timer Mode (Timer 1)................................................................................................................. 11-1

Overview.............................................................................................................................................. 11-1

Function Description............................................................................................................................ 11-1

Two 8-bit Timers Mode (Timer A and B) ...................................................................................................... 11-4

Overview.............................................................................................................................................. 11-4

Function Description............................................................................................................................ 11-4

Chapter 12 Watch Timer

Overview....................................................................................................................................................... 12-1

Watch Timer Control Register (WTCON) ............................................................................................ 12-2

Watch Timer Circuit Diagram............................................................................................................... 12-3

Chapter 13 LCD Controller/Driver

Overview....................................................................................................................................................... 13-1

LCD Circuit Diagram............................................................................................................................13-2

LCD RAM Address Area......................................................................................................................13-3

LCD Control Register (LCON)............................................................................................................. 13-4

LCD Voltage Dividing Resistor ............................................................................................................ 13-5

Common (COM) Signals...................................................................................................................... 13-6

Segment (SEG) Signals....................................................................................................................... 13-6

Chapter 14 Serial I/O Interface

Overview....................................................................................................................................................... 14-1

Programming Procedure...................................................................................................................... 14-1

SIO Control Registers (SIOCON)........................................................................................................ 14-2

SIO Pre-Scaler Register (SIOPS)........................................................................................................ 14-3

SIO Block Diagram....................................................................................................................................... 14-3

Serial I/O Timing Diagram (SIO).......................................................................................................... 14-4

Chapter 15 Battery Level Detector

Overview....................................................................................................................................................... 15-1

Battery Level Detector Control Register (BLDCON)............................................................................ 15-2

viii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER

Table of Contents (Continued)

Chapter 16 Embedded Flash Memory Interface

Overview........................................................................................................................................................16-1

User Program Mode......................................................................................................................................16-2

Flash Memory Control Registers (User Program Mode)......................................................................16-2

ISPTM (On-Board Programming) Sector.......................................................................................................16-5

Sector Erase..................................................................................................................................................16-7

Programming.................................................................................................................................................16-9

Reading.........................................................................................................................................................16-11

Hard Lock Protection.....................................................................................................................................16-12

Chapter 17 Electrical Data

Overview........................................................................................................................................................17-1

Chapter 18 Mechanical Data

Overview........................................................................................................................................................18-1

Chapter 19 S3F8275X/F8278X/F8274X Flash MCU

Overview........................................................................................................................................................19-1

Operating Mode Characteristics...........................................................................................................19-5

Chapter 20 Development Tools

Overview........................................................................................................................................................20-1

SHINE...................................................................................................................................................20-1

SAMA Assembler..................................................................................................................................20-1

SASM88................................................................................................................................................20-1

HEX2ROM............................................................................................................................................20-1

Target Boards.......................................................................................................................................20-1

TB8275/8/4 Target Board.....................................................................................................................20-3

SMDS2+ Selection (SAM8)..................................................................................................................20-6

Idle LED................................................................................................................................................20-6

Stop LED ..............................................................................................................................................20-6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER ix

List of Figures

Figure Title Page
Number Number

1-1 Block Diagram ............................................................................................................1-3

1-2 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments

(64-QFP-1420F).........................................................................................................1-4

1-3 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments

(64-LQFP-1010) .........................................................................................................1-5

1-4 Pin Circuit Type A.......................................................................................................1-8

1-5 Pin Circuit Type B (nRESET) .....................................................................................1-8

1-6 Pin Circuit Type E-4 (P0, P1) .....................................................................................1-8

1-7 Pin Circuit Type H-4 ...................................................................................................1-9

1-8 Pin Circuit Type H-8 (P2.1–P2.7, P3).........................................................................1-9

1-9 Pin Circuit Type H-9 (P4, P5, P6)...............................................................................1-10

1-10 Pin Circuit Type H-10 (P2.0).......................................................................................1-11

2-1 Program Memory Address Space..............................................................................2-2

2-2 Smart Option...............................................................................................................2-3

2-3 Internal Register File Organization (S3C8275X)........................................................2-6

2-4 Internal Register File Organization (S3C8278X/C8274X)..........................................2-7

2-5 Register Page Pointer (PP)........................................................................................2-8

2-6 Set 1, Set 2, Prime Area Register, and LCD Data Register Map...............................2-11

2-7 8-Byte Working Register Areas (Slices).....................................................................2-12

2-8 Contiguous 16-Byte Working Register Block.............................................................2-13

2-9 Non-Contiguous 16-Byte Working Register Block .....................................................2-14

2-10 16-Bit Register Pair ....................................................................................................2-15

2-11 Register File Addressing ............................................................................................2-16

2-12 Common Working Register Area................................................................................2-17

2-13 4-Bit Working Register Addressing ............................................................................2-19

2-14 4-Bit Working Register Addressing Example .............................................................2-19

2-15 8-Bit Working Register Addressing ............................................................................2-20

2-16 8-Bit Working Register Addressing Example .............................................................2-21

2-17 Stack Operations........................................................................................................2-22

3-1 Register Addressing...................................................................................................3-2

3-2 Working Register Addressing.....................................................................................3-2

3-3 Indirect Register Addressing to Register File.............................................................3-3

3-4 Indirect Register Addressing to Program Memory.....................................................3-4

3-5 Indirect Working Register Addressing to Register File ..............................................3-5

3-6 Indirect Working Register Addressing to Program or Data Memory..........................3-6

3-7 Indexed Addressing to Register File ..........................................................................3-7

3-8 Indexed Addressing to Program or Data Memory with Short Offset..........................3-8

3-9 Indexed Addressing to Program or Data Memory......................................................3-9

3-10 Direct Addressing for Load Instructions .....................................................................3-10

3-11 Direct Addressing for Call and Jump Instructions......................................................3-11

3-12 Indirect Addressing.....................................................................................................3-12

3-13 Relative Addressing....................................................................................................3-13

3-14 Immediate Addressing................................................................................................3-14

4-1 Register Description Format.......................................................................................4-4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xi

List of Figures

Figure Title Page
Number Number

5-1 S3C8-Series Interrupt Types..................................................................................... 5-2

5-2 S3C8275X/C8278X/C8274X Interrupt Structure....................................................... 5-3

5-3 ROM Vector Address Area ........................................................................................ 5-4

5-4 Interrupt Function Diagram........................................................................................ 5-7

5-5 System Mode Register (SYM) ................................................................................... 5-9

5-6 Interrupt Mask Register (IMR) ................................................................................... 5-10

5-7 Interrupt Request Priority Groups..............................................................................5-11

5-8 Interrupt Priority Register (IPR) ................................................................................. 5-12

5-9 Interrupt Request Register (IRQ)............................................................................... 5-13

6-1 System Flags Register (FLAGS) ............................................................................... 6-6

7-1 Crystal/Ceramic Oscillator (fx)................................................................................... 7-2

7-2 External Oscillator (fx)................................................................................................ 7-2

7-3 RC Oscillator (fx)........................................................................................................ 7-2

7-4 Crystal Oscillator (fxt)................................................................................................. 7-2

7-5 External Oscillator (fxt)............................................................................................... 7-2

7-6 System Clock Circuit Diagram................................................................................... 7-3

7-7 System Clock Control Register (CLKCON)............................................................... 7-4

7-8 Clock Output Control Register (CLOCON)................................................................ 7-5

7-9 Clock Output Block Diagram...................................................................................... 7-5

7-10 Oscillator Control Register (OSCCON) ..................................................................... 7-6

7-11 STOP Control Register (STPCON)............................................................................ 7-8

9-1 S3C8275X/C8278X/C8274X I/O Port Data Register Format.................................... 9-2

9-2 Port 0 High-Byte Control Register (P0CONH)........................................................... 9-4

9-3 Port 0 Low-Byte Control Register (P0CONL)............................................................ 9-4

9-4 Port 0 Pull-up Control Register (P0PUR) .................................................................. 9-5

9-5 External Interrupt Control Register, Low Byte (EXTICONL)...................................... 9-5

9-6 External Interrupt Pending Register (EXTIPND) ....................................................... 9-6

9-7 Port 1 High-Byte Control Register (P1CONH)........................................................... 9-8

9-8 Port 1 Low-Byte Control Register (P1CONL)............................................................ 9-8

9-9 Port 1 Pull-up Control Register (P1PUR) .................................................................. 9-9

9-10 External Interrupt Control Register, High Byte (EXTICONH) .................................... 9-9

9-11 External Interrupt Control Register, Low Byte (EXTICONL)...................................... 9-10

9-12 External Interrupt Pending Register (EXTIPND) ....................................................... 9-10

9-13 Port 2 High-byte Control Register (P2CONH)........................................................... 9-11

9-14 Port 2 Low-byte Control Register (P2CONL)............................................................. 9-12

9-15 Port 2 Pull-up Control Register (P2PUR) .................................................................. 9-12

9-16 Port 3 High Byte Control Register (P3CONH)........................................................... 9-13

9-17 Port 3 Low Byte Control Register (P3CONL) ............................................................ 9-14

9-18 Port 3 Pull-up Control Register (P3PUR) .................................................................. 9-14

xii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER

List of Figures (Continued)

Page Title Page
Number Number

9-19 Port 4 High-Byte Control Register (P4CONH) ...........................................................9-15

9-20 Port 4 Low-Byte Control Register (P4CONL).............................................................9-16

9-21 Port 5 High-Byte Control Register (P5CONH) ...........................................................9-17

9-22 Port 5 Low-Byte Control Register (P5CONL).............................................................9-18

9-23 Port 6 Control Register (P6CON)...............................................................................9-19

10-1 Basic Timer Control Register (BTCON) .....................................................................10-2

10-2 Basic Timer Block Diagram........................................................................................10-4

11-1 Timer 1/A Control Register (TACON).........................................................................11-2

11-2 Timer 1 Block Diagram (One 16-bit Mode) ................................................................11-3

11-3 Timer 1/A Control Register (TACON).........................................................................11-5

11-4 Timer B Control Register (TBCON)............................................................................11-6

11-5 Timer A Block Diagram(Two 8-bit Timers Mode).......................................................11-7

11-6 Timer B Block Diagram (Two 8-bit Timers Mode)......................................................11-8

12-1 Watch Timer Control Register (WTCON)...................................................................12-2

12-2 Watch Timer Circuit Diagram .....................................................................................12-3

13-1 LCD Function Diagram...............................................................................................13-1

13-2 LCD Circuit Diagram...................................................................................................13-2

13-3 LCD Display Data RAM Organization ........................................................................13-3

13-4 LCD Control Register (LCON)....................................................................................13-4

13-5 Internal Voltage Dividing Resistor Connection...........................................................13-5

13-6 Select/No-Select Signals in Static Display Mode.......................................................13-6

13-7 Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode .....................................13-7

13-8 Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode .....................................13-7

13-9 LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode............13-8

14-1 Serial I/O Module Control Register (SIOCON)...........................................................14-2

14-2 SIO Prescaler Register (SIOPS)................................................................................14-3

14-3 SIO Functional Block Diagram ...................................................................................14-3

14-4 Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) ..............14-4

14-5 Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)...............14-4

15-1 Block Diagram for Voltage Level Detect.....................................................................15-1

15-2 Battery Level Detect Circuit and Control Register......................................................15-2

16-1 Flash Memory Control Register (FMCON).................................................................16-2

16-2 Flash Memory User-Programming Enable Register (FMUSR)..................................16-3

16-3 Flash Memory Sector Address Register, High Byte (FMSECH)................................16-4

16-4 Flash Memory Sector Address Register, Low Byte (FMSECL) .................................16-4

16-5 Program Memory Address Space..............................................................................16-5

16-6 Sector Configurations in User Program Mode ...........................................................16-7

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xiii

List of Figures (Concluded)

Page Title Page
Number Number

17-1 Stop Mode Release Timing When Initiated by an External Interrupt......................... 17-5

17-2 Stop Mode Release Timing When Initiated by a RESET .......................................... 17-6

17-3 Input Timing for External Interrupts ........................................................................... 17-7

17-4 Input Timing for RESET............................................................................................. 17-8

17-5 Serial Data Transfer Timing....................................................................................... 17-8

17-6 LVR (Low Voltage Reset) Timing .............................................................................. 17-9

17-7 Clock Timing Measurement at XIN............................................................................. 17-11

17-8 Clock Timing Measurement at XTIN.......................................................................... 17-12

17-9 Operating Voltage Range .......................................................................................... 17-13

18-1 64-Pin QFP Package Dimensions (64-QFP-1420F) ................................................. 18-1

18-2 64-Pin LQFP Package Dimensions (64-LQFP-1010)................................................ 18-2

19-1 S3F8275X/F8278X/F8274X Pin Assignments (64-QFP-1420F)............................... 19-2

19-2 S3F8275X/F8278X/F8274X Pin Assignments (64-LQFP-1010)............................... 19-3

19-3 Operating Voltage Range .......................................................................................... 19-7

20-1 SMDS Product Configuration (SMDS2+)................................................................... 20-2

20-2 TB8275/8/4 Target Board Configuration.................................................................... 20-3

20-3 40-Pin Connectors (J101, J102) for TB8275/8/4....................................................... 20-7

20-4 S3E8270 Cables for 64-QFP Package...................................................................... 20-7

xiv S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER

List of Tables

Table Title Page
Number Number

1-1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions .................1-6

2-1 S3C8275X Register Type Summary..........................................................................2-5

2-2 S3C8278X/C8274X Register Type Summary............................................................2-5

4-1 Set 1 Registers...........................................................................................................4-1

4-2 Set 1, Bank 0 Registers..............................................................................................4-2

4-3 Set 1, Bank 1 Registers..............................................................................................4-3

5-1 Interrupt Vectors.........................................................................................................5-5

5-2 Interrupt Control Register Overview...........................................................................5-6

5-3 Interrupt Source Control and Data Registers.............................................................5-8

6-1 Instruction Group Summary.......................................................................................6-2

6-2 Flag Notation Conventions.........................................................................................6-8

6-3 Instruction Set Symbols..............................................................................................6-8

6-4 Instruction Notation Conventions...............................................................................6-9

6-5 Opcode Quick Reference...........................................................................................6-10

6-6 Condition Codes.........................................................................................................6-12

8-1 S3C8275X/C8278X/C8274X Set 1 Register and Values After RESET.....................8-2

8-2 S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After RESET...............8-3

8-3 S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After RESET...............8-4

9-1 S3C8275X/C8278X/C8274X Port Configuration Overview .......................................9-1

9-2 Port Data Register Summary .....................................................................................9-2

13-1 LCD Clock Signal Frame Frequency .........................................................................13-3

15-1 BLDCON Value and Detection Level.........................................................................15-2

16-1 ISP Sector Size ..........................................................................................................16-6

16-2 Reset Vector Address ................................................................................................16-6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xv

List of Tables (Continued)

Table Title Page
Number Number

17-1 Absolute Maximum Ratings........................................................................................17-2

17-2 D.C. Electrical Characteristics....................................................................................17-2

17-3 Data Retention Supply Voltage in Stop Mode............................................................17-5

17-4 Input/Output Capacitance...........................................................................................17-6

17-5 A.C. Electrical Characteristics....................................................................................17-7

17-6 Battery Level Detector Electrical Characteristics .......................................................17-9

17-7 LVR (Low Voltage Reset) Electrical Characteristics ..................................................17-9

17-8 Main Oscillation Characteristics .................................................................................17-10

17-9 Sub Oscillation Characteristics...................................................................................17-10

17-10 Main Oscillation Stabilization Time.............................................................................17-11

17-11 Sub Oscillation Stabilization Time..............................................................................17-12

17-12 A.C. Electrical Characteristics for Internal Flash ROM ..............................................17-13

19-1 Descriptions of Pins Used to Read/Write the Flash ROM..........................................19-4

19-2 Comparison of S3F8275X/F8278X/F8274X and

S3C8275X/C8278X/C8274X Features.......................................................................19-4

19-3 Operating Mode Selection Criteria .............................................................................19-5

19-4 D.C. Electrical Characteristics....................................................................................19-6

20-1 Power Selection Settings for TB8275/8/4...................................................................20-4

20-2 Main-clock Selection Settings for TB8275/8/4............................................................20-4

20-3 Select Smart Option Source Setting for TB8275/8/4..................................................20-5

20-4 Smart Option Switch Settings for TB8275/8/4............................................................20-5

20-5 Device Selection Settings for TB8275/8/4..................................................................20-6

20-6 The SMDS2+ Tool Selection Setting..........................................................................20-6

xvi S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER

List of Programming Tips

Description Page
Number
Chapter 2: Address Spaces

Using the Page Pointer for RAM Clear (Page 0, Page 1) ........................................................................2-9

Setting the Register Pointers....................................................................................................................2-13

Using the RPs to Calculate the Sum of a Series of Registers .................................................................2-14

Addressing the Common Working Register Area.....................................................................................2-18

Standard Stack Operations Using PUSH and POP .................................................................................2-23

Chapter 5: Interrupt Structure

How to clear an interrupt pending bit........................................................................................................5-15

Chapter 7: Clock Circuit

Switching the CPU Clock..........................................................................................................................7-7

Chapter 16: Embedded Flash Memory Interface

Sector Erase.............................................................................................................................................16-8

Program....................................................................................................................................................16-10

Reading.....................................................................................................................................................16-11

Hard Lock Protection................................................................................................................................16-12

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xvii

List of Register Descriptions

Register Full Register Name Page
Identifier Number

BLDCON Battery Level Detector Control Register ....................................................................4-5

BTCON Basic Timer Control Register.....................................................................................4-6

CLKCON System Clock Control Register..................................................................................4-7

CLOCON Clock Output Control Register ...................................................................................4-8

EXTICONH External Interrupt Control Register (High Byte) .........................................................4-9

EXTICONL External Interrupt Control Register (Low Byte)..........................................................4-10

EXITPND External Interrupt Pending Register...........................................................................4-11

FLAGS System Flags Register...............................................................................................4-12

FMCON Flash Memory Control Register .................................................................................4-13

FMSECH Flash Memory Sector Address Register (High Byte).................................................4-14

FMSECL Flash Memory Sector Address Register (Low Byte)..................................................4-14

FMUSR Flash Memory User Programming Enable Register..................................................4-15

IMR Interrupt Mask Register..............................................................................................4-16

IPH Instruction Pointer (High Byte)...................................................................................4-17

IPL Instruction Pointer (Low Byte)....................................................................................4-17

IPR Interrupt Priority Register ...........................................................................................4-18

IRQ Interrupt Request Register.........................................................................................4-19

LCON LCD Control Register.................................................................................................4-20

OSCCON Oscillator Control Register.........................................................................................4-21

P0CONH Port 0 Control Register (High Byte)............................................................................4-22

P0CONL Port 0 Control Register (Low Byte) ............................................................................4-23

P0PUR Port 0 Pull-Up Control Register..................................................................................4-24

P1CONH Port 1 Control Register (High Byte)............................................................................4-25

P1CONL Port 1 Control Register (Low Byte) ............................................................................4-26

P1PUR Port 1 Pull-up Control Register ..................................................................................4-27

P2CONH Port 2 Control Register (High Byte)............................................................................4-28

P2CONL Port 2 Control Register (Low Byte) ............................................................................4-29

P2PUR Port 2 Pull-up Control Register ..................................................................................4-30

P3CONH Port 3 Control Register (High Byte)............................................................................4-31

P3CONL Port 3 Control Register (Low Byte) ............................................................................4-32

P3PUR Port 3 Pull-up Control Register ..................................................................................4-33

P4CONH Port 4 Control Register (High Byte)............................................................................4-34

P4CONL Port 4 Control Register (Low Byte) ............................................................................4-35

P5CONH Port 5 Control Register (High Byte)............................................................................4-36

P5CONL Port 5 Control Register (Low Byte) ............................................................................4-37

P6CON Port 6 Control Register...............................................................................................4-38

PP Register Page Pointer................................................................................................4-39

RP0 Register Pointer 0.......................................................................................................4-40

RP1 Register Pointer 1.......................................................................................................4-40

SIOCON SIO Control Register..................................................................................................4-41

SPH Stack Pointer (High Byte)...........................................................................................4-42

SPL Stack Pointer (Low Byte)............................................................................................4-42

STPCON Stop Control Register.................................................................................................4-43

SYM System Mode Register...............................................................................................4-44

TACON Timer 1/A Control Register.........................................................................................4-45

TBCON Timer B Control Register............................................................................................4-46

WTCON Watch Timer Control Register....................................................................................4-47

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xix

List of Instruction Descriptions

Instruction Full Register Name Page
Mnemonic Number

ADC Add with Carry............................................................................................................6-14

ADD Add .............................................................................................................................6-15

AND Logical AND ...............................................................................................................6-16

BAND Bit AND.......................................................................................................................6-17

BCP Bit Compare ...............................................................................................................6-18

BITC Bit Complement..........................................................................................................6-19

BITR Bit Reset.....................................................................................................................6-20

BITS Bit Set.........................................................................................................................6-21

BOR Bit OR.........................................................................................................................6-22

BTJRF Bit Test, Jump Relative on False ...............................................................................6-23

BTJRT Bit Test, Jump Relative on True.................................................................................6-24

BXOR Bit XOR.......................................................................................................................6-25

CALL Call Procedure............................................................................................................6-26

CCF Complement Carry Flag .............................................................................................6-27

CLR Clear...........................................................................................................................6-28

COM Complement...............................................................................................................6-29

CP Compare.....................................................................................................................6-30

CPIJE Compare, Increment, and Jump on Equal .................................................................6-31

CPIJNE Compare, Increment, and Jump on Non-Equal .........................................................6-32

DA Decimal Adjust ...........................................................................................................6-33

DEC Decrement..................................................................................................................6-35

DECW Decrement Word ........................................................................................................6-36

DI Disable Interrupts.......................................................................................................6-37

DIV Divide (Unsigned).......................................................................................................6-38

DJNZ Decrement and Jump if Non-Zero..............................................................................6-39

EI Enable Interrupts........................................................................................................6-40

ENTER Enter...........................................................................................................................6-41

EXIT Exit..............................................................................................................................6-42

IDLE Idle Operation.............................................................................................................6-43

INC Increment ...................................................................................................................6-44

INCW Increment Word..........................................................................................................6-45

IRET Interrupt Return..........................................................................................................6-46

JP Jump...........................................................................................................................6-47

JR Jump Relative.............................................................................................................6-48

LD Load............................................................................................................................6-49

LDB Load Bit ......................................................................................................................6-51

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xxi

List of Instruction Descriptions (Continued)

Instruction Full Register Name Page
Mnemonic Number

LDC/LDE Load Memory..............................................................................................................6-52

LDCD/LDED Load Memory and Decrement....................................................................................6-54

LDCI/LDEI Load Memory and Increment......................................................................................6-55

LDCPD/LDEPD Load Memory with Pre-Decrement.............................................................................6-56

LDCPI/LDEPI Load Memory with Pre-Increment ..............................................................................6-57

LDW Load Word ..................................................................................................................6-58

MULT Multiply (Unsigned).....................................................................................................6-59

NEXT Next.............................................................................................................................6-60

NOP No Operation ..............................................................................................................6-61

OR Logical OR..................................................................................................................6-62

POP Pop from Stack...........................................................................................................6-63

POPUD Pop User Stack (Decrementing).................................................................................6-64

POPUI Pop User Stack (Incrementing) ..................................................................................6-65

PUSH Push to Stack..............................................................................................................6-66

PUSHUD Push User Stack (Decrementing)...............................................................................6-67

PUSHUI Push User Stack (Incrementing) ................................................................................6-68

RCF Reset Carry Flag.........................................................................................................6-69

RET Return.........................................................................................................................6-70

RL Rotate Left..................................................................................................................6-71

RLC Rotate Left through Carry...........................................................................................6-72

RR Rotate Right................................................................................................................6-73

RRC Rotate Right through Carry.........................................................................................6-74

SB0 Select Bank 0..............................................................................................................6-75

SB1 Select Bank 1..............................................................................................................6-76

SBC Subtract with Carry .....................................................................................................6-77

SCF Set Carry Flag.............................................................................................................6-78

SRA Shift Right Arithmetic..................................................................................................6-7

SRP/SRP0/SRP1 Set Register Pointer....................................................................................................6-80

STOP Stop Operation............................................................................................................6-81

SUB Subtract ......................................................................................................................6-82

SWAP Swap Nibbles..............................................................................................................6-83

TCM Test Complement under Mask ...................................................................................6-84

TM Test under Mask.........................................................................................................6-85

WFI Wait for Interrupt.........................................................................................................6-86

XOR Logical Exclusive OR..................................................................................................6-87

9

xxii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:

• Efficient register-oriented architecture

• Selectable CPU clock sources

• Idle and Stop power-down mode release by interrupt or reset

• Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to
specific interrupt levels.

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER

The S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X single-chip CMOS microcontrollers are fabricated
using the highly advanced CMOS process, based on Samsung's latest CPU architecture.

The S3C8275X/C8278X/C8274X is a microcontroller with a 16/8/4K-byte mask-programmable ROM embedded.
The S3F8275X/F8278X/F8274X is a microcontroller with a 16/8/4K-byte flash ROM embedded.
Using a proven modular design approach, Samsung engineers have successfully developed the

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X by integrating the following peripheral modules with the
powerful SAM8 core:

• Seven programmable I/O ports, including six 8-bit ports and one 4-bit port, for a total of 52 pins.

• Eight bit-programmable pins for external interrupts.

• One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).

• Two 8-bit timer/counter with selectable operating modes.

• Watch timer for real time

FLASH

The S3F8275X/F8278X/F8274X are FLASH version of the S3C8275X/C8278X/C8274X microcontroller. The
S3F8275X/F8278X/F8274X microcontroller has an on-chip FLASH ROM instead of a masked ROM. The
S3F8275X/F8278X/F8274X is comparable to the S3C8275X/C8278X/C8274X, both in function and in pin
configuration. The S3F8275X only is a full flash. The full flash means that data can be written into the program
ROM by an instruction.

1-1

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

FEATURES

CPU

• SAM88RC CPU core

Memory

• Program Memory(ROM)

- 16K×8 bits program
memory(S3C8275X/F8275X)

- 8K×8 bits program
memory(S3C8278X/F8278X)

- 4K×8 bits program
memory(S3C8274X/F8274X)

- Internal flash memory(Program memory)
√ Sector size: 128 Bytes
√ 10 Years data retention
√ Fast programming time:
+ Chip erase: 50ms
+ Sector erase: 10ms
+ Byte program: 30us
√ User programmable by ‘LDC’ instruction
√ Endurance: 10,000 erase/program cycles
√ Sector(128-bytes) erase available
√ Byte programmable
√ External serial programming support
√ Expandable OBP

TM

(On board program)

sector

• Data Memory (RAM)

- Including LCD display data memory

- 544 × 8 bits data memory(S3C8275X/F8275X)

- 288 × 8 bits data memory(S3C8278X/F8278X)

- 288 × 8 bits data memory(S3C8274X/F8274X)

Instruction Set

• 78 instructions

• Idle and Stop instructions added for power-down

modes

52 I/O Pins

• I/O: 16 pins

• I/O: 36 pins (Sharing with LCD signal outputs)

Interrupts

• 8 interrupt levels and 12 interrupt sources

• Fast interrupt processing feature

8-Bit Basic Timer

• Watchdog timer function

• 4 kinds of clock source

Two 8-Bit Timer/Counters

• Programmable interval timer

• External event counter function

• Configurable as one 16-bit timer/counters

Watch Timer

• Interval time: 3.91mS, 0.25S, 0.5S, and 1S
at 32.768 kHz

• 0.5/1/2/4 kHz Selectable buzzer output

LCD Controller/Driver

• 32 segments and 4 common terminals

• Static, 1/2 duty, 1/3 duty, and 1/4 duty selectable

• Internal resistor circuit for LCD bias

8-bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive mode

• LSB-first or MSB-first transmission selectable

• Internal or External clock source

Battery Level Detector

• 3-criteria voltage selectable (2.2V, 2.4V, 2.8V)

• En/Disable by software for current consumption

source

Low Voltage Reset (LVR)

• Criteria voltage: 2.2V

• En/Disable by smart option (ROM address: 3FH)

Two Power-Down Modes

• Idle: only CPU clock stops

• Stop: selected system clock and CPU clock stop

Oscillation Sources

• Crystal, ceramic, or RC for main clock

• Main clock frequency: 0.4 MHz − 8 MHz

• 32.768 kHz crystal for sub clock

Instruction Execution Times

• 500nS at 8 MHz fx(minimum)

Operating Voltage Range

• 2.0 V to 3.6 V at 0.4 − 4.2 MHz

2.5 V to 3.6 V at 0.4 − 8.0 MHz

•

Operating Temperature Range

• −25 °C to +85 °C

Package Type

• 64-QFP-1420F, 64-LQFP-1010

Smart Option

• Low Voltage Reset(LVR) level and
enable/disable are at your hardwired option
(ROM address 3FH)

• ISP related option selectable
(ROM address 3EH)

1-2

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW

BLOCK DIAGRAM

TAOUT/P0.4

T1CLK/P0.3

TBOUT/P0.5

P0.6/CLKOUT

P2.0/SEG31/V

P2.1-P2.7/SEG30-SEG24

P3.0-P3.7/SEG23-SEG16

P4.0-P4.7/SEG15-SEG8

8-Bit Timer/
8-Bit Timer/

P0.0/INT0
P0.1/INT1
P0.2/INT2

P0.3/T1CLK
P0.4/TAOUT
P0.5/TBOUT

P0.7/BUZ

P1.0/SCK

P1.1/SO

P1.2/SI
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7

BLDREF

Counter A
Counter B

16-Bit

Timer/

Counter 1

I/O Port 0

I/O Port 1

I/O Port 2

I/O Port 3

I/O Port 4

X

IN

X

nRESET

XT

Port I/O and Interrupt Control

SAM88RC CPU

544/288 Byte

Register File

IN

OUT

XT

16/8/4-Kbyte

OUT

ROM

Watchdog

REG

V

Timer

Basic Timer

Low Voltage

Reset

Clock Out

Block

Battery Level

Detector

Watch Timer

LCD

Driver

SIO

I/O Port 6

I/O Port 5

CLKOUT/P0.6

V

BLDREF

/

P2.0/SEG31
BUZ/P0.7

COM0-COM3/P6.0-P6.3
SEG0-SEG7/P5.7-P5.0
SEG8-SEG15/P4.7-P4.0

SEG16-SEG23/P3.7-P3.0
SEG24-SEG30/P2.7-P2.1
SEG31/P2.0/V
VLC0-VLC2

P1.0/SCK
P1.1/SO
P1.2/SI

P6.0-P6.3/
COM0-COM3

P5.0-P5.7/
SEG7-SEG0

BLDREF

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

PIN ASSIGNMENT

SEG1/P5.6

SEG2/P5.5

SEG3/P5.4

SEG4/P5.3

SEG5/P5.2

SEG6/P5.1

SEG7/P5.0

SEG8/P4.7

SEG9/P4.6

SEG10/P4.5

SEG11/P4.4

SEG12/P4.3

SEG13/P4.2

64636261605958575655545352

SEG0/P5.7
COM0/P6.0
COM1/P6.1
COM2/P6.2
COM3/P6.3

VLC0
VLC1
VLC2

DD

V

VSS

XOUT

XIN

TEST

XT

XTOUT

nRESET

REG

V
P0.0/INT0
P0.1/INT1

1
2
3
4
5
6
7

S3C8275X/F8275X

8

S3C8278X/F8278X

9
10

S3C8274X/F8274X

11
12
13

IN

14
15
16
17
18
19

(64-QFP-1420F)

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SEG14/P4.1
SEG15/P4.0
SEG16/P3.7
SEG17/P3.6
SEG18/P3.5
SEG19/P3.4
SEG20/P3.3
SEG21/P3.2
SEG22/P3.1
SEG23/P3.0
SEG24/P2.7
SEG25/P2.6
SEG26/P2.5
SEG27/P2.4
SEG28/P2.3
SEG29/P2.2
SEG30/P2.1
SEG31/P2.0/V
P1.7/INT7

BLDREF

20212223242526272829303132

P1.2/SI

P1.1/SO

P0.7/BUZ

P0.6/CLKOUT

P1.0/SCK

P1.3/INT3

P1.4/INT4

P1.5/INT5

P1.6/INT6

P0.2/INT2

P0.3/T1CLK

P0.4/TAOUT

P0.5/TBOUT

Figure 1-2. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-QFP-1420F)

1-4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW

SEG1/P5.6

SEG2/P5.5

SEG3/P5.4

SEG4/P5.3

SEG5/P5.2

SEG6/P5.1

SEG7/P5.0

SEG8/P4.7

SEG9/P4.6

SEG10/P4.5

SEG11/P4.4

SEG12/P4.3

SEG13/P4.2

SEG14/P4.1

SEG15/P4.0

SEG16/P3.7

SEG0/P5.7
COM0/P6.0
COM1/P6.1
COM2/P6.2
COM3/P6.3

VLC0
VLC1
VLC2

V

DD

VSS

XOUT

XIN

TEST

XT

XTOUT

nRESET

646362616059585756555453525150

1
2
3
4
5
6
7
8
9
10
11
12
13

IN

14
15
16

S3C8275X/F8275X
S3C8278X/F8278X
S3C8274X/F8274X

(64-LQFP-1010)

171819202122232425262728293031

VREG

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3/T1CLK

P0.4/TAOUT

P0.5/TBOUT

P0.6/CLKOUT

P0.7/BUZ

P1.1/SO

P1.0/SCK

P1.2/SI

P1.3/INT3

P1.4/INT4

P1.5/INT5

49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

32

P1.6/INT6

SEG17/P3.6
SEG18/P3.5
SEG19/P3.4
SEG20/P3.3
SEG21/P3.2
SEG22/P3.1
SEG23/P3.0
SEG24/P2.7
SEG25/P2.6
SEG26/P2.5
SEG27/P2.4
SEG28/P2.3
SEG29/P2.2
SEG30/P2.1
SEG31/P2.0/V
P1.7/INT7

BLDREF

Figure 1-3. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-LQFP-1010)

1-5

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

PIN DESCRIPTIONS

Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions

Pin

Names

P0.0−P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P1.0
P1.1
P1.2
P1.3−P1.7

P2.0
P2.1−P2.7

P3.0−P3.7

P4.0−P4.7
P5.0−P5.7
P6.0−P6.3

Pin

Type

Pin

Description

I/O I/O port with bit-programmable pins;

Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups;
P0.0−P0.2 are alternately used for external
interrupt input(noise filters, interrupt enable
and pending control).

I/O I/O port with bit-programmable pins;

Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups;
P1.3−P1.7 are alternately used for external
interrupt input(noise filters, interrupt enable
and pending control).

I/O I/O port with bit-programmable pins;

Input or push-pull, open-drain output and
software assignable pull-ups.

I/O I/O port with bit-programmable pins;

Input or push-pull, open-drain output and
software assignable pull-ups.

I/O I/O port with bit-programmable pins;

Input or push-pull output and software
assignable pull-ups.

Circuit

Type

E-4

Pin
No.

18−20

21
22
23
24
25

E-4 26

27
28

29−33

H-10

H-8

H-8

H-9

34

35−41

42−49 SEG23−SEG16

50−57

58−64, 1

2−5

Shared

Functions

INT0−INT2

T1CLK
TAOUT
TBOUT

CLKOUT

BUZ
SCK

SO

SI

INT3−INT7

SEG31/V

BLDREF

SEG30−SEG24

SEG15−SEG8

SEG7−SEG0

COM0−COM3

1-6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW

Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions (Continued)

Pin

Names

VLC0−VLC2 −
INT0−INT2

INT3−INT7

Pin

Type

Pin

Description

Circuit

Type

LCD power supply pins.

I/O External interrupts input pins. E-4

Pin

No.

Shared

Functions

− 6−8 −
18−20

29−33

P0.0−P0.2

P1.3−P1.7
T1CLK I/O Timer 1/A external clock input. E-4 21 P0.3
TAOUT I/O Timer 1/A clock output. E-4 22 P0.4
TBOUT I/O Timer B clock output. E-4 23 P0.5
CLKOUT I/O System clock output. E-4 24 P0.6
BUZ I/O Output pin for buzzer signal. E-4 25 P0.7
SCK, SO, SI I/O Serial clock, data output, and data input. E-4 26,27,28 P1.0, P1.1, P1.2
COM0–COM3 I/O LCD common signal outputs. H-9
SEG0–SEG15

SEG16–SEG30
SEG31

V

BLDREF

V

REG

I/O LCD segment signal outputs. H-9

H-8

H-10

I/O Battery level detector reference voltage H-10 34 P2.0/SEG31

O Regulator voltage output for sub clock

−

2−5 P6.0−P6.3

1,64− 50

49−35

34

P5.7−P4.0

P3.7−P2.1

P2.0/V

17

BLDREF

−

(needed 0.1uF)
nRESET I System reset pin B 16
XTIN, XT

XIN, X
TEST I
VDD, VSS

OUT

OUT

Sub oscillator pins

−

Main oscillator pins.

−

Test input: it must be connected to V

Power input pins

−

SS

−

−

−

−

14, 15
12, 11

13

9, 10

−

−

−

−

−

1-7

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

PIN CIRCUITS

V

DD

V

DD

P-Channel

In

N-Channel

Figure 1-4. Pin Circuit Type A

Open
Drain

Pull-Up

Resistor

In

Schmitt Trigger

Figure 1-5. Pin Circuit Type B (nRESET)

V

DD

Pull-up

DD

Resistor

Resistor
Enable

P-CH

V

Data

Output

Disable

N-CH

Schmitt Trigger

I/O

Figure 1-6. Pin Circuit Type E-4 (P0, P1)

1-8

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW

V

LC0

V

LC1

COM/SEG

Out

Output

Disable

V

LC2

V

SS

Figure 1-7. Pin Circuit Type H-4

V

DD

Pull-Up
Resistor

Resistor
Enable

P-CH

I/O

Open Drain

Data

V

DD

Output

N-CH

Disable 1

SEG

Output

Circuit

Type H-4

Disable 2

Figure 1-8. Pin Circuit Type H-8 (P2.1– P2.7, P3)

1-9

PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

V

DD

Pull-Up

V

DD

Resistor

Resistor
Enable

P-CH

Data

Output

Disable 1

COM/SEG

Disable 2

I/O

N-CH

Circuit

Output

Type H-4

Figure 1-9. Pin Circuit Type H-9 (P4, P5, P6)

1-10

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW

V

DD

Pull-Up

V

DD

Resistor

Resistor

Open-Drain

Enable

P-CH

Data

Output

N-CH

I/O

Disable 1

SEG

Alternative

Function

Circuit

Type H-4

BLDEN

BLD Select

To BLD

Figure 1-10. Pin Circuit Type H-10 (P2.0)

1-11

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

2 ADDRESS SPACES

OVERVIEW

The S3C8275X/C8278X/C8274X microcontroller has two types of address space:

• Internal program memory (ROM)

• Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.

The S3C8275X has an internal 16-Kbyte mask-programmable ROM. The S3C8278X has an internal 8-Kbyte
mask-programmable ROM. The S3C8274X has an internal 4-Kbyte mask-programmable ROM.

The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing
modes.

A 16-byte LCD display register file is implemented.
There are 605 mapped registers in the internal register file. Of these, 528 are for general-purpose.

(This number includes a 16-byte working register common area used as a “scratch area” for data operations, two
192-byte prime register areas, and two 64-byte areas (Set 2)). Thirteen 8-bit registers are used for the CPU and
the system control, and 48 registers are mapped for peripheral controls and data registers. Nineteen register
locations are not mapped.

2-1

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program codes or table data. The S3C8275X has 16K bytes internal mask­programmable program memory, the S3C8278X has 8K bytes, the S3C8274X has 4K bytes.

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you use the vector address area to store a program
code, be careful not to overwrite the vector addresses stored in these locations.

The ROM address at which a program execution starts after a reset is 0100H.
The reset address of ROM can be changed by a smart option only in the S3F8275X (Full-Flash Device). Refer to

the chapter 16. Embedded Flash Memory Interface for more detail contents.

(Decimal)

16,383

(HEX)
3FFFH

16K-bytes

Internal

Program

Memory

Available

ISP Sector Area

255

Interrupt Vector Area

Smart Option Area

0

S3C8275X/F8275X

Area

8FFH

FFH
3FH
3CH

00H

(Decimal)

8,191

8K-bytes

Internal

Program

Memory

Area

255

Interrupt Vector Area

Smart Option Area

0

S3C8278X/F8278X

(HEX)
1FFFH

FFH

3FH
3CH

00H

(Decimal)

4,095

255

4K-bytes

Internal

Program

Memory

Area

Interrupt Vector Area

Smart Option Area

0

S3C8274X/F8274X

(HEX)
0FFFH

FFH
3FH
3CH

00H

Figure 2-1. Program Memory Address Space

2-2

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

SMART OPTION

ROM Address: 003EH

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

ISP reset vector change enable/disable bit:
0 = OBP reset vector address
1 = Normal vector (address 0100H)

ISP reset vector address selection bit:
00 = 200H (ISP area size: 256 byte)
01 = 300H (ISP area size: 512 byte)
10 = 500H (ISP area size: 1024 byte)
11 = 900H (ISP area size: 2048 byte)

Not used

Not used

ISP protection enable/disable bit:
0 = Enable (not erasable by LDC)
1 = Disable (erasable by LDC)

ROM Address: 003FH

These bits should be

always logic "110b".

ROM Address: 003CH

ISP protection size selection:
00 = 256 bytes
01 = 512 bytes
10 = 1024 bytes
11 = 2048 bytes

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

LVR enable/disable bit
(criteria voltage: 2.2V):
0 = Disable LVR
1 = Enable LVR

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

(note)

Not used

ROM Address: 003DH

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

Not used

NOTES:

1. After selecting ISP reset vector address in selecting ISP protection size, don't select upper than ISP
area size.

2. When any values are written in the Smart Option are a (003CH-003FH) by LDC instruction, the data of
the area may be changed but the Smart Option is not affected. The data for Smart Option should be
written in the Smart Option area (003CH-003FH) by OTP/MTP tools (SPW2 plus single
programmer, or GW-PRO2 gang programmer).

Figure 2-2. Smart Option

2-3

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from
003CH to 003FH.

The ISP of smart option (003EH) is available in the S3F8275X only. The default value of ROM address 003EH is
FFH. And ROM address 003EH should be kept FFH when used the
S3C8275X/C8278X/F8278X/C8274X/F8274X.

The LVR of smart option (003FH) is available in all the device,
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X. The default value of ROM address 003FH is FFH.

2-4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

REGISTER ARCHITECTURE

In the S3C8275X/C8278X/C8274X implementation, the upper 64-byte area of register files is expanded two
64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register
banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area.

In case of S3C8275X the total number of addressable 8-bit registers is 605. Of these 605 registers, 13 bytes are
for CPU and system control registers, 16 bytes are for LCD data registers, 48 bytes are for peripheral control and
data registers, 16 bytes are used as a shared working registers, and 512 registers are for general-purpose use,
page 0-page 1 (in case of S3C8278X/C8274X, page 0).

You can always address set 1 register locations, regardless of which of the two register pages is currently
selected. Set 1 locations, however, can only be addressed using register addressing modes.

The extension of register space into separately addressable areas (sets, banks, and pages) is supported by
various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer
(PP).

Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1.

Table 2-1. S3C8275X Register Type Summary

Register Type Number of Bytes

General-purpose registers (including the 16-byte
common working register area, two 192-byte prime
register area, and two 64-byte set 2 area)
LCD data registers
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers

Total Addressable Bytes

528

16
13
48

605

Table 2-2. S3C8278X/C8274X Register Type Summary

Register Type Number of Bytes

General-purpose registers (including the 16-byte
common working register area, one 192-byte prime
register area, and one 64-byte set 2 area)
LCD data registers
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers

Total Addressable Bytes

272

16
13
48

349

2-5

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

Set1

FFH

C0H
BFH

FFH

General-Purpose

(Indirect Register, Indexed

Mode, and Stack

Page 1

Page 1

Page 0

Set 2

Data Registers

Operations)

Page 0

256

Bytes

64

Bytes

32

Bytes

FFH

E0H
DFH

D0H
CFH

C0H

Bank 1

Bank 0

System and

Peripheral Control

System and

Peripheral Control

(Register Addressing Mode)

(Register Addressing Mode)

General Purpose Register

(Register Addressing Mode)

Registers

Registers

System Registers

E0H

16

Bytes

Page 2

0FH

Prime

Data Registers

~ ~

(All addressing modes)

LCD Display Re igster

00H

Figure 2-3. Internal Register File Organization (S3C8275X)

192

Bytes

~

~ ~

(All Addressing Modes)

00H

Prime

Data Registers

~

~

2-6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

Set1

64

Bytes

32

Bytes

16

Bytes

FFH

E0H

DFH

D0H

CFH

C0H

0FH

Peripheral Control

(Register Addressing Mode)

System Registers

(Register Addressing Mode)

General Purpose Register

(Register Addressing Mode)

Bank 1

Bank 0

System and

Peripheral Control

System and

Registers

Registers

Page 2

Prime

Data Registers

~ ~

(All addressing modes)

LCD Display Reigster

00H

E0H

Bytes

192

FFH

(Indirect Register, Indexed

C0H
BFH

~

~ ~

(All Addressing Modes)

00H

Page 0

Set 2

General-Purpose

Data Registers

Mode, and Stack

Operations)

Page 0

Prime

Data Registers

256

Bytes

NOTE: In case of S3C8278X/C8274X, there are page 0 and page 2.

Page 2 is for LCD display register, 16 bytes.

Figure 2-4. Internal Register File Organization (S3C8278X/C8274X)

2-7

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by
the register page pointer (PP, DFH). In the S3C8275X/C8278X/C8274X microcontroller, a paged register file
expansion is implemented for LCD data registers, and the register page pointer must be changed to address
other pages.

After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
"0000", automatically selecting page 0 as the source and destination page for register addressing.

Register Page Pointer (PP)

DFH, Set 1, R/W

LSBMSB .7 .6 .5 .4 .3 .2 .1 .0

Source register page selection bits:

0000 Source: Page 0
0001 Source: Page 1 (Not used for the S3C8278X/C8274X)
0010 Source: Page 2

others Not used for the S3C8275X/C8278X/C8274X

Destination register page selection bits:

0000 Destination: Page 0
0001 Destination: Page 1 (Not used for the S3C8278X/C8274X)
0010 Destination: Page 2

others Not used for the S3C8275X/C8278X/C8274X

NOTES:

1. In the S3C8275X microcontroller, the internal register file is configured as three pages (Pages 0-2).
The pages 0-1 are used for general purpose register file, and page 2 is used for LCD data register or
general purpose register.

2. In the S3C8278X/C8274X microcontroller, the internal register file is configured as two pages (Pages 0, 2).
The page 0 is used for general purpose register file, and page 2 is used for LCD data register or general
purpose register.

3. A hardware reset operation writes the 4-bit destination and source values shown above to the register page
pointer. These values should be modified to address other pages.

Figure 2-5. Register Page Pointer (PP)

2-8

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

 PROGRAMMING TIP — Using the Page Pointer for RAM Clear (Page 0, Page 1)

LD PP,#00H ; Destination ← 0, Source ← 0
SRP #0C0H
LD R0,#0FFH ; Page 0 RAM clear starts

RAMCL0 CLR @R0
DJNZ R0,RAMCL0
CLR @R0 ; R0 = 00H

LD PP,#10H ; Destination ← 1, Source ← 0
LD R0,#0FFH ; Page 1 RAM clear starts

RAMCL1 CLR @R0
DJNZ R0,RAMCL1
CLR @R0 ; R0 = 00H

NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.

2-9

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and

bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware
reset operation always selects bank 0 addressing.

The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 48 mapped system and
peripheral control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte
common working register area (C0H–CFH). You can use the common working register area as a “scratch” area
for data operations being performed in other areas of the register file.

Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing (For more information about
working register addressing, please refer to Chapter 3, “Addressing Modes.”)

REGISTER SET 2

The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. For the S3C8275X,
the set 2 address range (C0H–FFH) is accessible on pages 0–1.
S3C8278X/C8274X, the set 2 address range (C0H–FFH) is accessible on page 0.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.

The set 2 register area is commonly used for stack operations.

2-10

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

PRIME REGISTER SPACE

The lower 192 bytes (00H–BFH) of the S3C8275X/C8278X/C8274X's two or one 256-byte register pages is
called prime register area. Prime registers can be accessed using any of the seven addressing modes
(see Chapter 3, "Addressing Modes.")

The prime register area on page 0 is immediately addressable following a reset. In order to address prime
registers on pages 0, 1, or 2 you must set the register page pointer (PP) to the appropriate source and destination
values.

FFH

FFH

Page 1

Page 0

Set 2

Set 2

FFH

FCH

E0H

Bank 0

Set 1

Bank 1

D0H
C0H

CPU and system control

General-purpose

Peripheral and I/O
LCD data register

NOTE: In case of S3C8278X/C8274X, there are page 0 and page 2. Page 2 is for LCD displa y

register, 16 bytes.

C0H
BFH

00H

Page 0

Prime

Space

0FH

LCD Data

Register Area

00H

Figure 2-6. Set 1, Set 2, Prime Area Register, and LCD Data Register Map

Page 2

2-11

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one
that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)
— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)

All the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.
The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).

1 1 1 1 1 X X X

RP1 (Registers R8-R15)

Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.

0 0 0 0 0 X X X

RP0 (Registers R0-R7)

Figure 2-7. 8-Byte Working Register Areas (Slices)

Slice 32
Slice 31

~ ~

Slice 2
Slice 1

FFH
F8H
F7H
F0H

Set 1
Only

CFH
C0H

10H
FH
8H
7H
0H

2-12

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

USING THE REGISTER POINTS

Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.
(see Figures 2-8 and 2-9).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice
(see Figure 2-8). In some cases, it may be necessary to define working register areas in different (non­contiguous) areas of the register file. In Figure 2-9, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to either of the two 8-byte slices in the working register block, you can
flexibly define the working register area to support program requirements.

 PROGRAMMING TIP — Setting the Register Pointers

SRP #70H ; RP0 ← 70H, RP1 ← 78H
SRP1 #48H ; RP0 ← no change, RP1 ← 48H,
SRP0 #0A0H ; RP0 ← A0H, RP1 ← no change
CLR RP0 ; RP0 ← 00H, RP1 ← no change
LD RP1,#0F8H ; RP0 ← no change, RP1 ← 0F8H

Register File
Contains 32

8-Byte Slices

0 0 0 0 1 X X X

RP1

0 0 0 0 0 X X X

RP0

8-Byte Slice

8-Byte Slice

FH (R15)
8H

7H
0H (R0)

16-Byte
Contiguous
Working
Register block

Figure 2-8. Contiguous 16-Byte Working Register Block

2-13

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

F7H (R7)
F0H (R0)

16-Byte
Contiguous
working
Register block

7H (R15)
0H (R0)

1 1 1 1 0 X X X

RP0

0 0 0 0 0 X X X

RP1

8-Byte Slice

Register File

Contains 32

8-Byte Slices

8-Byte Slice

Figure 2-9. Non-Contiguous 16-Byte Working Register Block

 PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H
contain the values 10H, 11H, 12H, 13H, 14H, and 15H respectively:

SRP0 #80H ; RP0 ← 80H
ADD R0,R1 ; R0 ← R0 + R1
ADC R0,R2 ; R0 ← R0 + R2 + C
ADC R0,R3 ; R0 ← R0 + R3 + C
ADC R0,R4 ; R0 ← R0 + R4 + C
ADC R0,R5 ; R0 ← R0 + R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to
calculate the sum of these registers, the following instruction sequence would have to be used:

ADD 80H,81H ; 80H ← (80H) + (81H)
ADC 80H,82H ; 80H ← (80H) + (82H) + C
ADC 80H,83H ; 80H ← (80H) + (83H) + C
ADC 80H,84H ; 80H ← (80H) + (84H) + C
ADC 80H,85H ; 80H ← (80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

2-14

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

REGISTER ADDRESSING

The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access any location in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and
the least significant byte is always stored in the next (+1) odd-numbered register.

Working register addressing differs from Register addressing as it uses a register pointer to identify a specific
8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

Rn+1

n = Even address

Figure 2-10. 16-Bit Register Pair

2-15

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

Special-Purpose Registers

Bank 1 Bank 0

FFH

Control
Registers

E0H

D0H

C0H
BFH

RP1

RP0

Each register pointer (RP) can independently point
to one of the 24 8-byte "slices" of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).

NOTE: In the S3C8275X/C8278X/C8274X microcontroller,

pages 0-2 are implemented.
Pages 0-2 contain all of the addressable
registers in the internal register file.

00H

System
Registers

CFH

Register
Pointers

General-Purpose Register

FFH

Set 2

C0H

Prime

Registers

LCD Data
Registers

Register Addressing Only

Can be Pointed by Register Pointer

Page 0

All

Addressing

Modes

Page 0

Indirect Register,

Indexed

Addressing

Modes

All

Addressing

Modes

Can be Pointed to

By register Pointer

Figure 2-11. Register File Addressing

2-16

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0H–CFH, as the active 16-byte working register block:

RP0 → C0H–C7H
RP1 → C8H–CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages.

FFH
FCH

E0H

Set 1

FFH

FFH

Page 1

Page 0

Set 2

Set 2

D0H
C0H

Following a hardware reset, register
pointers RP0 and RP1 point to the
common working register area,
locations C0H-CFH.

RP0 =
RP1 =

1 1 0 0 0 0 0 0
1 1 0 0 1 0 0 0

NOTE: In case of S3C8278X/C8274X, there are page 0 and page 2.

Page 2 is for LCD display register, 16 bytes.

Figure 2-12. Common Working Register Area

C0H
BFH

00H

Page 0

~ ~

Space

Prime

~

Page 2

0FH

LCD Data
Registers

00H

2-17

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

 PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.

Examples 1. LD 0C2H,40H ; Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H

LD R2,40H ; R2 (C2H) → the value in location 40H

2. ADD 0C3H,#45H ; Invalid addressing mode!
Use working register addressing instead:

SRP #0C0H
ADD R3,#45H ; R3 (C3H) → R3 + 45H

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).
— The five high-order bits in the register pointer select an 8-byte slice of the register space.
— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-13, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.

Figure 2-14 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-18

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

RP0
RP1

Selects
RP0 or RP1

Address OPCODE

Register pointer
provides five
high-order bits

Figure 2-13. 4-Bit Working Register Addressing

RP0

0 1 1 1 0 0 0 0

0 1 1 1 0 1 1 0

Together they create an

8-bit register address

Selects RP0

Register
address
(76H)

4-bit address
provides three
low-order bits

RP1

0 1 1 1 1 0 0 0

R6

0 1 1 0 1 1 1 0

OPCODE

Instruction
'INC R6'

Figure 2-14. 4-Bit Working Register Addressing Example

2-19

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.

As shown in Figure 2-15, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.

Figure 2-16 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).

These address
bits indicate 8-bit
working register
addressing

Selects
RP0 or RP1

Address

1100

Register pointer
provides five
high-order bits

8-bit physical address

Three low-order bits

Figure 2-15. 8-Bit Working Register Addressing

RP0
RP1

8-bit logical
address

2-20

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

RP0

0 1 1 0 0 0 0 0

1 1 0 0 1 0 1 1

Specifies working
register addressing

Figure 2-16. 8-Bit Working Register Addressing Example

Selects RP1

R11

8-bit address
form instruction
'LD R11, R2'

RP1

1 0 1 0 1 0 0 0

1 0 1 0 1 0 1 1

Register
address
(0ABH)

2-21

ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

SYSTEM AND USER STACK

The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH
and POP instructions are used to control system stack operations. The S3C8275X/C8278X/C8274X architecture
supports stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-17.

High Address

PCL

PCL

Top of

stack

PCH

Top of

stack

PCH

Flags

Stack contents

after a call
instruction

Low Address

Stack contents

after an

interrupt

Figure 2-17. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL, SPH)

Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.
The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least
significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.

Because only internal memory space is implemented in the S3C8275X/C8278X/C8274X, the SPL must be
initialized to an 8-bit value in the range 00H–FFH. The SPH register is not needed and can be used as a general­purpose register, if necessary.

When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the
register file), you can use the SPH register as a general-purpose data register. However, if an overflow or
underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register
during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,
overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can
initialize the SPL value to "FFH" instead of "00H".

2-22

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES

 Programming TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:

LD SPL,#0FFH ; SPL ← FFH
; (Normally, the SPL is set to 0FFH by the initialization
; routine)

•

•

•

PUSH PP ; Stack address 0FEH ← PP
PUSH RP0 ; Stack address 0FDH ← RP0
PUSH RP1 ; Stack address 0FCH ← RP1
PUSH R3 ; Stack address 0FBH ← R3

•

•

•

POP R3 ; R3 ← Stack address 0FBH
POP RP1 ; RP1 ← Stack address 0FCH
POP RP0 ; RP0 ← Stack address 0FDH
POP PP ; PP ← Stack address 0FEH

2-23

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES

3 ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.

The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction. The seven addressing modes and their symbols are:

• Register (R)

• Indirect Register (IR)

• Indexed (X)

• Direct Address (DA)

• Indirect Address (IA)

• Relative Address (RA)

• Immediate (IM)

3-1

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

REGISTER ADDRESSING MODE (R)

In Register addressing mode (R), the operand value is the content of a specified register or register pair
(see Figure 3-1).

Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).

Program Memory Register File

8-bit Register

File Address

One-Operand

Instruction

(Example)

Sample Instruction:

dst

OPCODE

Point to One

OPERAND

Register in Register

File

Value used in

Instruction Execution

DEC CNTR ; Where CNTR is the label of an 8-bit register address

4-bit

Working Register

Two-Operand

Instruction

(Example)

Sample Instruction:

Figure 3-1. Register Addressing

Program Memory

dst

OPCODE

src

MSB Point to

RP0 ot RP1

3 LSBs

Point to the

Working Register

(1 of 8)

Register File

RP0 or RP1

Selected
RP points
to start
of working
register
block

OPERAND

ADD R1, R2 ; Where R1 and R2 are registers in the currently

selected working register area.

Figure 3-2. Working Register Addressing

3-2

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in
set 1 using the Indirect Register addressing mode.

Program Memory Register File

8-bit Register

File Address

One-Operand

Instruction

(Example)

dst

OPCODE

Point to One

ADDRESS

Register in Register

File

Address of Operand

used by Instruction

Value used in

Instruction Execution

Sample Instruction:
RL @SHIFT ; Where SHIFT is the label of an 8-bit register address

OPERAND

Figure 3-3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

Program Memory

Example

Instruction

References

Program

Memory

Sample Instructions:
CALL @RR2

JP @RR2

REGISTER

dst

OPCODE

Points to

Register Pair

Value used in

Instruction

PAIR

Program Memory

OPERAND

Figure 3-4. Indirect Register Addressing to Program Memory

16-Bit
Address
Points to
Program
Memory

3-4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

MSB Points to

4-bit

Working
Register
Address

Program Memory

dst

OPCODE

src

RP0 or RP1

3 LSBs

Point to the

Working Register

(1 of 8)

RP0 or RP1

Selected
RP points

~~

ADDRESS

to start fo
working register
block

~~

Sample Instruction:
OR R3, @R6

Figure 3-5. Indirect Working Register Addressing to Register File

Value used in

Instruction

OPERAND

3-5

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

INDIRECT REGISTER ADDRESSING MODE (Concluded)

Register File

MSB Points to

4-bit Working

Register Address

Example Instruction

References either

Program Memory or

Data Memory

Program Memory

dst

OPCODE

src

RP0 or RP1

Next 2-bit Point

to Working

Register Pair

(1 of 4)

LSB Selects

Value used in

Instruction

RP0 or RP1

Register

Pair

Program Memory

or

Data Memory

OPERAND

Selected
RP points
to start of
working
register
block

16-Bit
address
points to
program
memory
or data
memory

Sample Instructions:
LCD R5,@RR6 ; Program memory access

LDE R3,@RR14 ; External data memory access
LDE @RR4, R8 ; External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory. Please note, however, that you cannot access
locations C0H–FFH in set 1 using Indexed addressing mode.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128
to +127. This applies to external memory accesses only (see Figure 3-8.)

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address
(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory, when implemented.

Two-Operand

Instruction

Example

Sample Instruction:
LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value

Program Memory

Base Address

dst/src

OPCODE

x

Value used in

Instruction

+

3 LSBs

Point to One of the

Woking Register

(1 of 8)

Register File

RP0 or RP1

~~

Selected RP
points to

OPERAND

start of
working
register
block

~~

INDEX

Figure 3-7. Indexed Addressing to Register File

3-7

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

INDEXED ADDRESSING MODE (Continued)

Register File

MSB Points to

4-bit Working

Register Address

Program Memory

OFFSET

dst/src

OPCODE

x

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

(1 of 4)

LSB Selects

RP0 or RP1

Selected
RP points

~~

Register

Pair

Program Memory

or

Data Memory

to start of
working
register
block

16-Bit
address
added to
offset

+

8-Bits

16-Bits

16-Bits

OPERAND

Sample Instructions:
LDC R4, #04H[RR2] ; The values in the program address (RR2 + 04H)

are loaded into register R4.

LDE R4,#04H[RR2] ; Identical operation to LDC example, except that

external program memory is accessed.

Value used in
Instruction

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES

INDEXED ADDRESSING MODE (Concluded)

Register File

MSB Points to

4-bit Working

Register Address

Program Memory

OFFSET
OFFSET

dst/src

OPCODE

src

RP0 or RP1

NEXT 2 Bits

Point to Working

Register Pair

LSB Selects

RP0 or RP1

Selected
RP points

~~

Register

Pair

Program Memory

or

Data Memory

to start of
working
register
block

16-Bit
address
added to
offset

+

8-Bits

16-Bits

16-Bits

Sample Instructions:
LDC R4, #1000H[RR2] ; The values in the program address (RR2 + 1000H)

are loaded into register R4.

LDE R4,#1000H[RR2] ; Identical operation to LDC example, except that

external program memory is accessed.

OPERAND

Value used in
Instruction

Figure 3-9. Indexed Addressing to Program or Data Memory

3-9

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Memory

Program Memory

Upper Address Byte

Lower Address Byte

dst/src

Sample Instructions:
LDC R5,1234H ; The values in the program address (1234H)
LDE R5,1234H ; Identical operation to LDC example, except that

"0" or "1"

OPCODE

are loaded into register R5.
external program memory is accessed.

Address
Used

LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory

Figure 3-10. Direct Addressing for Load Instructions

3-10

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES

DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Memory
Address
Used

Upper Address Byte
Lower Address Byte

OPCODE

Sample Instructions:
JP C,JOB1 ; Where JOB1 is a 16-bit immediate address

CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.

Program Memory

Next Instruction

LSB Must be Zero

Current

Instruction

Lower Address Byte
Upper Address Byte

Sample Instruction:
CALL #40H ; The 16-bit value in program memory addresses 40H

and 41H is the subroutine start address.

dst

OPCODE

Program Memory
Locations 0-255

Figure 3-12. Indirect Addressing

3-12

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The
instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory
Address Used

Current

Displacement

Current Instruction

Sample Instructions:
JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128

OPCODE

PC Value

Signed
Displacement Value

+

Figure 3-13. Relative Addressing

3-13

ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand
field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate
addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:
LD R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

4 CONTROL REGISTERS

OVERVIEW

In this chapter, detailed descriptions of the S3C8275X/C8278X/C8274X control registers are presented in an
easy-to-read format. You can use this chapter as a quick-reference source when writing application programs.
Figure 4-1 illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.

Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.

The locations and read/write characteristics of all mapped registers in the S3C8275X/C8278X/C8274X register
file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET
and Power-Down."

Table 4-1. Set 1 Registers

Register Name Mnemonic Address R/W

Decimal Hex

Locations D0H – D2H are not mapped.
Basic timer control register BTCON 211 D3H R/W
System clock control register CLKCON 212 D4H R/W
System flags register FLAGS 213 D5H R/W
Register pointer 0 RP0 214 D6H R/W
Register pointer 1 RP1 215 D7H R/W
Stack pointer (high byte) SPH 216 D8H R/W
Stack pointer (low byte) SPL 217 D9H R/W
Instruction pointer (high byte) IPH 218 DAH R/W
Instruction pointer (low byte) IPL 219 DBH R/W
Interrupt request register IRQ 220 DCH R
Interrupt mask register IMR 221 DDH R/W
System mode register SYM 222 DEH R/W
Register page pointer PP 223 DFH R/W

4-1

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

Table 4-2. Set 1, Bank 0 Registers

Register Name Mnemonic Address R/W

Decimal Hex

Oscillator control register OSCCON 224 E0H R/W
SIO control register SIOCON 225 E1H R/W
SIO data register SIODATA 226 E2H R/W
SIO pre-scaler register SIOPS 227 E3H R/W
Port 0 control register (high byte) P0CONH 228 E4H R/W
Port 0 control register (low byte) P0CONL 229 E5H R/W
Port 0 pull-up resistor enable register P0PUR 230 E6H R/W
Port 1 control register (high byte) P1CONH 231 E7H R/W
Port 1 control register (low byte) P1CONL 232 E8H R/W
Port 1 pull-up resistor enable register P1PUR 233 E9H R/W
Port 2 control register (high byte) P2CONH 234 EAH R/W
Port 2 control register (low byte) P2CONL 235 EBH R/W
Port 2 pull-up resistor enable register P2PUR 236 ECH R/W
Port 3 control register (high byte) P3CONH 237 EDH R/W
Port 3 control register (low byte) P3CONL 238 EEH R/W
Port 3 Pull-up resistor enable register P3PUR 239 EFH R/W
Port 0 data register P0 240 F0H R/W
Port 1 data register P1 241 F1H R/W
Port 2 data register P2 242 F2H R/W
Port 3 data register P3 243 F3H R/W
Port 4 data register P4 244 F4H R/W
Port 5 data register P5 245 F5H R/W
Port 6 data register P6 246 F6H R/W
External interrupt pending register EXTIPND 247 F7H R/W
External interrupt control register (high byte) EXTICONH 248 F8H R/W
External interrupt control register (low byte) EXTICONL 249 F9H R/W

Locations FAH are not mapped.

STOP control register STPCON 251 FBH R/W

Locations FCH are not mapped.

Basic timer counter BTCNT 253 FDH R

Locations FEH are not mapped.

Interrupt priority register IPR 255 FFH R/W

4-2

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

Table 4-3. Set 1, Bank 1 Registers

Register Name Mnemonic Address R/W

Decimal Hex

LCD control Register LCON 224 E0H R/W
Watch timer control register WTCON 225 E1H R/W
Timer A counter TACNT 226 E2H R
Timer B counter TBCNT 227 E3H R
Timer A data register TADATA 228 E4H R/W
Timer B data register TBDATA 229 E5H R/W
Timer 1/A control register TACON 230 E6H R/W
Timer B control register TBCON 231 E7H R/W
Clock output control register CLOCON 232 E8H R/W
Port 4 control register (high byte) P4CONH 233 E9H R/W
Port 4 control register (low byte) P4CONL 234 EAH R/W
Port 5 control register (high byte) P5CONH 235 EBH R/W
Port 5 control register (low byte) P5CONL 236 ECH R/W
Port 6 control register P6CON 237 EDH R/W

Locations EEH – EFH are not mapped.
Flash memory control register FMCON 240 F0H R/W
Flash memory user programming enable register FMUSR 241 F1H R/W
Flash memory sector address register (high byte) FMSECH 242 F2H R/W
Flash memory sector address register (low byte) FMSECL 243 F3H R/W
Battery level detector control register BLDCON 244 F4H R/W

Locations E5H – FFH are not mapped.

NOTES:

1. An “x” means that the bit value is undefined following reset.

2. A dash(“–“) means that the bit is neither used nor mapped, but the bit is read as “0”.

4-3

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

Bit number(s) that is/are appended to
the register name for bit addressing

Full Register nameRegister ID

FLAGS - System Flags Register

Bit Identifier
Reset Value
Read/Write
Bit Addressing
Mode

.7 Carry Flag (C)

.6 Zero Flag (Z)

.5

R/W R/W R/W

Register addressing mode only

0
1

0
1

Sign Flag (S)

0
1

Name of individual
bit or related bits

Register address
(hexadecimal)

D5H

.7 .6 .5

xxx

Operation does not generate a carry or borrow condition
Operation generates carry-out or borrow into high-order bit 7

Operation result is a non-zero value
Operation result is zero

Operation generates positive number (MSB = "0")
Operation generates negative number (MSB = "1")

.4 .3 .2 .1 .0

x

R/W

x

R/W

x

R/W

Register location
in the internal
register file

Set 1

x

R/W

0

R/W

R = Read-only
W = Write-only
R/W = Read/ write
'-' = Not used

Type of addressing
that must be used to
address the bit
(1-bit, 4-bit, or 8-bit)

Description of the
effect of specific
bit settings

Bit number:
MSB = Bit 7
LSB = Bit 0

nRESET value notation:
'-' = Not used
'x' = Undetermine d va lue
'0' = Logic zer o
'1' = Logic one

Figure 4-1. Register Description Format

4-4

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

BLDCON — Battery Level Detector Control Register F4H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6

.5

.4 Battery Level Detector Output Bit

.3 Battery Level Detector Enable/Disable Bit

.2–.0 Detection Voltage Selection Bits

– – 0 0 0 0 0 0
– – R/W R R/W R/W R/W R/W

Register addressing mode only

Not used for the S3C8275X/C8278X/C8274X

Source Bit

V

IN

0 Internal source
1 External source

0
1

> V

V

IN

V

< V

IN

(when BLD is enabled)

REF

(when BLD is enabled)

REF

0 Disable BLD
1 Enable BLD

= 2.2V

0 0 0
1 0 1
0 1 1

V
V
V

BLD
BLD
BLD

= 2.4V
= 2.8V

Other values Not available

4-5

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

BTCON — Basic Timer Control Register D3H Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.4 Watchdog Timer Function Disable Code (for System Reset)

.3–.2 Basic Timer Input Clock Selection Bits

.1

.0

1 Clear both clock frequency dividers

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

1 0 1 0 Disable watchdog timer function

Other values Enable watchdog timer function

0 0

fxx/4096

(3)

0 1 fxx/1024
1 0 fxx/128
1 1 fxx/16

Basic Timer Counter Clear Bit

(1)

0 No effect
1 Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters

(2)

0 No effect

NOTES:

1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write
operation, the BTCON.1 value is automatically cleared to “0”.

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the
write operation, the BTCON.0 value is automatically cleared to "0".

3. The fxx

4-6

is selected clock for system (main OSC. or sub OSC.).

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

CLKCON — System Clock Control Register D4H Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 Oscillator IRQ Wake-up Function Bit

.6–.5

.4–.3

.2–.0

0 – – 0 0 – – –

R/W – – R/W R/W – – –

Register addressing mode only

0 Enable IRQ for main wake-up in power down mode
1 Disable IRQ for main wake-up in power down mode

Not used for the S3C8275X/C8278X/C8274X (must keep always “0”)

(note)

CPU Clock (System Clock) Selection Bits

0 0 fxx/16
0 1 fxx/8
1 0 fxx/2
1 1 fxx

Not used for the S3C8275X/C8278X/C8274X (must keep always “0”)

NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load
the appropriate values to CLKCON.3 and CLKCON.4.

4-7

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

CLOCON — Clock Output Control Register E8H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.2

.1–.0 Clock Output Frequency Selection Bits

– – – – – – 0 0
– – – – – – R/W R/W

Register addressing mode only

Not used for the S3C8275X/C8278X/C8274X (must keep always “0”)

0 0 Select fxx/64
0 1 Select fxx/16
1 0 Select fxx/8
1 1 Select fxx/4

4-8

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

EXTICONH — External Interrupt Control Register (High Byte) F8H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6 P1.7 External Interrupt (INT7) Configuration Bits

.5–.4 P1.6 External Interrupt (INT6) Configuration Bits

.3–.2 P1.5 External Interrupt (INT5) Configuration Bits

.1–.0 P1.4 External Interrupt (INT4) Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Disable interrupt
0 1 Enable interrupt by falling edge
1 0 Enable interrupt by rising edge
1 1 Enable interrupt by both falling and rising edge

0 0 Disable interrupt
0 1 Enable interrupt by falling edge
1 0 Enable interrupt by rising edge
1 1 Enable interrupt by both falling and rising edge

0 0 Disable interrupt
0 1 Enable interrupt by falling edge
1 0 Enable interrupt by rising edge
1 1 Enable interrupt by both falling and rising edge

0 0 Disable interrupt
0 1 Enable interrupt by falling edge
1 0 Enable interrupt by rising edge
1 1 Enable interrupt by both falling and rising edge

4-9

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

EXTICONL — External Interrupt Control Register (Low Byte) F9H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6 P1.3 External Interrupt (INT3) Configuration Bits

.5–.4 P0.2 External Interrupt (INT2) Configuration Bits

.3–.2 P0.1 External Interrupt (INT1) Configuration Bits

.1–.0 P0.0 External Interrupt (INT0) Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Disable interrupt
0 1 Enable interrupt by falling edge
1 0 Enable interrupt by rising edge
1 1 Enable interrupt by both falling and rising edge

0 0 Disable interrupt
0 1 Enable interrupt by falling edge
1 0 Enable interrupt by rising edge
1 1 Enable interrupt by both falling and rising edge

0 0 Disable interrupt
0 1 Enable interrupt by falling edge
1 0 Enable interrupt by rising edge
1 1 Enable interrupt by both falling and rising edge

0 0 Disable interrupt
0 1 Enable interrupt by falling edge
1 0 Enable interrupt by rising edge
1 1 Enable interrupt by both falling and rising edge

4-10

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

EXTIPND — External Interrupt Pending Register F7H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 P1.7/INT7 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending (when read)

.6 P1.6/INT6 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending (when read)

.5 P1.5/INT5 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending (when read)

.4 P1.4/INT4 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending (when read)

.3 P1.3/INT3 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending (when read)

.2 P0.2/INT2 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending (when read)

.1 P0.1/INT1 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending (when read)

.0 P0.0/INT0 Interrupt Pending Bit

0 Interrupt request is not pending, pending bit clear when write 0
1 Interrupt request is pending (when read)

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

4-11

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

FLAGS — System Flags Register D5H Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 Carry Flag (C)

0 Operation does not generate a carry or borrow condition
1 Operation generates a carry-out or borrow into high-order bit 7

.6 Zero Flag (Z)

0 Operation result is a non-zero value
1 Operation result is zero

.5 Sign Flag (S)

0 Operation generates a positive number (MSB = "0")
1 Operation generates a negative number (MSB = "1")

.4 Overflow Flag (V)

0
1 Operation result is > +127 or < –128

.3 Decimal Adjust Flag (D)

0 Add operation completed
1 Subtraction operation completed

.2 Half-Carry Flag (H)

0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

.1 Fast Interrupt Status Flag (FIS)

0 Interrupt return (IRET) in progress (when read)
1 Fast interrupt service routine in progress (when read)

.0 Bank Address Selection Flag (BA)

0 Bank 0 is selected
1 Bank 1 is selected

x x x x x x 0 0

R/W R/W R/W R/W R/W R/W R R/W

Register addressing mode only

Operation result is ≤ +127 or ≥ –128

4-12

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

FMCON — Flash Memory Control Register F0H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.4 Flash Memory Mode Selection Bits

0 1 0 1 Programming mode

1 0 1 0 Sector erase mode
0 1 1 0 Hard lock mode
Other values Not available

.3 Sector Erase Status Bit

.2–.1

.0 Flash Operation Start Bit

0 0 0 0 0 – – 0

R/W R/W R/W R/W R – – R/W

Register addressing mode only

0 Success sector erase
1 Fail sector erase

Not used for the S3F8275X/F8278X/F8274X

0 Operation stop
1 Operation start (This bit will be cleared automatically just after the

corresponding operator completed).

4-13

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

FMSECH — Flash Memory Sector Address Register (High Byte) F2H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.0 Flash Memory Sector Address Bits (High Byte)

NOTE: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

The 15th - 8th bits to select a sector of flash ROM

FMSECL — Flash Memory Sector Address Register (Low Byte) F3H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 Flash Memory Sector Address Bit (Low Byte)

.6–.0 Bits 6–0

NOTE: The low-byte flash memory sector address pointer value is the lower eight bits of the 16-bit pointer address.

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

The 7th bit to select a sector of flash ROM

Don't care

4-14

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

FMUSR — Flash Memory User Programming Enable Register F1H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.0 Flash Memory User Programming Enable Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

1 0 1 0 0 1 0 1 Enable user programming mode

Other values Disable user programming mode

4-15

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

IMR — Interrupt Mask Register DDH Set 1

Bit Identifier .7 .6
Reset Value
Read/Write
Addressing Mode

x x

R/W R/W

Register addressing mode only

.5 .4 .3 .2 .1 .0

x x x x x x

R/W R/W R/W R/W R/W R/W

.7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P1.4–1.7

0 Disable (mask)
1 Enable (unmask)

.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P1.3

0 Disable (mask)
1 Enable (unmask)

.5 Interrupt Level 5 (IRQ5) Enable Bit; External Interrupt P0.2

0 Disable (mask)
1 Enable (unmask)

.4 Interrupt Level 4 (IRQ4) Enable Bit; External Interrupt P0.1

0 Disable (mask)
1 Enable (unmask)

.3 Interrupt Level 3 (IRQ3) Enable Bit; External Interrupt P0.0

0 Disable (mask)
1 Enable (unmask)

.2 Interrupt Level 2 (IRQ2) Enable Bit; Watch Timer Overflow

0 Disable (mask)
1 Enable (unmask)

.1 Interrupt Level 1 (IRQ1) Enable Bit; SIO Interrupt

0 Disable (mask)
1 Enable (unmask)

.0 Interrupt Level 0 (IRQ0) Enable Bit; Timer 1/A Match, Timer B Match

NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

0 Disable (mask)
1 Enable (unmask)

4-16

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

IPH — Instruction Pointer (High Byte) DAH Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.0 Instruction Pointer Address (High Byte)

x x x x x x x x

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).

— Instruction Pointer (Low Byte) DBH Set 1

IPL

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.0 Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction

x x x x x x x x

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).

4-17

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

IPR — Interrupt Priority Register FFH Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7, .4, and .1

0 0 0 Group priority undefined

0 0 1 B > C > A
0 1 0 A > B > C
0 1 1 B > A > C
1 0 0 C > A > B
1 0 1 C > B > A
1 1 0 A > C > B
1 1 1 Group priority undefined

.6 Interrupt Subgroup C Priority Control Bit

.5 Interrupt Group C Priority Control Bit

.3 Interrupt Subgroup B Priority Control Bit

.2 Interrupt Group B Priority Control Bit

.0 Interrupt Group A Priority Control Bit

x x x x x x x x

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

Priority Control Bits for Interrupt Groups A, B, and C

0 IRQ6 > IRQ7
1 IRQ7 > IRQ6

0 IRQ5 > (IRQ6, IRQ7)
1 (IRQ6, IRQ7) > IRQ5

0 IRQ3 > IRQ4
1 IRQ4 > IRQ3

0 IRQ2 > (IRQ3, IRQ4)
1 (IRQ3, IRQ4) > IRQ2

0 IRQ0 > IRQ1
1 IRQ1 > IRQ0

(note)

NOTE: Interrupt Group A – IRQ0, IRQ1
Interrupt Group B – IRQ2, IRQ3, IRQ4
Interrupt Group C – IRQ5, IRQ6, IRQ7

4-18

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

IRQ — Interrupt Request Register DCH Set 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 Level 7 (IRQ7) Request Pending Bit; External Interrupt P1.4–1.7

.6 Level 6 (IRQ6) Request Pending Bit; External Interrupt P1.3

.5 Level 5 (IRQ5) Request Pending Bit; External Interrupt P0.2

.4 Level 4 (IRQ4) Request Pending Bit; External Interrupt P0.1

.3 Level 3 (IRQ3) Request Pending Bit; External Interrupt P0.0

.2 Level 2 (IRQ2) Request Pending Bit; Watch Timer Overflow

.1 Level 1 (IRQ1) Request Pending Bit; SIO Interrupt

.0 Level 0 (IRQ0) Request Pending Bit; Timer 1/A Match, Timer B Match

0 0 0 0 0 0 0 0

R R R R R R R R

Register addressing mode only

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

0 Not pending
1 Pending

4-19

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

LCON — LCD Control Register E0H Set 1, Bank 1

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 Internal LCD Dividing Resistors Enable Bit

.6–.5 LCD Clock Selection Bits

.4–.2 LCD Duty and Bias Selection Bits

0 0 0 0 0 0 – 0

R/W R/W R/W R/W R/W R/W – R/W

Register addressing mode only

0 Enable internal LCD dividing resistors
1 Disable internal LCD dividing resistors

0 0
0 1
1 0
1 1

fw/2
fw/2
fw/2
fw/2

9

(64 Hz)

8

(128 Hz)

7

(256 Hz)

6

(512 Hz)

0 0 0 1/4duty, 1/3bias
0 0 1 1/3duty, 1/3bias
0 1 0 1/3duty, 1/2bias
0 1 1 1/2duty, 1/2bias
1 x x Static

NOTES:

1. "x" means don't care.

2. When 1/2 bias is selected, the bias levels are set as V

LC0

, V

LC1

(V

LC2

), and VSS.

.1

Not used for the S3C8275X/C8278X/C8274X

.0 LCD Display Control Bit

4-20

0 Turn display off (Turn off the P-Tr)
1 Turn display on (Turn on the P-Tr)

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

OSCCON — Oscillator Control Register E0H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 Sub Oscillator Circuit Selection Bit

0 – – – 0 0 – 0

R/W – – – R/W R/W – R/W

Register addressing mode only

0 Initial state
1 Power saving circuit for sub oscillator (Automatically cleared to "0" when the

sub oscillator is stopped by OSCCON.2).

NOTES:

1. The OSCCON.7 must be maintained to “1”, during the sub oscillator operation.

2. A capacitor (0.1uF) should be connected between V

and GND.

REG

.6–.4

Not used for the S3C8275X/C8278X/C8274X

.3 Main Oscillator Control Bit

0 Main oscillator RUN
1 Main oscillator STOP

.2 Sub Oscillator Control Bit

.1

0 Sub oscillator RUN
1 Sub oscillator STOP

Not used for the S3C8275X/C8278X/C8274X

.0 System Clock Selection Bit

0 Select main oscillator for system clock
1 Select sub oscillator for system clock

4-21

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

P0CONH — Port 0 Control Register (High Byte) E4H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6 P0.7/BUZ Configuration Bits

.5–.4 P0.6/CLKOUT Configuration Bits

.3–.2 P0.5/TBOUT Configuration Bits

.1–.0 P0.4/TAOUT Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (BUZ)

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (CLKOUT)

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (TBOUT)

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (TAOUT)

4-22

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

P0CONL — Port 0 Control Register (Low Byte) E5H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6 P0.3/T1CLK Configuration Bits

.5–.4 P0.2/INT2 Configuration Bits

.3–.2 P0.1/INT1 Configuration Bits

.1–.0 P0.0/INT0 Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Schmitt trigger input mode (T1CLK)
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

4-23

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

P0PUR — Port 0 Pull-Up Control Register E6H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 P0.7's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.6 P0.6's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.5 P0.5's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.4 P0.4's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.3 P0.3's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.2 P0.2's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.1 P0.1's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.0 P0.0's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

NOTE: A pull-up resistor of port 0 is automatically disabled only when the corresponding pin is selected as push-pull output
or alternative function.

4-24

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

P1CONH — Port 1 Control Register (High Byte) E7H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6 P1.7/INT7 Configuration Bits

.5–.4 P1.6/INT6 Configuration Bits

.3–.2 P1.5/INT5 Configuration Bits

.1–.0 P1.4/INT4 Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

4-25

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

P1CONL — Port 1 Control Register (Low Byte) E8H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6 P1.3/INT3 Configuration Bits

.5–.4 P1.2/SI Configuration Bits

.3–.2 P1.1/SO Configuration Bits

.1–.0 P1.0/SCK Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

0 0 Schmitt trigger input mode (SI)
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Not used for the S3C8275X/C8278X/C8274X

0 0 Schmitt trigger input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SO)

0 0 Schmitt trigger input mode (SCK)
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SCK)

4-26

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

P1PUR — Port 1 Pull-up Control Register F9H Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 P1.7's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.6 P1.6's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.5 P1.5's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.4 P1.4's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.3 P1.3's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.2 P1.2's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.1 P1.1's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.0 P1.0's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

NOTE: A pull-up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push-pull output
or alternative function.

4-27

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6 P2.7/SEG24 Configuration Bits

.5-.4 P2.6/SEG25 Configuration Bits

.3–.2 P2.5/SEG26 Configuration Bits

.1–.0 P2.4/SEG27 Configuration Bits

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SEG24)

0 0 Input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SEG25)

0 0 Input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SEG26)

0 0 Input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SEG27)

4-28

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER

P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7–.6 P2.3/SEG28 Configuration Bits

.5–.4 P2.2/SEG29 Configuration Bits

.3–.2 P2.1/SEG30 Configuration Bits

.1–.0

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

0 0 Input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SEG28)

0 0 Input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SEG29)

0 0 Input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1 Alternative function (SEG30)

P2.0/SEG31/V

0 0 Input mode
0 1 N-channel open-drain output mode
1 0 Push-pull output mode
1 1

BLDREF

Alternative function (SEG31 or V

Configuration Bits

BLDREF

)

4-29

CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X

P2PUR — Port 2 Pull-up Control Register ECH Set 1, Bank 0

Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value
Read/Write
Addressing Mode

.7 P2.7's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.6 P2.6's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.5 P2.5's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.4 P2.4's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.3 P2.3's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.2 P2.2's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.1 P2.1's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

.0 P2.0's Pull-up Resistor Enable Bit

0 Disable pull-up resistor
1 Enable pull-up resistor

0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

Register addressing mode only

NOTE: A pull-up resistor of port 2 is automatically disabled only when the corresponding pin is selected as push-pull output
or alternative function.

4-30