Samsung DVD-709, DVD-909, Dvd-707 Reference Information

2. Reference Information

2-1 IC Dsecriptions
2-1-1 AIC1 (AK4324 ; Digital-to-Analog Converter)
	DIF0	DIF1	DIF2	DEM0	DEM1	AVDD	AVSS
LRCK	Serial Input			De-emphasis
				Control
BICK							DZFL
	Interface
SDATA
PD		8X			∑	SCF	AOUTL+
	Interpolator			Modulator			AOUTL-
SMUTE
DFS		8X			∑	SCF	AOUTR+
	Interpolator			Modulator			AOUTR-
	Clock Divider
							DZFR
	MCLK	CKS		DVDD	DVSS	VREF

	PIN	I / O	NAME			FUNCTION		PIN	I / O	NAME	FUNCTION
	1	-	DVSS			Digital ground pin		13	I	DIF0	Digital input format pin
	2	I	DVDD			Digital power supply		14	I	DIF1	Digital input format pin
						Master clock select pin (Internal pull-down pin)
	3	I		CKS		Nomal speed "L":MCLK = 256fs,	"H":MCLK = 384fs	15	I	DIF2	Digital input format pin
						Double speed "L":MCLK = 128fs,	"H":MCLK = 192fs
	4	I	MCLK			Master clock input pin		16	0	AOUTR-	Rch negative analog output pin
						Power-Down mode pin. When at "L", the AK4324 is in
	5	I		PD		power-down and is held in rest.		17	O	AOUTR+	Rch positive analog output pin
						The AK4324 should always be reset upon power-pin
	6	I	BICK			Audio serial data input pin		18	O	AOUTL-	Lch negative analog output pin
						64fs clock is recommended to be input on this pin
	7	I	SDATA			Audio serial data input pin		19	O	AOUTL+	Lch positive analog output pin
						2's complement MSB-first data is input on this pin.
	8	I	LRCK			L/R clock pin.		20	-	AVSS	Analog ground pin
						Soft mute pin
	9	I	SMUTE			When this pin goes "H", soft mute cycle is initiated		21	O	VREF	Voltage reference input pin
						When returning "L", the output mute releases.
	10	I		DFS		Double speed sampling mode pin (Internal pull-down pin)		22	O	AVDD	Analog power supply pin.
						"L":normal speed, "H":double speed
	11	I	DEM0			De-emphasis frequency select pin		23	O	DZFR	Rch zero input detect pin
	12	I	DEM1			De-emphasis frequency select pin		24	O	DZFL	Lch zero input detect pin

Note : Allinput pins except internal pull-down pins should not be left floating.

Samsung Electronics

2-1

Reference Information

2-1-2 RIC1 (KS1461 ; RF)

VZOCTL

PLLGF

EQF

EQG

RDPF

AGCP

AGCB

AGCLEVEL

EQGND

AGCI

AGCC

RFAGCO

EQIN

BCATH

RFEQO

EQVCC

MIRRI

1 CP

1 CB

MROFST

RFRPN

RFRP

2 CP

2 CB

RFCT

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

to RF EQ

TUNING BLOCK

AGC-HOLD(OOH)

AGC_DET

ACD

1

75

BCAO

MUX

BCA

BCD

2

BLOCK

CCD

3

A

74

BCAI

DCD

4

RF

B

RF SLM

RF

ADVD

5

MUX C

& AGC

Equalizer

D

RFRP

BCA

BDVD

6

CDVD

7

GAIN_EQ(02H)

DDVD

8

73

RESET

RFCT

AUTO

CD1

S12 DVD1.2

OFSTCTL

&

72

OSC

CDRSEL(00H)

TE1RES

MIRR

RREFBF

9

VREF

RREFEQ

10

GENERATOR

D

GCA

EQ

RREF

11

D

MUX3

D

GCA

EQ

D

VREFEQ

12

EQ

VC AMP

GAIN_TE3(02H)

E	13		TE38
F	14	GCA
			OFSTHOLD
		TEOFST(04H)
		TBAL(01H)
ADVD1	15
BDVD1	16		D1
CDVD1	17		B1
DDVD1	18	SUB	C1
			A1
ACD1	19	RF
BCD1	20	MUX GAIN_FE(03H)
CCD1	21		FE
DCD1	22		FE_0FST(05H)
				OFSTHOLD
AVCC	23	ANALOG	LDONB(00H)
		CDRSEL(00H)
VREFA	24	VC AMP

ALPC

FOFST 25

FOFST

26 27 28 29 30 31 32 33 34 35

OFSTHOLD

BGI VREFLP

LDODVD

PDVD

LDOCD

PDCD

AGND

FE

FEN

TEN

	DELAY_SEL(OOH)	HOLD_CTL(O8H)	CD1
	PLLCTL	DPDMUTE	S12
	TBAL(O1H)	DPD_MUTE(O2H)	DVD1
		SEOFHOLD	DVD2
	DPDEQ1	FLT_CTL(OOH)	LDONB
		CAL_ENDB(O2H)	FLT_CTL		71	STB
			CDRSEL	S/IF
	DELAY	PD,LPF	TESEL		70	CLOCK
			AGC-HOLD	BLOCK
	COM
		TEOPST(04H)	TBAL		69	DATA
			GAIN_TE3
	PDLIMITRES		ENV_SEL
	TE1_LIMIT		DVCTL_SEL
	COM		DPD_MUTE
			GAIN_EQ
			GAIN_FE		68	RREFDLY
			GAIN_ABCD
	DPDEQ2		TE_OFST
		FAULTOUT	FE_OFST	DPD	67	VREFDPD
			ABCD_OFST
				BLOCK
			DELAY_CD
			DELAY_AB
			PDLIMIT		66	DPDGND
			ga_RFSUM
	DELAY_SEL(00H)		HOLD_CTL
	PLLCTL		ga_PLLDP		65	TE1RES
			ga_PLLDN
					64	PLLCTL
				to DPD	63	DPDMUTE
				BLOCK	62	FAUL TOUT
	CDRSEL(OOH)				61	DPDEQ2
	GAIN_ABCD(OOH)
					60	DPDEQ1
	ABCD
	SUM	EQIN			59	TE30FST
	ENV_SEL(02H)				58	BCA
	OFSTHOLD				57	MIRR
	ABCD_OFST(O6H)	MUX

56 DPDVCC

55

DFCT2

MUX

54

DFCT1

TESEL(OOH)

53 DFCTTH1

ENVELOPE	FOK		DEFECT

52 DFCTTH2

51 DVCC

	36		37	38		39		40		41	42	43		44		45		46		47		48		49	50
	TE		PDLIMITRES	ABCDN		ABCD		ABCDI		ENVP	ENVB	ENV		DGND		FOKTH		FOKB		CP1 DFCT		CP2 DFCT		CC1	CC2

2-2	Samsung Electronics

Electronics Samsung

3-2

	PIN NAME		I/O	FUNCTION
1		ACD	I	CD optical main beam A AC coupling input port for RF
2		BCD	I	CD optical main beam B AC coupling input port for RF
3		CCD	I	CD optical main beam C AC coupling input port for RF
4		DCD	I	CD optical main beam D AC coupling input port for RF
5		ADVD	I	DVD optical main beam A AC coupling input port for RF
6		BDVD	I	DVD optical main beam B AC coupling input port for RF
7		CDVD	I	DVD optical main beam C AC coupling input port for RF
8		DDVD	I	DVD optical main beam D AC coupling input port for RF
9		RREFBF	-	RF AMP I/O buffer bias resistance connection port
10		RREFEQ	-	RF EQ bias resistance connection port
11		RREF	-	Analog block bias resistance connection port
12		VREFEQ	O	CAP connection port for RF EQ center voltage
13		E	I	CD optical sub beam E input port for SERVO
14		F	I	CD optical sub beam F input port for SERVO
15		ADVD1	I	DVD optical main beam A input port for SERVO
16		BDVD1	I	DVD optical main beam B input port for SERVO
17		CDVD1	I	DVD optical main beam C input port for SERVO
18		DDVD1	I	DVD optical main beam D input port for SERVO
19		ACD1	I	CD optical main beam F input port for SERVO
20		BCD1	I	CD optical main beam F input port for SERVO
21		CCD1	I	CD optical main beam F input port for SERVO
22		DCD1	I	CD optical main beam F input port for SERVO
23		AVCC	P	Power voltage input port for analog part
24		VREFA	-/O	CAP connection port for analog part
				center voltage, Use at other block
25		FOFST	O	CAP connection port for focus auto offset (OPEN)
26		OFSTHOLD	I	ON/OFF connection port for auto offset block (L :
				auto offset adjustment H : serial offset adjustment)
27		VREFLP_BGI	I	BANDGAP voltage input port for ALPC
28		LDODVD	O	DVD optical laser diode driving voltage output port
29		PDDVD	I	DVD optical laser monitor diode voltage input port
30		LDOCD	O	CD optical laser diode driving voltage output port
31		PDCD	I	CD optical laser monitor diode voltage input port
32		AGND	P	Power GND port for analog part
33		FE	O	FE AMP output port

	PIN NAME		I/O	FUNCTION
34		FEN	I	FE Input port for AMP GAIN setting
35		TEN	I	Input port for TE AMP GAIN setting
36		TE	O	TE AMP output port
37		PDLIMTRES	-	Bias resistance port for PDLIMIT
38		ABCDN	I	Input port for ABCD AMP GAIN setting
39		ABCD	O	ABCD AMP output port
40		ABCDI	I	ABCD AC coupling input port for SERVO monitor
41		ENVP	-	Peak hold time constant setting RC
				connection port for RF envelope detect
42		ENVB	-	Bottom hold time constant setting RC
				connection port for RF envelope detect
43		ENV	O	RF envelope detect output port
44		DGND	P	Power GND input port for digital circuit
45		FOKTH	I	Focus OK comparing level input port
46		FOKB	O	Focus OK comparator output port
				(L: FOCUS OK)
47		DFCT_CP1	-	Peak hold time constant connection port SERVO
				defect max. time setting
48		DFCT_CP2	-	Peak hold time constant connection port PLL defect
				min. time setting
49		CC1	O	Output port of peak detector for defect
50		CC2	I	AC coupling input port for defect
51		DVCC	P	Power voltage input port for digital circuit
52		DVCTTH2	-	Resistance connection port for PLL defect comparat-
				ing level setting
53		DFCTTH1	-	Resistance connection port for SERVO defect com-
				parating level setting
54		DFCT1	O	Defect output port for SERVO
55		DFCT2	O	Defect output port for PLL
56		DPDVCC	P	Power voltage input port for DPD TE
57		MIRR	O	Mirror output port
58		BCA	O	BCA output port
59		TE3OFST	-	Resistance connection port for 3BTE offset
60		DPDEQ1	O	DPD EQ (A+C) output port
61		DPDEQ2	O	DPD EQ (B+D) output port
62		FAULTOUT	O	DPD defect waveform output port (MONITOR)
63		DPDMUTE	I	DPD TE MUTE control port (H : MUTE)
64		PLLCTL	I	DPD TE PLL variable input port

	PIN NAME		I/O	FUNCTION
65		TE1RES	I	DPD TE PLL variable bias resistance
66		DPDGND	P	Power GND input port for DPD TE
67		VREFDPD	O	CAP connection port for DPD TE center
68		RREFDLY	-	Bias resistance connection port for delta block
69		DATA	I	Data input port
70		CLOCK	I	Clock input port
71		STB	I	Data enable input port
72		OSC		OSC time constant input port for auto offset block
73		RESET	I	Reset input port for auto offset block (L : RESET)
74		BCAI	I	BCA FILTER1
75		BCAO	O	BCA FILTER2
76		RFCT	O	RF ripple center voltage output port for mirror
77		CB2	-	Bottom hold time constant RC connection port for
				RFCT generation
78		CP2	-	Peak hold time constant RC connection port for
				RFCT generation
79		RFRP	O	RF ripple AMP output port for mirror
80		RFRPN	I	RF ripple AMP GAIN input port for mirror
81		MROFST	I	RF ripple offset control port for mirror
82		CB1	-	Bottom hold time constant RC connection port for
				RFCT generation
83		CP1	-	Peak hold time constant RC connection port for
				RFCT generation
84		MIRRI	I	Input port for MIRR signal generation
85		EQVCC	P	Power voltage input port for RF EQ
86		RFEQO	O	RF EQ output port
87		BCATH	I	BCA comparating level control port
88		EQIN	I	RFAGCO input port for RF EQ
89		RFAGCO	O	RF AGC AMP output port
90		AGCC	-	AGC time constant CAP connection port
91		AGCI	I	When AGC is “HOLD”, AGC voltage input port
92		EQGND	P	Power GND input port for RF EQ
93		AGCLEVEL	I	AGC level control voltage input port
94		AGCB	-	RF bottom hold time constant RC connection port for RF AGC
95		AGCP	-	RF peak hold time constant RC connection port for RF AGC

	PIN NAME		I/O	FUNCTION
96		RDPF	-	Bias resistance connection port for RF EQ frequency setting
97		EQG	I	RF EQ boost gain control voltage input port
98		EQF	I	RF EQ peak frequency control voltage input port
				RF EQ boost, peak frequency gain control port corre-
99		PLLGF	I	sponding to wideband PLL (PLLG. PLLF resistance
				internal design)
100		VZOCTL	I	RF EQ control port (When No. PLLG isn’t adjusted,
				apply DC CTL voltage.)

Information Reference

Reference Information

2-1-3 SIC1 (KS1452 ; Digital Servo)

DIRC

PS1

SSTOP /PSO

SMON

LOCK

DFCT

FOKB

MIRR

TZCA

PHI1

XOUT

XO

XI

TEST

RSTB

TILTO

TILTI

FLKB

TLKB

LDONB

SQCK

SQSI

SCOR

DAB

CSB

MWRB

MRDB

MDATA[7:0]

SENSE

PSB

MDOUT[3:0]

PLLLOCK

RFD

RPD

EFMRTD

PLCK

RVCO

VCTRL

EQCTL

MAGICO

FDCTL

INTO 224

PLLHD

INTERFACE

BLOCK

SUB CODE

READ BLOCK

SYSCON

INTERFACE

BLOCK

WIDE

CAPTURE

RANGE PLL

I/O

TIMING

GENERATOR

DSP CORE

FOR

DIGITAL SERVO

ROM

A/D

CONVERTER

BLOCK

TRACK

COUNTER

D/A

CONVERTER

BLOCK

EFM

ASYMETRY

VREF

ENV

TZCO

SME

TE

FE

COUT

FOD

TRD

SLD

SPD

FBAL

TBAL

DVCTL

EFMI

RFI

ASYDVD

ASYCD

EFM

EFMOA

2-4	Samsung Electronics

Electronics Samsung

5-2

PIN NAME

I/O

FUNCTION

PIN NAME

I/O

FUNCTION

PIN NAME

I/O

FUNCTION

PIN NAME

I/O

FUNCTION

1

MDOUT3

O

Mode data3 out controlled by micom

34

FOKB

I

Focus OK signal input pin

65

FE

I

Focus error signal input pin

73

SLD

O

Sled motor drive signal output pin

2

SSTOP/PSO

I

Limit switch/sled position sensor input pin0

35

FDCTL

I

PLL frequency detect control input pin

66

ENV

I

RF envelope input pin

74

SPD

O

Spindle motor drive signal output pin

3

PS1

I

Sled motor position sensor input pin 1

36

LDONB

O

Laser diode ON signal output pin

67

TILTI

I

Tilt in (reserved)

75

FOD

O

Focus actuator drive signal output pin

4

TEST

I

Test pin (L : normal H : test)

37

DFCT

I

Defect Detection signal input pin

68

AVDD

P

Analog block VDD power supply pin

76

TRD

O

Tracking actuator drive signal output pin

5

COUT

O

Counter clock

38

MIRR

I

Mirror signal input pin

69

TILTO

O

Tilt out (reserved)

77

TZCA

I

TE signal for tracking zero cross input pin

6

FLKB

O

Focus servo lock signal output pin

39

PLLHD

I

PLL hold signal from micom

70

DVCTL

O

Depth variation control signal output pin

78

MDOUT0

O

Mode data 0 out controlled by micom

7

TLKB

O

Tracking servo lock signal output pin

40

INTO_224

O

Servo interrupt monitor pin

71

TBAL

O

Tracking balance signal output pin

79

MDOUT1

O

Mode data 1 out controlled by micom

8

PSB

I

0 : 1BIT

1 : 8BIT

41

PVDD

P

PLL logic block VDD power supply pin

72

FBAL

O

Focus balance signal output pin

80

MDOUT2

O

Mode data 2 out controlled by micom

9

RSTB

I

System reset signal input pin

42

PLCK

O

PLCK

10

CSB

I

Micom chip select pin

43

PLLLOCK

O

Frequency lock detect output

11

DAB

I

Micom data/address select pin

(H : Lock L : Unlock)

12

MWRB

I

Micom write clock signal input pin

44

EFMRTD

O

Latched EFM output signal

13

MRDB

I

Micom read clock signal input pin

45

PVSS

P

PLL logic block VSS power supply pin

14

MDATA0

I/O

Micom data pin 0

46

RVCO

I

Resistor pin for VCO GAIN

15

MDATA1

I/O

Micom data pin 1

47

RFD

I

Gain adjust resister for frequence detector

16

MDATA2

I/O

Micom data pin 2

48

RPD

I

Gain adjust resister for phase detector

17

MDATA3

I/O

Micom data pin 3

49

VCTL

I

Control voltage for VCO

18

MDATA4

I/O

Micom data pin 4

50

MAGICO

I

Input for hysteresis control of FD output (for test)

19

MDATA5

I/O

Micom data pin 5

20

MDATA6

I/O

Micom data pin 6

51

EFMOA

I

EFM offset adjustment pin

21

MDATA7

I/O

Micom data pin 7

52

TZCO

O

Tracking zero cross output pin

22

SENSE

O

Internal status monitor pin

53

SVDD

P

Servo CPU VDD power supply pin

23

DVDD

P

Servo logic & ROM VDD power supply pin

54

EQCTL

O

EQ control signal

24

XI

I

System clock signal input pin

55

EFMI

I

EFM signal for test

25

XO

O

System clock signal output pin

56

EFMO

O

EFM signal

26

XOUT

O

Clock out (33.9688MHz) to DSP

57

LPFDVD

I

Asymmetric input signal for DVD

27

DVSS

P

Servo logic & ROM VSS power supply pin

58

LPFCD

I

Asymmetric input signal for CD

28

SQCK

O

Clock output pin for subcode data read

59

RFI

I

RF input signal

29

SQSI

I

Subcode data input pin

60

SVSS

P

Servo CPU VSS power supply pin

30

SCOR

I

Timing detection input pin for subcode data read

61

AVSS

P

Analog block VSS power supply pin

31

SMON

I

Motor ON signal input pin

62

SME

I

Spindle error input pin

32

LOCK

I

Lock signal input pin

63

VREF

I

Reference voltage input pin

33

DIRC

I

Direct jump control (for 1 track jump)

64

TE

I

Tracking error signal input pin

Information Reference