Samsung Bonn-L Schematic
3
3
1
2
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
CPU :
BONN-L
Remarks :
Chip Set :
Intel Penryn
DRAW
1
APPROVAL
CHECK
DATE
MODULE CODE
Signature :Owner : SEC Mobile R & D X
ELECTRONICS
EXCEPT AS AUTHORIZED BY SAMSUNG.
OF
SAMSUNG
PART NO.
PAGE
LAST EDIT
TITLE
Dev. Step : PR
REV
DEV. STEP
Revision : 1.2
MAIN
GCE :
2009.06.03
HAN :
NAN :
Intel Cantiga & ICH9M
Montevina Platform
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
Design
THIS DOCUMENT CONTAINS CONFIDENTIAL
APPROVALCHECK
A
SAMSUNG PROPRIETARY
B
A
C
B
D
C
4
D
Model Name : R519
4
2
PBA Name :
PCB Code :
SY.KIM
HK.PARK
H.J.KIM
10/10/2008
PR
1.2
June 03, 2009 16:14:25 PM
BA41-
1 49
BONN-L
MAIN
COVER
D:/users/mobile64/mentor/r519/pr_re1.1_0603
T.R. Date :
KBD
USB 0,2,6
800/1067 MT/S
PAD
LCD
SATA
PG 31
Termination
x4, 1.5V
Clocking
Aud.
PG 36
LPC
ANT
PG 18
Dual channel
Lane 3
MODULE CODE
CHECK
HD Audio
USB 1
PG 13-17
PG 8
2P
DC/DC
Channel B (Reverse)
VCCP / DC-DC
Charging
B
PAGE
80 Port
ON BOARD
3
MMC
Mini Card 1
CRT
PG 41
PG 19
PG 39
LCD
ELECTRONICS
PG 18,19
MICOM
CLINK
PG 38
DDR II
PCIE x1
PG 26
TITLE
Touch
Module
PG 9-11
DATE
Smart
Battery
MIC-IN
GENESIS
High Definition Audio
USB 0,2,6
SPKR L
D
676 BGA
DEV. STEP
PG 48
SAMSUNG
RTL103EL
D
3.3V LPC, 33MHz
TMKBC (TBD)
GMCH-M
1329 FCBGA
FSB
12P
PG 12
DRAW
PG 37
PG 53
PG 20 - 24
OF
ODD
1
SATA 0
B
PG 36
A
SD
SAMSUNG ELECTRONICS CO’S PROPERTY.
SPI
Express Card
HDD
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
PG 36
PG 35
Channel A (Standard)
Audio
DDR II Power
2
SODIMM 1
LED
IMVP-6
(WLAN)
CRT
MEC1308
Camera
3
PG 34
Mobile Processor
USB 4
PG 40
PG 40
PG 27
Sub board
Touchpad
CPU
PG 8
USB 7
PCIE x1
478pin
LAST EDIT
Bluetooth
PROPRIETARY INFORMATION THAT IS
Cantiga-GM
PART NO.
C
THIS DOCUMENT CONTAINS CONFIDENTIAL
ANT
SATA
PG 34
LED
FAN
REV
GL40
2
PG 25
1
PCIE x1
C
PG 43
Lane 1
4
USB 8
SATA 1
PG 43
EMC2112
OPTION
DDR II
Circuit
PG 30
FSB 1067
Penryn-6M
2P
4
PG 25
52P
DDR II 667/800
2 IN 1
PG 40
USB 5
DC/DC
PG 33
CPU
ICH9-M
PG 38
PG 31
PG 47
AMP
RJ45
ALC269
CK-505
L2 Cache : 6/3MB
HP
SAMSUNG PROPRIETARY
DDR II 667/800
SODIMM 0
SPI ROM
Thermistor
SPKR R
EXCEPT AS AUTHORIZED BY SAMSUNG.
A
PG 42, 52
Direct Media Interface
APPROVAL
Lane 4
D:/users/mobile64/mentor/r519/pr_re1.1_0603
BLOCK DIAGRAM
BONN-L
492
BA41-
June 03, 2009 16:14:25 PM
1.2
PR
9/23/2008
undefined
H.J.KIM
HK.PARK
SY.KIM
MAIN
USB2.0 #1 (USB1) : D
-
E
-
I C / SMB Address
Address
DRAW
C
SODIMM1
D
DATE
4
1010 010x
3
-
2
A0h
1
SMBUS Master
-
Devices
Clock, Unused Clock Output Disable
THIS DOCUMENT CONTAINS CONFIDENTIAL
D2h
Hub to PCI
CK-505M (Clock Generator)
Internal MAC
Voltage Rails
AD29(internal)
-
AD31(internal)
-
REQ/GNT#
PORT #
Interrupts
SYSTEM PORT 0
USB2.0 #0 (USB0) : A
See rev notes for more information.
SAMSUNG PROPRIETARY
1
IDSEL#
Cardbus
PROPRIETARY INFORMATION THAT IS
4
SAMSUNG ELECTRONICS CO’S PROPERTY.
LCD Pannel Detect
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
Resolution
EXCEPT AS AUTHORIZED BY SAMSUNG.
Crystal / Oscillator
APPROVAL
Crystal
MODULE CODE
FREQUENCY
ICH9-M
REV
Real Time Clock
TITLE
Crystal
PAGE
HD64F2169/2160
SAMSUNG
25MHz
BOARD INFORMATION
LAN
A
14.318MHz
B
CPU Thermal Sensor
CHECK
NC
Master
0111 101x
DEV. STEP
USB2.0 #4 (EHCI) : H
LAST EDIT
(TBD)
PART NO.
PORT #
OF
NC
ELECTRONICS
0
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
2
A
Mini Card 2 (ROBSON or DVB-T)
B
5
C
LOM
D
GLAN
4
-
3
9
2
Mini PCI Express 2
1
Bluetooth
PCI Devices
Thermal Sensor on SODIMM1
2
3
USB
VCC_CORE
LPC bridge/IDE/AC97/SMBUS
P5.0V_ALW
AD25
3.3V always power rail (for Micom)
AD30(internal)
5.0V switched on power rail (off in S4-S5)
AD24(internal)
1.8V switched power rail (off in S3-S5)
3
P0.9V
A,B,C
P1.8V_AUX
B
P3.3V
USB2.0 #2 (USB4) : C
1.8V power rail for DDR (off in S4-S5)
-
3.3V switched power rail (off in S3-S5)
-
P1.05V (VCCP)
-
SYSTEM PORT 2
Devices
P1.5V
ICH9-M
CLOCK-Generator
SODIMM0
-
6
7
1010 000x
Thermal Sensor on SODIMM0
Hex
0011 000x
7Ah
0011 010x
Bus
34h
Thermal Sensor
-
-
Core Voltage for CPU
A4h
VDC
2
5.0V always power rail
1101 001x
0.9V power rail for DDR (off in S3-S5)
AC Link
P5.0V_AUX
B
P1.8V
USB PORT Assign
VTT for CPU, Crestline & ICH9-M
ASSIGNED TO
P3.3V_MICOM
SYSTEM PORT 1
P5.0V
0
P3.3V_AUX
Primary DC system power supply (9 to 20V)
5.0V switched power rail (off in S3-S5)
NC
3.3V switched on power rail (off in S4-S5)
5
REVISION HISTORY
Devices
F
PANNEL_DETECT_0
1.5V switched power rail (off in S3-S5)
32.768KHz
CK-505
TYPE
30h
DEVICE
USB2.0 #3 (USB5) : E
USAGE
Camera
10MHz
PCI Express Assign
MICOM
ASSIGNED TO
NC
Crystal
1
RealTek 88E8057
3
Crystal
SY.KIM
HK.PARK
H.J.KIM
undefined
9/23/2008
PR
1.2
June 03, 2009 16:14:25 PM
BA41-
3 49
BONN-L
MAIN
BOARD INFO
D:/users/mobile64/mentor/r519/pr_re1.1_0603
4
Mini Card 1 (WLAN)
NC
-
8NCNC
Samsung
Samsung
Samsung
Confidential
Confidential
Confidential
PART NO.
CRESTLINE
AC Adapter
P1.25V
ICH9-M
LEDs
DRAW
M_PCI
+0.9V
MODULE CODE
2
DEV. STEP
REVAPPROVAL
LAN
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
ON
M_PCI
P1.2V
KBC3_SUSPWR
S5
1
GDDR-3 for PEG
ON
+V*A(LWS)
CHECK
PROPRIETARY INFORMATION THAT IS
+V*AUX
D
MDC
VDC
PCMCIA
D
DATE
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
(CHP3_S4_STATE*)
TITLE
ON
ON
C
LAST EDIT
4
Rail
C
HEATSINK
EXCEPT AS AUTHORIZED BY SAMSUNG.
(VCCP)
KBC3_PWRON
ICH8-M
2
FAN CIRCUIT
P0.9V
MDC
Battery DC
Cantiga
A
LCD
It should be updated
S0
ICH8-M
CRESTLINE
EGFX_CORE
AUX DISPLAY
P3.3V
P3.3V_MICOM
P2.5V_LAN
LAN
MEROM
P1.8V_LAN
ON
LAN
State
B
FDD
OF
P1.8V
P5V_AUX
3
S4
P1.5V
SODIMM
VCC_CORE
PCMCIA
PAGE
SAMSUNG
DDR II-Termination
POWER DIAGRAM
ICH8-M
+V
SPI
MDC
PEG
ICH8-M
PEG
MICOM
CRESTLINE
SAMSUNG ELECTRONICS CO’S PROPERTY.
+V* (CORE)
P1.05V
SODIMM (DDR III)
P1.05V_AUX
MEROM
1
BT
P12.0V_ALW
CRESTLINE
S5-S4
P1.5V_AUX
KBC3_VRON
DDR III-Termination
P1.5V_AUX
3
PEG
P5.0V_ALW
nVidia (TBD)
P5.0V
P3.3V_ALW
USB
IGFX_CORE
ICH8-M
HDD
ON
A
Thermal Sensor
4
ON
ON
MICOM
S0
(CHP3_SLPS3*)
CRT
+V*LAN
+1.8V_AUX
ON
ON
S3
PEG
P3.3V_AUX
Power On/Off Table by S-state
B
P1.2V_LAN
OPTION FOR ME
D:/users/mobile64/mentor/r519/pr_re1.1_0603
POWER DIAGRAM
MAIN
BONN-L
494
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June 03, 2009 16:14:25 PM
1.2
PR
9/23/2008
undefined
H.J.KIM
HK.PARK
SY.KIM
ICH8-M
CRESTLINE
ELECTRONICS
P0.9V
Rev 0.1
MICOM
S3
Samsung
Samsung
Samsung
Confidential
Confidential
Confidential
0.5 A (TBD)
0.16 A (TBD)
USB (x 3)
3.3V_AUX
SPI
3.3V
41 A (TBD)
0.29 A (TBD)
4.5 A (TBD)
RTC_Battery
3.3V_AUX
3.3V_AUX
KeyBoard
ODD
7.7 A (TBD)
0.75A (TBD)
1.8V_AUX
0.07 A (TBD)
3.1 A (TBD)
5V
MDC
KBC
0.67 A (TBD)
1.2V (PEX IO)
1.05V (MCH CORE)
SATA HDD
1.8V
Touch Pad
0.6 A (TBD)
0.2 A (TBD)
0.08 A (TBD)
5V
Sensor
DDR-2
1.05V
1.0V-1.1V (EGFX CORE)
GMCH
PWR LED
4.48 A (TBD)
3.3V
0.001 A (TBD)
0.08 A (TBD)
3.79 A (TBD)
LCD
1.75 A (TBD)
1.5V
1.25V
0.1 A (TBD)
1.8V_AUX
( ~ 2.0 W )
DATE
1.25V ( TBD A )
0.209 A (TBD)
3.3V_AUX ( TBD A )
CPU CORE
0.006 A (TBD)
3.3V
Mini Card
5V
P1.2V_LAN
POWER RAILS ANALYSIS
1.05V
17.75 A (TBD)
Adapter
1.8V
Thermal
DRAW
0.22 A (TBD)
APPROVAL
MICOM 3V ( TBD A )
4
P1.8V/2.5V_LAN
0.125 A (TBD)
(8 - 8.5 W )
2
1.8V ( TBD A )
PAGE
5V
SAMSUNG
(Dual slots)
THIS DOCUMENT CONTAINS CONFIDENTIAL
CPU CORE ( TBD A )
1.13 A (TBD)
P3.3V_AUX
2.43A (TBD)
220V
C
0.25 A (TBD)
D
( ~ 5.0 W )
DEV. STEP
0.1 A (TBD)
5V_AUX
0.9V( TBD A )
2.4A (TBD)
PEX IO (TBD A)
1
KBD LED
0.06 A (TBD)
Rev. 0.6 (060920)
LAN (RTL103EL)
MODULE CODE
5.0V ( TBD A )
3.3V
5.0V_AUX ( TBD A )
LAST EDIT
VDC INV ( TBD A )
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
CLOCK
4
HD Audio
ELECTRONICS
ITP
ICH9-M
Battery
A
1.8V_AUX ( TBD A )
TITLE
0.1 A (TBD)
PROPRIETARY INFORMATION THAT IS
0.2 A (TBD)
D
0.15 A (TBD)
3.3V
VGA CORE (TBD A)
3
(Value by measurement)
B
1.5V ( TBD A )
REV
MICOM 3V
SAMSUNG PROPRIETARY
3.3V
3.3V_AUX
19V (VDC INV)
5V
5V
PEG
3.3V
A
3.3V ( TBD A )
EXCEPT AS AUTHORIZED BY SAMSUNG.
5V
CHECK
SD Card
1.5V
0.01 A (TBD)
Penryn-6M
3.3V
3
Value by Datasheet/Application notes
PART NO.
0.08 A (TBD)
OF
3.3V
SATA
3.3V (LCD 3V)
0.9V
1.05V ( TBD A )
SAMSUNG ELECTRONICS CO’S PROPERTY.
( 35 W )
B
3.3V_AUX
C
1.5 A (TBD)
3.3V
1.5V
RTC_Battery
FAN
0.13 A (TBD)
1.5 A (TBD)
2
0.5 A (TBD)
1
1.8V
1 A (TBD)
1.5V
0.75 A (TBD)
2 A (TBD)
GDDR
5V
0.33 A (TBD)
5V
1.05V (VCCP)
3.1 A (TBD)
3.3V
0.67 A (TBD)
0.5 A (TBD)
3.3V
LAN
1.5 A (TBD)
0.374 A (TBD)
Audio AMP
SY.KIM
HK.PARK
H.J.KIM
undefined
9/23/2008
PR
1.2
June 03, 2009 16:14:25 PM
BA41-
5 49
BONN-L
MAIN
POWER RAILS
D:/users/mobile64/mentor/r519/pr_re1.1_0603
0.001 A (TBD)
0.015 A (TBD)
Cantiga
1.05V (VCCP)
MICOM 3V
6.53 A (TBD)
3.3V
Samsung
Samsung
Samsung
Confidential
Confidential
Confidential
B
4
4
3
3
ICH8-M
KBC
RTC
Battery
CHP3_RTCRST#
4) POWER_SW*
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
6) P1.8V_AUX
5) KBC3_SUSPWR
11) VCCP3_PWRGD
19) PCI3_RST*
EXCEPT AS AUTHORIZED BY SAMSUNG.
DRAW
CHECK
APPROVAL
20) CPU1_CPURST*
14) VCC_CORE
DDR3
Memory
MODULE CODE
TITLE
PART NO.
PAGE
CK-505
PRTC_BAT
LOM
6-1) P1.8V/P2.5V_LAN
OF
A A
B
BCP69
6-1) P1.2V_LAN
10-1) P1.05V
10-1) P1.5V
REV
LAST EDIT
SAMSUNG
ELECTRONICS
Sheet 46-47
Sheet 46
VRMPWRGD
PWROK
POWER SEQUENCE
Rev. 0.7
C C
Sheet 40
Sheet 40
2
3
D D
2
2
4
6
PRTC
7) P1.05V_AUX
1
1
SAMSUNG PROPRIETARY
20
ISL6227
ICSL6256
Adapter
GMCH
VRM
9) KBC3_PWRON
10-1) P3.3V
Battery
2) VDC
SC486
10) P1.5V
6) MEM1_VREF
10-1) ICH_CORE (P1.05V)
18) CPU1_PWRGDCPU
POWER
17) KBC3_PWRGD
7) P1.5V_AUX
9) KBC3_PWRON
9) KBC3_PWRON
S/W
PCI
P3.3V_AUX & P5V_AUX
SC486
13) KBC3_VRON
12)GCORE3_PWRGD (PM-model)
6) P1.8V_AUX
10-1) P3.3V
DDR2 POWER
Sheet 50
DATE
DEV. STEP
PWROK
CL_PWROK
19) PLT3_RST*
(Test Option)
19) PLT3_RST*
6) P3.3V_AUX
Sheet 8
TPS51120
P3.3V_MICOM
6) P5.0V_AUX
9
18
AP6680A
16-1) Clock Running
Sheet 22-25
DC/DC B’d
16
14
6) P3.3V_AUX
19) PCI3_RST*
Sheet 10-12
1
Sheet 15-19
Sheet 20-21
8
9
M-2) KBC3_ME_PWRON = 15) KBC3_PWRON
Host / ME Boot
Marvell
INTVRMEN
AP6680A
CPU
(SLPS4* = S4_STATE*) > (SLPM* = SLPS3*)
Host Boot / ME Off
3
P5.0V_ALW
5
AC_DC / Battery
Devices
10) P1.1
7
7) KBC3_RSMRST#
11
SC471
10) P1.05V
11-1) P1.8V
PEG
2) VDC
11-1) GFX_CORE
12)GCORE_PWRGD
17) KBC3_PWRGD
17) KBC3_PWRGD
PRTC
8) KBC3_SUSPWR
13) KBC3_VRON (Back-up)
16) CLK3_PWRGD
10-1) P3.3V
10-1) P1.8V
10-1) P1.8V
10) P1.5V
6) P1.8V_AUX
10-2) P0.9V
CPU
6) P1.8V_AUX
17) KBC3_PWRGD
17) KBC3_PWRGD
P3.3V_MICOM
110ms Delay
PCIe
Devices
8) CHP3_SLPS5#/4#/3#
5) KBC3_SUSPWR
9) KBC3_PWRON
6
PM-model only
10) P1.05V (IGFX_CORE)
2) VDC
15) VRM3_CPU_PWRGD
15
19
11) VCCP3_PWRGD
Host S5 / ME Boot
(SLPS4* = S4_STATE*) > SLPM* > SLPS3*
(SLPS4* = SLPM*) > S4_STATE* > SLPS3*
19
6) P3.3V_AUX
10
17
2-1) P12.0V_ALW
10) P5.0V
9-1) KBC3_PWRON_INV#
9-1
M-1) KBC3_DDR_PWRON (TBD) = 8) KBC3_SUSPWR
LAN100_SLP
AP4435
10) P5.0V
10-2) 0.9V
12
13
15)VRM3_CPU_PWRGD
D:/users/mobile64/mentor/r519/pr_re1.1_0603
POWER SEQUENCE
MAIN
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undefined
H.J.KIM
HK.PARK
SY.KIM
15)VRM3_CPU_PWRGD
10) P1.5V
10-1) P1.2V
10-1) P3.3V
10-1) P3.3V
2) VDC
CL_PWROK
Samsung
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Samsung
Confidential
Confidential
Confidential
48MHz PLL
APPROVAL
MODULE CODE
33 MHz
DEV. STEP
REV
MUX
A A
PEG
B
C
CPU_STP*
D D
PCI_STP*
4
3
100 MHz (SRC 6,8,9,10)
2
2
CLK1_MINIPCIE/PCIE*
OF
SAMSUNG
333/400 MHz
CLK1_MCLK3/3#
CLK1_MCLK4/4#
ITM3_CLKREQ*
333/400 MHz
CLK1_EXPCARD#
Cantiga
PCI Express Gfx
100 MHz (SRC0)
OSC
266 MHz CLK0_HOST_GMCH/GMCH*
MINI PCIE
CARD 2
PCIE LAN
LOM3_CLKREQ*
AUD3_BCLK
CPU
CLK3_USB4848 MHz
CLK1_SATA/SATA*100 MHz (SRC 2)
SAMSUNG PROPRIETARY
CHP3_SATACLKREQ*
CLK3_PCLKICH33 MHz
33 MHz
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
CLK3_PCLKMICOM
BSEL
14 MHz
OSC
EXCEPT AS AUTHORIZED BY SAMSUNG.
DRAW
CK-505M (w/ CLKREQ* & SSDC)
xSLG8SP513r05)
100 MHz
CLK1_DREFCLK/CLK*
96 MHz
CLK1_PCIEICH/ICH*100 MHz (SRC 3)
CLK1_PCIELOM/LOM*100 MHz (SRC 9)
MDC3_BCLK
32.768 KHz
RTC Clock
25 MHz
10 MHz
Page 8
MCH3_CLKREQ*
CLK1_PEG/PEG*
100 MHz (SRC 6)
CLK1_MINI2PCIE/PCIE*
100 MHz (SRC 8)
1
SPI
SPI3_CLK
17.86 MHz
HPLL
PCIE PLL
DPLLA
MPLL
DPLLB
ICH9-M
USBPLL
SATAPLL
TITLE
PART NO.
PAGE
CLK3_ICH1414.318 MHz
ELECTRONICS
CLOCK DISTRIBUTION
Rev. 0.1
667/800 MHz
CLK3_PCLKPORT80
33 MHz
CLK1_MCLK0/0#
CLK1_MCLK1/1#
SODIMM #0
SODIMM #1
Main PLL
SSC
EXPRESS CARD
266 MHz CLK0_HOST_CPU/CPU*
PLL3
SSC
CLK1_DREFSSC/SSC*
100 MHz (SRC4) CLK1_MCH3GPLL/3GPLL*
HD 24 MHz
Buffer
MUX
MCH
KBC
14.318 MHz
SY.KIM
1
MUX
FSB
THIS DOCUMENT CONTAINS CONFIDENTIAL
DMI
FS(2:0)
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
ITP_EN
SS(96/100) SEL
CHECK
P3.3V
CLK3_PWRGD*
DATE
MINI PCIE
CARD 1
LAST EDIT
MIN3_CLKREQ*
EXP3_CLKREQ*
B
333/400 MHz
333/400 MHz
C
32.768 KHz
PCIEPLL
4
HD Audio
MDC
3
(Marvell)
PORT 80
1
D:/users/mobile64/mentor/r519/pr_re1.1_0603
CLOCK DIAGRAM
MAIN
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1.2
PR
9/23/2008
undefined
H.J.KIM
HK.PARK
Samsung
Samsung
Samsung
Confidential
Confidential
Confidential
AMD CPU/DIODE MODE
1
D
0
A
TRIP_SET 1500 : 95 degree
Line Width = 20 mil
DATE
INTEL TR MODE
SHDN_SEL MODE
10mil width and 10mil spacing.
C
PROPRIETARY INFORMATION THAT IS
THERMAL SENSOR & FAN CONTROL
SAMSUNG ELECTRONICS CO’S PROPERTY.
C
4
To support heatsink
Check if PU is doubled to Micom Side.
For Intel 45nm(From penryn)
CHECK
APPROVAL
OF
SAMSUNG PROPRIETARY
SMBUS Address 7Ah
1
B
2
1
HIGH Z
EXCEPT AS AUTHORIZED BY SAMSUNG.
ADDRESSS_SEL MODE
1
4
PART NO.
LAST EDIT
REV
ELECTRONICS
SAMSUNG
TITLE
3
THIS DOCUMENT CONTAINS CONFIDENTIAL
PAGE
0
0111 101xb (7A)
0101 111xb
DEV. STEP
HIGH Z
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
A
MODULE CODE
DESIGN
2
June 03, 2009 16:14:25 PM
BA41-
8 49
BONN-L
THERMAL SENSOR
THERMAL SENSOR EMC2112
D:/users/mobile64/mentor/r519/pr_re1.1_0603
SY.KIM
HK.PARK
H.J.KIM
9/23/2008
PR
1.2
0101 110xb
3
EXT.DIODE 2 MODE
B
Opposite side of CPU.
D
34-B3,49-C3
8-B2,48-C2
P3.3V_AUXP5.0V
C538
100nF
10V
10000nF-X5R
C537
6.3V
10V
100nF
C551
3
4
MNT1
5
6
MNT2
P3.3V
HDR-4P-1R-SMD
J1
3711-000456
1
2
nostuff
M503
BA61-01090A
DIA
HEAD
LENGTH
8-C3,48-D4
R533
0
Q509
1
3
2
50V
C642
MMBT3904
21
7
TRIP_SET
1
VDD_3V
16
VDD_5V_1
19
VDD_5V_2
P3.3V
2.2nF
DP1
DP3_DN2
4
17
FAN_1
18
FAN_2
GND
13
9
RESET#
6
SHDN_SEL
15
SMCLK
SMDATA
14
8
SYS_SHDN#
20
TACH
THERMAL_PAD
U505
EMC2112-BP-TR
1209-001887
ADDR_SEL
10
12
ALERT#
CLK
11
2
DN1
DN3_DP2
5
3
BA61-01090A
M501
50V
LENGTH
HEAD
DIA
10-C4,48-D2
C552
2.2nF
34-D1,48-B4
10-C4,48-D2
R534
10K
10K
R531
1%
1%
10K
R544
1%
DIA
BA61-01090A
M502
DIA
BA61-01090A
M504
LENGTH
HEAD
LENGTH
HEAD
48-B2 22-C3,34-C3
1%
R545
49.9
R546
P3.3V_AUX
R532
1.5K
8-C3,48-C2
0
10000nF-X5R
C6
6.3V
1%
P3.3V_AUX
1%
34-B3,49-B3
10K
R529
8-B2,48-D4
1%
R530
10K
THM3_VDD_5V_MN THM3_VDD_3V_MN
FAN3_FDBACK#
THM3_STP#
KBC3_THERM_SMDATA
KBC3_THERM_SMCLK
CPU2_THERMDA
CPU2_THERMDC
THM3_ALERT#
FAN5_VDD
FAN3_FDBACK#
FAN5_VDD
THM3_TRIP_SET_MN
THM3_SHDN_SEL_MN
THM3_THERMDN_MN
THM3_THERMDP_MN
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ADDR GROUP
ICH
0
ADDR GROUP
1
CONTROL
2 / 4
DATA GRP 0
DATA GRP 2
DATA GRP 1
DATA GRP 3
ELECTRONICS
TITLE
B
A
D
4 3
MODULE CODE
3
PENRYN (1/3)
D:/users/mobile64/mentor/r519/pr_re1.1_0603
PROPRIETARY INFORMATION THAT IS
1
LAST EDIT
1
SAMSUNG PROPRIETARY
PART NO.
DRAW
C
4
EXCEPT AS AUTHORIZED BY SAMSUNG.
CPU Mount
D
PAGE
2
C
CPU Socket : 3704-001153
DATE
APPROVAL
THIS DOCUMENT CONTAINS CONFIDENTIAL
A
SAMSUNG ELECTRONICS CO’S PROPERTY.
REV
2
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
OF
DEV. STEP
B
CHECK
SAMSUNG
SY.KIM
HK.PARK
H.J.KIM
undefined
9/23/2008
PR
1.2
June 03, 2009 16:14:25 PM
BA41-
9 49
BONN-L
CPU
0
3
4
0
42
43
44
31
38
39
40
41
59
60
37
55
56
9
10
5
6
51
52
48
31
53
54
58
57
49
50
SUPLECODE
1
MNT1
MNT2
2
3
MNT3
MNT4
4
M505
BA75-02034A
P1.05V
R656
56
15
13
14
15
16
12
13
14
8
9
10
11
29
30
7
21
22
12
11
19
20
27
28
46
47
29
30
45
25
26
5
6
36
23
24
32
33
34
35
61
62
63
19
20
21
22
16
17
18
Y26
DSTBN3#
AE25
DSTBP0#
H26
DSTBP1#
M26
DSTBP2#
AA26
DSTBP3#
AF24
D63#
AC23
D7#
E23
D8#
K24
D9#
G24
DINV0#
H25
DINV1#
N24
DINV2#
U22
DINV3#
AC20
DSTBN0#
J26
DSTBN1#
L26
DSTBN2#
D53#
AC26
D54#
AD20
D55#
AE22
D56#
AF23
D57#
AC25
D58#
AE21
D59#
AD21
D6#
E25
D60#
AC22
D61#
AD23
D62#
AF22
W24
D44#
W25
D45#
AA23
D46#
AA24
D47#
AB25
D48#
AE24
D49#
AD24
D5#
G25
D50#
AA21
D51#
AB22
D52#
AB21
D34#
V24
D35#
V26
D36#
V23
D37#
T22
D38#
U25
D39#
U23
D4#
F23
D40#
Y25
D41#
W22
D42#
Y23
D43#
D24#
P25
D25#
P23
D26#
P22
D27#
T24
D28#
R24
D29#
L25
D3#
G22
D30#
T25
D31#
N25
D32#
Y22
D33#
AB24
K22
D15#
H23
D16#
N22
D17#
K25
D18#
P26
D19#
R23
D2#
E26
D20#
L23
D21#
M24
D22#
L22
D23#
M23
0143854500|bga_479p_sock
CPU1-2
PENRYN
D0#
E22
D1#
F24
D10#
J24
D11#
J23
D12#
H22
D13#
F26
D14#
RESET#
C1
RS0#
F3
RS1#
F4
RS2#
G3
SMI#
A3
STPCLK#
D5
TRDY#
G2
IGNNE#
C4
INIT#
B3
LINT0
C6
LINT1
B4
LOCK#
H4
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
V1
BNR#
E2
BPRI#
G5
BR0#
F1
DBSY#
E1
DEFER#
H5
DRDY#
F21
FERR#
A5
HIT#
G6
HITM#
E4
IERR#
D20
A34#
AB2
A35#
AA3
A4#
L5
A5#
L4
A6#
K5
A7#
M3
A8#
N2
A9#
J1
ADS#
H1
ADSTB0#
M1
ADSTB1#
A24#
R4
A25#
T5
A26#
T3
A27#
W2
A28#
W5
A29#
Y4
A3#
J4
A30#
U2
A31#
V4
A32#
W3
A33#
AA4
P4
A15#
P1
A16#
R1
A17#
Y2
A18#
U5
A19#
R3
A20#
W6
A20M#
A6
A21#
U4
A22#
Y5
A23#
U1
0143854500|bga_479p_sock
CPU1-1
PENRYN
A10#
N3
A11#
P5
A12#
P2
A13#
L2
A14#
33
34
35
32
3
2
1
4
7
8
4
17
18
3
23
27
28
25
24
26
1
2
CPU1_ADS#
CPU1_IERR#_MN
CPU1_CPURST#
CPU1_INTR
CPU1_DBI0#
CPU1_D#(63:48)
CPU1_D#(47:32)
CPU1_ADSTB0#
CPU1_ADSTB1#
CPU1_D#(31:16)
CPU1_D#(15:0)
CPU1_REQ#(4:0)
CPU1_A#(16:3)
CPU1_DSTBP2#
CPU1_DSTBP3#CPU1_DSTBP1#
CPU1_DSTBN1#
CPU1_DSTBP0#
CPU1_DBI1#
CPU1_DSTBN0#
CPU1_A#(35:17) CPU1_DBI2#
CPU1_DBI3#
CPU1_DSTBN2#
CPU1_DSTBN3#
CPU1_LOCK#
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
CPU1_SMI#
CPU1_STPCLK#
CPU1_TRDY#
CPU1_A20M#
CPU1_BNR#
CPU1_BPRI#
CPU1_BREQ#
CPU1_DBSY#
CPU1_DEFER#
CPU1_DRDY#
CPU1_FERR#
CPU1_HIT#
CPU1_HITM#
CPU1_IGNNE#
CPU1_INIT#
CPU1_NMI
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RSVD
THERMAL
H CLK
XDP/ITP SIGNALS
A
0
-> delete and change layout (ECAE)
1
1.3125 V
0
1
0.8125 V
1
FSC FSB
Route the VCC/VSSsense as a Zo=55ohm traces with equal length.
1
0
1
0
0
0
FSA
0
0
CPU Socket : 3704-001153
1
1
0
0
*"1111111" : 0V power good asserted.
1
0
0
200M
0
0
0
1
0
0.2250 V
0
1
1
0
1
1
1
0
1
0
1
0.5500 V
0
0
0.7125 V
1
1
1
1
0
SI team request
1
2
1.4625 V
0
1
1
1
*Yonah Processor (2.33 GHz / 800 MHz : TBD)
1
1
1
1.5000 V
1
0
1
1
1
0
0
1
0
1
0
near the CPU
0
1
BSEL0, BSEL2
0
1
1
0
0
0
0
0
BSEL
FRQ
0
1
0
0
1
0
1
1
OF
1.2250 V
0
1
166M
0
1
0
1
1.1750 V
0
0
0
0
1
0
1
0
0 1
1
REV
1
0
Minimize coupling of any switching signals to this net.
0
0
0
0
0
0
0
0
1
1
1
0
0.4875 V
DPRSLPVR
1
1
1
1
SAMSUNG ELECTRONICS CO’S PROPERTY.
0
0
0.0000 V
1
1
BSEL0, BSEL1, BSEL2
1
0
0
0
0
0.9125 V
0
1
0.7250 V
1
1
(preferred 50mil) from any other signal. And GND via 100mil away
1
1
1
1
266M
1
1
0
0
0.1625 V
1
1
0
0
0
APPROVAL
MODULE CODE
1
0
0
Active
1
0
0
1
0
0
0
1
0
1
0
0
1
Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away
1
FSB 800 MHz
0
1
0
1
0
0
0.5375 V
0
1
0
0
0
1
1.3000 V
1
DEV. STEP
0
0
0.6000 V
0
1
1
1
0
0
0.2500 V
FSB 1067 MHz
0.2625 V
1
1
1
1
0
0
0.5000 V
0
0
0
1
0
0
01
0
2
1
0
0
1
1.0625 V
0
1
1.1375 V
0.1500 V
1
3
0
0
0.5125 V
0
1
1
1
1
0
1
1
1
1
1
1
0
0.3750 V
Pull-down
0
DATE
1
0
0.3500 V
0
1
0
0
1
1
0
1
1
1
1
0
1
0
1
0
1
0.0375 V
1
1
1.1875 V
1
0
1
0
1
1
1
1
1
0
0.0000 V
1
1
0
1
0
0.3375 V
0
0
1
0
0.8250 V
0
0
0
0
1
0.2875 V
1
1
0.5250 V
Dual Mode Region
1
0
0
1
0.2375 V
1
1
0
0
0
0
0
0
0.4750 V
1
0.0625 V
1
DPRSTP*
0
1
0
0
0
DRAW
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0.4625 V
0
SAMSUNG
0
1
0
1
1
0.0750 V
1
1
0
1
0
1
1
1
1
0
0
1
1
1
0
1
1
0
1
1.3625 V
1.4875 V
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
0
1
0
Deeper Sleep/Extended Deeper Sleep
1
0
0.6875 V
0
0
1
0.0875 V
0
0
1
0
1.1125 V
1
0
0
0
1
1
0
Voltage
0
0
0
1
1
0.6375 V
1
0
0
0
1
0
1
1
1
1
0
1.2625 V
1
0.3125 V
0
0
0
1
0
0
0
0
0.7875 V
1
0
1
0.4500 V
0
1
0
0
1
0
0.8500 V
0.0250 V
0
1
1
1
0
0 or 1
PSI2*
1
0
1
1
0
1
0.0500 V
1
0
0.5875 V
0
1
0
1
0
0.6500 V
1
0.8375 V
1
1
0
0
1
1
1
0.1375 V
1
0.0000 V
1
C
0
4
0
TITLE
1
1
0
1
1
IMVP-6
0
1
1
1
0
0
1
1
1
0.2750 V
1
0
1.0750 V
1
0
1.0375 V
1
0.0125 V
Deeper Slp
1
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1.4500 V
0
0
0
0
1
0
D
0
0
0
1
0
0
1
0
1
1
0
0
0.4000 V
1
1
0
0.5750 V
1
EXCEPT AS AUTHORIZED BY SAMSUNG.
0
0.3250 V
0
0.3000 V
0.4375 V0
1
1
1
1
0
1
0 1
1
0
0.7000 V
1
0
1
0
0
0.1125 V
1.2750 V
0
1
1.4750 V
1
1
1
1.4000 V
1
0.3625 V
0
0
1
1
1
1
1
1
0
0
1
0.7375 V
0.6250 V
0
0
0
Active Mode
0
1
0
C
0
0.0000 V
1
0
1
of the first GTLREF0 pin with Zo=55ohm trace.
0
0
1
VID(6:0)
1
1
1
0
0
1
0
1
0
0
CHECK
0
1.3250 V
PSI2*
0
1
0
1.0500 V
1.4125 V
1
1
GTLREF : Keep the Voltage divider within 0.5"
1
0
1
0.9375 V
1
1
1
1.2875 V
1
trace shorter than 1/2" to their respective Banias socket pins.
0
1
1
1
1
0
1
0.7750 V
1
0
1.2125 V
0.6750 V
0
0
1
1
1.0875 V
0
1
1
Active/Deeper Sleep
1
PAGE
0
1
0
1
1
1
1
0
0
0
0
1
01
0.4250 V
1
1
1
1
0
1.2375 V
1
0
0
0.7625 V
0
0
0
0
1
0
0
1
0
0.3875 V
1
1
0
0.0000 V
0
0
1
1
0
1
0
1
0
B
D
PROPRIETARY INFORMATION THAT IS
0
0
1
0
1
1.1500 V
0
1 1
0
1.0125 V
1
1
1.4375 V
1
0
0
0
1
3
0.5625 V
1
0
1.0000 V
1
0
0
1
1
0
1.0250 V
0
1
0
0
1
1
1
1
0
1
1
0
0.9875 V
1
0
1
0
1.3875 V
1
0
Voltage
0.0000 V
1
1
1
1
1
1
0.8000 V
1
1
0
0
1
1
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
100
1
1
0
0
1
1.1000 V
0
1.1250 V
0
0
1
1
0
1
1
0
1.3750 V
1
1
0
1
1
0
1
0
1
0
0.7500 V
1
0
0
1
0
0.9625 V
0
1
1
1
0
1
0
1
0
1
1
SAMSUNG PROPRIETARY
0
0
0
0
0
0
0
0
0
A
1
0
Dual Mode Region
1
0
0
1
0
1
1
0
0
1
0.0000 V
1
1
PART NO.
0
1
0
0
1
1
0
1
1
1
0
COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm)
0
0
1
1
1
0 or 1
0.1250 V
1
0
1
1
LAST EDIT
1
1
1
0
0
1
1.2500 V
0
0
0
1
0
0
0
0
0
1
1
0
1
1
0
1
1
0
0
0.9750 V
0
0
0
1
0
0
0
1
0
0
CPU Core Voltage Table
1
0
from each of the VCC/VSS test point vias.
0
1
0
0.8625 V
1
1
DPRSTP*
0.2125 V
0.6125 V
0
1
0
1
0
0
0
0
1
1
VID(6:0)
0
0
0
1
1
0.6625 V
0
0
0
1 0
0
1
0.4125 V
0.0000 V
0
0
1.1625 V
1
0
1
0
1
0
0
1
1
1
1
0
0
0
1
4
1
0
0
0
1
1
THIS DOCUMENT CONTAINS CONFIDENTIAL
0
1
0
1
0
1
0
0
0
1
1
0
1
0
0
1
1
1
GND test points within 100mil of the VCC/VSSsense at the end of the line.
1
1
0
0
0
0
1
0
0
1
0
Voltage
1
1
1
1
1
0
1
VID(6:0)
0
0.8875 V
1
1
0
0
0.1000 V
0.8750 V
0
1
1
0
0
0.1750 V
1
1
1
1
1.2000 V
1
0.9000 V
1
0
1
1
0
1
1
1
0
ELECTRONICS
0
0
1
0
0
0.2000 V
1
D:/users/mobile64/mentor/r519/pr_re1.1_0603
0.1875 V
1
1
0
DPRSLPVR
0
1
0
1.3375 V
1
0
0
1
0.9500 V
1
0
0.9250 V
1
1
1
1
1
0
1.4250 V
0
0
1
1
1.3500 V
1
0
SY.KIM
HK.PARK
H.J.KIM
undefined
9/23/2008
PR
1.2
June 03, 2009 16:14:25 PM
BA41-
10 49
BONN-L
CPU
PENRYN (2/3)
1
P1.05V
R672
1%
27.4
100nF
C681
10V
56
R655
nostuff
R643
2K
P1.5V
1%
P1.05V
25V
C50
10nF
49-B411-C4,43-A4
35-C1
R74
54.9
10V
C680
100nF
6
1%
27.4
1%
R646
1%
R673
54.9
10V
C667
100nF
1%
54.9
nostuff
R645
1%
R644
1K
10V
3
R662
56
C657
100nF
P1.05V
1%
10V
C682
100nF
R72
54.9
P1.05V
100nF
C666
10V
nostuff
EC512
220uF
2.5V
AD
0
R661
2
5
C49
10000nF
6.3V
11-B4,43-A449-B4
0
4
100nF
C668
10V
R73
54.9
1%
VSSSENSE
P1.05V
R75
54.9
J21
VCCP_8
M21
VCCP_9
AF7
VCCSENSE
VID_0
AD6
VID_1
AF5
VID_2
AE5
VID_3
AF4
VID_4
AE3
VID_5
AF3
VID_6
AE2
AE7
VCCP_12
V21
VCCP_13
W21
VCCP_14
V6
VCCP_15
G21
VCCP_16
J6
VCCP_2
M6
VCCP_3
N6
VCCP_4
T6
VCCP_5
R6
VCCP_6
K21
VCCP_7
C7
THERMTRIP#
THRMDA
A24
THRMDC
B25
AB5
TMS
AB6
TRST#
B26
VCCA_1
C26
VCCA_2
K6
VCCP_1
N21
VCCP_10
T21
VCCP_11
R21
AA6
TDI
AB3
TDO
C23
TEST1
TEST2
D25
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
M4
RSVD_2
N5
RSVD_3
T2
RSVD_4
V3
RSVD_5
B2
RSVD_6
D2
RSVD_7
D22
RSVD_8
D3
RSVD_9
F6
D7
SLP#
AC5
TCK
DBR#
C20
E5
DPRSTP#
B5
DPSLP#
D24
DPWR#
AD26
GTLREF
PRDY#
AC2
PREQ#
AC1
D21
PROCHOT#
AE6
PSI#
D6
PWRGOOD
RSVD_1
BPM2#
AD1
BPM3#
AC4
BSEL0
B22
BSEL1
B23
BSEL2
C21
R26
COMP0
U26
COMP1
COMP2
AA1
Y1
COMP3
0143854500|bga_479p_sock
CPU1-3
PENRYN
BCLK0
A22
BCLK1
A21
BPM0#
AD4
BPM1#
AD3
CPU1_TDI
CPU1_TMS
ITP3_DBRESET#
CPU1_PROCHOT#_MN
CPU1_COMP3_MN
CPU1_COMP1_MN
CPU1_COMP2_MN
CPU1_COMP0_MN
CPU1_GTLREF_MN
CPU1_TRST#
CPU1_THRMTRIP#
CPU1_TCK
CPU1_TDI
CPU1_TMS
CPU1_TRST#
CPU1_VID(6:0)
CLK0_HCLK0
CLK0_HCLK0#
CPU1_PWRGDCPU
CPU1_DPSLP#
CPU1_SLP#
CPU1_VSSSENSE
CPU1_DPRSTP#
CPU2_THERMDA
CPU2_THERMDC
CPU1_DPWR#
CPU1_PSI#
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
CPU1_VCCSENSE
CPU1_TCK
Samsung
Samsung
Samsung
Confidential
Confidential
Confidential
4 / 4
EXCEPT AS AUTHORIZED BY SAMSUNG.
PAGE
REV
DRAW
PART NO.
TITLE
LAST EDIT
DEV. STEP
A
ELECTRONICS
MODULE CODE
CHECK
C
DATE
A
C
OF
1
APPROVAL
B B
PENRYN (3/3)
CPU
BONN-L
4911
BA41-
June 03, 2009 16:14:25 PM
1.2
PR
9/23/2008
undefined
H.J.KIM
HK.PARK
SY.KIM
4
D
3
PROPRIETARY INFORMATION THAT IS
4
2
SAMSUNG PROPRIETARY
1
Prodlizer & Cbulk common used(Socket inside)
SAMSUNG ELECTRONICS CO’S PROPERTY.
D
SAMSUNG
3
2
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
THIS DOCUMENT CONTAINS CONFIDENTIAL
C71
10000nF-X5R
D:/users/mobile64/mentor/r519/pr_re1.1_0603
10000nF-X5R
C67
6.3V
6.3V
10000nF-X5R
C68
6.3V
6.3V
C66
10000nF-X5R
10000nF-X5R
C76
6.3V
6.3V
C75
10000nF-X5R
10000nF-X5R
C65
6.3V
6.3V
C60
10000nF-X5R
10000nF-X5R
C62
6.3V
6.3V
C74
10000nF-X5R
10000nF-X5R
C59
6.3V
6.3V
C61
10000nF-X5R
10000nF-X5R
C73
6.3V
6.3V
C72
10000nF-X5R
10000nF-X5R
C70
6.3V
10%
CPU_CORE
10%
6.3V
C69
10000nF-X5R
F11
VSS_99
CPU_CORE
CPU_CORE
D8
VSS_89
A8
VSS_9
E11
VSS_90
E14
VSS_91
E16
VSS_92
VSS_93
E19
E21
VSS_94
E24
VSS_95
E3
VSS_96
E6
VSS_97
VSS_98
E8
VSS_79
A4
VSS_8
C8
VSS_80
D1
VSS_81
D11
VSS_82
D13
VSS_83
D16
VSS_84
D19
VSS_85
D23
VSS_86
D26
VSS_87
D4
VSS_88
A25
VSS_7
B6
VSS_70
B8
VSS_71
C11
VSS_72
C14
VSS_73
C16
VSS_74
C19
VSS_75
C2
VSS_76
C22
VSS_77
C25
VSS_78
C5
A23
VSS_6
AF21
VSS_60
AF25
VSS_61
AF6
VSS_62
AF8
VSS_63
VSS_64
B11
B13
VSS_65
VSS_66
B16
B19
VSS_67
B21
VSS_68
B24
VSS_69
VSS_5
AE19
VSS_50
AE23
VSS_51
AE26
VSS_52
AE4
VSS_53
AE8
VSS_54
AF11
VSS_55
AF13
VSS_56
AF16
VSS_57
AF19
VSS_58
AF2
VSS_59
AD2
VSS_40
AD22
VSS_41
AB23
VSS_42
AD25
VSS_43
AD5
VSS_44
AD8
VSS_45
AE1
VSS_46
AE11
VSS_47
AE14
VSS_48
AE16
VSS_49
A2
AC19
VSS_30
AC21
VSS_31
AC24
VSS_32
AC3
VSS_33
AC6
VSS_34
VSS_35
AC8
AD11
VSS_36
AD13
VSS_37
AD16
VSS_38
AD19
VSS_39
A19
VSS_4
VSS_20
AB13
VSS_21
AB16
VSS_22
AB19
VSS_23
AB26
VSS_24
AB4
VSS_25
AB8
VSS_26
AC11
VSS_27
AC14
VSS_28
AC16
VSS_29
A16
VSS_3
W4
VSS_159
AA25
VSS_16
Y21
VSS_160
Y24
VSS_161
Y3
VSS_162
Y6
VSS_163
AA5
VSS_17
AA8
VSS_18
AB1
VSS_19
A14
VSS_2
AB11
U24
VSS_149
AA22
VSS_15
U3
VSS_150
U6
VSS_151
V2
VSS_152
VSS_153
V22
V25
VSS_154
V5
VSS_155
W1
VSS_156
W23
VSS_157
W26
VSS_158
VSS_139
AA2
VSS_14
R2
VSS_140
R22
VSS_141
R25
VSS_142
R5
VSS_143
T1
VSS_144
T23
VSS_145
T26
VSS_146
T4
VSS_147
U21
VSS_148
AA19
VSS_13
M25
VSS_130M5VSS_131N1VSS_132
N23
VSS_133
N26
VSS_134N4VSS_135
P21
VSS_136
P24
VSS_137P3VSS_138
P6
AA16
VSS_12
K1
VSS_120
K23
VSS_121
K26
VSS_122K4VSS_123
VSS_124
L21
L24
VSS_125
VSS_126
L3
L6
VSS_127M2VSS_128
M22
VSS_129
VSS_11
G26
VSS_110
G4
VSS_111
H21
VSS_112
H24
VSS_113
H3
VSS_114
H6
VSS_115
J2
VSS_116
J22
VSS_117
J25
VSS_118
J5
VSS_119
F13
VSS_100
F16
VSS_101
F19
VSS_102
F2
VSS_103
F22
VSS_104
F25
VSS_105
F5
VSS_106
F8
VSS_107
G1
VSS_108
G23
VSS_109
AA14
E9
VCC_91
F10
VCC_92
F12
VCC_93
F14
VCC_94
F15
VCC_95
VCC_96
F17
F18
VCC_97
F20
VCC_98
F7
VCC_99
A11
VSS_1
AA11
VSS_10
VCC_81
D9
VCC_82
E10
VCC_83
E12
VCC_84
E13
VCC_85
E15
VCC_86
E17
VCC_87
E18
VCC_88
E20
VCC_89
A9
VCC_9
E7
VCC_90
C15
VCC_72
C17
VCC_73
C18
VCC_74
C9
VCC_75
D10
VCC_76
D12
VCC_77
D14
VCC_78
D15
VCC_79
A7
VCC_8
D17
VCC_80
D18
B14
VCC_62
B15
VCC_63
B17
VCC_64
B18
VCC_65
B20
VCC_66
VCC_67
B7
B9
VCC_68
C10
VCC_69
A20
VCC_7
C12
VCC_70
C13
VCC_71
VCC_52
AF12
VCC_53
AF14
VCC_54
AF15
VCC_55
AF17
VCC_56
AF18
VCC_57
AF20
VCC_58
AF9
VCC_59
A18
VCC_6
B10
VCC_60
B12
VCC_61
AD9
VCC_43
AE10
VCC_44
AE12
VCC_45
AE13
VCC_46
AE15
VCC_47
AE17
VCC_48
AE18
VCC_49
A17
VCC_5
AE20
VCC_50
AE9
VCC_51
AF10
AC18
VCC_33
AC7
VCC_34
AC9
VCC_35
AD10
VCC_36
AD12
VCC_37
VCC_38
AD14
AD15
VCC_39
A15
VCC_4
AD17
VCC_40
AD18
VCC_41
AD7
VCC_42
VCC_23
AB18
VCC_24
AB20
VCC_25
AB7
VCC_26
AB9
VCC_27
AC10
VCC_28
AC12
VCC_29
A13
VCC_3
AC13
VCC_30
AC15
VCC_31
AC17
VCC_32
AA17
VCC_14
AA18
VCC_15
AA20
VCC_16
AA7
VCC_17
AA9
VCC_18
AB10
VCC_19
A12
VCC_2
AB12
VCC_20
AB14
VCC_21
AB15
VCC_22
AB17
VCC_1
A10
AA10
VCC_10
F9
VCC_100
AA12
VCC_11
AA13
VCC_12
AA15
VCC_13
10-C4,43-A4
49-B4
0143854500|bga_479p_sock
CPU1-4
PENRYN
49-B4
10-C4,43-A4
R670
100
1%
100 1%
CPU1_VCCSENSE
CPU1_VSSSENSE
R671
Samsung
Samsung
Samsung
Confidential
Confidential
Confidential
100 MHz
DEV. STEP
VDD_CPUVDD_CPU_IO
PART NO.
0
B
CLK REQ F
0
C
4
VDD_48
GMCH
VDD_PLL3
3
1
Pin 20/21
CLK REQ B
1
FSA
BSEL1
1
BSEL0
FSC
0
0
0
1
200 MHz
DATE
HIGH
1
SAMSUNG
MINI CARD
1
PEG_CLK/PEG_CLK#
SAMSUNG ELECTRONICS CO’S PROPERTY.
500mils of CK-505
BSEL2
VDD_SRC
1
1
2
SATA
D
27M & 27M_SS
166 MHz
REV
EXP3_CLKREQ#
VDD_IO
CLK REQ A
SAMSUNG PROPRIETARY
CK505M
CLK REQ E
0
0
VDD_PCI
DRAW
DOT_96/DOT_96#
PROPRIETARY INFORMATION THAT IS
Place 14.318MHz within
1
SRC2
1
PAGE
ELECTRONICS
333 MHz
1
3
SRC4
FSB
A
VDD_PLL3_IO
0
DEVICE
Pin 24/25
HOST CLK
2
SL : 1205-003533
VDD_REF
1
VDD_SRC_IO
THIS DOCUMENT CONTAINS CONFIDENTIAL
C
LOW
EXCEPT AS AUTHORIZED BY SAMSUNG.
0
B
IDT : 1205-003159
SRC6
CLK REQ
TITLE
APPROVAL
LAST EDIT
SEL_LCDCLK*
0
4912
BA41-
June 03, 2009 16:14:25 PM
1.2
PR
9/23/2008
undefined
H.J.KIM
HK.PARK
SY.KIM
4
SRC_0/SRC_0#
1
MODULE CODE
400 MHz
0
SRC PORT
This part is 64pin QFN package.
1
133 MHz
266 MHz
A
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
D
OF
RSVD
SRC8
CHECK
0
10V
CK_Clock_505M
D:/users/mobile64/mentor/r519/pr_re1.1_0603
MAIN_CLOCK_CIRCUIT
BONN-L
10V
C721
100nF
B517
BLM18PG181SN1
100nF
C697
0.033nF
5%
50V
C145
10-C4,13-A3
14-A1,48-B2
P1.5V
25-A4
C146
50V
32-C4
6.3V
0.018nF
50V
nostuff
C691
10000nF-X5R
18-B4,19-B4 22-B4,48-B4
0.022nF
C142
14-C1
34-B4
13-B1
32-C4,49-C4
14-C1
B518
BLM18PG181SN1
R87
2.2K
22-C3,48-B2
nostuff
22-C1
C695
10000nF-X5R
6.3V
1
VSS_SRC1
30
36
VSS_SRC2
VSS_SRC3
49
XTAL_IN
3
2
XTAL_OUT
14-B1
VDD_REF
4
VDD_SRC
46
VDD_SRC_IO1
33
VDD_SRC_IO2
43
VDD_SRC_IO3
52
18
VSS_48
VSS_CPU
59
VSS_IO
22
VSS_PCI
15
VSS_PLL3
26
VSS_REF
SRC9
37
38
SRC9#
65
THERM_GND
USB_FS_A
17
VDD_48
16
VDD_CPU
62
VDD_CPU_IO
56
VDD_IO
19
VDD_PCI
9
VDD_PLL3
23
27
VDD_PLL3_IO
SRC2#
29
SRC3#_CLKREQD#
32
SRC3_CLKREQC#
31
34
SRC4
35
SRC4#
SRC6
48
SRC6#
47
SRC7#_CLKREQE#
50
SRC7_CLKREQF#
51
SRC8#_ITP#
53
SRC8_ITP
54
13
REF_FS_C_TEST_SEL
5
SCL
7
SDA
6
SRC0#_DOT96#
21
SRC0_DOT96
20
SRC10
41
SRC10#
42
SRC11#_CLKREQG#
39
SRC11_CLKREQH#
40
SRC2
28
FSB_TESTMODE
64
LCDCLK#_27M_SS
25
LCDCLK_27M
24
55
NC
PCIF_5_ITP_EN
14
PCISTOP#
45
PCI_0_CLKREQ_A#
8
PCI_1_CLKREQ_B#
10
PCI_2
11
PCI_3
12
PCI_4_SEL_LCDCLK#
U5
CLKPWRGD_PWRDN#
63
CPU0
61
CPU0#
60
CPU1_MCH
58
CPU1_MCH#
57
CPUSTOP#
44
nostuff
SLG8SP513
1205-003156
1%
6.3V
10000nF-X5R
C692
R91
10K
R96
nostuff
5%22
6.3V
10000nF-X5R
C694
20-B1
475
0.018nF
C147
50V
1%
R94
C693
100nF
10V
R95
475
14-C1
1%
C144
50V
5%
0.033nF
R88
33
10V
100nF
C698
22-B3,49-C3
1%
10K
R89
10-D4
33
R86
22-B3
R92
10K
1%
21-C2
C717
100nF
10V
6.3V
10000nF-X5R
C696
R90
22 5%
P3.3V
30-B3,48-B2
5%
22-A3
30-A4
22
R93
32-C4
22-C1
14-C1
10V
C720
100nF
13-B1
100nF
C718
14-B1
10V
C719
10000nF-X5R
6.3V
R97
33
22-A3
10-D4
20-B1
18-B4,19-B4 22-B4,48-D4
10-C4,13-A3
22-C3,48-B2
1
2
10-C4,13-A3
31-B4
2801-004667
14.31818MHz
Y2
0.033nF
5%
50V
C143
30-A4
CLK3_PCLKICH_R_MN
CLK3_DBGLPC_R_MN
CLK3_PCLKMICOM_R_MN
CLK3_VDD_SRC_IO_MN
MCH3_CLKREQ#_R_MN
CHP3_SATACLKREQ#_R_MN
CLK3_VDD_REF_MN
CLK1_DREFCLK#
CLK1_MINIPCIE#
CLK1_DREFSSCLK
CLK1_DREFSSCLK#
CLK3_USB48_R_MN
CLK3_ICH14_R_MN
CLK1_MCH3GPLL
CHP3_SATACLKREQ#
CLK3_PCLKMICOM
MCH3_CLKREQ#
CLK3_DBGLPC
MIN3_CLKREQ#
CLK1_PCIEICH
CLK1_PCIELOM
LOM3_CLKREQ#
CLK1_DREFCLK
CLK0_HCLK0
CLK3_USB48
SMB3_CLK
SMB3_DATA
CHP3_CPUSTP#
CHP3_PCISTP#
CPU1_BSEL2
CPU1_BSEL0
CLK3_ICH14
CLK3_PCLKICH
CLK3_FM48
CLK1_PCIEICH#
CLK1_PCIELOM#
CLK1_MINIPCIE
CLK1_MCH3GPLL#
CLK1_SATA
CLK1_SATA#
CLK3_PWRGD
CPU1_BSEL1
CLK0_HCLK1#
CLK0_HCLK1
CLK0_HCLK0#
Samsung
Samsung
Samsung
Confidential
Confidential
Confidential
1 OF 5
VTT
HOST DATA BUS
VTTLF
NC
HOST CONTROL
HOST ADDRESS BUS
VCC CORE
CFG
CFG(16)
4
B
ME Crypto no confidentiality
PEG Reversal (def.)
LAST EDIT
CHECK
DRAW
(def. : default Option)
SAMSUNG
DEV. STEP
2
Enabled (def.)
*POCAFEB-12 Only (Remove in MP Model)
APPROVAL
3
Dynamic ODT Disabled
DMIx2
REV
CFG(19)
D
4
1
ELECTRONICS
PCIE Loop Back Enable
SDVO and PCIE X1
D
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
Only(def.)
DMI Lane Normal (def.)
DATE
CFG(7)
1
iTPM Host Interface Disable (def.)
C
CFG#
PCIE Loop Back Disable(def)
Current Setting
ME Crypto confidentiality (def.)
1608
TITLE
Normal
CFG(5)
High
PART NO.
CFG(6)
SDVO or PCIE X1
PAGE
Dynamic ODT
3
iTPM option
EXCEPT AS AUTHORIZED BY SAMSUNG.
A
B
THIS DOCUMENT CONTAINS CONFIDENTIAL
Low
C
DMI Lane Reversal
CFG(20)
2
SAMSUNG PROPRIETARY
OF
iTPM Host Interface Enable
CFG(10)
A
CFG(9)
SAMSUNG ELECTRONICS CO’S PROPERTY.
DMIx4 (def.)
Simultaneously
MODULE CODE
PROPRIETARY INFORMATION THAT IS
D:/users/mobile64/mentor/r519/pr_re1.1_0603
CANTIGA (1/5)
MCH_CANTIGA_GM_DDR2
BONN-L
4913
BA41-
June 03, 2009 16:14:25 PM
1.2
PR
9/23/2008
undefined
H.J.KIM
HK.PARK
SY.KIM
C599
10000nF-X5R
6.3V
50
60
16
R535
221
1%
18
15
20
3
31
23
P1.05V
10000nF-X5R
C556
1000nF-X5R
nostuff
6.3V
C554
47
6.3V
29
0
7
14
1%
R549
1K
35
36
16V
4
C540
470nF
31
19
30
56
32
23
4
8
52
T13
VTT_4T2VTT_5T5VTT_6T6VTT_7T7VTT_8T8VTT_9
3
VTT_17U5VTT_18U6VTT_19
T11
VTT_2
U7
VTT_20U8VTT_21U9VTT_22
VTT_23V1VTT_24V2VTT_25
V3
T12
VTT_3
AB2
VTTLF_2
L1
VTTLF_3
T10
VTT_1
T9
VTT_10U1VTT_11
U10
VTT_12
U11
VTT_13
U12
VTT_14
U13
VTT_15U2VTT_16
U3
VCC_NCTF_40
W30
VCC_NCTF_41
W32
VCC_NCTF_42
Y29
VCC_NCTF_43
Y30
VCC_NCTF_44
Y32
VCC_NCTF_5
AC29
VCC_NCTF_6
AC30
VCC_NCTF_7
AC32
VCC_NCTF_8
AE29
VCC_NCTF_9
AE30
A8
VTTLF_1
AL29
VCC_NCTF_31
AL30
VCC_NCTF_32
AL32
VCC_NCTF_33
AM30
VCC_NCTF_34
AM32
VCC_NCTF_35
U30
VCC_NCTF_36
U32
VCC_NCTF_37
V29
VCC_NCTF_38
V30
VCC_NCTF_39
W29
VCC_NCTF_4
AB30
AK23
VCC_NCTF_21
AK24
VCC_NCTF_22
AK25
VCC_NCTF_23
AK26
VCC_NCTF_24
AK28
VCC_NCTF_25
AK29
VCC_NCTF_26
AK30
VCC_NCTF_27
AK32
VCC_NCTF_28
AL26
VCC_NCTF_29
AL28
VCC_NCTF_3
AA32
VCC_NCTF_30
VCC_NCTF_11
AF30
VCC_NCTF_12
AG29
VCC_NCTF_13
AG30
VCC_NCTF_14
AG32
VCC_NCTF_15
AH29
VCC_NCTF_16
AH30
VCC_NCTF_17
AH32
VCC_NCTF_18
AJ29
VCC_NCTF_19
AJ32
VCC_NCTF_2
AA30
VCC_NCTF_20
W33
VCC_34
Y33
VCC_35
Y34
AB34
VCC_4
AC26
VCC_5
AC28
VCC_6
AC33
VCC_7
AC34
VCC_8
AE26
VCC_9
VCC_NCTF_1
AA29
VCC_NCTF_10
AE32
AJ23
VCC_24
AJ26
VCC_25
AJ33
VCC_26
AK33
VCC_27
AM33
VCC_28
T32
VCC_29
U33
AA34
VCC_3
VCC_30
U34
VCC_31
V33
VCC_32
V34
VCC_33
VCC_14
AF33
VCC_15
AG24
VCC_16
AG25
VCC_17
AG26
VCC_18
AG33
VCC_19
AG34
AA33
VCC_2
VCC_20
AH23
VCC_21
AH25
VCC_22
AH28
VCC_23
B14
H_RS#_0
B6
H_RS#_1
F12
H_RS#_2
C8
C5
H_SWING
H_TRDY#
C9
AA28
VCC_1
AE33
VCC_10
AF23
VCC_11
AF25
VCC_12
AF28
VCC_13
AA6
H_DSTBP#_3
AE5
B11
H_DVREF
H_HIT#
H9
H_HITM#
E12
H_LOCK#
H11
E3
H_RCOMP
H_REQ#_0
B15
H_REQ#_1
K13
H_REQ#_2
F13
H_REQ#_3
B13
H_REQ#_4
H_DINV#_2
Y13
H_DINV#_3
Y1
H_DPWR#
J11
H_DRDY#
F9
H_DSTBN#_0
L10
H_DSTBN#_1
M7
H_DSTBN#_2
AA5
H_DSTBN#_3
AE6
H_DSTBP#_0
L9
H_DSTBP#_1
M8
H_DSTBP#_2
AE11
H_D#_61
AE8
H_D#_62
AG2
H_D#_63
AD6
H_D#_7
F6
H_D#_8
D4
H_D#_9
H3
H_DBSY#
B10
H_DEFER#
E9
H_DINV#_0
J8
H_DINV#_1
L3
AA2
H_D#_51
AD8
H_D#_52
AA3
H_D#_53
AD3
H_D#_54
AD7
H_D#_55
AE14
H_D#_56
AF3
H_D#_57
AC1
H_D#_58
AE3
H_D#_59
AC3
H_D#_6
H2
H_D#_60
H_D#_41
Y9
H_D#_42
AA13
H_D#_43
AA9
H_D#_44
AA11
H_D#_45
AD11
H_D#_46
AD10
H_D#_47
AD13
H_D#_48
AE12
H_D#_49
AE9
H_D#_5
H6
H_D#_50
M3
H_D#_32
Y3
H_D#_33
AD14
H_D#_34
Y6
H_D#_35
Y10
H_D#_36
Y12
H_D#_37
Y14
H_D#_38
Y7
H_D#_39
W2
H_D#_4
G2
H_D#_40
AA8
M5
H_D#_22
J3
H_D#_23
N2
H_D#_24
R1
H_D#_25
N5
H_D#_26
N6
H_D#_27
P13
H_D#_28
N8
H_D#_29
L7
H_D#_3
E6
H_D#_30
N10
H_D#_31
H_D#_12
J1
H_D#_13
J2
H_D#_14
N12
H_D#_15
J6
H_D#_16
P2
H_D#_17
L2
H_D#_18
R2
H_D#_19
N9
H_D#_2
F8
H_D#_20
L6
H_D#_21
G17
A11
H_AVREF
H_BNR#
A9
H_BPRI#
F11
H_BREQ#
G12
H_CPURST#
C12
H_CPUSLP#
E11
H_D#_0
F2
H_D#_1
G8
H_D#_10
M9
H_D#_11
M11
F21
H_A#_34
K21
H_A#_35
L20
H_A#_4
C15
H_A#_5
F16
H_A#_6
H13
H_A#_7
C18
H_A#_8
M16
H_A#_9
J13
H_ADS#
H12
H_ADSTB#_0
B16
H_ADSTB#_1
H_A#_24
A17
H_A#_25
B17
H_A#_26
L16
H_A#_27
C21
H_A#_28
J17
H_A#_29
H20
H_A#_3
A14
H_A#_30
B18
H_A#_31
K17
H_A#_32
B20
H_A#_33
M13
H_A#_14
E17
H_A#_15
P17
H_A#_16
F17
H_A#_17
G20
H_A#_18
B19
H_A#_19
J16
H_A#_20
E20
H_A#_21
H16
H_A#_22
J20
H_A#_23
L17
P24
CFG_5
C25
CFG_6
N24
CFG_7
M24
CFG_8
E21
CFG_9
C23
AH7
HPLL_CLK
HPLL_CLK#
AH6
H_A#_10
P16
H_A#_11
R16
H_A#_12
N17
H_A#_13
CFG_13
T21
CFG_14
R20
CFG_15
M20
CFG_16
L21
CFG_17
H21
CFG_18
P29
CFG_19
R28
CFG_2
P25
CFG_20
T28
CFG_3
P20
CFG_4
GL40
U3-1
CFG_0
T25
CFG_1
R25
CFG_10
C24
CFG_11
N21
CFG_12
P21
0904-002489
10V
26
100nF
C32
nostuff
EC501
220uF
2.5V
AD
AD
2.5V
220uF
EC508
470nF
C539
nostuff
470nF
C35
16V
33
16V
53
14
39
40
1
2
41
38
25
7
8
nostuff
27
46
2.2K
R586
3
6
63
R536
24.9 1%
42
43
2K
R547
44
22
55
1%
25
P1.05V
0
20
10V
C597
100nF
C645
100nF
10V
9
57
51
59
17
22
12
58
9
10V
100nF
C647
6
12
19
54
5
27
28
16
21
37
1511
32
48
10
45
1%
17
R43
100
2
13
5
28
13
10
18
P1.05V
P1.05V
10000nF-X5R
C555
6.3V
11
33
34
61
30
21
24
62
34
29
24
1
P1.05V
49
22-D2
4
26
MCH1_H_RCOMP_MN
MCH1_VTTLF2_MN
MCH1_CFG6_MN
35
CPU1_LOCK#
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
CPU1_TRDY#
CPU1_REQ#(4:0)
CPU1_DPWR#
MCH1_HVREF
MCH1_VTTLF1_MN
MCH1_VTTLF3_MN
MCH1_HXSWING
MCH1_HVREF
CPU1_BSEL0
CPU1_BSEL1
CPU1_BSEL2
CPU1_D#(63:0)
CPU1_A#(35:3)
CPU1_ADS#
CPU1_ADSTB0#
CPU1_ADSTB1#
CPU1_BNR#
CPU1_BPRI#
CPU1_BREQ#
CPU1_SLP#
CPU1_CPURST#
CLK0_HCLK1#
CLK0_HCLK1
CPU1_DBSY#
CPU1_DEFER#
CPU1_DBI0#
MCH1_HXSWING
CPU1_DBI1#
CPU1_DBI2#
CPU1_DBI3#
CPU1_DRDY#
CPU1_DSTBN0#
CPU1_DSTBN1#
CPU1_DSTBN2#
CPU1_DSTBN3#
CPU1_DSTBP0#
CPU1_DSTBP1#
CPU1_DSTBP2#
CPU1_DSTBP3#
CPU1_HIT#
CPU1_HITM#
Samsung
Samsung
Samsung
Confidential
Confidential
Confidential
2 OF 5
LVDSHDA
NC RSVD
GFX VCC NCTF
GFX VCC NCTF
GFX VCC
TV VGA
PCIE GFX
PCIE GFX
DMICLKMEPMMISC
PROPRIETARY INFORMATION THAT IS
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
RSVD11
SAMSUNG ELECTRONICS CO’S PROPERTY.
1
D
RSVD12
RSVD13
For ESD
PART NO.
DRAW
4
CHECK
A
SAMSUNG PROPRIETARY
C
2
470nF->100nF
22uF->10uF
220uF->100uF
PAGE
C
DATE
OF
4
TITLE
LAST EDIT
1.02kohm
3
REV
3
THIS DOCUMENT CONTAINS CONFIDENTIAL
D
1
SY.KIM
HK.PARK
H.J.KIM
undefined
9/23/2008
PR
1.2
June 03, 2009 16:14:25 PM
BA41-
14 49
BONN-L
MCH_CANTIGA_GM_DDR2
CANTIGA (2/5)
D:/users/mobile64/mentor/r519/pr_re1.1_0603
2
EXCEPT AS AUTHORIZED BY SAMSUNG.
ME Debug Port
IGFX_CORE
Default : TV Disable
SAMSUNG
1608
RSVD10
ELECTRONICS
A
B
DEV. STEP
APPROVAL
MODULE CODE
B
10-C4,20-B1
49-C3
1%
150
R578
AE16
VCC_AXG_NCTF_8
AE17
VCC_AXG_NCTF_9
VCC_AXG_NCTF_52
W23
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
W24
W25
VCC_AXG_NCTF_55
W26
VCC_AXG_NCTF_56
W28
VCC_AXG_NCTF_57
Y16
VCC_AXG_NCTF_58
Y17
VCC_AXG_NCTF_59
AC16
VCC_AXG_NCTF_6
Y19
VCC_AXG_NCTF_60
AC17
VCC_AXG_NCTF_7
V23
VCC_AXG_NCTF_43
V24
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
V25
VCC_AXG_NCTF_46
V26
V28
VCC_AXG_NCTF_47
W16
VCC_AXG_NCTF_48
W17
VCC_AXG_NCTF_49
AB19
VCC_AXG_NCTF_5
VCC_AXG_NCTF_50
W19
W20
VCC_AXG_NCTF_51
W21
AM20
VCC_AXG_NCTF_33
AM21
VCC_AXG_NCTF_34
U16
VCC_AXG_NCTF_35
U19
VCC_AXG_NCTF_36
U20
VCC_AXG_NCTF_37
U21
VCC_AXG_NCTF_38
V16
VCC_AXG_NCTF_39
AB17
VCC_AXG_NCTF_4
V17
VCC_AXG_NCTF_40
V19
VCC_AXG_NCTF_41
V21
VCC_AXG_NCTF_42
VCC_AXG_NCTF_23
AK19
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
AK20
AK21
VCC_AXG_NCTF_26
AL16
VCC_AXG_NCTF_27
AL19
VCC_AXG_NCTF_28
AL21
VCC_AXG_NCTF_29
AB16
VCC_AXG_NCTF_3
AM16
VCC_AXG_NCTF_30
AM17
VCC_AXG_NCTF_31
AM19
VCC_AXG_NCTF_32
AG16
VCC_AXG_NCTF_14
AG17
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
AG19
VCC_AXG_NCTF_17
AH16
AH17
VCC_AXG_NCTF_18
AH19
VCC_AXG_NCTF_19
AA19
VCC_AXG_NCTF_2
AJ16
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
AJ19
AK16
VCC_AXG_NCTF_22
AK17
Y26
AA24
VCC_AXG_5
AA25
VCC_AXG_6
AB15
VCC_AXG_7
AB20
VCC_AXG_8
AB23
VCC_AXG_9
AA16
VCC_AXG_NCTF_1
AE19
VCC_AXG_NCTF_10
AF16
VCC_AXG_NCTF_11
AF17
VCC_AXG_NCTF_12
AF19
VCC_AXG_NCTF_13
VCC_AXG_32
T14
VCC_AXG_33
VCC_AXG_34
T16
T17
VCC_AXG_35
VCC_AXG_36
U14
VCC_AXG_37
U15
VCC_AXG_38
V15
VCC_AXG_39
Y15
AA23
VCC_AXG_4
Y21
VCC_AXG_40
VCC_AXG_41
Y24
VCC_AXG_42
AG15
VCC_AXG_23
AG21
VCC_AXG_24
VCC_AXG_25
AH15
VCC_AXG_26
AH20
AJ15
VCC_AXG_27
AJ21
VCC_AXG_28
AL15
VCC_AXG_29
AA21
VCC_AXG_3
VCC_AXG_30
AM14
AM15
VCC_AXG_31
AN14
AC23
VCC_AXG_13
AC24
VCC_AXG_14
AE15
VCC_AXG_15
AE20
VCC_AXG_16
AE21
VCC_AXG_17
AE23
VCC_AXG_18
AE24
VCC_AXG_19
AA20
VCC_AXG_2
AE25
VCC_AXG_20
AF15
VCC_AXG_21
AF20
VCC_AXG_22
B12
F25
TVA_DAC
TVB_DAC
H25
K25
TVC_DAC
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
H24
TV_RTN
AA15
VCC_AXG_1
AB25
VCC_AXG_10
AC20
VCC_AXG_11
AC21
VCC_AXG_12
AH13
RSVD_3
AH9
RSVD_4
AK34
RSVD_5
AL34
RSVD_6
RSVD_7
AM35
RSVD_8
AN35
AY21
RSVD_9
SDVO_CTRLCLK
G36
E36
SDVO_CTRLDATA
THERMTRIP#
T20
TSATN#
BF23
RSVD_13
BG23
RSVD_14
BH18
RSVD_15
RSVD_16
K12
M1
RSVD_17
RSVD_18
M36
N36
RSVD_19
AH12
RSVD_2
R33
RSVD_20
T24
RSVD_21
T33
RSVD_22
U39
PM_DPRSTP#
B7
N33
PM_EXT_TS#_0
PM_EXT_TS#_1
P32
PM_SYNC#
R29
PWROK
AT40
AT11
RSTIN#
AH10
RSVD_1
B2
RSVD_10
B31
RSVD_11
BF18
RSVD_12
PEG_TX_13
AA39
PEG_TX_14
AD42
PEG_TX_15
AD46
PEG_TX_2
M48
PEG_TX_3
M39
PEG_TX_4
M43
R47
PEG_TX_5
PEG_TX_6
N37
PEG_TX_7
T39
U36
PEG_TX_8
PEG_TX_9
M42
PEG_TX#_5
R48
N38
PEG_TX#_6
PEG_TX#_7
T40
PEG_TX#_8
U37
PEG_TX#_9
U40
J42
PEG_TX_0
PEG_TX_1
L46
PEG_TX_10
Y39
Y46
PEG_TX_11
PEG_TX_12
AA36
Y42
PEG_TX#_0
J41
PEG_TX#_1
M46
PEG_TX#_10
Y40
PEG_TX#_11
AA46
PEG_TX#_12
AA37
AA40
PEG_TX#_13
AD43
PEG_TX#_14
PEG_TX#_15
AC46
PEG_TX#_2
M47
M40
PEG_TX#_3
PEG_TX#_4
PEG_RX_13
AD36
PEG_RX_14
AC48
PEG_RX_15
AD40
PEG_RX_2
L43
PEG_RX_3
L41
PEG_RX_4
N40
P47
PEG_RX_5
PEG_RX_6
N43
PEG_RX_7
T42
U42
PEG_RX_8
PEG_RX_9
N41
PEG_RX#_4
PEG_RX#_5
P48
PEG_RX#_6
N44
PEG_RX#_7
T43
PEG_RX#_8
U43
PEG_RX#_9
Y43
H43
PEG_RX_0
PEG_RX_1
J44
PEG_RX_10
W47
PEG_RX_11
Y37
PEG_RX_12
AA42
PEG_COMPO
PEG_RX#_0
H44
PEG_RX#_1
J46
PEG_RX#_10
Y48
PEG_RX#_11
Y36
PEG_RX#_12
AA43
AD37
PEG_RX#_13
AC47
PEG_RX#_14
PEG_RX#_15
AD39
PEG_RX#_2
L44
L40
PEG_RX#_3
F1
NC_42
NC_43
F48
A5
NC_5A6NC_6B4NC_7
B45
NC_8
NC_9
B47
F43
PEG_CLK
PEG_CLK#
E43
PEG_COMPI
T37
T36
BH47
NC_33
BH5
NC_34
BH6
NC_35C3NC_36
C46
NC_37
C48
NC_38D2NC_39
D47
A47
NC_4
NC_40E1NC_41
E48
BG2
NC_23
BG4
NC_24
BG45
BG47
NC_25
NC_26
BG48
NC_27
BH2
NC_28
BH3
NC_29
BH43
A46
NC_3
BH44
NC_30
BH46
NC_31
NC_32
BD1
NC_13
BD48
NC_14
BE2
NC_15
BE47
NC_16
NC_17
BF1
NC_18
BF3
BF46
NC_19
A44
NC_2
NC_20
BF48
NC_21
BG1
NC_22
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
L_DDC_CLK
K33
J33
L_DDC_DATA
M29
L_VDD_EN
A43
NC_1
B48
NC_10
BC1
NC_11
BC48
NC_12
H38
LVDSB_DATA#_2
G37
J37
LVDSB_DATA#_3
LVDSB_DATA_0
B42
LVDSB_DATA_1
G38
LVDSB_DATA_2
F37
K37
LVDSB_DATA_3
C44
LVDS_IBG
LVDS_VBG
B43
E37
LVDS_VREFH
E38
LVDS_VREFL
LVDSA_DATA#_1
E46
G40
LVDSA_DATA#_2
LVDSA_DATA#_3
A40
LVDSA_DATA_0
H48
D45
LVDSA_DATA_1
LVDSA_DATA_2
F40
LVDSA_DATA_3
B40
LVDSB_CLK
A37
B37
LVDSB_CLK#
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
E33
C34
GFX_VR_EN
HDA_BCLK
B28
HDA_RST#
B30
HDA_SDI
B29
C29
HDA_SDO
A28
HDA_SYNC
ICH_SYNC#
H36
C40
LVDSA_CLK
LVDSA_CLK#
C41
LVDSA_DATA#_0
H47
DMI_TXP_2
AH43
DMI_TXP_3
B38
DPLL_REF_CLK
DPLL_REF_CLK#
A38
E41
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
F41
DPRSLPVR
R32
B33
GFX_VID_0
GFX_VID_1
B32
G33
GFX_VID_2
F33
GFX_VID_3
GFX_VID_4
DMI_RXP_0
AE40
AE38
DMI_RXP_1
AE48
DMI_RXP_2
AH40
DMI_RXP_3
AE35
DMI_TXN_0
AE43
DMI_TXN_1
AE46
DMI_TXN_2
AH42
DMI_TXN_3
DMI_TXP_0
AD35
AE44
DMI_TXP_1
AF46
CRT_HSYNC
CRT_IRTN
G29
J28
CRT_RED
E29
CRT_TVO_IREF
L29
CRT_VSYNC
DDPC_CTRLCLK
N28
DDPC_CTRLDATA
M28
AE41
DMI_RXN_0
AE37
DMI_RXN_1
AE47
DMI_RXN_2
AH39
DMI_RXN_3
CLKREQ#
K36
AH37
CL_CLK
CL_DATA
AH36
CL_PWROK
AN36
CL_RST#
AJ35
CL_VREF
AH34
E28
CRT_BLUE
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
G28
CRT_GREEN
J29
0904-002489
GL40
U3-2
23-D4 11-D335-C1
11-D337-C3
7.5K
R770
1%
20K
R771
1%
4.7K
R585
26-B1
27-B4,48-C2
27-C3,48-C3
26-B1
26-B2
1%
27-C4,48-C3
26-C2,49-D4
R539
100
P1.05V
27-B4,48-D2
1%49.9
R639
10K
R636
1%
P3.3V
75
R583
C588
0.033nF
50V
10000nF
C595
6.3V
12-A1
26-B2
26-A1
21-C1,25-A4
30-B3,32-C334-B3
50V
0.033nF
C589
1%
R579
40.2
12-A1
26-B1
26-B1
26-B1
1%
R588
10K
R640
26-B2
R590
1K
1%
499
1%
48-B322-B3,34-C4
P3.3V
C598
10000nF-X5R
6.3V
EC504
220uF
2.5V
AD
26-C4,48-B2
26-A1,49-D4
0
R589
10V
100nF
C596
100nF
C553
10V
100nF
C601
10V
1%
R582
40.2
P3.3V
27-C3,48-C4
27-C3,48-D4
1%
R584
75
P3.3V
P1.05V_PEG
26-B2
26-B1
C590
0.033nF
50V
1000nF-X5R
C557
6.3V
26-B2
1%
R48
2.4K
12-A1
P1.05V
26-B2
12-A1
R576
1K
26-A1,49-C3
1%
P1.05V
56
R548
26-B2,48-C4
10K
R637
1%
R577
150
26-A2
R580
75
1%
27-C4,48-C3
1%
1%
R581
150
26-B1
26-B2
LCD1_BDATA0
LCD1_BDATA2
MCH1_COMPIO_R_MN
MCH1_CL_VREF_MN
PLT3_RST#_R_MN
CPU1_THRMTRIP#_R_MN
CPU1_THRMTRIP#
PLT3_RST#
CRT3_RED
CRT3_GREEN
CRT3_BLUE
DMI1_TXN_1
DMI1_TXP_1
DMI1_TXN_2
DMI1_TXP_2
DMI1_TXN_3
DMI1_TXP_3
DMI1_RXN_0
DMI1_RXP_0
DMI1_RXN_1
DMI1_RXP_1
DMI1_RXN_2
DMI1_RXP_2
DMI1_RXN_3
DMI1_RXP_3
CHP3_CL_CLK_0
CHP3_CL_DATA_0
KBC3_PWRGD
CHP3_DPRSLPVR
CLK1_DREFSSCLK#
LCD1_ADATA2
CHP3_PM_SYNC#
LCD3_BRIT
MCH3_BKLTEN
CRT3_HSYNC
CRT3_VSYNC
LCD1_BDATA1
LCD1_BCLK
LCD1_BDATA0#
LCD1_BDATA2#
LCD1_BCLK#
LCD1_BDATA1#
MCH3_CLKREQ#
MCH3_LCDVDDON
LCD1_ACLK
LCD1_ADATA0#
LCD1_ADATA1#
LCD1_ADATA2#
LCD1_ADATA0
LCD1_ADATA1
LCD1_ACLK#
CRT3_DDCCLK
CRT3_DDCDATA
MCH3_ICHSYNC#
LCD3_EDID_CLK
LCD3_EDID_DATA
MCH3_CLKREQ#
CLK1_MCH3GPLL#
CLK1_MCH3GPLL
CHP3_CL_RST_0#
KBC3_PWRGD
CLK1_DREFSSCLK
CLK1_DREFCLK#
CLK1_DREFCLK
CPU1_DPRSTP#
DMI1_TXN_0
DMI1_TXP_0
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3 OF 5
SYSTEM MEMORY A
SYSTEM MEMORY A
SYSTEM MEMORY B
SYSTEM MEMORY B
C
10nF->100nF
2
2
4
OF
DDR3 : Connect to VRM.
DDR2 : GND
DATE
A
SM_RCOMP# : 80 ohm to VSS
A
Route as short as possible
PLACE EACH CAP NEAR AV42 PIN
SM_PWROK
DDR2
C
SAMSUNG ELECTRONICS CO’S PROPERTY.
CHECK
TITLE
1
SM_RCOMP : 80 ohm to P1.8V_AUX
EXCEPT AS AUTHORIZED BY SAMSUNG.
Cantiga
PROPRIETARY INFORMATION THAT IS
B
4915
BA41-
June 03, 2009 16:14:25 PM
1.2
PR
9/23/2008
H.J.KIM
HK.PARK
SY.KIM
SAMSUNG PROPRIETARY
B
3
PART NO.
MODULE CODE
1
APPROVAL
4
LAST EDIT
DEV. STEP
DRAW
REV
D
3
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
THIS DOCUMENT CONTAINS CONFIDENTIAL
ELECTRONICS
PAGE
SAMSUNG
D
nostuff
10V
CANTIGA (3/5)
MCH_CANTIGA_GM_DDR2
BONN-L
1
2
100nF
C651
4
5
1
2
1
2
3
1
2
24
25
14
44
0
1
3
13
63
6061
10
28
7
0
59
4
27
1617
1K
R591
1%
1%
R595
1K
nostuff
12 49
10V
2200nF
C610
2
10V
C609
100nF
5
6
1
2
1%
1
14
80.6
R592
10V
nostuff
3233
C650
100nF
6
0
54
55
4
50510
5
6
1
4541
7
0
403637
5
6
2
6263
1
2223
8 60
18
4
1314
0
515219
13
2
1%
R593
80.6
4
8 94 5
3
1
12
13
59
31325
58
46 616256
7
30 45
2
4647
55
4243
23 4748
1
2
499
R46
1%
5
6
1%
R594
3.01K
3126
27
6 7 1793
7
0
1
3
20
1415
3
4
0
4
5
6
7
3536
3
11
12
7
8
7
432526
6
414229 3824 53
19
11 21
0
37
1011
10
3435
1516
30
4
3940 5758
3
2 3
7
0
0
0
54
57
5
BG22
SM_RCOMP
SM_RCOMP#
BH21
SM_RCOMP_V_OH
BF28
SM_RCOMP_V_OL
BH28
SM_REXT
BF17
SM_VREF
AV42
56
SB_MA_5
BB28
SB_MA_6
AU28
SB_MA_7
AW28
SB_MA_8
AT33
SB_MA_9
BD33
SB_ODT_0
BF15
SB_ODT_1
AY13
SB_RAS#
AU17
SB_WE#
BF14
SM_DRAMRST#
BC36
SM_PWROK
AR36
AU46
SB_MA_0
AV17
SB_MA_1
BA25
SB_MA_10
BB16
SB_MA_11
AW33
SB_MA_12
AY33
SB_MA_13
BH15
SB_MA_14
AU33
SB_MA_2
BC25
SB_MA_3
AU25
SB_MA_4
AW25
SB_DQ_57
AL2
SB_DQ_58
AJ1
SB_DQ_59
AH1
SB_DQ_6
AM48
SB_DQ_60
AM2
SB_DQ_61
AM3
SB_DQ_62
AH3
SB_DQ_63
AJ3
SB_DQ_7
AP48
SB_DQ_8
AU47
SB_DQ_9
SB_DQ_47
BD3
SB_DQ_48
AV2
SB_DQ_49
AU3
SB_DQ_5
AJ48
SB_DQ_50
AR3
SB_DQ_51
AN2
SB_DQ_52
AY2
SB_DQ_53
AV1
SB_DQ_54
AP3
SB_DQ_55
AR1
SB_DQ_56
AL1
BF11
SB_DQ_38
BF8
SB_DQ_39
BG7
SB_DQ_4
AJ46
SB_DQ_40
BC5
SB_DQ_41
BC6
SB_DQ_42
AY3
SB_DQ_43
AY1
SB_DQ_44
BF6
SB_DQ_45
BF5
SB_DQ_46
BA1
SB_DQ_28
BH40
SB_DQ_29
BG39
SB_DQ_3
AP46
SB_DQ_30
BG34
SB_DQ_31
BH34
SB_DQ_32
BH14
SB_DQ_33
BG12
SB_DQ_34
BH11
SB_DQ_35
BG8
SB_DQ_36
BH12
SB_DQ_37
SB_DQ_18
BG43
SB_DQ_19
BF43
SB_DQ_2
AP47
SB_DQ_20
BE45
SB_DQ_21
BC41
SB_DQ_22
BF40
SB_DQ_23
BF41
SB_DQ_24
BG38
SB_DQ_25
BF38
SB_DQ_26
BH35
SB_DQ_27
BG35
AN6
SB_DQ_0
AK47
SB_DQ_1
AH46
SB_DQ_10
BA48
SB_DQ_11
AY48
SB_DQ_12
AT47
SB_DQ_13
AR47
SB_DQ_14
BA47
SB_DQ_15
BC47
SB_DQ_16
BC46
SB_DQ_17
BC44
SB_DQS#_5
BC2
SB_DQS#_6
AT2
SB_DQS#_7
AN5
SB_DQS_0
AL47
SB_DQS_1
AV48
SB_DQS_2
BG41
SB_DQS_3
BG37
SB_DQS_4
BH9
SB_DQS_5
BB2
SB_DQS_6
AU1
SB_DQS_7
SB_DM_2
BD40
SB_DM_3
BF35
SB_DM_4
BG11
SB_DM_5
BA3
SB_DM_6
AP1
SB_DM_7
AK2
SB_DQS#_0
AL46
SB_DQS#_1
AV47
SB_DQS#_2
BH41
SB_DQS#_3
BH37
SB_DQS#_4
BG9
BG16
SB_CK#_0
AU24
SB_CK#_1
AV20
SB_CKE_0
AY36
SB_CKE_1
BB36
SB_CK_0
AV24
SB_CK_1
AU20
SB_CS#_0
AV16
SB_CS#_1
AR13
SB_DM_0
AM47
SB_DM_1
AY47
SA_MA_7
BG27
SA_MA_8
BF25
SA_MA_9
AW24
SA_ODT_0
BD17
SA_ODT_1
AY17
SA_RAS#
BB20
SA_WE#
AY20
SB_BS_0
BC16
SB_BS_1
BB17
SB_BS_2
BB33
SB_CAS#
SA_MA_1
BC24
SA_MA_10
BC21
SA_MA_11
BG26
SA_MA_12
BH26
SA_MA_13
BH17
SA_MA_14
AY25
SA_MA_2
BG24
SA_MA_3
BH24
SA_MA_4
BG25
SA_MA_5
BA24
SA_MA_6
BD24
AJ9
SA_DQ_59
AJ8
SA_DQ_6
AM44
SA_DQ_60
AN12
SA_DQ_61
AM13
SA_DQ_62
AJ11
SA_DQ_63
AJ12
SA_DQ_7
AM42
SA_DQ_8
AN43
SA_DQ_9
AN44
SA_MA_0
BA21
SA_DQ_49
AV7
SA_DQ_5
AJ40
SA_DQ_50
AT9
SA_DQ_51
AN8
SA_DQ_52
AU5
SA_DQ_53
AU6
SA_DQ_54
AT5
SA_DQ_55
AN10
SA_DQ_56
AM11
SA_DQ_57
AM5
SA_DQ_58
SA_DQ_39
BC12
SA_DQ_4
AJ36
SA_DQ_40
BB9
SA_DQ_41
BA9
SA_DQ_42
AU10
SA_DQ_43
AV9
SA_DQ_44
BA11
SA_DQ_45
BD9
SA_DQ_46
AY8
SA_DQ_47
BA6
SA_DQ_48
AV5
BB38
SA_DQ_3
AM38
SA_DQ_30
AV36
SA_DQ_31
AW36
SA_DQ_32
BD13
SA_DQ_33
AU11
SA_DQ_34
BC11
SA_DQ_35
BA12
SA_DQ_36
AU13
SA_DQ_37
AV13
SA_DQ_38
BD12
SA_DQ_2
AN38
SA_DQ_20
AV41
SA_DQ_21
AY43
SA_DQ_22
BB41
SA_DQ_23
BC40
SA_DQ_24
AY37
SA_DQ_25
BD38
SA_DQ_26
AV37
SA_DQ_27
AT36
SA_DQ_28
AY38
SA_DQ_29
SA_DQ_1
AJ41
SA_DQ_10
AU40
SA_DQ_11
AT38
SA_DQ_12
AN41
SA_DQ_13
AN39
SA_DQ_14
AU44
SA_DQ_15
AU42
SA_DQ_16
AV39
SA_DQ_17
AY44
SA_DQ_18
BA40
SA_DQ_19
BD43
AU9
SA_DQS#_7
AM8
SA_DQS_0
AJ44
SA_DQS_1
AT44
SA_DQS_2
BA43
SA_DQS_3
BC37
SA_DQS_4
AW12
SA_DQS_5
BC8
SA_DQS_6
AU8
SA_DQS_7
AM7
SA_DQ_0
AJ38
SA_DM_4
BB12
SA_DM_5
AY6
SA_DM_6
AT7
SA_DM_7
AJ5
SA_DQS#_0
AJ43
SA_DQS#_1
AT43
SA_DQS#_2
BA44
SA_DQS#_3
BD37
SA_DQS#_4
AY12
SA_DQS#_5
BD8
SA_DQS#_6
AR21
SA_CKE_0
BC28
SA_CKE_1
AY28
SA_CK_0
AP24
SA_CK_1
AT21
SA_CS#_0
BA17
SA_CS#_1
AY16
SA_DM_0
AM37
SA_DM_1
AT41
SA_DM_2
AY41
SA_DM_3
AU39
U3-3
GL40
0904-002489
SA_BS_0
BD21
SA_BS_1
BG18
SA_BS_2
AT25
SA_CAS#
BD20
SA_CK#_0
AR24
SA_CK#_1
8
P1.8V_AUX
P1.8V_AUX
4950
39
7
11
44
382021
9
10
48
C611
2200nF
10V
nostuff
100nF
C608
10V
2829
9
6
5253
5
6
3412 22
3
2 18 33
MEM1_ODT3
CLK1_MCLK3#
CLK1_MCLK3
MEM1_ODT1
MEM1_CKE2
MEM1_ODT0
MEM1_VREF
MEM1_VREF
MCH1_SM_RCOMP#_MN
MCH1_SM_RCOMP_MN
MCH1_SM_RCOMP_V_OH_MN
MEM1_SM_REXT_MN
MCH1_SM_RCOMP_V_OL_MN
4
MEM1_ABS(2:0)
MEM1_BDQ(63:0)
MEM1_ADQ(63:0)
MEM1_ARAS#
MEM1_ACAS#
MEM1_AWE#
MEM1_CS1#
MEM1_ADM(7:0)
MEM1_ADQS#(7:0)
MEM1_ADQS(7:0)
MEM1_AMA(14:0)
MEM1_BBS(2:0)
MEM1_BRAS#
MEM1_BCAS#
MEM1_BWE#
MEM1_BDM(7:0)
MEM1_BDQS#(7:0)
MEM1_BDQS(7:0)
MEM1_BMA(14:0)
MEM1_CS0#
MEM1_CKE0
MEM1_CS2#
MEM1_CKE1
MEM1_CS3#
CLK1_MCLK2#
MEM1_CKE3
CLK1_MCLK0#
CLK1_MCLK0
CLK1_MCLK1#
CLK1_MCLK1
MEM1_ODT2
CLK1_MCLK2
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