Samsung 20050812095225703 Schematic Diagram 7

3-1 Main Board

3-1-1 Schematic Diagrams

3-1SENS V20 Series

3 Schematic Diagrams and PCB Silkscreen

Sheet 34.

MP

Sheet 29.

DC Jack & B/D to B/D & bypass

Sheet 33.

LED / SWITCH

Sheet 14. 845G GLUE LOGIC

APPROVAL

CHARGING CIRCUIT

Sheet 22.

Kevin, Lee

Aug, 15, 2002

845G

X

Model Name :

DRAW

SDR MEMORY

Sheet 21.

CPU :

Sheet 37.

Signature :

Brookdale-GL / ICH4

Sheet 28.

HDD / CD

MICOM GLUE LOGIC

Sheet 1.

Sheet 38.

W.S. Jung

SUPER I/O

PBA Name :

Sheet 35.

PCB Code :

CH7017

T.R. Date :

Owner :

DRACO

Sheet 17.

Sheet 10. Thermal Sensor

Kinnereth & MDC

Chip Set :

Sheet 18-20.

H.J. KIM

1.0

Dev. Step :

DRACO

Sheet 31.

Sheet 16.

CHECK

Sheet 32.

AC97 CODEC

CPU (Pentium-IV)

ICH4

Sheet 2-6.

Sheet 15.

MICOM

Sheet 8-9.

Sheet 36.

Revision :

BLOCK / POWER / CLK / PLATFORM INFO / RESET

Sheet 27.

Sheet 25.

[CONTENTS]

Sheet 11-13.

AMP / SPK / MIC / SPDIF

Sheet 24.

Sheet 23.

MAIN BOARD

Cover & Contents

PIO & USB

LCD / CRT

Sheet 7.

FWH

POWER LED / KBD / PS2 / TOUCHPAD

1394 Controller & PHYSheet 30.

MINIPCI

CPU DC/DC

Clock Generator

CARDBUS CONTROLLER

Sheet 26.

Pentium-IV

CARDBUS SOCKET

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-2

3-1-1(a) Main Board Schematic Sheet 2 of 39

(CLOCK GENERATOR)

ANT

400MT/S

PG 32

H-PHONE

PG 29

CPU

KBD

PG 16

PG 24

Power

U-ATA 100

Brookdale-G/GL

PG 28

Hub Interface

DC/DC

TV

PS/2

8Bit, 1.5V, 266MB/S

PG 32

15

PG 21

PG 27

HDD

SPDIF

CARDBUS

System

AC97

SDR-SODIMM 0

Wireless LAN

PSB

PG 20

SDR 3.3V, 133MHz

Touch

LCD

2 FAN

Super I/O

PG 10

RJ45

PG 15

USB 2.0 SUPPORT

ANT

PG 27

DC/DC

PG38

PG 18,19,20

MIC-IN

PG 16

PG 25

760 BGA

Hitachi H8S

Charging

DRACO Block Diagram

MDC Modem

1394

Smart

PG 29

U-ATA 100

Pentium-IV

PG 8,9

R5C475II

PG 11,12,13

PG 31

SOCKET

33MHz, 3.3V PCI

LVDS & TV

FWH

PG 24

RJ11

PG 22

CRT

Audio

SDR-SODIMM 1

AC97 Link

PC87391

CPU

PG 34

PG 37

MINIPCI

30Pin Connector

Kinnereth(LAN PHY)

PG 17

2169

USB1

L2 Cache : 512KB

Scan

421 BGA

Sensor

Battery

DVO I/F, 1.5V

PG 30

LAN

CS4202

PAD

SMC/KBC

PG 33

CLK GEN

PG 17

Circuit

ODD(CD/DVD/RW/COMBO)

Life Time > 2Hrs

Thermal

Parallel

USB0

Mouse,KBD

TSB43AB22

PG 24

ICH4

14.1

Module

Primary IDE

Secondary IDE

3.3V LPC, 33MHz

Serial

PG 7

478 PGA

1 TYPE II

CH7017

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series

3-1-1(b) Main Board Schematic Sheet 3 of 39

(POWER DIAGRAM

)

P1.5V

CARDBUS Cont.

AVDD

HDD

PCORE

ICH4

ICH4

LAN

MICOM

FDD

CRT

MODEM

SODIMM

LCD

AUDIO

FWH

ICH-4

ODD

Power Diagram

VID Pull-Up

VCC_VID

CBT3384

CARDBUS Cont.(R5C485)

CARDBUS Cont.(R5C485)

QS3257

ICH4

SIO

FAN

P1.5V_AUX

CARDBUS Cont.

MK1707 ?

KBC3_SUSPWR

CH7017

ADM1032

MIC-AMP

SPK-AMP

(1.2V)

ADM1032

LEDs

1394

M_PCI

MICOM_P3V

845GL

P3.3V_AUX

KBC3_PWRON

W320

Pentium-IV

CARDBUS Cont.(R5C475II)

P5V

SUPERI/O

MICOM

P3.3V

KBC3_COREON

P12V

USB

M_PCI

VCH

VCH

PS/2

MDC MODEM

KBC3_PWRON

MICOM

ICH4

M_PCI

VDC

TOUCHPAD

ICH-4

MICOM

LEDs

Pentium-IV 845GL

3-3

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-4

3-1-1(c) Main Board Schematic Sheet 4 of 39(CLK DIARAM)

100MHz Differential CLK

PENTIUM-IV

48KHz FOR AC97 SYNC

48MHz FOR USB

33MHz FOR LPC

133MHz

66MHz HUB LINK

33MHz FOR PCI

CARDBUS Cont.

100MHz Differential CLK

66MHz FOR HUB LINK

MCLK 2/3

FWH

33MHz FOR LPC

MCLK 0/1

SDR SODIMM 1

133MHZ

HEIGHT : 0.2 => 0.25

33MHz FOR LPC

65MHz FOR XGA

66MHz DVO

24.576MHz FOR AC97

33MHz FOR PCI

14.318MHz

14.318MHz

E

48MHz FOR DISPLAY

NO_STUFF : helvetica bold , 0.25

32.768KHz

G

33MHz FOR PCI

LCD

N

* => #

ROADMAPPER Height : 0.1 => 0.15

AC97 AUDIO CODEC

12.288MHz FOR AC97

C

L

Kinnereth LAN PHY

25MHz

MICOM

SDR SODIMM 0

40MHz FOR SVGA

Mini-PCI

FONT : STROKE => HELVETICA

1394 Controller

24.576MHz

CLK Diagram

14.318MHz FOR I/O

MC97 MODEM CODEC

33MHz FOR PCI

pin_group : change attribute - visibility

K

ICH-4

66MHz FOR HUB LINK

10MHz

14.318MHz FOR 8254 TIMER

845-G

CH7017

400MHz STB/STB#

SUPER I/O

5 ~ 50MHz

3 Schematic Diagrams and PCB Silkscreen

3-5SENS V20 Series

3-1-1(d) Main Board Schematic Sheet 5 of 39(

PLATFORM INFORMATION

)

1.300 V

PORT NUMBER

-

1.350 V

-

1

SMBUS Master

1

1010 000x

1

A,B

SYSTEM B

1

1

1

REVISION HISTORY

(RESERVED)

-

0

11

LPC bridge/IDE/AC97/SMBUS

0

Devices

1.275 V

I C / SMB Address

ASSIGNED TO

Interrupts

AD17(internal)

0

1

Master

0

1

IDSEL#

1

USB2.0 #0 : A

1

AD29(internal)

1

011

1110 101x

0

1

DRACO REFERENCE PLATFORM

1

SODIMM1

Hub to PCI

0

0

0

1

1

Address

SDR SODIMM0

0

1

1

SDR SODIMM1

1

1.375 V

0

MiniPCI

CK-Titan (Clock Generator)

SODIMM0

Devices

VID2

1

1

AGP

ICH4

0

VID4

1.500 V 0

CPU Core Voltage Table

-

Kinnereth

0

01

AD31(internal)

1

1, 3~5

0

VID1

EAh

A,B

0

Voltage

1

1

0

1.425 V

0

VID0

AD24(internal)

1

1

1

0

VID3

USB PORT Assign

1

1

-

Hex

1

1.250 V

1

VID1

1

00

0

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

1

0

2

-

USB

0100 110x

See rev notes in the changes file for more information.

AD30(internal)

ADM1032 (CPU Thermal Sensor)

0

1.325 V

1.450 V

1

0

00

1

0

2

1.125 V

0

1

Clock, Unused Clock Output Disable

1

VID4VID0

I2C BUS

1.175 V

0

0

Voltage

A2h

B

LVDS & TV Encoder(CH7017)

Bus

0

1010 000x

1.400 V

0

1

PCI Devices

1.100 V

0

A,B

1

1

1

Cardbus

0

1

1

SYSTEM A

1.475 V

AD23

1

1

1

4Ch

-

0

A0h

REQ/GNT#

VID3

0

1 1.525 V

USB2.0 #1 : D

1

1

D2h

1.150 V

1

1

1

0

1

AD19

0

1.550 V

1

Thermal Sensor

1

1.225 V

0

1101 001x

1

0

2

1.200 V

VRM output off

VID2

1

1

1

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-6

3-1-1(e) Main Board Schematic Sheet 6 of 39(

CLK GEN

)

KBC3_PWRSW#

KBC3_SUSPWR

P3.3V_AUX

KBC3_RSMRST#

CHP3_SLP3#

KBC3_PWRON

P3.3V

P5V

RESET DIAGRAM

VID_PWRGD

PCORE

VRM3_PWRGD

KBC3_PWRGD

CPU1_PWRGDCPU

PCI3_RST#

CPU1_CPURST#

3 Schematic Diagrams and PCB Silkscreen

3-7SENS V20 Series

3-1-1(f) Main Board Schematic Sheet 7 of 39(CLK GEN)

11

Place near to Receiver

0 1 100MHz

@

future use

0

HOST CLK

1

Clock Generator

S1 S0

133MHz

0

200MHz

0 66MHz

NO_STUFF

NO_STUFF

NO_STUFFNO_STUFFNO_STUFFNO_STUFFNO_STUFF

NO_STUFF

NO_STUFFNO_STUFF

NO_STUFF

NO_STUFFNO_STUFFNO_STUFF

KBC3_VRPWRGD#

CLK3_DOT48

CLK0_HCLK1

CLK0_HCLK1#

CLK0_HCLK0

CLK0_HCLK0#

CLK3_ICH48

CLK3_SIO14

CLK3_ICH14

CPU3_BSEL0

KBC3_VRPWRGD#

SMB3_DATA

CLK3_MCH66

CLK3_ICH66

CLK3_PCLKICH

CLK3_PCLKFWH

CLK3_PCLK1394

CLK3_PCLKCB

CLK3_PCLKMIN

CLK3_PCLKMICOM

CLK3_PCLKSIO

SMB3_CLK

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-8

3-1-1(g) Main Board Schematic Sheet 8 of 39(Pentium-IV [1/2])

And connect ITP I/F Board

1 PCORE

12 CLK2_HCLK1

13 GND

Table A

To use ITP Debugginh Mode, Do not install

the resistors on the TCK, TDI, and TMS.

ITP I/F Board Signal

9 CPU1_PREQ*

10 CPU1_PRDY*

2 CPU1_CPURST*

3 CPU1_TCK

4 CPU1_TMS

5 CPU1_TDI

6 CPU1_TDO

7 PVCCT

Northwood Processor

8 CPU1_TRST*

11 GND

NO_STUFFNO_STUFFNO_STUFFNO_STUFFNO_STUFF

CPU1_NMI

CPU1_SMI#

CPU1_STPCLK#

CPU1_INIT#

CPU1_DSTBN3#

CPU1_DSTBP2#

CPU1_DSTBP3#

CPU1_D(63:48)

CPU1_D(47:32)

SMB3_ALERT#

CPU1_PROCHOT#

CPU1_SLP#

CHP3_CPUPERF#

CPU1_A20M#

CPU1_IGNNE#

CPU1_INTR

CPU1_DBI2#

CPU1_DBI3#

CPU1_DSTBN2#

CPU1_DBI0#

CPU1_DBI1#

CPU1_D(15:0)

CPU1_RS2#

CPU1_RS1#

CPU1_RS0#

CPU1_D(31:16)CPU1_REQ#(4:0)

CPU1_ADSTB0#

CPU1_ADSTB1#

CPU1_ADS#

CPU1_A(16:3)

CPU1_BREQ#

CPU1_LOCK#

CPU1_TRDY#

CPU1_DRDY#

CPU1_DBSY#

CPU1_A(31:17)

CPU1_DSTBP1#

CPU1_DSTBP0#

CPU1_DSTBN1#

CPU1_DSTBN0#

CPU1_INIT#

CPU1_CPURST#

CPU1_DEFER#

CPU1_BPRI#

CPU1_HITM#

CPU1_HIT#

CPU1_BNR#

3 Schematic Diagrams and PCB Silkscreen

3-9SENS V20 Series

3-1-1(h) Main Board Schematic Sheet 9 of 39(Pentium-IV [2/2])

BPM0

DBRST*

44uF : 2402-001045,7343

TEST ONLY

ESR<0.3ohm

ESL<5nH

PRDY*

BPM1

Northwood Processor

4.7uH at 80mA

10uH at 60mA

22~100uF

PREQ*

Tol +/-20%

Alternative

4.7uH : 2703-001816

Don t allow signal line to use the GTLREF routing as part of their return path.

GTL REFERENCE

ITP I/F Signal

Keep the Voltage divider within 1.5" of the first GTLREF pin.

CPU3_BSEL0

CPU2_THERMDC

CPU_GTLREF0

CPU1_PROCHOT#

CPU1_SLP#

CPU1_THRMTRIP#

CPU_GTLREF0

CPU3_VID(0:4)

CPU1_NMI

CPU1_INTR

CPU1_IGNNE#

CPU1_A20M#

CPU1_FERR#

CPU1_STPCLK#

CPU1_PWRGDCPU

CPU1_SMI#

CPU2_THERMDA

CLK0_HCLK0

CLK0_HCLK0#

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-10

3-1-1(i) Main Board Schematic Sheet 10 of 39(THERMAL SENSOR)

- Keep traces away from fast data buses and CRTs.

- Use guard traces flanking DXP and DXN and connecting to GND

- Use recommended trace widths and spacings (10mil)

- Place a ground plane under the traces.

[ 350mA ]

VID POWER

CPU Thermal Sensor

Refer To Thermal Sensor Layout Guidelines.

- Place the Thermal Sensor close to a remote diode.

1.2V, Max-300mA

- Keep traces away from high voltage (+12V bus)

ADM1032ARM

CPU2_THERMDCSMB3_ALERT#

THERM3_OVERT#

KBC3_THERM_SMDATA

KBC3_THERM_SMCLK CPU2_THERMDA

KBC3_PWRON

VID_PWRGD

CPU3_VID(0:4)

KBC3_COREON

CPU3_THRMTRIP#

KBC3_PWRON

CPU1_THRMTRIP#

VRM3_PWRGD

CPU3_THRMTRIP#

3 Schematic Diagrams and PCB Silkscreen

3-11SENS V20 Series

3-1-1(j) Main Board Schematic Sheet 11 of 39(845GL [1/3])

BROOKDALE-GL (1/3)

Reference Voltage Input for Compensation Logic.

Routing : 12 mil trace, 10 mil space

FOR SDR SDRAM

MCH_HVSWING1

KBC3_PWRGD

CPU1_DBI3#

CPU1_DSTBP0#

CPU1_DSTBN0#

CPU1_DBI0#

CPU1_DSTBP1#

CPU1_DSTBN1#

CPU1_DBI1#

CPU1_DSTBP2#

CPU1_DSTBN2#

CPU1_DBI2#

CPU1_DSTBP3#

CPU1_DSTBN3#

CPU3_BSEL0

MCH_HVSWING0

VGA3_DDCC

VGA3_DDCD

CLK3_DOT48

CPU1_ADS#

CPU1_TRDY#

CPU1_DRDY#

CPU1_DEFER#

CPU1_HITM#

CPU1_HIT#

CPU1_LOCK#

CPU1_BREQ#

CPU1_BNR#

CPU1_BPRI#

CPU1_DBSY#

CPU1_RS0#

CPU1_RS1#

CPU1_RS2#

CPU1_CPURST#

MCH_HVSWING1

CLK0_HCLK1#

CLK0_HCLK1

CPU1_A(31:3)

CPU1_REQ#(4:0)

CPU1_D(63:0)

MCH_HVSWING0

CPU1_ADSTB0#

CPU1_ADSTB1#

VGA_RED

VGA_RED

VGA_RED#

VGA_GREEN

VGA_GREEN

VGA_GREEN#

VGA_BLUE

VGA_BLUE

VGA_BLUE#

VGA3_HSYNC

VGA3_VSYNC

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-12

3-1-1(k) Main Board Schematic Sheet 12 of 39(845GL [2/3])

within 0.5" from GMCH

BROOKDALE-GL (2/3)

SDRAM only

As close as possible

at least 10mA

NO_STUFF

NO_STUFF

MEM3_MAA(0:12)

MEM3_DQMA(0:7)

CLK3_MCLK0

CLK3_MCLK1

MEM3_CSA2#

CLK3_MCLK3

MEM3_CSA3#

CLK3_MCLK2

MEM3_MD(63:0)

MEM3_CSA0#

MEM3_BS0

MEM3_SRASA#

MEM3_CSA1#

MEM3_BS1

MEM3_MWEA#

MEM3_SCASA#

MEM3_CKE0

MEM3_CKE1

MEM3_CKE3

MEM3_CKE2

CLK3_MCLK0

CLK3_MCLK1

3 Schematic Diagrams and PCB Silkscreen

3-13SENS V20 Series

3-1-1(l) Main Board Schematic Sheet 13 of 39(845GL [3/3])

ADD_DETECT#

DVO device down scenario

DVO device down scenario

BROOKDALE-GL (3/3)

DVOC1_D(0:11)

DVOB1_BLANK#

DVOB1_VSYNC

DVOB1_HSYNC

DVOB1_FLDSTL

DVOC1_CLKOUT

DVOC1_CLKOUT#

DVOC1_HSYNC

DVOC1_VSYNC

DVOC1_BLANK#

TV1_CLKOUT

DVOC1_FLDSTL

DVOB1_D(0:11)

HUB1_HL(0:10)

HUB1_STBF

HUB1_STBS

PCI3_RST#

DVOB1_CLK

DVOB1_CLK#

CLK3_MCH66

HI_VREF_GMCH

HI_VSWING_GMCH

MI2C1_CLK

MI2C1_DATA

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-14

3-1-1(m) Main Board Schematic Sheet 14 of 39(845GL Bypass)

GMCH bypass for 845G

0.1uF X 15

22uF X 2

150uF X 3

0.1uF X 10

10uF X 3

0.1uF X 6

10uF X 2

100uF X 1

0.25" LESS

Between GMCH and ICH

0.7V, 2%

0.35V, 2%

HI_VSWING_ICH

HI_VSWING_GMCH

HI_VREF_GMCH

HI_VREF_ICH

3 Schematic Diagrams and PCB Silkscreen

3-15SENS V20 Series

3-1-1(n) Main Board Schematic Sheet 15 of 39(VCH)

(VDDV/2)

PIN35(LGND6)

NO_STUFFNO_STUFF

NO_STUFF

NO_STUFF

NO_STUFF

VGA3_HSYNC VGA5_DDCC

VGA5_DDCD

VGA5_VSYNC

VGA5_HSYNC

VGA5_VSYNC

VGA5_HSYNC

VGA3_DDCC VGA5_DDCD

VGA5_DDCC

MI2C1_DATA

MI2C1_CLK

VDDV

DVOB1_FLDSTL

DVOC1_FLDSTL

VGA3_HSYNC

VGA3_DDCD

VGA3_VSYNC

VREF1

CHP3_PAL_NTSC#

DVOC1_HSYNC

TV1_CLKOUT

DVOC1_VSYNC

DVOC1_CLKOUT

DVOC1_CLKOUT#

DVOC1_D(0:11)

PCI3_RST#

DVOC1_BLANK#

VDDV

VREF1VDDV

VCH3_Y

VCH3_C

VGA3_DDCC

VGA3_DDCD

VGA3_VSYNC

DVOB1_D(0:11)

DVOB1_BLANK#

DVOB1_CLK

DVOB1_CLK#

DVOB1_VSYNC

DVOB1_HSYNC

VCH3_LCDVDDON

VCH3_BKLTON

LVDS1_ACLK-

LVDS1_ACLK+

LVDS1_A0-

LVDS1_A0+

LVDS1_A1-

LVDS1_A1+

LVDS1_A2-

LVDS1_A2+

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-16

3-1-1(o) Main Board Schematic Sheet 16 of 39(LCD & CRT)

17-A

Close to VGA as possible

Main To LCD Connector

CRT

NO_STUFFNO_STUFFNO_STUFF

NO_STUFF

NO_STUFF

VGA_BLUE#

LVDS1_A1-

LVDS1_A1+

LVDS1_A2+

LVDS1_A2-

LVDS1_ACLK+

LVDS1_ACLK-

LVDS1_A0+

LVDS1_A0-

LCD3_BKLTON

VCH3_BKLTON

KBC3_BKLTON

LCD_VDD3V

LCD5_BRIT

KBC3_BRIT

VGA_RED

VGA_GREEN

VGA_BLUE

VGA5_HSYNC

VGA5_VSYNC

VGA5_DDCD

VGA5_DDCC

VCH3_LCDVDDON

LCD_VDD3V

IVT_VDC

LCD5_BRIT

LCD3_BKLTON

VGA_RED#

VGA_GREEN#

3 Schematic Diagrams and PCB Silkscreen

3-17SENS V20 Series

3-1-1(p) Main Board Schematic Sheet 17 of 39(SDR SIDIMM)

SODIMM

(Only PC-133)

SLOT 0 SLOT 1

REVERSE TYPE

Kenara has 100Kohm pullups at SMB3_SDx/SCx

Place capacitors near SDRAM Connector

1G Max

AC Termination

Add one 10nF Cap X7R per 5 signals that switch plane references.

MEM3_MWEA# MEM3_CKE1

MEM3_CSA0# MEM3_MAA(12)

MEM3_CSA1#

CLK3_MCLK1

MEM3_MD(0:63)

MEM3_MAA(8) MEM3_BS0

MEM3_MAA(9) MEM3_BS1

MEM3_MAA(10) MEM3_MAA(11)

MEM3_DQMA(5) MEM3_DQMA(1)

MEM3_DQMA(4) MEM3_DQMA(0)

SMB3_SDA SMB3_SCA

MEM3_DQMA(7) MEM3_DQMA(3)

MEM3_DQMA(6) MEM3_DQMA(2)

MEM3_MAA(0) MEM3_MAA(3)

MEM3_MAA(1) MEM3_MAA(4)

MEM3_MAA(2) MEM3_MAA(5)

CLK3_MCLK0 MEM3_CKE0

MEM3_SRASA# MEM3_SCASA#

MEM3_MAA(3)

MEM3_MAA(1) MEM3_MAA(4)

MEM3_MAA(2) MEM3_MAA(5)

CLK3_MCLK2 MEM3_CKE2

MEM3_SRASA# MEM3_SCASA#

MEM3_MWEA# MEM3_CKE3

MEM3_CSA2# MEM3_MAA(12)

MEM3_CSA3#

CLK3_MCLK3

MEM3_MD(0:63)

CLK3_MCLK0

CLK3_MCLK1

CLK3_MCLK2

CLK3_MCLK3

MEM3_MAA(6) MEM3_MAA(7)

SMB3_DATA

CHP3_SPDSELB#

SMB3_SDB

SMB3_CLK

SMB3_SCB

CHP3_SPDSELA#

SMB3_SCA

SMB3_SDA

MEM3_MAA(6) MEM3_MAA(7)

MEM3_MAA(8) MEM3_BS0

MEM3_MAA(9) MEM3_BS1

MEM3_MAA(10) MEM3_MAA(11)

MEM3_DQMA(5) MEM3_DQMA(1)

MEM3_DQMA(4) MEM3_DQMA(0)

SMB3_SDB SMB3_SCB

MEM3_DQMA(7) MEM3_DQMA(3)

MEM3_DQMA(6) MEM3_DQMA(2)

MEM3_MAA(0)

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-18

3-1-1(q) Main Board Schematic Sheet 18 of 39(

ICH4 [1/3]

)

NO_STUFFNO_STUFFNO_STUFFNO_STUFFNO_STUFFNO_STUFF

GPIO5

GPIO3

GPIO3

GPIO4

GPIO5

PCI3_REQ1#

PCI3_REQ2#

PCI3_REQ3#

PCI3_INTA#

PCI3_DEVSEL#

PCI3_PERR#

PCI3_FRAME#

PCI3_REQ4#

CHP3_PCREQB#

CHP3_PCREQA#

ISA3_IRQ(14)

ISA3_IRQ(15)

PCI3_GNT4#

PCI3_GNT3#

PCI3_GNT2#

PCI3_GNT1#

GPIO17

PCI3_PAR

GPIO2

GPIO2

GPIO4

HDD5_D(0:15)

PCI3_PLOCK#

PCI3_SERR#

PCI3_STOP#

PCI3_TRDY#

CLK3_PCLKICH

CHP3_PME#

HDD5_A0

HDD5_A1

HDD5_A2

HDD5_CS1#

HDD5_CS3#

HDD5_DACK#

HDD5_DREQ

HDD5_IOR#

HDD5_IOW#

HDD5_IORDY

CDD5_D(0:15)

PCI3_STOP#

PCI3_SERR#

PCI3_IRDY#

PCI3_TRDY#

PCI3_INTB#

PCI3_INTC#

PCI3_INTD#

PCI3_PLOCK#

PCI3_REQ0#

PCI3_CBE2#

PCI3_INTA#

PCI3_INTB#

PCI3_INTC#

PCI3_INTD#

PCI3_REQ0#

PCI3_REQ1#

PCI3_REQ2#

PCI3_REQ3#

PCI3_REQ4#

PCI3_GNT0#

GPIO17

PCI3_DEVSEL#

PCI3_FRAME#

PCI3_IRDY#

PCI3_PAR

PCI3_RST#

PCI3_RSTF#

PCI3_GNT4#

PCI3_GNT3#

PCI3_GNT2#

PCI3_GNT1#

CHP3_PCREQB#

PCI3_PERR#

PCI3_RSTF#

1394_EEPROM_WE#

CHP3_PCREQA#

PCI3_AD(0:31)

CDD5_DREQ

CDD5_DACK#

CDD5_IOR#

CDD5_IOW#

ISA3_IRQ(14)

ISA3_IRQ(15)

CDD5_IORDY

CDD5_CS1#

CDD5_CS3#

CDD5_A2

CDD5_A1

CDD5_A0

PCI3_CBE3#

PCI3_CBE0#

PCI3_CBE1#

3 Schematic Diagrams and PCB Silkscreen

3-19SENS V20 Series

3-1-1(r) Main Board Schematic Sheet 19 of 39(

ICH4 [2/3]

)

#. KBC3_PWRGD : Active minimum 10ms after 3.3V, 1.8V OK.

NO_STUFFNO_STUFFNO_STUFF

NO_STUFF

NO_STUFFNO_STUFFNO_STUFF

NO_STUFFNO_STUFF

NO_STUFF

NO_STUFF

NO_STUFF

NO_STUFFNO_STUFF

NO_STUFF

CHP3_AC97_BCLK

USB3_P2+

CHP3_VBIAS

CHP3_USBPWR2#

CHP3_USBPWR0#

CHP3_PAL_NTSC#

CHP3_HDDRST#

CDD5_CDRST#

CHP3_CDBUFEN#

THRM#

CHP3_AUTOBIOS#

CPU1_THRMTRIP#

AGPBUSY#

BATLOW#

RI#

BATLOW#

SMBALERT#

SMBALERT#

CHP3_SPDSELA#

CHP3_SPDSELB#

CHP3_AUTOBIOS#

CHP3_BIOSWP#

CHP3_SLPS4#

KBC3_PWRGD

THRM#

HI_RCOMP

HI11

HI_VSWING_ICH

KBC3_RUNSCI#

PCI3_CLKRUN#

CHP3_CPUPERF#

LPC3_LDRQ1#

AGPBUSY#

CHP3_SLPS3#

CHP3_SLPS1#

CHP3_SUSSTAT#

KBC3_LAN_PWROK

KBC3_RSMRST#

CHP3_SLPS5#

CHP3_AC97_SDO

CHP3_AC97_SDI2

CHP3_AC97_SDI0

CHP3_AC97_SDI1

CPU1_SMI#

CPU1_NMI

CPU1_INTR

CPU1_IGNNE#

CPU1_INIT#

CPU1_PWRGDCPU

HUB1_HL(0:10)

HI_RCOMP

LAN3_RXD0

LAN3_RXD1

LAN3_TXD2

LAN3_TXD1

LAN3_TXD0

LAN3_RXD2

CHP3_AC97_SDI2

CLK3_ICH48

CHP3_SLPS3#

RI#

SMB3_CLK

SMB3_DATA

SMB3_CLK

SMB3_DATA

CHP3_SERIRQ

CPU1_FERR#

KBC3_LAN_PWROK

PCI3_RST#

KBC3_RSMRST#

CHP3_RTCRST#

KBC3_EXTSMI#

KBC3_WAKESCI#

CHP3_AC97_SDI1

LAN3_PHYRST

LAN3_PHYCLK

CLK3_ICH66

HI_VREF_ICH

HUB1_STBS

HUB1_STBF

CLK3_ICH14

CHP3_SPKR

VRM3_PWRGD

CHP3_SUSSTAT#

KBC3_ICHPWR#

CHP3_BIOSTBL#

HI11

LPC3_LDRQ1#

CHP3_SLPS5#

USB3_OC2#

CPU1_A20M#

CPU1_SLP#

KBC3_A20G

KBC3_CPURST#

CPU1_STPCLK#

LPC3_LAD(0:3)

LPC3_LFRAME#

LPC3_LDRQ0#

USB3_P0-

USB3_P0+

USB3_P2-

LPC3_LFRAME#

CHP3_SERIRQ

KBC3_PWRGD

USB3_OC0#

CHP3_VBIAS

CHP3_AC97_RST#

CHP3_AC97_SYNC

CHP3_AC97_SDO

CHP3_AC97_BCLK

CHP3_AC97_SDI0

3 Schematic Diagrams and PCB Silkscreen

SENS V20 Series3-20

3-1-1(s) Main Board Schematic Sheet 20 of 39(

ICH4 [3/3]

)

0.1uF X 2

100uF X 1

RTC_Battery

22uF X 2

0.1uF X 8

4.7uF X 1

FAN A

60

70

22uF X 1

0.1uF X 7

67

4V(2800rmp) <-> 4.5V(3100rpm) <-> 5V(3400rpm)

22uF X 1

65

Main FAN(FAN A)

+

22uF X 1

PRTC_BAT:Can drop to 2.0V(min)

22uF X 1

FAN B

0.1uF X 12

0.1uF X 2

NO_STUFFNO_STUFFNO_STUFF

NO_STUFFNO_STUFF

NO_STUFFNO_STUFF

NO_STUFFNO_STUFFNO_STUFF

THERM3_OVERT#

CHP3_VBIAS

KBC5_FANB_ON#

CHP3_RTCRST#

CHP3_AUTOBIOS#

CHP3_RTCRST#

KBC3_FANCTRL

3 Schematic Diagrams and PCB Silkscreen

3-21SENS V20 Series

3-1-1(t) Main Board Schematic Sheet 21 of 39(FWH)

SST : 1107-001288

Firmware Hub(DV:Socket)

PORT80 DEBUG TABLE

Intel : 1107-001142

NO_STUFF

LPC3_LFRAME#

LPC3_LAD(0:3)

CHP3_BIOSTBL#

CHP3_BIOSWP#

PCI3_RST#

KBC3_FWHRST#

CLK3_PCLKFWH

CPU1_INIT#