SAIFUN SA25F005EM8, SA25F005EM8F, SA25F005EM8FX, SA25F005EM8X, SA25F005EMLF Datasheet

This Data Sheet states Saifun's current technical specifications regarding the Products described herei n. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 1984 Rev: 1 Amendment: 0
Issue Date: 24 July 2003

SA25F005
Advanced

Information

Features

•= Saifun NROM™ Flash Cell

•= Serial Peripheral Interface (SPI) Compatible,

Supports SPI Modes 0 (0,0) and 3 (1,1)

•= Page Program Operation:

– 256 pages (256 Bytes/Page)
– Single Page Rewrite Cycle (Erase and Program) in 10ms

Typical

•= Page Program Mode (up to 256 bytes) in 9ms Typical

•= Page Erase (256 bytes) in 3 ms

•= Sector Erase (256 Kb) in 0.3 s

•= Bulk Erase (512 Kb)

•= Single Supply Voltage: 2.7 V to 3.6 V

•= 25MHz Clock Rate

•= Block Write Protection: Protect Quarter, Half or Entire Array

•= Write Protect Pin and Write Disable Instructions of Both

Hardware and Software Data Protection

•= 100,000 Erase Cycles (Minimum)

•= More than 20-Year Data Retention

•= Low-power Standby Current (less than 1µA)

•= 8-SOIC Narrow Package

•= MLF Leadless Package

•= Temperature Range:

– Industrial: -40°C to +85°C
– Commercial: 0°C to +70°C

512Kb Serial Flash

with 25MHz SPI Bus

Interface

http://www.saifun.com

Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.

SA25F005 Advanced Information

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General Description

The SA25F005 is a 512Kb (256K X 2)
CMOS non-volatile serial Flash Memory.
This device fully conforms to the SPI 4-wire
protocol, is enabled through the Chip Select
(CSb) pin, and uses Clock (SCK), Data-in
(SI) and Data-out (SO) pins to
synchronously control data transfer
between the SPI microcontroller and the
Serial FLASH memory.

The memory can be programmed from 1 up
to 256 bytes at a time via the Page
Program (PP) instruction.

The memory is organized into two sectors.
Each sector contains 128 pages, with each
page being 256 bytes wide. The entire
memory can therefore be viewed as
consisting of 256 pages, or 65,536 bytes.

The memory can be erased in one of the
following ways:

•= 256 bytes at a time, using the Page

Erase (PE) instruction

•= 256 Kb at a time, using the Sector

Erase (SE) instruction

•= 512 Kb at a time, using the Bulk

Erase (BE) instruction

Each device requires only a 3.0V power
supply (2.7 V to 3.6 V) for both read and
write functions. Internally generated and
regulated voltages are provided for the
program and erase operations. The
SA25F005 does not require a V

PP

supply.

The HOLDb pin may be used to suspend
any serial communication without resetting
the serial sequence. In addition, the serial
interface allows a minimal-pin-count
packaging designed to simplify PC board
layout requirements and offers the designer
a variety of low-voltage and low-power
options.

The SA25F005 is available in a
space-saving, 8-lead narrow SOIC package

The SA25F005 is part of the SPI Flash and
EEPROM family. It is designed to work with
any SPI-compatible, high-speed
microcontroller, and offers both hardware
(WPb pin) and Software (“block protect”)
data protection. For example, programming
a 2-bit code into the status register prevents
program with top ¼, top ½ or entire array
write protection and enables block write
protection. Separate program enable and
program disable instructions are provided
for additional data protection. Hardware
data protection is provided via the WPb pin
to protect against inadvertent write attempts
to the status register.

Saifun’s SPI Serial Flash products are
designed and tested for applications
requiring high endurance and low power
consumption for a continuously reliable
non-volatile solution for all markets.

SA25F005 Advanced Information

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Table of Contents

Features......................................................................... 1

General Description ...................................................... 2

Memory Organization.................................................... 5

Connection Diagrams................................................... 6

Ordering Information .................................................... 7

Product Specifications ................................................. 8

Absolute Maximum Ratings..................................... 8

ESD/Latch Up Specification (JEDEC 8 Spec) ......... 8

Operating Conditions............................................... 8

DC Characteristics ........................................................ 9

AC Test Conditions ..................................................... 10

Timing Diagrams......................................................... 11

Signal Description....................................................... 13

Chip Select (CSb).................................................. 13

Serial Clock (SCK) ................................................ 13

Serial Input (SI) ..................................................... 13

Serial Output (SO)................................................. 13

Hold (HOLDb)........................................................ 13

Write Protect (WPb) .............................................. 13

Serial Interface Description........................................ 14

SPI Modes ............................................................ 14

Master........................................................... 14

Slave............................................................. 14

Transmitter/Receiver ..................................... 14

Serial Opcode................................................ 14

Invalid Opcode .............................................. 14

Chip Select (CSb).......................................... 14

Hold Condition............................................... 15

Write Protect ................................................. 16

Functional Description ............................................... 17

Instructions............................................................ 17

Read Status Register (RDSR)............................... 18

Write Enable (WREN) ........................................... 20

Write Disable (WRDI)............................................ 20

Write Status Register (WRSR).............................. 21

Read Data Bytes (READ)...................................... 23

Fast Read (FAST_READ) ..................................... 24

Page Programming (PP) ....................................... 25

Page Erase (PE)................................................... 27

Sector Erase (SE) ................................................. 28

Bulk Erase (BE)..................................................... 29

Software Protection (SP)/ Deep Powerdown (DP) . 30

Release from Software Protect (RES) ................... 31

Release from Software Protection and Read

Electronic Signature (RES).................................... 32

Powerup and Powerdown...................................... 33

Physical Dimensions................................................... 34

Contact Information .................................................... 37

Life Support Policy...................................................... 37

SA25F005 Advanced Information

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List of Figures

Figure 1. SA25F005 Block Diagram ................................ 5

Figure 2. SOIC 8 (150 mil)/PDIP/MLF Package

(Top View)............................................................. 6

Figure 3. SA25F005 Ordering Information....................... 7

Figure 4. SPI Mode 0 (0,0) Input Timing........................ 11

Figure 5. SPI Mode 0 (0,0) Output Timing..................... 11

Figure 6. AC Measurements I/O Waveform................... 12

Figure 7. Supported SPI Modes .................................... 14

Figure 8. Hold Condition................................................ 15

Figure 9. SPI Serial Interface ........................................ 17

Figure 10. Read Status Register (RDSR) Instruction

Sequence ............................................................ 19

Figure 11. Write Enable (WREN) Instruction Sequence 20

Figure 12. Write Disable (WRDI) Instruction Sequence. 20

Figure 13. Write Status Register (WRSR) Instruction

Sequence ............................................................ 22

Figure 14. Read (READ) Instruction Sequence ............. 23

Figure 15. Fast Read (FAST_READ) Instruction

Sequence ............................................................ 24

Figure 16. Page Programming (PP) Instruction

Sequence ............................................................ 26

Figure 17. Page Erase (PE) Instruction Sequence ........ 27

Figure 18. Sector Erase (SE) Instruction Sequence ...... 28

Figure 19. Bulk Erase (BE) Instruction Sequence.......... 29

Figure 20. Software Protection Instruction Sequence .... 30

Figure 21. Release from Software Protect (RES) Instruction

Sequence ............................................................ 31

Figure 22. Release from Software Protection and Read

Electronic Signature (RES) Instruction Sequence 32

Figure 23. 8-pin SOIC Package..................................... 34

Figure 24. 8-pin MLF Leadless Package ....................... 35

Figure 25. Molded Dual-in-line Package (N) Package

Number N08E...................................................... 36

List of Tables

Table 1. Memory Organization ........................................ 5

Table 2. Pin Names......................................................... 6

Table 3. DC Characteristics............................................. 9

Table 4. AC Test Conditions.......................................... 10

Table 5. AC Measurements........................................... 12

Table 6. Instruction Set ................................................. 17

Table 7. Status Register Format.................................... 18

Table 8. Read Status Register Definition....................... 18

Table 9. Block Write Protect Bits................................... 21

Table 10. WPBEN Operation ........................................ 21

Table 11. Powerup ........................................................ 33

SA25F005 Advanced Information

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Memory Organization

The memory is organized in the following
manner:

•= 65,596 bytes (8 bits each)

•= 2 sectors (256 Kb total, 32,768

bytes each), as shown in Table 1

•= 256 pages (256 bytes each)

Each page can be individually
programmed, with the bits programmed
from 1 to 0. The SA25F005's memory
can be erased via the Page, Sector or
Bulk Erase commands, with the bits
erased from 0 to 1.

Table 1. Memory Organization

Sector Address Range

1 8000h 0FFFFh

0 00000h 07FFFh

HOLDb

WPb

Vcc

GND

SO

SI

SCK

CSb

PSSRAM

IO

Array - R

X
D
E
C

Logic

Array - L

DATA PATHRD

Figure 1. SA25F005 Block Diagram

SA25F005 Advanced Information

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Connection Diagrams

SA25F005

1

2

3

4

8

7

6

5

CSb

SO

WPb

GND

VCC

HOLDb

SCK

SI

Figure 2. SOIC 8 (150 mil)/PDIP/MLF Package (Top View)

Table 2. Pin Names

Pin Name Signal Name

CSb Chip Select

SCK Serial Data Clock

SI Serial Data Input

SO Serial Data Output

GND Ground

VCC Power Supply

WPb Write Protect

HOLDb Suspend Serial Input

SA25F005 Advanced Information

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Ordering Information

LXXF25SA Letter

L

005

F

25

SA

Interface

Density

Voltage Operating Range

Description

2.7 V to 3.6 V

512 Kb with Write
Protect

Flash

SPI-2 Wires

Saifun Non-Volatile
Memory

X

Blank
X

Tube
Tape and Reel

PP

Package

N
M8
MLF

8-pin DIP
8-pin SOIC (150 mil)
8-lead MLF

F

Blank
F

Non-lead Free
Lead Free

E

Blank
E

Temp. Range 0 to 70 C

-40 to +85 C

o

o

Figure 3. SA25F005 Ordering Information

SA25F005 Advanced Information

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Product Specifications

Absolute Maximum Ratings

Storage Temperature

-65

°C to +150 °C

All input or output voltages with
respect to Ground

4.5 V to -0.3 V

Lead Temperature
(Soldering, 10 seconds)

+235

°C

ESD Rating 2000 V min.

ESD/Latch Up Specification (JEDEC 8 Spec)

Human Body Model Minimum 4 KV

Machine Model Minimum 500 V

Charge Device Model Minimum 1 KV

Latch Up

100 mA on all pins +125

°C

Operating Conditions

Operating Temperature:
SA25F005
SA25F005E

0

°C to +70 °C

-40

°C to +85 °C

Positive Power Supply:
SA25F005

2.7 V to 3.6 V

SA25F005 Advanced Information

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DC Characteristics

Applicable over recommended operating range from TAI = -40 ºC to 85 ºC, VCC = 2.7-3.6 V.

Table 3. DC Characteristics

Limits

Symbol Parameter Test Conditions

Min Typ* Max

Unit

VCC

Supply Voltage 2.7 3 3.6

V

I

CC1

Active Power Supply
Current (Read)

SCK = 0.1V

CC

/0.9 VCC @

25 MHz

9 12

mA

I

CC2

Active Power Supply
Current (Page Program)

CSb = VCC 15 mA

I

CC3

Active Power Supply
Current (WRSR)

CSb = VCC 15 mA

I

CC4

Active Power Supply
Current (SE)

CSb = VCC 15 mA

I

CC5

Active Power Supply
Current (BE)

CSb = VCC 15 mA

ISB Standby Current

V

CC

= 3.0 V,

CSb = V

CC

1

µA

IIL

Input Leakage Current V

IN

= GND to VCC 1

µA

IOL

Output Leakage Current V

IN

= GND to VCC 1

µA

VIL

Input Low Voltage -0.3 0.3 V

CC

V

VIH

Input High Voltage 0.7 V

CC

V

CC

+

0.5

V

VOH

Output High Voltage I

OH

= -0.1 mA

VCC -

0.2

V

VOL

Output Low Voltage I

OL

= 1.6 mA; VCC = 2.7 V 0.4

V

*Typical values are at TAI = 25 ºC and 3 V.

SA25F005 Advanced Information

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AC Test Conditions

Table 4. AC Test Conditions

25 MHz

Symbol Parameter

Min Typ Max

Unit

F

SCK

SCK Clock Frequency D.C. 25 MHz

t

CRT

Clock Rise Time (Slew Rate) 0.1

V/ns

t

CFT

Clock Fall Time (Slew Rate) 0.1

V/ns

t

WH

SCK High Time 18

ns

t

WL

SCK Low Time 18 ns

tCS CSb High Time 100 ns

t

CSS

**

CSb Setup Time 10 ns

t

CSH

**

CSb HOLD Time 10 ns

t

HD

**

HOLDb Setup Time 10 ns

t

CD

**

HOLDb Hold Time 10 ns

tV Output Valid 0 15 ns

tHO Output Hold Time 0 ns

t

HD:DAT

Data in Hold Time 5 ns

t

SU:DAT

Data in Setup Time 5 ns

t

LZ

**

HOLDb to Output Low Z 15 ns

t

HZ

**

HOLDb to Output High Z 20 ns

t

DIS

**

Output Disable Time 15 ns

t

WPS

**

Write Protect Setup Time 20

ns

t

WPH

**

Write Protect Hold Time 100

ns

tPP* 256-byte Page Programming 8 10 ms

tEP*

Page Erase and
Programming

10 15 ms

tPE Page Erase Time 3 6 ms

tSE Sector Erase Time 0.3 0.4 sec

tBE Bulk Erase Time 0.5 0.8 sec

t

RES

Release SP Mode 1000 ns

Endurance 100K Erase cycles

* 256 bytes in the checkerboard programming formation.

** Value guaranteed by characterization, not 100% tested in production

SA25F005 Advanced Information

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Timing Diagrams

All timing diagrams are based on SPI protocol modes 0 and 1.

SCK

SI

CS

t

CSH

t

CSH

t

CSS

t

CSS

MSB IN

t

SU:DATtHD:DAT

t

CRT

t

CFT

LSB IN

t

CS

SO

High Impedance

Figure 4. SPI Mode 0 (0,0) Input Timing

SCK

CS

t

WL

t

V

t

WH

LSB OUT

SO

t

HO

t

V

t

HO

t

DIS

Figure 5. SPI Mode 0 (0,0) Output Timing

SA25F005 Advanced Information

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0.7Vcc

0.2Vcc

0.8Vcc

0.3Vcc

Input Levels

Input and Output

Timing Reference Levels

Figure 6. AC Measurements I/O Waveform

Table 5. AC Measurements

Symbol Parameter Min Max Unit

C

L

Load Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltage 0.2 VCC to 0.8 VCC V

Input and Output Timing
Reference Voltages

0.3 VCC to 0.7 VCC V