A
B
C
D
E
DVA620 REV-A2
ES60X8 + 8051 + PT2320
Layout---------RUTHERFORD REV-A1B1
4 4
Background
This DVD design is based on ESS third generation ES60X8 single chip DVD processor. The ES60X8 is built upon ESS proven
Programmable Multimedia Processor architecture with various speed enhancement and optimization. It supported all features we
developed from previous generation chip plus new features including DVD-Audio (with built-in CPPM logic), built-in TV-Encoder
(Macrovision compliance) and support Progressive Scan output. With the advance of ES60X8 integration, a complete DVD
design can now be implemented with minimum external components.
andy_ho@esstech.com.hk
System Clock Requirement
ES60X8 require a 27MHz clock to operate. This 27MHz can either be generated externally and feed into pin 105 or thru a 27MHz
crystal attached to pin 49 and 50. This 27Mhz will be used for all video processing reference. In addition, internal multiplier will
generate a much higher operating frequency for the internal RISC+DSP code to operate. Audio clock is generated from ES60X8
by its internal PLL circuitry.
Revision History
Rev-A1
1.Base on FYEMANN-A1B1,add PT2320,add MCU,add output.
Rev-A2
1.CHONGHONG DVA620, ADD RDS,AND SPDIF IN, AND
PHONES, CANCLE EQ A/D.
SDRAM Usage
ES60X8 support the use of higher density 4Mx16 SDRAM. This is the prefered choice for simplier design and lower memory cost.
The current DVD code requires only 2Mx16 memory size to operate. This provide an option to use cheaper half-bank 4Mx16
SDRAM. The design has put into consideration to support this type of half-bank SDRAM.
3 3
System Configuration
CHIP
ES60X8
32/64MBit SDRAM
4/8Mbit EPROM/FLASH
24C01 SERIAL EE
SST39VF080
PCM1606
WM8739
SERVO PART
LCSx#
LCS0#
LCS1#
LCS2#
LCS3#
2 2
AUXx
AUX0
AUX1
AUX2
AUX3
AUX4
AUX5
AUX6
AUX7
FUNCTION
Single chip processor that handles all system control and DVD
decoding. Built-in TV-Encoder direct drive a TV set.
Data storage and frame buffer
Program storage
System setup configuration storage
FLASH
6-Channel AudioDAC
2-Channel AudioADC
ATAPI INTERFACE
FUNCTION
SPARE
SPDIF IN CONTROL
SPDIF IN CONTROL
ROM/FLASH
FUNCTION
I2C DATA
I2C CLOCK
ESS COMMUNICATION PROTOCOL WITH MCU
AUDIODAC ML
INTERRUPT
AUDIODAC MC
ESS COMMUNICATION PROTOCOL WITH MCU
ESS COMMUNICATION PROTOCOL WITH MCU
EAUXx
EAUX30
EAUX31
EAUX32
EAUX40
EAUX41
1 1
OTHER
FUNCTION
HSYNC
VSYNC
COMPACT FLASH DETECT SIGNAL
AUDIODAC MD
AUDIOADC CSB
FOR ATAPI INTERFACE
MCU part,please view 6/6 page.
ESS TECHNOLOGY, INC.
Title
INDEX
Size Document Number Rev
DVA620
A
B
C
D
Date: Sheet
E
17Tuesday, February 19, 2002
A2
of
A
Pull high ES60X8 pin 41 to use
DCLK for clock source, no need
VCC
for XIN/XOUT crystal circuitry
R2
4
3
VCC
R8
OPEN
(10K)
12
A0
11
A1
10
A2
9
A3
8
A4
7
A5
6
A6
5
A7
27
A8
26
A9
23
25
4
28
29
3
2
30
31
1
22
CE
24
INSTALL REMOVE TYPE
R31, R34
R33, R35
LD[0..15]
2
4
RP1 47x4
1 8
2 7
3 6
4 5
RP2 47x4
1 8
2 7
3 6
4 5
RP3 33x4
1 8
2 7
3 6
4 5
RP4 33x4
1 8
2 7
3 6
4 5
RP5 33x4
1 8
2 7
3 6
4 5
4 5
3 6
2 7
1 8
RP7 33x4
1 8
2 7
3 6
4 5
OPEN(33)
RST#
C6
OPEN
(47UF)Package: SOT-23 5L
RST#
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA14
LA15
LA16
LA17
R26 OPEN
R28 0 OHM
R29 OPEN
R31 0 OHM
R36 OPEN
C1
OPEN
(22PF)
R33, R35
R31, R34
HD0
HD1
HD2
HD4
HD5
HD7
HD8DD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
1
N
V
2
G
Q
N1 OPEN(27/33M)
4 4
3 3
2 2
1 1
N8
809
EM-MARIN
RESET IC
N2
V6300
8MBIT EPROM
4MBIT EPROM/FLASH
RST#
DRST#
DRD#
DWR#
DIORDY
DIOCS16#
DACS1#
DACS3#
DIRQ
DA0
DA1
DA2
DD[0..15]
ESS CONFIDENTIAL
The information has been checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies. Circuit diagrams are provided as a means of illustrating typical applications; consequently complete information for construction purposes is not necessarily given. ESS reserves the right to make changes at any time in order to improve the design.
VCC
1
GND
2
RES
3
VDD
VCC
D1
1
NC
2
GND
3
NC
4
RES
5
VDD
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
VCC
4-PIN EXTENSION FOR ROM EMULATOR INTERFACE
OPEN
(1N4148)
2 1
N4
13
D0
14
D1
15
D2
17
D3
18
D4
19
D5
20
D6
21
D7
A10
A11
A12
A13
A14
A15
32
A16
VCC
A17
A18
A19
16
GND
OE
27C040/080-90
N6
RESET1CLK/CE1
WE3ADDR/CE1
ROM EMULATOR SOCKET
DRST#
DRD#
DWR#
DIORDY
DIOCS16#
DACS1#
DACS3#
DIRQ
DA0
DA1
DA2
DD0
DD1
DD2
DD3
DD4
DD5
DD6 HD6
DD7
RP6 33x4
DD9
DD10
DD11
DD12
DD13
DD14
DD15
A
LCS1#
LCS2#
LCS3#LA[0..19]
WRLL#
LOE#
LA19
LA18
U1.105
LA[0..19]
EPROM
FLASH
LD[0..15]
27/33M
HRST#
HRD#
HWR#
HIORDY
HIOCS16#
HCS1#
HCS3#
HIRQ
HA0
HA1
HA2
VCC
R13
4.7K
R14
OPEN
Pull high TDMDX
to select 8-bit
ROM boot, pull
low to select
16-bit ROM boot
LCS1#
LCS2#
LCS3#
WRLL#
LOE#
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9LA13
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA21LA21
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
105
173
174
175
176
198
199
170
204
205
206
207
178
179
180
181
182
185
186
187
188
189
190
191
194
195
196
197
145
150
149
143
142
146
151
152
153
144
154
155
158
122
123
124
125
126
127
128
131
132
133
134
135
136
137
140
141
B
TDM-CLK
TDM-CLK
TDM-FS
TDM-FS
TDM-DATA
TDM-DATA
CLK
24
RESET
LCS0
LCS1
LCS2
LCS3
LWRLL
LWRHL
LOE
LA0
LA1
LA2
LA3
2
LA4
3
LA5
4
LA6
5
LA7
6
LA8
7
LA9
10
LA10
11
LA11
12
LA12
13
LA13
14
LA14
15
LA15
16
LA16
19
LA17
20
LA18
21
LA19
22
LA20
23
LA21
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
HRST/EAUX3[5]
HRD/DCI_ACK/EAUX4[6]
HWR/DCI_CLK/EAUX4[5]
HRDQ/EAUX4[0]
HWRQ/DCI_REQ/EAUX4[1]
HIORDY/EAUX3[3]
HIOCS16/CAMPCLK/EAUX3[4]
HCS1FX/EAUX3[7]
HCS3FX/EAUX3[6]
HIRQ/DCI_ERR/EAUX4[7]
HA0/EAUX4[2]
HA1/EAUX4[3]
HA2/EAUX4[4]
HD0/DCI[0]/EAUX1[0]
HD1/DCI[1]/EAUX1[1]
HD2/DCI[2]/EAUX1[2]
HD3/DCI[3]/EAUX1[3]
HD4/DCI[4]/EAUX1[4]
HD5/DCI[5]/EAUX1[5]
HD6/DCI[6]/EAUX1[6]
HD7/DCI[7]/EAUX1[7]
HD8/DCI_FDS/EAUX2[0]
HD9/EAUX2[1]
HD10/EAUX2[2]
HD11/EAUX2[3]
HD12/EAUX2[4]
HD13/EAUX2[5]
HD14/EAUX2[6]
HD15/EAUX2[7]
B
VC33
27
VC33
VCC33VCC33E
VC3359VC3368VC3375VC3392VC33
CHIP
FREQ SOURCE
DCLKINPUT OR CRYSTALOSC 27MHZ
DCLKINPUT OR CRYSTALOSC
ES6018
ES6028
DCLKINPUT OR CRYSTALOSC
DCLKINPUT AND CRYSTALOSC
VCC33
99
104
130
148
157
159
164
VC33
VC33
VC33
VC33
VC33
VC33
25
28
29
31
30
TDMFS
TDMDR
TDMCLK
TDMTSC
TDMDX/RSEL
INSTALL REMOVE CLK SOURCE
R10 X4ES6008
R3
DCLK INPUT
CRSTAL OSC
R3
R10
REMOVE
R11,R12
R4,R12 X3R11,R5
R11,R5
R4,R5
MULTIINSTALL
R4,R5
X4.5
X3.5R4,R12
X4
R11,R12
VCC33P
FB2
FERB
FB3
FERB
1
18
51
111
VC33
AVCC(PLL)
AVCC(VDAC)
ES60x8
VSS
VSS
VSS
NC/CAMVS
42
AVSS(VDAC)
CAMYUV0
CAMYUV1
112
202
203
VSS
VSS
AVSS(PLL)
52
VSS
VSS
VSS
VSS
8
17
VSS
26
34
43
60
67
76
84
91
C
DCLKINPUT
R52
NA
INSTALL
NA
INSTALL
NA
33.3MHzES6038
REMOVE
VCC33
VCC33
VCC33
R4
R3
4.7K
OPEN(4.7K)
R11
R10
OPEN
4.7K
Q1
8050
13
2
9
35
183
193
201
VC25
VC33
VC33
VC33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
98
129
103
120
138
147
156
163
(4.7K)
VCC27
83
121
139
172
44
VC25
VC25
VC25
VC25
VC25
VC25
TWS/SEL_PLL2
TSD0/SEL_PLL0
TSD1/SEL_PLL1
SPDIF/SEL_PLL3
PCLK2XSCN/CAMYUV4
PCLKQSCN/CAMYUV5/AUX3[2]
HSSCN/CAMYUV7/EAUX3[0]
VSSCN/CAMYUV6/EAUX3[1]
YUV0/CAMYUV2
YUV7CAMYUV3
DBANK0/DRAS1
DBANK1/DRAS2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
171
177
184
192
200
208
C
N3
ES60X8
YUV1/VREF
YUV2/CDAC
YUV3/COMP
YUV4/RSET
YUV5/YDAC
YUV6/VDAC
DRAS0
DSCK/DOE
DMA10
DMA11
NC/APLL
48
C16
OPEN
(150PF)
MCLK
TBCK
TSD2
TSD3
RBCK
DCS0
DCS1
DCAS
DSCK
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
DB10
DB11
DB12
DB13
DB14
DB15
AUX0
AUX1
AUX2
AUX3
AUX4
AUX5
AUX6
AUX7
XOUT
RWS
DWE
DQM
RSD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
R5
4.7K
R12
OPEN
(4.7K)
XIN
MULTI
X4
X3.5
39
40
32
33
36
37
38
47
46
45
41
116
117
119
118
106
107
108
109
110
113
114
115
100
97
72
73
74
69
71
70
101
102
53
54
55
56
57
58
61
62
63
64
65
66
77
78
79
80
81
82
85
86
87
88
89
90
93
94
95
96
160
161
162
165
166
167
168
169
49
50
C17
27PF
VCC33
SPDIF
AUX0
AUX1
108.0MHz
108.0MHz
108.0MHz
116.7MHz
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
XOUT
FREQ
CRYSTALOSC
27MHZ
27MHZX4INSTALL
27MHZ
R6
4.7K
R19 33 OHM
R20 33 OHM
R21 33 OHM
R22 33 OHM
VREF
R33 33 OHM
R34 33 OHM
VCC
R44
100K
Y1
27M
VCCV
FB1
FERB
R9
33 OHM
VCC
R39
R40
1K
1K
C18
27PF
Option to use 27MHz crystal at XIN/XOUT for clock
generation, need to pull low ES60X8 pin 41, no need
for DCLK portion OSC circuitry
C4
OPEN
(15PF)
R24 270
RN1 33x4
1 8
2 7
3 6
4 5
RN2 10x4
1 8
2 7
3 6
4 5
RN3 10x4
1 8
2 7
3 6
4 5
RN4 10x4
1 8
2 7
3 6
4 5
VCC
XIN
L5
3.3UH
C19
1000PF
D
VCC
MCLK
SPDIF1
EAUX32
HSYNC
VSYNC
C14 0.1UF
R35 10 OHM
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
DB[0..15]
SERIAL EEPROM
N7
8
S0
VCC
7
S1
WC
6
S2
SCL
5
GND4SDA
24C01A
R52 33 OHM
D
TBCK
C5
OPEN
(22PF)
TWS
TSD0
TSD1
TSD2
VCC33E
R25 0 OHM
R27 open
R30 33 OHM
R32 0 OHM
MA[0..11]
C15
OPEN
(15PF)
1
2
3
R43 4.7K
R45 4.7K
R46 4.7K
R49 4.7K
R50 4.7K
R51 4.7K
27/33M
C11
0.1UF
CVBS and
S-VIDEO
CV
VDAC
YDAC Y
C
CDAC
UDAC
R7
75 OHM
R15
75 OHM
R18
75 OHM
R23
75 OHM
64M SDRAM
32M SDRAM BA0=0
32M SDRAM BA0=1
32M SDRAM BA1=0
32M SDRAM BA1=1
CVBS and COLOR
DIFFERENCE
CV
Y
PB R
PR
R,G,B
E
MODE 8
C
G
Y
PB
PR
B
VIDEO OUT
VDAC
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
6
12
46
52
28
41
54
R47
OPEN
OPEN
OPEN
CLOSE
OPEN
YDAC
CDAC
UDAC
VCCV
1N6263
2 1
1N6263
2 1
VCCV
1N6263
2 1
1N6263
2 1
D2
D4
D6
D8
VCC33
R42
OPEN
OPEN
CLOSE
OPEN
OPEN
CVBS
LUMA
CHROMA
U
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
VCC33
R42
OPEN
R48
OPEN
27Tuesday, February 19, 2002
R48
OPEN
CLOSE
OPEN
OPENOPEN
OPEN
VCCV
1N6263
2 1
1N6263
2 1
VCCV
1N6263
2 1
1N6263
2 1
of
L1 2.4UH
C2
470PF
C7
470PF
C9
470PF
C12
470PF
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
CKE
CS0#
RAS0#
CAS#
WE#
DQMX
BANK0
BANK1
VCC
R25
CLOSE
OPEN
OPEN
CLOSE
CLOSE
ESS TECHNOLOGY, INC.
Title
Size Document Number Rev
Date: Sheet
C3
470PF
L2 2.4UH
C8
470PF
L3 2.4UH
C10
470PF
L4 2.4UH
C13
470PF
N5
23
A0
24
A1
25
A2
26
A3
29
A4
30
A5
31
A6
32
A7
33
A8
34
A9
22
A10
35
A11
38
CLK
37
CKE
19
CS
18
RAS
17
CAS
16
WE
15
DQML
39
DQMH
20
BA0
21
BA1
36
NC
40
NC
4Mx16 SDRAM (9ns)
32/64MBIT SDRAM
AUX2
AUX3
AUX4
AUX5
AUX6
AUX7
R27
R32
OPEN
CLOSE
CLOSE
OPEN
CLOSE
OPEN
OPEN
OPEN
OPEN
ES60X8, Memory and Video
DVA620
VCC33
R41
OPEN
OPEN
OPEN
OPEN
CLOSE
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VCCQ
VCCQ
VCCQ
VCCQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VCC
VCC
VCC
VSS
VSS
VSS
R41
OPEN
R47
OPEN
E
D3
D5
D7
D9
A2
A
B
C
D
E
DD[0..15]
DD[0..15]
DRST#
DRST#
4 4
DWR#
DWR#
DRD#
DRD#
DIORDY
DIORDY
DIRQ
DIRQ
DA1
DA1
DA0
DA0
DACS1#
DACS1#
DACS3#
DACS3#
DA2
DA2
EAUX32
DIOCS16#
DIOCS16#
VCCVCC
R54
R53
4.7K
4.7K
DECOUPLING CAPACITORS
3 3
C211
0.1UF
C220
0.1UF
C229
0.1UF
C212
0.1UF
C221
0.1UF
C230
0.1UF
VCC33
C209
0.1UF
C210
0.1UF
C219
0.1UF
C228
0.1UF
ES60X8
ATAPI DVD LOADER CONNECTOR
XS5
RESET1GND
DD15
3
D7
5
D6
DD13
7
D5
DD12
9
D4
DD11
11
D3
DD10
13
D2
DD9
15
D1
DD8
17
D0
19
GND
21
DRQ
23
IOW
25
IOR
IOCHRDY27BALE
29
DACK
IRQ1431IOCS16
A133RESERVED
35
A0
37
CS0
ACTIVITY39GND
HDR20X2-100
VCC33EVCC27
C213
C214
0.1UF
C223
0.1UF
C232
0.1UF
0.1UF
C224
0.1UF
C233
0.1UF
C215
10UF
C222
0.1UF
C231
0.1UF
N27
LA0
21
GND
2
A0
20
A1
19
A2
18
A3
17
A4
16
A5
15
A6
14
A7
8
A8
7
A9
36
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
40
A17
13
A18
37
A19/A-1
22
CE#
24
OE#
9
WE#
10
RESET
SST39VF080
TSOP40:1MX8
1
VOUT
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LCE#
+9V
Q5
LM7805
3
VIN
C218
10UF
VCC
We use LCS#2 to burn Flash and
then use LCS#3 for running !!!
R81 10 OHM
+9VD
+9VA
+9VV
LCS3#
LCS2#
LOE#
WRLL#
R87 10 OHM
FB5
FERB
FB6
FERB
FB8
FERB
220UF
LCS3#
LCS2#
LOE#
WRLL#
C202
2
DD0
4
D8
DD1DD14
6
D9
DD2
8
D10
D11
D12
D13
D14
D15
KEY
GND
GND
GND
GND
CS1
DD3
10
DD4
12
DD5
14
DD6
16
DD7
18
20
FB9 FERB
22
24
26
28
30
32
34
36
A2
38
40
VCC33P
C217
C216
0.1UF
10UF
C225
0.1UF
0.1UF
C235
C234
0.1UF
0.1UF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RDY/BUSY
VCC
VCC
GND
GND
FB7
FERB
LD[0..15]LA[0..19]
RST#
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LCE#
LOE#
WRLL#
RST#
LD0
25
LD1
26
LD2
27
LD3
28
LD4
32
LD5
33
LD6
34
LD7
35
38
NC
29
NC
12
11
VPP
31
FLASHVCC
30
23
39
VCCA
VCC33 VCC
R108
10 OHM
N34
25
A0
24
A1
23
A2
22
A3
21
A4
20
A5
19
A6
18
A7
8
A8
7
A9
6
A10
5
A11
4
A12
3
A13
2
A14
1
A15
48
A16
17
A17
16
A18
26
CE
28
OE
11
WE
12
RST
47
BYTE
A29800
TSOP48:512KX8,1MX8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
LD0
29
DQ0
LD1
31
DQ1
LD2
33
DQ2
LD3
35
DQ3
LD4
38
DQ4
LD5
40
DQ5
LD6
42
DQ6
LD7
44
DQ7
30
DQ8
32
DQ9
34
36
39
41
43
LA0
45
13
VPP
14
WP#
15
BY#
0 OHM
FLASHVCC
37
VCC
46
GND
27
GND
R1
BURR-BROWN 6-CHANNEL AUDIODAC
VCCA VCCA
ML
MC
TWS-
20
19
18
17
16
14
1
2
3
4
5
6
N9
SCKI
BCKIN
LRIN
DIN0
DIN1
DIN2
FMT1
FMT0
DEMP1
DEMP0
VCOM
ZRA
PCM1606
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
AGND
15
VCC
L
10
R
11
LFE
12
Ls1
13
C
8
Rs1
9
7
C21 10UF
C22 10UF
C23 10UF
C24 10UF
C25 10UFC226
C26 10UF
AOUT0L
AOUT0R
AOUT1L
AOUT1R
AOUT2L
AOUT2R
C203
220UF
TSD0
TWS
TSD1
TSD2
TBCK
MCLK
AUX3
AUX5
R62 33 OHM
RP11 33x4
1 8
2 7
3 6
4 5
R57 33 OHM
R58 33 OHM
C27
0.1UF
TBCK-
TSD0-
C28
10UF
TSD1TSD2-
CAP
C236
C237
10UF
C241
0.1UF
SDRAM
C238
10UF
C242
0.1UF
24C01
C250
0.1UF
C243
0.1UF
C244
10UF
C245
10UF
C204
220UF
MCU+5V -9VVCC
C205
220UF
D
VCC
VCCAVCC
C251
0.1UF
C246
0.1UF
PCM1606
C252
0.1UF
B
EPROM
C247
10UF
C253
10UF
3.3V REGUALTOR
Q2 OPEN
IN3OUT
C20
OPEN
(10UF)
No need to install
EZ1085 circuitry if
J12 provide +3.3V
ADJ
1
(EZ1085)
2
R59
R55
820 OHM
820 OHM
1%
1%
R56
750 OHM
1%
C
C208
OPEN
(100UF)
ADJ
FRONT
EZ1085
OUT
INP
C206
220UF
+9V
DVDMUTE
POWERDOWN
C207
220UF
ESS TECHNOLOGY, INC.
Title
Loader Interface, Audio and Power
Size Document Number Rev
DVA620
Date: Sheet
XS1
1
2
3
4
5
6
7
8
9
HEADER 9
E
A2
of
37Tuesday, February 19, 2002
10UF
2 2
1 1
VCC33 VCC VCC33
C240
C239
0.1UF
0.1UF
VCC
C248
0.1UF
OSC
C249
10UF
ESS CONFIDENTIAL
The information has been checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies. Circuit diagrams are provided as a means of illustrating typical applications; consequently complete information for construction purposes is not necessarily given. ESS reserves the right to make changes at any time in order to improve the design.
A
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