Roland MicroComposer MC-4 Service Notes

JAN.13,1982

MC-4

MC-4

[SERVICE

NOTES

SPECIFICATIONS

First

Edition

Memory Capacity

MC-4A [w/out

OM-4]

apst

3900 notes

|1

&

K byte

version]

MC-4E[withOM-*]

apx 12000

notes

[4«

K byte

version]

"

OM^s

optf oral

memory board

with

interface tOr MTR-IOO

Output

4 channels

each

channel h^:

CVO

[OV-ia.-^ZV.

125

steps,B3.3mV/step]

CV-2

[0

V-1 0.42V,T

23 steps,

33.3 mW;Stepl

Cat«

[off

=

0V,on^12V]

MPX

[QH

=

0V.on

=

l2V]

Ut

Input

cv

[OV~1043V]

Cat£

[thfeshoJd

+2,5V]

Calibration Knob

Teir(p<i

CV Inpyt

CV [OV-10.42V3

EdtSrnc

Input

[thresiiold

+2 5V]

Output

I0-5V]

Total

Tune Knob (+/- loo ctnts]

T«mpo

Knob

[-50%

to

+100%)

ShiHMip 7: CVl + GATE a:

GATE

REWRITE 9

TUNE

4;CV2

5:MPX

TCVI 3'

STEP TIME

3: GATE TIME

0:

Available

Mpfriory

{%:

Dimensions 47^x343x1

24 mm

Weight

61kg[MC-4Al,6Jks(MC^B)

Power 30W

Hs^t$inkH2&{04BK025l

Sida

panel HSSB

[0S1

H03S'2)

Psne!K74C i07aHO74Ci

Key

switch

KEH10903

(13129714)

Key iopKT3-1

blLie, ivory

!

12479705)

Key

:op KT3 2

2479704)

lOKevassv

KEH4A006 (13129716)

^

Switch

SLE722-18P (131391321

"

TCS0 2EO'1-'3 {13429608)

HU-102-]-^

!1

34492201

FCM-7CI4Q034

AU/L {13439173)

COMTROL

BOARD

0PH141

t149Hl4T)

JACK eOARD 0PH142 !149H142)

&idB

panal H37B

(0S1H037-2)

Covar HB2B

{O65H0S2B1

Jack

HSJ0779-01^1Cl

(13449406MI

^NECTOR BOARD

0PH144

[149H144)

iWER

SUPPLY

PSHS6

(100V) (146H066}

RAM BOARD

0PH143

{149H143)

Pot

EVHLWAD25B14

(13219312}

^Switch SUE

623-TSP

I13T39135)

Pot

VR1CIRS20A15 (13219601)

Knob K -34 Type

(M)

(2247540600)

CPU

BOARD OPH 140

(149H140)

CHASSIS Hi 12 (061

HI

12)

PAMEL

OPENABLE

SCREWS

SELF

TAPPING

3 n 6mrr>

BINDING

ai Br

SwfTChSLE522'18P

{13139136)

IS

Roland

Printed

in Japan

1-2

MC-4

JAN,13,1982

MTR-100

Connector

Board

POWER

Cassette

Tape-

Transport

MT-2

MC-4

CPU

1G31

BUFFER

IC13
IC15

ADDRESS

BUS

DATA

BUS

ou

10K Byte ROM

IC32-IC36

nil

16K Byte RAM

IC1-IC3

CONTROL

BUS

-^'

_jji

:t_

CLOCK

OSC

IL

TIMER

IC30

ITC

CPU

BOARD

1

[

1^^,otg^?

Pq":P?_

.

ELCK

READ

SEL

4^av

r"

BUFFER

IC12

A

32K

Byte

RAM

ICMC8

IC16-tC23

CONNECTO

R

BOARD

n

BUFFER

fC27

B

BUFFER

JC12

C

1

iC12

CM

Digital

Cassette

Interface

UT

I/O

PORT

(8

bit X

6)

IC29,

I CBS

Audio

Cassette

Tape,

Sync

I

nterf

ace

D/A

S/H

LATCHES

A-CMT

SYNC

CV

GATE

MPX

1

^

i

I

i

I

DISPLAY

LED

RAM

BOARD

{OM-41

"n

KEYSW

MATRIX

J

1

I

I

SIGNALS THROUGH

RAM

BOARD

CONNECTORS

RS0^RS2

:

ADDRESSES

A0-A2

Select

one

of

MT-2

internal

8

registers.

DO-D?

:

PARALLEL

BUS

Transfers 8 bit data

from

/to MT-2,

ELCK ;

SYNC

CLOCK derived

from

CPU

CLOCK

Controls MT-2 MT-2

operations.

READ :

Signals

MT-2

direction of data

flow on

the

data

buss.

SE L

:

Indicates that CPU

nam^s

MT 2.

Gates

Buffers A, B

and

C.

-I-5V

:

Informs

I ntarface

that IVtT-2

power

is

ON,

JACK

BOARD

CONTROL

BOARD

MC-4

JAN

.13,1982

{Top

Vitfw)

^PD7S0

C/D-(

8 BIT

MICROPROCESSOR

1}

CPU AKD

5T^5TEH

CONTROL

SIGNALS

ADDRESS

BUS

A14,

A15

Used

to

select

the

follt>-wing

memory

blocks

through

respeotive

Address

Decoders.

Address

Decoder

IC60'

IClOj

IC12

1024,

1025

Memory

TO'52-1036

ROKq

on

CPU

Board

IC1-IC8,

RJU^s

on

CKf Board

IC1-IC8,

IG16-I023

SJffls on

HAM

Board

A0^A7

Used

to

select

1/0

DeYices

through

Port

Addresa

Decoder

1C57

on

CPU

Board.

(See

I/O

MAP

right)

1029\10]

D/A,

MODE

LED

Display,

DIH

OUT,

A/D

IN,

Clock

Out,

^-^

CYCLE

3W IN

IQ5o[40)

Timing

Signals

generation,

-Total

Time

measurement

IC58r77ri

Key

Scanning,

Dot

Display,

iXIetronome,

Mode

sw

IN,

i^

DIN

IN

Tiie

numbers

|4ol

,

[60|

and

[to]

above,

also

shown

in

the^CHj

circuit

diagWn,

We

abbreviated

J/0

divice

numbers

±n

hex,

to

be

represented

on

address

bus,

that

is

x

x

4

x,

iC x b

x

a:id

X

X

7

X. If

bits

0111

(7)

appear

on

A7-A4,

IG57

selects

IC29.

Then

bits

on

Al-AO

will

cause

one

ot

the

following

in

IC29

to

be

selected;

00-Port

A,

01-Port

B,

10-Port

and

11^

Control

Word

Register.

Similarly,

if

0100 (4)

are on

A7-A4,

IG57

selects

IG30, and

00

on

Al-AO

Counter 0.

^PD8255C

PROGRAMMABLE

PERIPHERAL

INTERFACE

2A

Programmable

WO

Pins

BASIC

OPERATION

APDS253C-5

PROGRAMMABLE

IMTEflVAL

TIMER

3

Ind«p«nden1

16-Blt Counters

SND

d

pc(**Qi

PCo-{i±

PCi**[i5

pci-*!

PCs*-

EI

PBi**[i|

PB2'

*PAl

:l]«PB.s

1/0

mr

40

IC50

8253

'jO

EXT

MTR-100

60

IC5S

8255

70

IC29

8255

DATA

BUS

Used to

transfer

Instructions

and

Data

to/from

l/O

Devices

and

HAJ4s,

4MHs,

square

Clock

signal

derived

from

devide-by-2

divider

ICIS

^

An

HO

WH

S

INPUT

OPERATION

[REAOl

t

1 D

POFIT

A-DATABUS

r>

\

1

POfiTB-OATA&US

1

1

1

PORT

C-CJATA

BUS

OUTPUT

OPE

BAT!PN

WRITE]

n 1 a

tJATABUS-PORT

A

f>

;

1

DATA BUS

-

PORT B

\

1

DATA

BUS-

PORT C

1

1 a

DATA

PUS

-fCONTROt

DISABLE

FUMCnON

X

X x X I

DATA

BUS-

J-STATE

1 t

1

ILLEGAL

CONDITION

x: X

1 1

Q DATA

BUS-

J-STATE

D,

^

D,

»

D,

*

Do*

CLKO

»

OUTO*

GATE

'

GNDo

<-

2*

2S

21

10

19

1&

P

17

IS

ID

I]

14

13

13

.,

*o

A;

A.

CLK2

OUT 2

GATE

2

«

CLKl

CATEl

In

the

MCA

B25&C

operates

in

MODE

and

8253

in

different

MODEs.

ED

¥R

IHT

NMI

VIAIT

Ml

RESET

cs

RD

WH

At

Ad

1

toadCouniBrNo.O

B

\

(.Mci

CoumsF

No.

1

1 D

1

Load

Counter

No. 7

1

»

VJfilt

Mode

Word

1

CI

RmiJ

Coumer

No,

1

Read

Cojrbter

Nd,

1

n }

1

Read

Coumer

No. 2

Q

1 1

Nrj

OpwratlDn

3-StBt«

1

X

X

X X

DiwblE:

3-StaW

%

1 X X

No-Operation

3-Sut*

Indicates

that

the

address

bus

holds

a

valid

memory

address

for a

memory

read

or

memory

write

cycle.

Indicates

that

lover

3

bits

(I/O

Device

tober)

are

on

the

address

bus

for

an

l/O

read

or

I/O

write

cycle.

Indicates

that

the

GPU

wants

to

read

data

from

memory

or an

I/O

device.

Indicates

that

the

CHJ

data

bus

holds

valid

data

to

be

stored

in

the

addressed

memory

or

I/O

device.

Used

as

Tempo

GlocK

in

PLAY

mode

and

is

accepted

by

the

CHJ

after

it

completes

the

current

instruction

being

executed

provided

that

CPU

internal

INT

enable

flip-flop

Is

set on.

Used

to

time

the

lightings

of

Dot

Matrix

Display

and

•

Shift

lEDs,

Key

Switch

Scanning,

and

the

outputtmgs

of

CV

and

GATE.

Accepted

by the

CPU

unconditi-onally

upon

finishing

of

current

instruction.

Used

to

keep

the

CPU

wait

for

1

clock

cycle

to

Provide

enough

performance

time

for

relatively

low

speed

ROM

and

RAM being

accessed

by

the

CPU",

Indicates

Fetch

cycle.

Used

to

reset

and

start

the

GPU

from

a

power

down

condition

resulting

from

failure

or

initial

start-

up

of

the

processor.

CIRCUIT DESCRIPTION

JAN.13,1982

CPU BOARD

when

CPU

is initialized with power-on

RESET

signgi,

it wants

to read

operational program

(software

-

instruction) stored at address

(QOOOJi*

to starts controlling the

MC-4.

With

Os on

the

addreES

bus [All

A15) and

MREQ,

ROM

Address

Decoder IC60 selects ROM [a]

IC36

which

in turn transfers

data

from

accessed memory cells

to DO D7. CPU proceeds

steps with

fetch&d'

instruction.

The following

Is

one of steps wilt be done.

(1)

To transfer

d9ta

to or

fronn

RAMs

(2)

To transfer

data

to

or

from I/O ports or Programmable

Tinner

ADDRESS

MAP

ft

_l

Ti

l^

Tj

AO~/^lS^

1

IC

1

fi.Zli

MJltfl

"

W

J

'

WA3T

„

.J

U.

SiT

-

1

J

r^ 1

vSi^

0000

27P?

ROM0 IC56

ROM

AREA

IlOMjYj

IQYd

BLAHE

4000

ICl-ICS

(CPU BOARD)

Rjm AREA

ICl-ICS

(RAM

BOARD)

(RAM BOAED)

6000

cooo

{1>

Accessing 1o HAMS ICl-IGS

The

CPU

places

RAM address onto Address bus,

then

outputs necessary

signals

as

shown in Fig,

2.

Eight 16K X

t bit

RAMs

are

connected

in

parallol

to

form

a

16K

)c8 bit

^

RAM

block.

The

14 address bits required

to

decode 1 of the 16,384 cell

a9-xU

locations within M5K4T15 are

multlptexed

onto 7 address inputs

ICffifq

(A0-A6-) of RAMs, First,

low&r order

7 bits ara fad

to

RAM$ through

f^

RAM Address Multiplexers

(I

C9

and

ICl

1

) and latched

Into

the RAMs'

on-chip ,gddres5

latches by HAS. Second, higlier

order

7 bits ara fed to

"^

the

RAMs when SEL pins of IC9 and

IC11

go Sow by the delayed

t]o~dt

MREQ coming

th

rough pjn

8

of

fC12.

Thess

7

bits

are latched into

wait

RAMs'

chips

with

CAS

fed

via RAM Address

Decoders

(iCTOand

IC12),

and

an acGes to RAMs completes.

Data are

stored into selected cells by

a combination

of

WRITE a nd CAS, qr

re^trieved

from the memories

in a read cycle in which

CAS

is

actJ'vt

low.

OJk

CONVERTER

The digital

outputs

from

the PORT

A of INTE RFACE

\

\ C29| are level-

shifted by

the

transistors

{TR5-TR11), pa$s through

the

CMOS

INVERTERS

(IC27,

!C2a),

and

undergo addition by the

weighing

resistors

to become

an

analog

voltage. Since

the MC-4 has

eight

CVe,'

eighi

data

are sampled in

the

tine sharing

system by

the

4051 DMPX

!IC46^h?|[Jbythe

081

(IC47-fC54]

and

output to

the

output jacks.

The resolution

of the

D/A

converter

is 1/'12V, which

corresponds

to a

half-tone

Etep

voltage.

The resistance

error

at the

most sfgniflcant t>it,

which affects

the output

error

most significantly,

is

corrected by

adjusting the

VR3,

The VR2,

equivalent

to

the width control

of

a

synthesiser,

should be

adjusted

so that the

output changes in

1/12V

step.

The VR4 is used

for

offset

adjustment

of

IC25.

For the GATEs

(GT1-GT4)

and

MPXs {MPX1-MPX4), digital

data

are

sampled

by IC43

in the tinie

sharing

system [see

Fig.

4).

CMT

BUOCK

Thi5 block

is

composed of

the

input/output

circuits

for

CMT DATA

and TAPE

SYNC

CLOCK,

Th&

selection of

CMT

mode (CMT DATA}

and

PLAY

mode

[TAPE

SYJ^C)

IS don& by tha hardware

(IC41).

The output

section

delivers an

approximately

2JKH!;

signal

wher>

the

DIGITAL

DATA

is H and

an

approximately

I.SKH::

signal when

the

data is L

(see J^ig,

5}.

M

T.

Tr

T,

Mrr,*Qr,WrJtcCjTrlt

^

T,

T.

T.

—

1'"

^MftijOU. .

1

nynnr

w^in

i

l|

\^

_r~

\

i j

\_

,. . ;

rpi

I U

DtmDtT

>"

.J L

.

ij

L

(2)

Accessing to Timer IC30

or lyo Ports

IC29 and IC58

The CPU

places port address (lower order

8 bits, A0-A7] onto the

address

bus, then outputs lORQ, etc.

as

shown

in

Fig.

3.

As

previously

explained in CPU terminal

functions

"ADDRESS BUS",

Port

Address Decoder ^IG571 selects the

device

which in

turn

reads or

writes

data.

iirr:

_r

r

MPxV

\

\

\\

\

GT

'^

GT \

GT

\

QT

\

4 3

\

2

\

1 \

MPX

MPX MPX

C

1 1 1

I Q

B

110

110

A 1 1 1 I Q

Fig. 4

S.6Vpp (appr&x.)

JiMJiiJijmriJiiuiMMJUii^

Fig. 5

Fig. 3

For

frequency

modulation.

IC4:2

is wired as a

function generator

whose

frequency

shifts

to the

other

as R121

is

connected to

distjonnected

from

charging/discharging

time constant

by

F£T

SW (TRT5|.

The

zen&r

diodes (D11,

Dl2) are

used

to prevent tiie

output

of the

comparator

OP amp

[operating on

413V arid

-15V)

from

becoming

ur^balanced

and

to

keep tfio duty ratio

of

the oscillation

square wave-

form

to

50%. At the

input section, a

signal

from the

CMT/SYNC

IN

passes

through

a

passive

band pass filter

and rs ampljfied

by

the

OP amp

(1023). The

signal

funher

pas&es through a diode

limitler,

is amplified

by !C22

and is

separated

into a signal

for

control

and

a signal for

denriodulation,

The

signal

fordemodulation

is

democfulat&d

bythePLL

(IC19) and the

comparator

{IC20) and

is

read via tha

S255

INTERFACE

{IC5S).

The

signal

for

control

passes through

a

rectification

circuit

and

Is

applied TO

the

tr&nsistor

switches

(TR^,

TR3t to set

TP3 in active

state.

(While the

CMT or SYNC

signal is not

inputted,

TP3 is

fixed

at L level.)

ISee Fig,

6,|

i«5

-^

7

juirurLrumjUL

^

J

I I

I

Fig. 6

CONTROL

BOARD

DOT

display/

SHIFT

LEDs.

KEY

SWITCHES

These

circuits

^re

configured

in

separate

matrices in a

conyenlional

fashion

but

one

dimension

of

these

share

the same output

pins

of

an

address

decoder

1C1.

The

address

decoders

(IC1

and

IC2

in

combination)

places

an

I

at

output

pins

in

sequence

in

symathy

with

NM1

cIogI<

brought

into

th^

pin

€f

CPU

as

shown

in

Fig.

7.

The

following

description

will

explicate

Dot

Display

only

since

Shift

UEDs-

and

KEY-

scanning

are

self

explanative,

^...p \

PCS

(23}

Q

ADDRsi

PC2<21)

Q

Q

PCI

[19)

D

1

1

PC^[17|

10

1

Fig,

7

DOT

DISPLAY

Character

signal

consistirig

of

&

x 7

dots

from

the

Dot

Matrix

Decoder

IC9

is

applied

to

fluorescent

lamp

indicator

16'MD-02Z

In

which

the

same

dots

in

the

Individual

digits

are

connected

in

parallel

and

led out

as

a

common

terminal, and

the digit

electrodes

have

indtvldual

leads

(G1-G15)

for

externa!

connection.

Although

the same

dot

signals

are

fed to

all

digits

simaltenousiy,

only

one digit

whose grid

is

now H is

allowed

to

illuminate

-

called

dynamic

lighting.

But for

human eyes

those

flickers

are not

perceptible.

Since

filament

laid

across

the

tube

serves as a

common

cathode for

all

digits,

DC

heating will

cause

brightness

imbalance

among

digits

due to

potential

variations

between

el&ctrodes

and the

chathode.

METRONOME

Output

from

oscillator

IC7

is shaped

into

metronome-lick

sound

with

percussive

envelope

developed

In Tr35,

C5 and

R1

16

circuit.

TEMPO

CLOCK

GEMERATOR

When

nothing

is

connected

to

the

TEMPO

CV

jack,

a

constant

DC

voltage of

approximately

4.17V

is

applied to

pin

5

of

tC6

when

the

TEMPO

control is

set at

the

center.

The

voltage is

applied

to the

VCO

through

106

and IC5,

and

the VCO

oscillates

at

approximately

lOOKHz,

Since

the VCO's

oscillation

frequency

changes

linearly

to

the

input

voltage,

when

the

input

voltage

is

doubled,

the

oscillation

frequency

is

also

doubled.

When

the

linearity

is

improper

{especially

at

the

high

frequency

range),

the slew

rate

of

IC3 is

slow

or

TR31 is

defective

in

most

cases.

When an

external

CV is

applied to

the

TEMPO

CV

IN

jack,

the

TEMPO

CLOCK

is

subjected to

frequency

modulation.

JAN,13,19a2

MCr4

C3

DZ

Metal

film

CRB2&DZ(0,b%25PPM)

Q

2SC1815-GR

-3 aO

Carbon

R-25J

O

cr>

Metal

film

CRB25FX(1%100PPM)

#HCrJ

Metal

film

CRB25DY

(0.5%

SOPPM)

1"'^

*Crj

Metal

film

CRB25BY

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12 13

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at

the

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display

hy 12 at

every

step as

shown

below.

J}lote

that

the

data

displayed

on

indicator

lamp

precede

actual

data

by

one

step-

Lata

displayed

Ac

tiial

data

OVl

(To he

+lraV)

volt

12

0.000

24

12

1.000

56

24

2. 000

48

35

3.000

60

48

4.000

72

60

5.000

84

72

6.000

96

84

7.000

108

96

8.000

120

103

9.000

. .

.

120

10.000

(

120

10.000

)

-5

Adjust

VE2

to the

tahle

above.

Use

VR3 to

compensate

for

higher

CV only

(data

72

and

above).

14

5

CMT

FREQ

5-1

Flip

MODS

for

PLAY.

5-2 Vith freq.uenc7

counter

connected

to TP-4

adjust

VR6

for

1.31^a+5?&.

5-5 Verfy

that

frequency

changes

to

2.1kHz

+5?£

when

mode is

set to

Om.

6

PLL

FREQ

prrl^l

CC^Y

m

xio

30

JSj

111-1

1

f

1 SI

112-

n

)

1 3o|

Isimultaneou

h

1

1

M

|l 1 1

isl

ll

1

1

51

ii

^ ^

_^

h

1

1

&1

|i

1

2

-

6-1

Connect

CMT/

SYNC

I!T

Emd OUT with

a

cord.

6-2

Connect

scope

to

TP-5.

5-5

Input

data by

following the

chart

shown at

the left.

"Waveform

will

appear

on the screen.

n

1

101

-1

1

cycle

LTLJTJI

Li i

1.

1

_p

AiB

=

1:2

IKK

1

B:G

= 1:1

6-4 Adjust

VR5 for

50

duty

ratio

except

A portion*

VJhen

waveform

disappears

during

adjust-

ment,

push

[T]

and

[i^J

.

In

a

few

seconds

waveform

will

reappear.

T

h 1

1001

^

M00ESW2

(flip

MODE

twice)

1

CMTCVREF

CAUTION

If

trijaimer

wiper is

frozen,

try

adjusting

at

component

side.

PAIHT

LOOKED !

1-1

et

controls:

TOTAL TUNE
TBMPO

center

center

[IB

r2D 30

is]

e:

o Vk4

VKl

o

o

V^2

(view

from foil

aide]

1-2 Connect

GH-4

aV2

and

TBMPO

CV

IH jacks

with

a cord.

1-3

Input data as

shown

right.

^^

¥hile plugging

out

and

in the

cord at

TEMPO CV

IN

jackj

adjust

VR4

so that

"time" being

displayed remains

unchanged.

CONTROL

BOARD

2

CMT

FREQ, LINEAR, OFFSET

2-1

Observe steps

1-1

and

1-2

above

-

2-2

Enter

data as

illustrated

at

right.

2-5

Connect frequency counter to

collector

of TR2S.

2-4

Adjust VHs respectively for the

frequency in the table

below.

To

change

data

push

FWL

,

First,

coarsely adjust

TRJ>

for

lOOkHz,

then the remainder

.

2-5 Repeat

adjustment

until

correct

frequencies

are

obtained.

ENT

^NT
ent

COPf

[E

EnttI

1

4

;oi

1

0V2 YR Preq,

10

7E2

20kHE

50

YR5 lOOkHz

100

imi 200kHs

flip MODE for

PLAY

[4"

IM 4.'?!

EVT

ENT

^MT

no 30

fsl

|4

1

1

-

|4

T

4

H

K"

1 1 5*1

EH

15

PARTS

LIST

CHASSIS

Oe^Hlia

chassis

Hn3

061

H1

12

CtiaSSisH112

0S3HQ37

Side

panel

H37

(right)

Cie3H03B

Slds

panel

H3S

{lehl

072H074

Pa^el

H74

Q48H02&

Heat

sink

H25

116H0CI5

Jqintscr&w

H5

065H0B2

Cover

H82

ifluorescent

lube)

D66H091

Cover

H31

(rear

cover)

KNOB

2247540600

K34

TYPE

METAL

KEY

TOP

12479704

124797D5 ,

134492^0

1

344940600

KT3-2

blue

[tandem)

KT3-1

iyory,

btue

HUl

02^01

010

HSJ-779-OI.O'EO

(miniy

SLIDE

SWITCH

13159113

SSB042-6LS

POWER

SWITCH

13U9103

2WiXll

LEVER

SWITCH

13T3913&

SLE-622-18P

ICYCLE)

13139135

SLE-623-1S?

(5YHC)

13139132

SLE722-18PIMODE>

KEY

SWITCH

13129714

KeH109O3wrskevtop

1312^716

KEH4A006f10KEYASS'Y}

PCB

149H140

I49hll4t

149H142
149H143

149H144

146H066

M6H067

CPU

BOARD

OPHl40(pcbO52H249C}

CONTROL

BOARD

0PH141

[pab

052H250E)

JACK

BOARD

OPH142

(pqb052H285C)

RAM

BOARD

0PHt43

(pcb052H333C)

CONNECTOR

BOARD

OPH144

Iptb

0b2H3311

POWER

SUPPLY

eOARD

PSHeS

(pctj052H251Al

100/n7V

POWER

SUPPLY

SOARD

PSH77

^pcb

052H2&1

A)

22C/240V

15169301

HO

15169303HO

1516Q346BO

1516930480
15169335HO

15169347BO

15169311HO

15169340BO

15169318H0

15169319HO

15169332HO

15169324CO

1616932SHO

1516^117

151891160A

15189117

15189118

151891

11

NO

15189105

1&219105

15159104TO

151591

12T0

15159113HO

1&1S9117TO

1515912C1TO

15159309TO

TRANSISTOR

15129816

15129606

15129&0O
15119402

1&119123
15119113

151196Q1

15129121

1

51

29703

1512913200

15129114

15139103
15139110

74LSO0

QUAD

2

INPUT

NAND

74LS02

0UAD2-INPUT

NOR

74LSa3

HEX

INVERTERS

74L504

HEX

INVERTERS

74LS20

DUAL

4-U^PUT

NAM

D

74LS32

QUAD

2-lNPUTQR

74LS74

OI-IAL

D-FFs

WITH

PRESET

AND

CLEAR

74L5132

QUAD

2.INPUT

NAND

SCHP^ITT

TRIGGERS

74LS138

1-0F-8

DECODER/DEMULTIPLEXER

74LS139

DUAU1-0F-4

DECODER

74LS157

QUAD

2-INPUT

MULTIPLEXER

74LS245

OCTAL

3-STATE

BUS

TRANSCEIVERS

74LS36a

HEX

3-STATE

INVERTER

BUFFER

7407

HEX

0,C.

BUFFERS

TLOflOCP

OP

AMP

{factory

selected)

TL0B1CP

OP

AMP

TL0B2CP

OP

AMP

^PC3nC

OP

AMP

;jPC4558C

OP

AMP

LM565

PHASE

LOCKED

LOOP

TC4011BP

QUADRUPLE

2-fNPUT

NAND

GATE

TC4049BP

HEX

BUFFER/CONVERTER

(IMVERTING)

TC4051BP

G-CHANNEL

ANALOG

MULTIPLEXER/DEMALTlPLEXER

TC4070eP

QUAD

EXCLUSIVE

''OP"

GATE

TC4099BP

3

BIT

ADDRESSABLE

LATCH

TC452eBP

DUAL

MOWOSTABLE

MU

LTlVIBRATOR

SEMICONDUCTOR

1C

15199116

;,PC14312H

3-PIN

REGULATOR

ITA7S012P)

15179111

;iPD7a0.1

B-BIT

MICROPROCESSOR

(LH-QOSOA)

15179306

MBB11SN

16,384

X

1-BIT

DYNAMIC

RAM

1B179605BO

M&L27t6K

16K

(2K x

81

UV

ERASABLE

PROM

(i^Basisi

15179110BO

M5LS253P-5

PROGRAMMABLE

INTERVAL

TIMER

[iiP

08253-51

15179120

LI204e

5

« 7

DOT

MATRIX

DECODER

15199^09NO

MPC7BL05

3-PlM

REGULATOR

1S17S12S

*JpDS2^^''^

PROGRAMMABLE

PEFllPHERAL

INTERFACE

(MSL8255AP}

DIODE

15019247

150

1920S

1501^123

15019103
1501&624

15019B31

15019532
15019612
1501962B
15029103

t 50291

05

15029133
15019250

15019243

2SD380-Y

or

0,

GH

2SD844-Y

2SD571-L

2SA682'Y

2SA1

175

JF or

HE, FF.

EF,

K^F,

|2SA11

15-E

or F),

(^A937^

2SA1015-GR

2SB605^L

2SC202VRDrS

2SC1226

A

2SC1923-0

2SC1S15-GR

2SK30A

G R

MF510or2N4392

GP-30G

(Hi-Fi

Special)

1SR35-200

1

SI

585

1S2473

1SZ52

DSZ7.5Y

5Z36

X

0525.1

X

05Z5,6-U

TLR124

[redl

TLG124Atgrn)

TLY124

(yel)

D65BN'M

1B4B1

1

BO29703

16MD

02Z

fluorescar^t

lamp

ir^dicator

POTENTIOMETER

ROTARY

13219601

VM10R-S2aA1b

[lOOKA]

TEMPO

13219312

EVHLWAD25B14

(10KB)

TRIMMER

SR19R

13299111

2,2K&

13299114

10KB

13299115

22KB

RJ-6S

132993D6

50OnE

13299307

1KB

RJ-6P

13299131

20KB

RESISTOR

CRB25FX(1%+lDDppm/°Cl

137691S2DO

1.3K

1376918900

47 K

137691

97

DO

10OK

13769201

DO

150K

CRB25DZ

[0.5%

+25ppmrc}

13789601

DO

100K

13789602DO

T30K

CRB25BY|0.1%+50ppmrC)

137S9501DO

UK

137B95Q7DO

31K

137S9503DO

125K

1378950400

250K

CRB25DY

(0.5?£

+50ppmr'CI

1

378911300

600

K

137S9114D0

1M

ARRAY

13919108

4R7Kx4(RC3SD4x472K)

13919109

4R7KxS^RGSD8x472K]

13919110

22K

k8(RGSD8x223K)

M0'4S

138391

43 FO

0.33n

3W

13S39145F0

82t^

3W

FLAT

CABLE

D&3H131

FLAT

CABLE

K1 31

053H132

053H133

053 HI

34

IC

SOCKET

13429S1

1

1

3429608

13439178
13429179
13439176
13439177

13439120

13439121

13439122

13439126

OTHERS

22

15050

100

2215050300

065H090

065H19G

064H055

D64H0B3

064Ha92

064H111

107H061

NOlSe

FFLTER

12449219

ZGB1

201-11 (100/1

17V)

1

2449220

ZMB

2201-13

(220y240V)

FUSE

1 25591

33

1

2559532

1

25

595 18

12559516

SPEAKER

12389806

MGP1.0A

PRIM.

100/117V

CEETeaOrnA

PRIM.

22Of240V

CEET500mA

SEC.

220/240V

CEET3.15A

SEC.

22O/240V

EAF-16R02C

FLAT

CABLE HI

32

FLAT

CABLE

HI 33

FLAT

CABLE

H1

34

22P

50V

J

(palyatyrene)

IC-49-2406#2

{24P}

TCSO

25^1-1

FCN-7O4Q034'AU/L

34PIN

FCN-724P034-AU/L

34PIN

FCN'724P040-AU/L

40PIN

FCN-724P0&0-AUyL

50P1N

5045

04A

504&O5A

504506A

5045^

10A

LONG

NUT

#1

LONG

NUT^^3

Cover

H90

(radiation

cover)

Cover H

190

[lever SW)

Holder

H55

{pot.)

Holder

H83

Ikev

SW

asay

41

Holder

H92

(key SW

assy

1,

2,

3)

Holder

Hill

[keySW^ssyB)

Cushion

Hei

CAPACITOR

13563153

CQ09S-1

H^220O0-JO&

2200?

50V

J

(pDlYStyren&]

13569152

CO09S-lH'240RO

240P

50V J

!polv^tvrer>e)

13569151

CQO9S.1H-022RO

CONVERTER

TRANSFORMER

12449105

SI

67724

POWER

TRANSFORMER

022H044J

1

ODV

022H044C

117V

022H044D

220/240V

16

JAN.13,1982

MTR-100

JAN.13,1982

MTR-100

SERVICE NOTES

First Edition

SPECIFICATIONS

Memory

Capacity

-

250

K

bytes

(Each side of a tape)

Dimensions 218

x 348

x 118 mm

Weight....

3,4

Kg

Power

25

W

(Dom),

30 W (Exp)

Accessaries .^..-tt ,, t Connection

cable x 1

Data cassette

x 1

Pan^J

HS9

1

072H 0891

LED

board

149H 160

Side panel

H40

E0S3H04Q)

Powar

supply

board

(100/117V>

146H06S

(220/240V)

l-lSHOeS

Conriectoi"

FNC'7MQ03'1AU/L

(13^139178)

PARTS LIST

CHASSIS

061H129

Chassis

H129 (MAIN)

061H130

Chassis

H130

PANEL

072H089

PANEL

HS9

107H062

Cushion

H62

04SH026

Heat

sink H26

083H039

Side panel

(right)

H39

0a3H040 Side

panel (left) H40

FLAT

CABLE

053H135 Flat cable

HI

35

053H136

Flat

cable HI 36

POTENTIOMETER

TRiMJVIER

13299109

1KB{SR19R)

RESISTOR

M0-4S

13839146FQ 4.0n (3W}
13S39T47F0

].bn (3W}

CONNECTOR

13439178

FCN-7D4Q034-AU/L

34 pin

13439123

5045-07

A

13439180 S273-07A

CASSETTE

UNIT

POWER TRANSFORMER

|hH^^^

12439502

MT-2 022H046J

PTH046J

1D0V

022Ka46C

PTH-046C 117V3PCSA

tJi^lKir^^]

POWER

SWITCH

022H046D

PTH-046D

220V, 240V

^SiM^M

13149103

2wixn

FUSE

HHhIh

^^^

12559133

MGP1.0A

146H068

146H069

Power supply

board

PSH6a

10D/117V

(pcb052H334)

Power supply

board

PSH69

220/240V

12559532
12559614
12559516

CEET630mA

CEET2.0A

CEET3.15A

149H160

{pcb052H334)

LED

bo^rd

OPH160

(pcb 052H336}

NOISE

FILTER

149H145

Connector

board

(pcb

052H331)

12449219
12449220

ZGB1201-11 (100/117V)

ZMB220T 13 (220/240V)

SEM [CONDUCTOR

-"

IC

15199101F0

OTHERS

CossaltB jnit

MT-2 1T2<13&502)

;iA7230C

2215050300 Long

nut #3

(18mm)

2215O5OT0O Long nut #1 (lOmml

Ctiessi5H130(06^Hi:^0)

TRANSISTOR

15129114

2SC1815-GR

15129825

2SD844-0

DIODE

Flalt^ableHK

{

053 K

135)

5

Chassis H

129 (061

H

1291

15029103

TLR124[LED)

15019103 1S2473

15019250

DS5BfM-M

15019634

RD3.9Ee

IS

Roland

?7

MTR-100

13 m

POWER

SUPPLY

BOARD

PSH66(146H068) 1 00/11

7V/PSH69(146H069)

220/240V

(pcb 052H334)

;

-^2:

]\

F

-|

V8

21

1

/Vl2v

-!

/apJ

?

'i^

^::L

!

;MT-2

FLAr;

^i^n

^ *^

4^

H

l\

11

;o

It «

4

b

8

^0

\l

i^tt

IS

tt

zt1+:i

n

?D

^i M

I

V

ADJUSTMENT

Measurements

must

be done

without

disconnecting

connector

housing.

1.

Adjust VRl for

+

5.00V.

2.

Adjust VR2

for

+

12,00V,

3.

Confirm RESET Signal at

Pin

14 upon power ON.

^V

p«vtflE^

OU

\ ,®

(^

lOOV ELU

.1177

PiRN

230V BRIT RED
240y

RED

BRB

(MOTE; MT-2

is,

9S

a

whale, named

maker-only-repairable component.

The

Roland

Company will promptly supply

the replacement or

repair

the

unit upon reception.

Please

do not

disassemble

the

unit In question as

this

will

void

the service

polycy,

Return

complete MT-2 with

a

tag

identifying

the

unit

by using the mode! version and serial

number

of

the

iVlTRlOO

in

which

it is

usad.

PT secondary winding ratings

[email protected],6300^F IN

[email protected], 22O0jiiF EN

'T.

'%

T

18