Roland CR-68 User Manual

MARCH.15.1979

CR-68

SERVICE

SPECIFICATIONS

OUTPUT

TRIGGER PULSE

POWER

LEVEL

IMPEDANCE

OUTPUT

CONSUMPTION

DIMENSIONS

WEIGHT

**

Note

are

of

upward

downward

Cabinet

(081-117)

that

two

SLR322:

no.117

there

versions

throw

and

Pot.

NOTES

OdBm

Hi:

On:

8

26O(W)

4.5kg

EVHCOAP25B54

(026-023)

•Knob

Pot.

EVHCOAP25B15

(026-024)

max@Vol.

220k-ohm

+15V

watts

x

no.44

(016-044)

max

Lo:

Off:

275(D)

x

180(H)mm

Pot.

EVH2CAP25B54

Knob no.43

LED

Accent

lOk-ohm

OV

(028-966)

min

(016-043)

SLP-131B(019-013)

Switch

SDG5P

Knob

(OC1-217)

no.81

(016-081)

Pot.

EVHCOAP25B14

(026-021)

*-*

Switch SLR322

(001-264)

Switch

SCK-41097

upward

no.273

(001-273)

Switch

(001-230)

Switch

SRA1015

SRA101B

(001-229)

Base

no.20(foot)~|-

(111-020)J.

Nameplate

(076-356)

Cabinet

Screws

oval

Removal

4x20mm

Switch

HSW-0372-01-030

(001-206)

Jacks

SG7622

(009-012)

'Switch

SCK-41097

no.273

(001-273)

Switch

SUF-6-2

(001-263)

**

Switch

SLR322

(001-231)

.downward

Switch

SUF-B-2

(001-240)

Buttons

no.8

no.89Blue

no.88

no.87

no.86

no.85

L

Grey-

Yellow

Green

Red

White

(016-0**)

VK-O0

TEMPO

START

STOP

n

FOOT

START

MANUAL

FOOT

ARI

^TEMPO

J^*^

CLOCK

OSC

BALANCE

BD

CY

HH

M

ONE

SHOT

jxPB

8048

VOICES

ITER

OSC

CONTROL-

|PANEL|SWITh|eS

ACCENT

OUTPUT

IMP

L

COMPUTER

The

onasingle

ROM

an

Usedonthis

program

the

1.

SCANNING

The

the

138,

put

oneofproperly

For

pressed.

inputs

goes

Since

and1of

IC10

and

peating

ry

switch

This

continouslyinvery

rationsofseveral

is

pressed,

BOARD

uPD8048isan

program

8-bit

and

program

uPD8048

lines

through

Decoder)

from

IC8

example

When A

are

low

and

GL-10

sillicon

memory,

timer/counter

boardisa

data

dedicatedtothe

memory.

for

IDENTIFYING

reads

panel

Port2(P24-P27)ofIC10,IC8

and Port1(P10-P17)ofIC10.

(Binary-to-octal

arranged

let's

assume

inputofIC8ishigh

lowasshown

other

Port1(P10-P17)

IC8islow with

goes

low.

IC10

identifies

such

scanning

that

scanning,

settinginsequence.

and

reading,inSTOP mode,are performed

this

scanningisperformed

CIRCUIT

8-bit

parallel

chip.

a 64 x8RAM

and

uPD8048C-015

switch

switches

that

in Fig.

outputsgohigh.

functions

SWING

reads

this

SWING

switchisdepressed.Byre

the

computer

short

periodsbypulses

microsecons,bur

computer

The

8048

memory,27I/O

clock

circuits.

CR-68

PANEL

SWITCH

settingsbyscanning

decoder)

and

SWING

1.

nowasan input

switch

conditionofPort

fabricated

containsaIkx8

lines,

versioninwhich

are

stored

SETTINGS

(74LS-

The

goes

matrixtoport

switch

andB,C

The

through

is de

and

outputof1

port

on,

only

P10

can

identify

after

START

onceameasure

eve

with

switch

DESCRIPTION

2.

in

out

G2B

of

du

1#

1

SENDING

After

above,

is

selected

Port1and

Tow

74LSl38's

constituteabinary-to-hexadecimal

case,

3.

VARIATION

Since

MANUAL

one

reading

memorize

(74LS00)

IC4a

set

when

rhythm

goes

this

In

reading,

remains

ent of

buttonispressed,

low

andRSflip-flopisset.

and

pin6of

OUT

RHYTHM

panel

settings

the

data

correspondingtothe

from

containsofthe

Port

2.

(IC8

and

Port1of

the

IC10

TURNEDONWITH

computer

buttonispressed

and

another,acircuitisrequired

the

switching,

and

other

and

IC4b

constituteanRS

START/STOP

unit.

When

resetinthis

high,

and

pin6of

conditionisheld.

with

MANUAL

low

and

pin8of

the

conditionofpin10of

IC4b

goes

PATTERNS

are

identified

IC9)

are

as

ROM

described

identification

and

fed

usedinparallel

decoder.Inthis

functionsasan

MANUAL

reads

data

onceinone

during

which

output

BUTTON

the

period

consists

measure,if

of

components.

flip-flop

whichisre

buttonistappedtostart

way,

IC4b

goes

button

pin5of IC4b

high

off,

IC4cisheld

Pin3of

and

this

pin3of IC4a

low

and

hereafter

pin6of

high

independ

IC4c.

immediately

When

IC4a

goes

condition

into

to

port.

between

to

IC4

the

IC4b

MANUAL

goes

low

is

Whenanegative

while

reading

by

IC2c

and

pin10of

negative

and

detects

Immediately

negative

fed

going

into

that

going

flop.Toprevent

vertionbyIC2a)

NANDedtoproduceareset

4.

CLOCK

GENERATOR

This

circuit,a

emittedtosynchronize

the

computer,isaCRoscillator

IC3f

and

other

clock

signalsofabout

pinofIC10.

5.

MASTER

This

oscillator

isamultivibrator

components,

10ms-200ms

6.

START

CIRCUIT

This

circuit

components.

nectedtoTl of

Immediately

positive

and

going

C208isgeneratedatpin11of

IC5b.Qon

Consequently,

always

the

When

setinthe

computer

START

eratedatpin4of

IC5b.Qgoes

goes

high

The

one

shot

IC2b

and

ofanoutput

eratesapulse

resets

starts.

the

going

pulseissent

switch

this

IC4c.

positions,

inverted

Since

pin9of

positive

pulseissent

Port1through

MANUAL

after

button

reading,

pulse

from0of

malfunction,

andapulse

pulse.

IC3e,

IC3f

clock

generator

the

components.

3MHz

OSCILLATOR

Q101,

determines

consisting

whose

oscillation

with

TEMPO

control

IC5b,

ICla-ICld,

consistsofIC5b(Dflip-flop)

The

output

IC10.

after POWER

pulse

pin1goes

when

stops

buttonispressed,apositive

high

to-start

pulse

other

components

waveform

withadurationofabout

master

"Q"onpin1of

switchissettoON a

with

low

POWER

switchissettoON,

idling

andQgoes

oscillator

mode.(WhenTlof

all

functions except

IClb

whichisfed

the

rhythm

generator

fromQon

out

from4of

the

pulseisinverted

pulseisfed

IC4ciskept

out

from pin8of

D209.

Thus,

has

been

pressed.

the

computer

IC8toresetRSflip-

this

pulse

from

ALEofIC10

see

from

which

operations

high,

the

sends

(after

Fig.

pulses

carried

consistingofIC3e,

The

oscillator

which

are fed

Q102

the

tempo

of Q101,

generates

to

of the

Q102

periodisvariable

VR2.

IC2b

IC5b

the

time

constantofR212

ICld

and

andQon

pin2goes

IC10islow,

scanning).

pulseisgen

into

pin3of

low.

Then

unit.

consistingofICla,

detects

pin1of

when

the

see

Pig.

the

3

Tl

leading

IC5b and

30ms

rhythm

IC8

to

a

IC4c

computer

out

a

in-

are

2

are

out

by

XTAL

rythm

and

other

from

and

other

is

con

short

resets

high..

IC10

is

of

IC10

IClc,

edge

gen

which

unit

8.

DIVLDEft

To

send

TRIGGER

output

and

1/6.

(D

flip-flop,

components.

waveforms

divide-by-3

are

fed

IC5a

and

sent

Signals

of

IC6a

with8beat

see

Fig.4

VOICING

1.

LATCH

This

take

2

through

the

master

producing5Vpositive

tern,

master

The

output

by

Q25-Q35

swing

2.

ACCENT

This

cordingtoa

sound

consistsofthe

lU'/a, ±u;?a,

out

clock

pulses

OUT

jack,acircuitisrequiredtodivide

signals

into

and

fed

are

BOARD

circuit,consistingofthree

output

with

oscillator.

and fed

see

circuitisusedtoadd

from

the

The

circuit

IC7a,

from

the

circuit

the

IC6b

to be

fromQon

divided

and

VG-12

IC1—IC3

pulsestobe

IC2d

and

oscillatortoclear

the

same

pulses

into

Fig.

5

CIRCUIT

consistsoffour

IC5a,

usedasan

master

from

divide-by-3

convertedtosignals

pin1of

pin2of

again

sent

out

IC2e

going

durationasoutput

from

negative

inputsofthe

Q21,

preset accent

levelatthe

output

ACCENT

components.Anaccent

passes

tergratedtobe

whichisfed

Q24isoff

In

Q9isdividedbythe

input

signalisfed

With

the

into

usedtoadd

through

Q21

into

whenasignalisnot

this

case,

the

impedanceof010

into

ACCENT

accent

R137,

controlat10,

potentiometer

givingahigh

accent.

and

converted

the

voltageofthe

ratioofR137

the

iCba,

lUbb

with8beat

master

IC6a,

inverter,

and16beat

oscillator

and

IC6b)

shapes

into

MC14O13BTs

and

other

output

oscillatortoprevent

malfunctioning.

circuit

The

singals

consisting

with16beat

IC6b.

IC6btoCPonpin

to be

convertedtosignals

fromQon

latched

(clock),

pulse,

the

flip-flops

going

Q24,

VR14

accenttoa

pin13of IC6a.

74LS175

from

and

the

preceding

i.e.

pulses

voicing

flip-flops,

Port1and

take

pulses

rhythm

pulse

are

converted

witha+15V-0V

circuits,

rhythm

latch,

of

patternbychanging

amplifier.

(VR14),

pulse

Q21,

fromQon

thenisdifferentiated

to a

proper envelope

gateofFET

(Q24).

Q24

pin3of

The

and

circuit

and

signal

providedatthe

output

signal

(68k-ohm)tothe

andisfed

gate,

most

and

level

into

010.

Q24isturned

the

signal

Q24,

but

very

output

signal

When

on.

flows

little

which

to

the

1/3

the

of

11

Port

from

pat

the

ac

the

other

IC1

in-

gate.

from

a

into

is

7.

FOOT

SWITCH

The

foot

IC3a,

IC3b

TION

consistingofIC3c,IC3d

almost the

combined

prevent

malfunction

CIRCUIT

switch

withaschmitt

circuit

and

other

same circuit.ACR

IC3a-IC3d

for

START/STOP

components,

trigger circuitisused

caused

and

other

time

by foot

that

constant

switch

consisting

for

components,are

circuit

chattering.

of

VARIA

to

3.

LEAKAGE

These

voicing

poweristurnedonor

not

function

specttothe

The

voltage

itisat

is

shut

SOUND

KILLER

circuits

off.

are

designedtokill

generatedbytransient

normally

emitter.

dropatthe gateofQ23isquicker

the

drainorsource

Q20,

off.

until

Q23

When

powerison,

C79

charges

after

sound

from

voltage

Q20

enoughinre

trun,sothat

the

when

will

than

Q23

tot

Al

AL

ssC

ml

(AC

AlfC

OB«L

08,

O8,[

iL

ZL

C

t

[

—^y~

9

10

n

17

8048

8748

8035

SN54175.

SN54LS175.

SN74175!

40

39

SN74LS175.

SN54S17b

SN74S175

(TOP

...JOHW

...JORNPACKAGE

VIEW)

KACKAOt

W

»

34

3)

JM6

32

)P14

3»

30

n

i*

7»

CONNECTION

DIP

(TOP

VIEW)

NOTE:

The

Flatpak

pinouts

Dual

version

(Connection

In-line

Package.

F4013

TRUTH

SYNCHRONOUS

INPUTS

CP

S

J"

Conditions:Sq-Cq*

DIAGRAM

CP2

3,0

D2

3'

has

the

Diagram)asthe

same

TABLES

OUTPUTS

D

Qn+1

L

H

LOW

Qn+1

H

L

oe,C

O8,C

74

71

77

19

7'

20

DECODERS/DEMULTIPLEXERS

SN54LS138.

SN74LS138.

SN54S138

SN74S138

16U15

...JORWPACKAGE

...JORNPACKAGE

(TOP

VIEW)

OATA

OUTPUTS

iinn

SELECT

ENABLE

LS138

S138

MAXIMUM

FREQUENCY

'174/175

'LS174

LS175

'S174

*S175

QUADRUPLE

FUNCTION

(EACH

INPUTS

CLEAR

CLOCK

L

H

H"high

level

input

levelofQ

(steady

from

conditions

LS175.

HEX

L=low

X**irrelevant

t«transition

Qq-the

T-'175.

TYPICAL

CLOCK

35

MHz

40

MHz

110

MHz

D-TYPE

FLIP-FLOP)

X

t

L

state)

lowtohigh

before

were

and

'S175

INVERTERS

TYPICAL

POWER

DISSIPATION

PER

FLIP-FLOP

38

mW

14

mW

75

mW

FLIP-FLOPS

TABLE

OUTPUTS

Q

D

X

H

L

X

the

Qt

L

H

L

H

Qq

Qo

level

indicated

established

only

steady

state

ASYNCHRONOUS

INPUTS

L

H

-

LOW

L

H

S

X

Level

-

HIGH

Level

»

Positive-Going

- Don't

Care

-

State

After

F4001

QUAD

LOGIC

AND

DIP

LU

UJ UJ

OUTPUTS

CD

"IT"

Clock

CONNECTION

L

H

L

H

Transition

Positive

2-INPUT

(TOP

F4001

VIEW)

LlJ

LlI Lil LzJ

NOR

H

L

Transition

GATE

DIAGRAM

vss

INPUTS

ENABLE

G1

X

L

H

•G2-G2AfG2B

H=high

C

G2*

xxx

H

XXX

X

L

H

L

H

L

H

HHL

L

H

L

level.L-

FUNCTION

SELECT

B

L

H

L

H H

low

■LS138.

S138

TABLE

YOY1Y2

A

HHHHHHHH

LHHHHHHH

L

HLHHHHHH

H

HHLHHHHH

L

HHHLHHHH

H

HHHHLHHH

L

HHHHHLHH

H

HHHHHHLH

hhhhhhhl

level.X-

OUTPUTS

Y3 Y4

Y5 Y6

irrelevant

Y7

SN5404

(J)

SN54H04

(J)

SN54L04

(J)

SN54LS04(JW)

SN54S04(JW>

QUADRUPLE

POSITIVE

SN5400

(J)

SN54H00

(J)

SN54L00

(J)

SN54LS00U

SN54S00(JW)

W)

SN74O4(JN)

SN74H04(JN)

SN74L04(JN)

SN74LS04(JN)

SN74S04(JN)

2-INPUT

NANO

QATES

SN7400U

SN74H00U

SN74L00U

SN74LS00U

SN74S00U

GN0

N)

MARCH.15.1979

Rear

(061-225)

Chassis

no.225

Chassis

no.224

(061-224)

Sub

Chassis;

n"oT233

^(061-233)

.