ROHM BU9888FV-W Technical data

A

High Reliability Serial EEPROMs

Microwire BUS BR93□□□family

BU9888FV-W

●Description

BU9888FV-W is a serial EEPROM of serial 3-line interface method.

●Features

1) 256word×16bits architecture 4k bit serial EEPROM

2) Operating voltage range(3.0～3.6V)

3) Address auto increment function at read action

4) Write mistake prevention function Write prohibition at power on Write prohibition by command code Write mistake prevention function at low voltage

5) Program cycle auto delete and auto end function

6) Program condition display READY /

7) Low current consumption At write action(3.6V): Icc1 = 3.5mA(Max.) At read action(3.6V): Icc2 = 2.0mA(Max.) At standby action (3.6V) : ISB = 2.0μA(Max.)

8) Compact package SSOP-B8pin

9) Data retention for 40 years

10) Data rewrite up to 100,000 times

11) Data at shipment all addresses FFFFh

●Absolute maximum rating (Ta=25℃)

Parameter Symbol Ratings Unit

BUSY

No.11001EAT20

Supply Voltage Vcc -0.3～+6.5 V

Power Dissipation Pd 300 *1 mW

Storage Temperature Tstg -65 ～+125 ℃

Operating Temperature Topr -20 ～+85 ℃

Terminal Voltage － -0.3～Vcc+0.3 *2 V

*1 Degradation is done at 3.0mW/℃ for operation above 25℃ *2 The Max value of Terminal Voltage is not over 6.5V

●EEPROM recommended operating condition

Parameter Symbol Ratings Unit

Supply Voltage Vcc 3.0～3.6

Input Voltage VIN 0 ～ Vcc

●Memory cell characteristics(Ta=25℃, Vcc = 3.0～3.6V)

Limits

Parameter

Min. Typ. Max.

Erase/Write Cycle *1 100,000 －－ Cycles

Data Retention *1 40 －－ Years

*1 Not 100％ TESTED

V

Unit

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Technical Note

●DC Operating Characteristics(Unless otherwise specified Ta=-20～+85℃, Vcc=3.0～3.6V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Test Condition

"L" Input Voltage VIL -0.3 － 0.2×Vcc V

"H" Input Voltage VIH 0.8×Vcc － Vcc+0.3 V

"L" Output Voltage VOL 0 － 0.4 V IOL=2.1mA

"H" Output Voltage VOH 2.4 － Vcc V IOH=-0.4mA

Input Leakage Current ILI -1 － 1 μA VIN=0～Vcc

Output Leakage Current ILO -1 － 1 μA VOUT=0～Vcc, CS=0V

ICC1 －－ 3.5 mA

Operating Current

fSK=2MHz, tE/W=2ms(WRITE), TEST1=Vcc

ICC2 －－ 2.0 mA fSK=2MHz, (READ), TEST1=Vcc

Standby Current ISB －－ 2.0 μA CS=0V, TEST1=Vcc, DO=OPEN

○This product is not designed for protection against radioactive rays.

●EEPROM AC Operating Characteristics (Ta=-20～+85℃, Vcc = 3.0～3.6V)

Paramete Symbol

Min. Typ. Max.

Limits

Unit

SK Clock Frequency fSK －－ 2 MHz SK High Time tSKH 230 －－ ns SK Low Time tSKL 230 －－ ns CS Low Time tCS 200 －－ ns CS Setup Time tCSS 200 －－ ns DI Setup Time tDIS 100 －－ ns CS Hold Time tCSH 0 －－ ns DI Hold Time tDIH 100 －－ ns Data "1" Output Delay Time tPD1 －－ 200 ns Data "0" Output Delay Time tPD0 －－ 200 ns CS to Status Valid tSV －－ 150 ns CS to Output High-Z tDF －－ 150 ns Write Cycle time tE/W －－ 2 ms

●Synchronous data input/output timing

CS

tCSS tSKH

tSKL

tCSH

SK

DO(READ)

tDIS tDIH

DI

tPD0

tPD1

tDF

DO(WRITE)

STAT U S VALID

Fig.1 Sync data input / output timing

○Data is taken by DI in sync with the rise of SK. ○At read action, data is output from DO in sync with the rise of SK. ○The status signal at write (READY /

BUSY ) is output after tCS from the fall of CS after write command input, at the area

DO where CS is “H”, and valid until the next command start bit is input. And, while CS is “L”, DO becomes High-Z.

○After completion of each mode execution, set CS “L” once for internal circuit reset, and execute the following action mode.

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●Characteristic data (The following characteristic data are Typ. Values.)

6

5

(V)

Ta=-40℃

IH

Ta=25℃

4

Ta=85℃

3

SPEC

2

H INPUT VOLTAGE : V

1

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.2　'H' input

Fig.2 'H' input tvoltage

IH(CS,SK,DI)

5

(V)

4

OH

V

Ta=-40℃ Ta=25℃

voltage　

V

(CS,SK,DI)

IH

Ta=85℃

3

SPEC

2

1

H OUTPUT VOLTAGE : V

0

0 0.4 0.8 1.2 1.6

H OUTPUT CURRENT : I

Fig.5 'H' output voltage

Fig.5　'H' output voltage VOH-IOH(Vcc=3.0V) Fig.6

OH-IOH(Vcc=3.0V)

V

(mA)

OH

6

5

(V)

IL

Ta=-40℃

4

Ta=25℃

=

3

2

L INPUT VOLTAGE : V

1

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.3　'L' input voltage　V

Fig.3 'L' input voltage

IL (CS,SK,DI)

1.2

V

SPEC

(CS,SK,DI)

IL

SPEC

1

(uA )

LI

0.8

0.6

Ta=-40℃ Ta=25℃

0.4

Ta=85℃

0.2

INP UT L EAK C UR R E NT : I

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.6 Input leak current

　Input leak current

LI(CS,SK,DI)

I

ILI(CS,SK,DI) Fig.7

1

(V)

0.8

Ta=-40℃

OL

Ta=25℃ Ta=85℃

0.6

0.4

0.2

L OUTPUT VOLTAGE : V

0

1.2

(uA)

LO

0.8

0.6

0.4

0.2

OUTPUT LEAK CURRENT : I

SPEC

012345

L OUTPUT CURRENT : I

Fig.4 'L' output voltage

Fig.4 'L' output voltage VOL-IOL(Vcc=3.0V)

OL-IOL(Vcc=3.0V)

V

1

Ta=-40℃ Ta=25℃ Ta=85℃

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.7 Output leak current

　Output leak current

5

4

3

Ta=-40℃ Ta=25℃

2

Ta=85℃

AT W R ITING : Ic c1 (mA )

1

CURRENT CONSUMPTION

SPEC

0

0123456

Fig.8 Current consumption at WRITE

10000

1000

100

10

SUPPLY VOLTAGE : Vcc(V)

Fig.8

Current consumption at WRITE action

1(fSK=2MHz)

I

action ICC1(fSK=2MHz)

CC

Ta=-40℃ Ta=25℃ Ta=85℃

1

SK FRE Q U EN C Y : fSK （ MHz ）

0.1 0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.11 SK frequency fSK Fig.12 SK high time tSKH Fig.13 SK low time tSKL

Fig.11　 SK frequency f

SPEC

SK

3

2.5

SPEC

2

1.5

AT READING : Icc2(mA)

0.5

CURRENT CONSUMPTION

Fig.9 Consumption current at READ

Ta=-40℃ Ta=25℃ Ta=85℃

1

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.9

Consumption current at READ

CC2(fSK=2MHz)

action I

1

action

I

2(fSK=2MHz)

CC

Ta=-40℃

0.8

(μ s)

SKH

H SK TIME : t

Ta=25℃ Ta=85℃

0.6

0.4

0.2

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.12 SK high time t

SPEC

SKH

2.5

(uA)

2

SB

1.5

Ta=-40℃ Ta=25℃

1

Ta=85℃

0.5

ST AND B Y CU R R EN T : I

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.10 Consumption current

Fig.10

　Consumption current at standby action

at standby action I

1

Ta=-40℃

0.8

(μ s)

SKL

L SK TIME : t

Ta=25℃ Ta=85℃

0.6

0.4

0.2

0

0123456

SUPPLY VOLTAGE : Vcc（V）

Fig.13 SK

Technical Note

(mA)

OL

SPEC

low time　

ILO(DO)

SB

t

SKL

LO(DO)

I

SB

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Technical Note

●Characteristic data (The following characteristic data are Typ. Values.)

1.2

1

0.8

(μ s)

Ta=-40℃

CS

Ta=25℃

0.6

Ta=85℃

0.4

L CS TIME : t

0.2

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.14 CS Low time tCS Fig.15 CS Setup time tCSS Fig.16 DI Hold time tDIH

Fig.14 CS

SPEC

loe time

300

200

(ns)

CSS

100

0

SPEC

Ta=-40℃ Ta=25℃

-100

CS S E T U P TIM E : t

t

CS

Ta=85℃

-200 0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.15

　CS setup time　

t

CSS

150

SPEC

100

(ns)

DIH

Ta=-40℃ Ta=25℃

50

Ta=85℃

0

DI HO LD T IME : t

-50 0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.16

　DI hold time　

150

(ns)

100

DIS

50

Ta=-40℃ Ta=25℃ Ta=85℃

SPEC

0

DI S ET U P TIM E : t

-50 0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.17 DI Setup time tDIS Fig.18 Data '0' output delay time tPD0 Fig.19 Data '1' output delay time tPD1

Fig.17

　DI setup time　ｔ

DIS

1

(μ s)

PD0

Ta=-40℃

0.8

Ta=25℃ Ta=85℃

0.6

0.4

SPEC

0.2

0

DA T A '0' OU T PUT D ELA Y TIM E : t

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.18

'0' output delay time　t

　Data

PD0

1

(μ s )

PD1

0.8

Ta=-40℃ Ta=25℃

0.6

Ta=85℃

0.4

0.2

0

DATA '1' OUTPUT DELAY TIME : t

0123456

SUPPLY VOLTAGE : Vcc(V)

SPEC

Fig.19　Data '1' output delay time t

1

Ta=-40℃

0.8

Ta=25℃ Ta=85℃

(μ s)

SV

0.6

0.4

TIME BETWEEN CS

0.2

AN D O U T PU T : t

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.20 Time from CS to output

Fig.20

　Time from

establishment t

SPEC

CS to output establishment t

SV

250

Ta=-40℃

(ns)

Ta=25℃

200

DF

Ta=85℃

150

SPEC

100

TIME BETWEEN CS

50

AND OUTPUT HIGH-Z : t

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.21 Time from CS to High-Z tDF Fig.22 Write cycle time tE/W

Fig.21 Time from CS to High-Z t

DF

5

Ta=-40℃

4

(ms)

Ta=25℃

E/W

Ta=85℃

3

SPEC

2

1

WRITE CYCLE TIME : t

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.22

　Write cycle time

t

DIH

PD1

t

E/W

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High

Technical Note

●Pin assignment

TEST1

TEST2

Vcc

GND

BU9888FV-W: SSOP-B8

CS SK DI

DO

Fig.23 Pin assignment diagram

●Pin function

Pin name I / O Function

CS Input Chip select input

SK Input Serial clock input

DI Input Serial data input

DO Output Serial data output

TEST1 Input Test pin. Please connect to power. TEST2 - Test pin. Please open at using.

Vcc - Power source

GND - All input / output reference voltage, 0V

●Block diagram

CS

SK

Command decode

Control

Clock generation

Power source voltage detection

Write prohibition

voltage occurrence

DI

Command register

DO

Dummy bit

Address buffer

Data register

Fig.24 Block diagram

8bit

16bit

Address decoder

R/W amplifier

8bit

16bit

4,096bit EEPROM

●Command mode

Command Start bit Ope code Address Data

Read (READ)

Write enable (WEN)

Write (WRITE)

Write disable (WDS)

(*1)

(*2)

1 10 A7, A6, A5, A4, A3, A2,A1, A0 D15～D0(READ DATA) 1 00 1 1 ＊＊＊＊＊＊ 1 01 A7, A6, A5, A4, A3, A2, A1, A0 D15～D0(WRITE DATA) 1 00 0 0 ＊＊＊＊＊＊

・Input the address and the data in MSB first manners. ・As for ＊, input either VIH or VIL.

*Start bit

Acceptance of all the commands of this IC starts at recognition of the start bit. The start bit means the first “1” input after the rise of CS. *1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and

address data in significant order are sequentially output continuously. (Auto increment function)

*2 When the read and the write all commands are executed, data written in the selected memory cell is automatically

deleted, and input data is written.

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Technical Note

●Timing chart

1. Read cycle (READ)

CS

SK

DI

DO

High-Z

（※1）

12 4

1 1 A7 A6

～～

A0

A10

0

Fig.25 Read cycle

～～

28

（※2）

D027D1512D14D15 D14 D1

(※2）Next address data(Auto increment function)

～～

(※1) Start bit

When data “1” is input for the first time after the rise of CS, this is recognized as a start bit. And when “1” is input after plural “0” are input, it is recognized as a start bit, and the following operation is started. This is common to all the commands to described hereafter.

○When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0,

in sync with the rise of SK, “0” (dummy bit) is output. And, the following data is output in sync with the rise of SK. This IC has an address auto increment function valid only at read command. This is the function where after the above read execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto increment, keep CS at “H”.

2. Write cycle (WRITE)

CS

SK

DI

DO

High-Z

12 4 11

～～

A1 A00

～～

12 27

Fig.26 Write cycle

tE/W

tSV

～～

STATUS

～～

READYBUSY

～～

tCS

D0D1D15 D141A7A61

○In this command, input 16bit data (D15～D0) are written to designated addresses (A7~A0). The actual write starts by the

fall of CS of D0 taken SK clock. When STATUS is not detected, (CS=”L” fixed) Max. 2ms in conformity with tE/W, and

when STATUS is detected (CS=”H”), all commands are not accepted for areas where “L” ( therefore, do not input any command.

BUSY ) is output from D0,

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