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BU9847GUL-W
Technical data
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ROHM BU9847GUL-W Technical data

A
WL-CSP EEPROM family I2C BUS
BU9847GUL-W
●Description
BU9847GUL-W series is a serial EEPROM of I available at 400kHz.
●Features
1) Completely conforming to the world standard I and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) Actions available at 400kHz clock (1.7V～5.5V)
4) 1.7～5.5V single power source action most suitable for battery use.
5) Page write mode useful for initial value write at factory shipment.
6) Auto erase and auto end function at data rewrite.
7) Low current consumption At write action (5V) : 1.2mA (Typ.) At read action (5V) : 0.2mA (Typ.) At standby action (5V) : 0.1μA (Typ.)
8) Write mistake prevention function Write (write protect) function added. Write mistake prevention function at low voltage.
9) Data rewrite up to 1,000,000times.
10) Data kept for 40 years.
11) Noise filter built in SCL / SDA terminal
12) Shipment data all address FFh.
●BU9847GUL-W
Capacity Bit format Type Power source voltage VCSP50L1
4Kbit 512×8 BU9847GUL-W 1.7~5.5V ●
●Absolute maximum ratings (Ta=25°C)
Parameter Symbol Ratings Unit
Impressed voltage Vcc -0.3~+6.5 V
Permissible dissipation Pd 220 *1 mW Storage temperature range Tstg -65~125 ℃ Operating temperature range Topr -40~85 ℃
Terminal voltage - -0.3~Vcc+1.0 V
* When using at Ta=25℃ or higher, 2.2mW (*1) to be reduced per 1℃
●Recommended action conditions
Parameter Symbol Ratings Unit
Power source voltage
Input voltage
●Memory cell characteristics (Ta=25°C, Vcc=1.7~5.5V)
Parameter
Number of data rewrite times *1 1,000,000 - - Times
Data hold years
*1 Not 100% TESTED
2
C BUS interface method. 1.7V single power source action and actions
2
C BUS. All controls available by 2 ports of serial clock (SCL)
●Page write
Number of pages 16Byte
Product number BU9847GUL-W
Vcc 1.7~5.5
Vin 0~Vcc
Limits
Min Typ. Max
40 - - Years
Unit
V
No.10001EAT14
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© 2010 ROHM Co., Ltd. All rights reserved.
1/18
2010.09 - Rev.
BU9847GUL-W
A
●Electrical characteristics
(Unless otherwise specified, Ta=-40~+85°C, Vcc=1.7~5.5V)
Parameter Symbol
Min. Typ. Max.
Limits
Technical Note
Unit Conditions
“HIGH” input voltage1 V
“LOW” Input voltage1 V
“HIGH” input voltage2 V
“LOW” input voltage2 V
“HIGH” input voltage3 V
“LOW” input voltage3 V
“LOW” output voltage1 V
“LOW output voltage2 V
0.7Vcc - Vcc+1.0 V 2.5V≤Vcc≤5.5V
IH1
-0.3 - 0.3Vcc V 2.5V≤Vcc≤5.5V
IL1
0.8Vcc - Vcc+1.0 V 1.8V≤Vcc<2.5V
IH2
-0.3 - 0.2Vcc V 1.8V≤Vcc<2.5V
IL2
0.9Vcc - Vcc+1.0 V 1.7V≤Vcc<1.8V
IH3
-0.3 - 0.1Vcc V 1.7V≤Vcc<1.8V
IL3
- - 0.4 V IOL=3.0mA, 2.5V≤Vcc≤5.5V, (SDA)
OL1
- - 0.2 V IOL=0.7mA, 1.7V≤Vcc<2.5V, (SDA)
OL2
Input leak current ILI -1 - 1 μAVIN=0V~Vcc
Output leak current ILO -1 - 1 μAV
I
- - 2.0 mA
Current consumption at action
CC1
I
- - 0.5 mA
CC2
Standby current ISB - - 2.0 μA
◎Radiation resistance design is not made.
=0V~Vcc(SDA)
OUT
Vcc=5.5V, f
=400kHz, tWR=5ms,
SCL
Byte write, Page write Vcc=5.5V, f
=400kHz
SCL
Random read, vurrent read, sequential read Vcc=5.5V, SDA·SCL=Vcc,
A2=GND, WP=GND
●
Action timing characteristics
(Unless otherwise specified, Ta=-40～+85°C、Vcc=1.7～5.5V)
FAST-MODE
1.7V
Parameter Symbol
≤Vcc≤5.5V
Min. Typ. Max.
SCL frequency fSCL - - 400 kHz
Data clock “HIGH“ time tHIGH 0.6 - - μs
Data clock “LOW“ time tLOW 1.2 - - μs
SDA, SCL rise time *1 tR *1 - - 0.3 μs
SDA< SCL fall time *1 tF *1 - - 0.3 μs
Start condition hold time tHD:STA 0.6 - - μs
Start condition setup time tSU:STA 0.6 - - μs
Input data hold time tHD:DAT 0 - - ns
Input data setup time tSU:DAT 100 - - ns
Output data delay time tPD 0.1 - 0.9 μs
Output data hold time tDH 0.1 - - μs
Stop condition setup time tSU:STO 0.6 - - μs
Bus release time before transfer start tBUF 1.2 - - μs
Internal write cycle time tWR - - 5 ms
Noise removal valid period (SDA, SCL terminal) tI - - 0.1 μs
WP hold time tHD:WP 0 - - ns
WP setup time tSU:WP 0.1 - - μs
WP valid time tHIGH:WP 1.0 - - μs
*1 Not 100% tested.
Unit
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© 2010 ROHM Co., Ltd. All rights reserved.
2/18
2010.09 - Rev.
BU9847GUL-W
A
f
A
●Sync data input / output timing
SCL
SDA (Input)
SDA (Output)
SCL
SDA
tHD:STA tHD:DAT tSU:DAT
tBUF tPD tDH
○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL
Fig.-1(a) Sync data input / output timing
tSU:STA tSU:STOtHD:STA
START BIT
Fig.1-(b) Start – stop bit timing
SCL
SDA
D0 ACK
Write data
（ｎ-th address）
Stop condition Start condition
Fig.1-(c) Write cycle timing
tLOW
Technical Note
tHIGH tR tF
SCL
DATA(1)
D1 D0ACK
SDA
WP
tSU：WP
fig.1-(d) WP timing at write execution
SCL
DATA(1)
D1 D0 ACK ACK
SDA
STOP BIT
WP
Fig.1-(e) WP timing at write cancel
○At write execution, in the area from the DO taken clock rise of the first DATA (1),
to tWR, set WP=”LOW”
○By setting WP “HIGH” in the area, write can be cancelled. When it is set WP=”HIGH” during tWR, write is forcibly ended, and data o
address under access is not guaranteed, therefore write it once again.
tWR
DATA(n)
DATA(n)
tHIGH:WP
CK
WR
ｔ
stop condition
ストップコンディション
tWR
ｔHD：
WP
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© 2010 ROHM Co., Ltd. All rights reserved.
3/18
2010.09 - Rev.
BU9847GUL-W
A
A
●Block diagram
VCC
GND
9bit
Address
decoder
4Kbit EE PROM array
9bit
Slave – word
address register
A2
START STOP
Control circuit
High voltage
generating circuti
Power source
volta ge detection
Fig.2 Block diagram
●Pin assignment and description
B
B1
○
B2
○○
B3
A1
○
A2
○
A3
○
1
Fig.3 BU9847GUL-W(bottom view)
2
3
Land No. Terminal name Input/ Output Function
B3 A2 Input Slave address setting terminal
B2 GND - Reference voltage of al input / output, 0V
B1 SDA Input/Output Slave and word address, Serial data input serial data output.
A3 Vcc - Connect the power source.
A2 WP Input Write protect terminal
A1 SCL Input Serial clock input
●Characteristic data (The following values are Typ. ones.)
6
5
4
3
VIH1,2,3[V]
2
1
0
0123456
SPEC
Ta=85°C
Ta=-40°
Ta=25°C
Vcc[V]
6
5
4
3
Ta=85°C
VIL1,2,3[V]
Ta=-40°
2
Ta=25°C
1
0
0123456
SPEC
Vcc[V]
Fig.4 H input voltage VIH1,2,3
(A2,SCL,SDA,WP)
Fig.5 L input voltage VIL1,2,3
(A2,SCL,SDA,WP)
Technical Note
8bit
Data
register
ACK
INDEX Post
1
0.8
0.6
VOL2[V]
0.4
0.2
Ta=85°C
SPEC
0
0123456
IOL2[mA]
Fig.6 L output voltage VOL2-IOL2
(VCC=1.7V)
WP
SCL
SDA
Ta=25°C
Ta=-40°
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© 2010 ROHM Co., Ltd. All rights reserved.
4/18
2010.09 - Rev.
BU9847GUL-W
A
Technical Note
1
0.8
0.6
VOL1[V]
0.4
0.2
0
0123456
SPEC
Ta=85°C
Ta=-40°
IOL1[mA]
Fig.7 L input voltage
VOL1-IOL1 (Vcc=2.5V)
2.5
Ta=25°C
Ta=85°C
SPEC
1.5
ICC1[mA]
2
fSCL=400kHz DATA=AAh
1
0.5
0
0123456
Fig.10 Consumption current
at write action Icc1 (fSCL=400kHz)
10000
1000
Ta=85°C
100
fSCL[kHz]
10
1
0123456
SPEC
Fig.13 SCL frequency
f
SCL
1
0.8
0.6
0.4
tHD:STA[μs]
0.2
0
0123456
SPEC
Fig.16 Start condition hold time
tHD:STA
200
100
0
tSU:DAT(HIGH)[ns]
-100
-200 0123456
SPEC
Ta=85°C
Fig.19 Input data setup time
tSU:DAT
Vcc[V]
Vcc[V]
Vcc[V]
Vcc[V]
Ta=-40°
Ta=-40°
Ta=25°C
Ta=85°C
Ta=25°C
Ta=-40°C
Ta=-40°C
Ta=25°C
Ta=25°C
1.2
SPEC
Vcc[V]
Ta=85°C
Ta=25°C
Ta=-40°
1
0.8
0.6
ILI[μA]
0.4
0.2
0
0123456
Fig.8 Input leak current
ILI(A2,SCL, WP)
0.6
0.5
0.4
0.3
ICC2[mA]
0.2
0.1
0
SPEC
fSCL=400kHz DATA=AAh
Ta=25°C
Ta=85°C
Ta=-40°
0123456
Vcc[V]
Fig.11 Consumption current
at write action Icc2 (fSCL=400kHz)
1
0.8
0.6
0.4
tHIGH [μs]
0.2
0
0123456
SPEC
Ta=85°C
Ta=25°C
Ta=-40°
Vcc[V]
Fig.14 Data clock “H” time
tHIGH
1
0.8
0.6
0.4
0.2
tHD:DAT(HIGH)[ns ]
0
-0.2 0123456
SPEC
Ta=85°C
Ta=25°C
°
Vcc[V]
Fig.17 Start condition setup time
tSU:STA
1
0.8
0.6
0.4
tPD0 [μs]
0.2
0
0123456
Fig.20 Output data delay time
SPEC
Ta=85°C
Ta=25°C
Ta=-40°
SPEC
Vcc[V]
tPD0
1.2
1
0.8
0.6
ILO[μA]
0.4
0.2
0
SPEC
Ta=85°C
Ta=25°C
Ta=-40°
0123456
Vcc[V]
Fig.9 Output leak current
ILO (SDA)
2.5
SPEC
SPEC
Vcc[V]
I
SB
Ta=85°C
Ta=25°C
Vcc[V]
Ta=85°C
Ta=25°C
Ta=-40°
Ta=-40°
2
1.5
ISB[μA]
1
0.5
0
0123456
Fig.12 Standby current
1.6
1.2
0.8
tLOW[μs]
0.4
0
0123456
Fig.15 Data clock “L” time
tLOW
50
0
-50
-100
tHD:DAT(HIGH)[ns ]
-150
-200
SPEC
Ta=85°C
Ta=25°C
Ta=-40°
0123456
Vcc[V]
Fig.18 Input data hold time
tHD:DAT
1
0.8
0.6
0.4
tPD1 [μs]
0.2
0
0123456
Fig.21 Output data delay time
SPEC
Ta=85°C
Ta=25°C
Ta=-40°
SPEC
Vcc[V]
tPD1
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© 2010 ROHM Co., Ltd. All rights reserved.
5/18
2010.09 - Rev.
BU9847GUL-W
A
Technical Note
1
4
5
0.8
0.6
0.4
tDH0[μs]
0.2
0
SPEC
0123456
Ta=85°C
Ta=25°C
Ta=-40°C
Vcc[V]
Fig.22 Output data hold time
5
4
3
tBUF[μs]
2
1
0
0123456
tDH1
SPEC
Vcc[V]
Ta=-40°
C
Ta=25°C
Fig.25 Bus release time
before transfer start tBUF
0.6
0.5
0.4
SPEC
Ta=-40°
Ta=85°C
Vcc[V]
0.3
Ta=25°C
tI(SCL L) [ μs]
0.2
0.1
0
0123456
Fig.28 Noise removal time
Ta=25°C
tI (SCL L)
SPEC
Ta=85°C
Ta=-40°
Vcc[V]
0.2
0
-0.2
tSU:WP[μs]
-0.4
-0.6
0123456
Fig.31 WP setup time
tSU:WP
3
2
tDH1[μs]
1
SPEC
0
0123456
Ta=85°C
Ta=25°C
Ta=-40°C
Vcc[V]
Fig.23 Output data hold time
6
5
4
3
tWR[ms]
2
1
0
0123456
tDH1
SPEC
Ta=85°C
Vcc[V]
Ta=-40°
Ta=25°C
Fig.26 Internal write cycle time
0.6
0.5
0.4
0.3
Ta=25°C
0.2
tI(SDA H) [μs]
0.1
0
0123456
Fig.29 Noise removal time
1.2
1
0.8
0.6
tHIGH:WP[μs]
0.4
0.2
0
0123456
tWR
Ta=-40°
Ta=85°C
SPEC
Vcc[V]
tI (SDA H)
SPEC
Ta=-40°C
Ta=25°C
Ta=85°C
Vcc[V]
Fig.32 WP valid time
tHIGH: WP
4
3
2
tSU:STO[μs]
1
0
SPEC
0123456
Vcc[V]
Ta=85°C
Ta=25°C
Ta=-40°C
Fig.24 Stop condition setup time
Ta=-40°
tSU:STO
SPEC
Vcc[V]
Ta=25°C
Ta=85°C
0.6
0.5
0.4
0.3
tI(SCL H) [μs]
0.2
0.1
0
0123456
Fig.27 Noise removal time
0.6
0.5
0.4
0.3
tI(SDA L) [ μs]
0.2
0.1
tI (SCL H)
Ta=-40°
Ta=25°C
SPEC
0
0123456
Fig.30 Noise removal time
Ta=85°C
Vcc[V]
tI (SDA L)
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© 2010 ROHM Co., Ltd. All rights reserved.
6/18
2010.09 - Rev.
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